A method for fabricating high-speed three-dimensional stacked ferroelectric field effect transistor

Abstract

This invention provides a method for fabricating a high-speed three-dimensional stacked ferroelectric field-effect transistor, belonging to the field of micro-nano electronics technology. In the three-dimensional stacked FeFET device fabricated using this invention, the synergistic optimization of the ferroelectric layer and oxide channel effectively assists in the polarization switching of the ferroelectric layer. This reduces the operating voltage while increasing the write speed, achieving excellent overall performance. Combined with the high density and high bandwidth capabilities of three-dimensional stacking, it provides a low-cost, high-speed, and reliable storage solution for the rapidly growing data in the AI ​​era.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a method for fabricating a high-speed three-dimensional stacked ferroelectric field-effect transistor (FeFET). Background Technology

[0002] With the development of artificial intelligence, especially large language models (LLM), there is an urgent need for new types of memory that combine high storage density and ultra-fast read and write capabilities. Three-dimensional stacked ferroelectric field-effect transistors (3D FeFETs) are considered important candidates for next-generation high-performance memory due to their advantages such as single-transistor architecture, non-volatility, and ease of vertical high-density integration similar to 3D NAND.

[0003] However, existing 3D FeFETs face severe technical bottlenecks in achieving high-frequency data interaction, namely extremely slow write speeds and excessively high operating voltages. This is primarily due to fundamental physical limitations: to meet the thermal budget and process compatibility requirements of high-density 3D integration, 3D FeFETs typically use oxide semiconductors (such as indium gallium oxide, IGZO) as the channel material. These oxide semiconductors generally exhibit strong n-type conductivity and extremely large band gaps, making p-type inversion extremely difficult. This results in a situation where, during programming (applying a positive bias voltage to the gate), there are sufficient electrons in the channel to shield the depolarization field of the ferroelectric layer, making programming relatively easy; however, during erasure (applying a negative bias voltage to the gate), the channel enters a deep depletion state, lacking holes to shield the depolarization field in the ferroelectric layer, making the switching of ferroelectric polarization exceptionally difficult. Therefore, existing oxide-channel 3D FeFETs have to rely on applying extremely high negative voltages and extremely long operating times to forcibly complete the erase operation, which severely slows down the overall write speed of the device.

[0004] In summary, there is an urgent need in this field for a technical solution that can overcome the physical limitation of "difficulty in erasing" in oxide channels, so as to effectively reduce the operating voltage of 3D FeFETs and multiply their write speed, thereby meeting the needs of high-performance computing. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a method for fabricating high-speed three-dimensional stacked FeFETs. By optimizing the channel layer in the FeFET and introducing an oxide channel layer with more oxygen vacancy defects, the operating voltage and write speed of the three-dimensional stacked FeFET are significantly optimized.

[0006] The technical solution of this invention is as follows:

[0007] A method for fabricating a three-dimensional stacked ferroelectric field-effect transistor, comprising the following steps:

[0008] 1) A silicon dioxide layer is grown on a silicon substrate by wet oxygen oxidation to form a wafer sample;

[0009] 2) A word line stack is formed by alternating growth of an isolation layer material and a gate metal electrode material on a silicon dioxide layer from bottom to top, wherein the gate metal electrode material is grown by sputtering and the isolation layer material is grown by chemical vapor deposition.

[0010] 3) Define the pattern of the vertical trench by ultraviolet lithography, use photoresist as a barrier layer, and dry etch the vertical trench on the word line stack to prepare the vertical trench, the bottom of the vertical trench reaching the silicon dioxide layer on the silicon substrate;

[0011] 4) Ferroelectric layers are grown on wafer samples using atomic layer deposition (ALD). Specifically, one cycle of hafnium oxide layer is grown first, followed by one cycle of zirconium oxide layer. Then, hafnium oxide and zirconium oxide layers are grown alternately in this order to form a hafnium-zirconium ferroelectric layer.

[0012] 5) A titanium nitride sacrificial layer is grown on the ferroelectric layer by sputtering and then subjected to rapid thermal annealing to activate the ferroelectricity.

[0013] 6) The titanium nitride sacrificial layer was removed using a wet etching method;

[0014] 7) An indium gallium oxide channel layer is grown on the ferroelectric layer using atomic layer deposition (ALD); an oxygen-deficient environment is created in the reaction chamber, resulting in a growing indium gallium oxide channel layer with more oxygen vacancy defects.

[0015] 8) The pattern of the indium gallium oxide channel region is defined by ultraviolet lithography, and the indium gallium oxide material in the non-channel region is removed by etching with diluted dilute hydrochloric acid, thereby realizing the deposition of a hafnium zirconium ferroelectric layer and an indium gallium oxide channel layer on the inner wall of the vertical trench.

[0016] 9) Define the source and drain metal pattern regions by electron beam lithography, then deposit the source and drain metal materials on the wafer sample by vapor deposition or physical vapor deposition (PVD), and then remove the metal materials in the non-pattern regions by lift-off technology. Source and drain metal electrodes are formed on both sides of the indium gallium oxide channel layer, and the channel region is between the source and drain metal electrodes.

[0017] 10) Define the pattern of word line contact holes layer by layer by ultraviolet lithography, use photoresist as a barrier layer, and use dry etching and wet etching methods to prepare word line contact holes in each gate metal electrode material layer in the word line stack. The bottom of the word line contact hole is in contact with the surface of the gate metal electrode material.

[0018] Furthermore, the vertical groove has a circular or rectangular shape when viewed from above.

[0019] Furthermore, the thickness of the indium gallium oxide channel layer is 3~5 nm.

[0020] Furthermore, the thickness of the hafnium zirconium ferroelectric layer is 5~8 nm.

[0021] Furthermore, in step 7), the indium gallium oxide channel layer is grown using the ALD method, and indium cyclopentadiene (InCp), triethyl gallium (TEGa), and ozone are used as precursors for indium, gallium, and oxygen, respectively.

[0022] The technical effects of this invention are as follows:

[0023] I. In the three-dimensional stacked FeFET device prepared by the present invention, by preparing a hafnium zirconium ferroelectric layer and an indium gallium oxide channel with a large number of oxygen vacancy defects, the polarization switching in the ferroelectric layer is effectively assisted, thereby reducing the operating voltage and improving the write speed.

[0024] In conventional three-dimensional stacked FeFETs with oxide channels, the channels, typically made of indium gallium oxide (IGNOO) or similar n-type semiconductor materials, contain a large number of electrons. When a positive voltage is applied to the FeFET gate for programming, these n-type electrons effectively reduce the depolarization field in the ferroelectric layer, making programming easy. However, when a negative voltage is applied to the FeFET gate for erasure, the large bandgap of the oxide channel makes inversion difficult, resulting in almost no p-type holes in the channel. This makes it difficult to shield the depolarization field in the ferroelectric layer, hindering ferroelectric polarization reversal and requiring a larger voltage and longer erasure time. In contrast, using an IGNOO channel with more oxygen vacancy defects, these defects exist as shallow donor or sub-bandgap defect states in the oxide semiconductor. When a negative voltage is applied to the gate for erasure, the semiconductor surface enters deep depletion, the bandgap bends upward, and the Fermi level (E) reaches its maximum. F The oxygen vacancy level drops below the oxygen vacancy defect level. At this point, the neutral oxygen vacancy will conduction electrons to the conduction band, ionizing itself to form a positively charged defect state (V0). o 2+ These large quantities of positively charged V o 2+ This effectively reduces depolarization in the ferroelectric layer, making it easier for the ferroelectric polarization to flip and for erasure to be easier. By comparison, it was found that the erase voltage of an indium gallium oxide (IGNOW) channel FeFET with more oxygen vacancy defects was reduced from -2.5 V to -2 V, and the required erase time was reduced from 50 ns to 20 ns, compared to an IGNOW channel FeFET with fewer oxygen vacancy defects.

[0025] Second, reduced array-level power consumption enables next-generation high-performance architectures and in-memory computing applications. The reduction in operating voltage (from -2.5 V to -2.0 V) directly results in a quadratic decrease in device operating power consumption. For high-density integrated 3D stacked memory arrays, this significantly alleviates the internal heat dissipation pressure and improves system energy efficiency. More importantly, the ultra-fast erase and write capability at the 20 ns level allows this 3D stacked FeFET to perfectly fill the performance gap in current memory tiers. Especially in cutting-edge applications such as hardware acceleration for large language models (LLMs) and in-memory computing (CIM / IMC), for hot data that requires extremely frequent updates (such as key-value caches in attention mechanisms), this invention's device not only provides operating latency comparable to traditional DRAM but also completely eliminates the enormous static power consumption caused by periodic refreshes in DRAM. This provides an ideal physical carrier for next-generation memory systems that combine high density, high speed, and extremely low power consumption.

[0026] The three-dimensional stacked FeFET device fabricated in this invention achieves excellent overall performance by reducing the operating voltage and improving the write speed through synergistic optimization of the ferroelectric layer and oxide channel. Combined with the high density and high bandwidth capabilities of the three-dimensional stack, it provides a low-cost, high-speed and reliable storage solution for the rapidly growing data in the AI ​​era. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the steps involved in fabricating a high-speed three-dimensional stacked FeFET according to an embodiment of the present invention, wherein:

[0028] (a) is a cross-sectional view of a 300 nm thick silicon dioxide layer grown on a silicon substrate by wet oxygen oxidation.

[0029] (b) is a cross-sectional view of the stacked silicon dioxide isolation material and titanium nitride gate metal electrode material (four layers each) formed by alternating growth of silicon dioxide isolation material and titanium nitride gate metal electrode material through plasma enhanced chemical vapor deposition (PECVD) and sputtering, respectively, based on (a);

[0030] (c) is a cross-sectional view of the vertical trench pattern defined by ultraviolet lithography and formed by dry etching, based on (b).

[0031] (d) is a cross-sectional view of (c) after growing a hafnium zirconium ferroelectric layer by atomic layer deposition and then performing rapid thermal annealing.

[0032] (e) is a cross-sectional view of (d) after growing an indium gallium oxide channel with more oxygen vacancy defects by sublayer deposition and removing the excess part by ultraviolet lithography and etching.

[0033] (f) is a cross-sectional view of the source and drain metal materials grown by electron beam evaporation after defining the source and drain patterns by electron beam lithography and then stripping them, based on (e).

[0034] (g) is a cross-sectional view after defining the word line contact hole pattern layer by layer by ultraviolet lithography based on (f), and removing the excess dielectric material in the word line contact hole by dry etching and wet etching.

[0035] Figure 1 middle:

[0036] 1 — Silicon substrate 2 — Silicon dioxide layer oxidized by wet oxygen

[0037] 3 — Silicon dioxide insulating layer; 4 — Titanium nitride gate metal electrode

[0038] 5 — Vertical trench; 6 — Hafnium zirconium ferroelectric layer

[0039] 7—Indium gallium oxide channel layer with a large number of oxygen vacancy defects

[0040] 8 — Source 9 — Leak

[0041] 10 — Pin contact hole

[0042] Figure 2 The images shown are renderings of a three-dimensional FeFET device prepared according to a specific embodiment of the present invention. (a) and (b) are the results of programming and erasing speed tests on a three-dimensional FeFET device prepared by prior art; (c) and (d) are the results of programming and erasing speed tests on a three-dimensional stacked FeFET device prepared according to an embodiment of the present invention. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0044] The process steps of the three-dimensional stacked FeFET fabrication method of this invention are as follows: Figure 1 As shown, it specifically includes:

[0045] 1) A 300 nm thick silicon dioxide layer 2 is grown on a silicon substrate 1 by wet oxygen oxidation, as shown in (a);

[0046] 2) Word line stacks are formed by alternating growth of isolation layer material and gate metal electrode material from bottom to top on the wet oxygen-oxidized silicon dioxide layer 2. The silicon dioxide isolation layer 3 is grown by plasma-enhanced chemical vapor deposition (PECVD), and the titanium nitride gate metal electrode 4 is grown by sputtering. There are four layers of titanium nitride gate metal electrode 4 and four layers of silicon dioxide isolation layer 3, each with a material thickness of 30 nm, as shown in (b).

[0047] 3) Define the pattern of the vertical trench 5 by ultraviolet lithography, and then use photoresist as a barrier layer to remove the gate metal electrode and isolation layer in the vertical trench 5 by dry etching until the bottom of the vertical trench reaches the wet oxygen oxidized silicon dioxide layer 2, as shown in (c).

[0048] 4) A hafnium-zirconium ferroelectric layer 6 is grown on the entire wafer by atomic layer deposition (ALD). Specifically, one cycle of hafnium oxide layer is grown first, followed by one cycle of zirconia layer, and then the hafnium oxide and zirconia layers are grown alternately in this order until the total number of cycles reaches 60-100. The hafnium-zirconium ferroelectric layer is formed and attached to the inner wall of the vertical trench. The thickness of the hafnium-zirconium ferroelectric layer is 5-8 nm, as shown in (d).

[0049] 5) A titanium nitride sacrificial layer is grown on the ferroelectric layer by sputtering and then subjected to rapid thermal annealing (500°C, 60s) to activate the ferroelectricity.

[0050] 6) After immersing the wafer sample in a liquid with a volume ratio of ammonia, hydrogen peroxide and water of 1:1:5, the titanium nitride sacrificial layer is removed by wet etching.

[0051] 7) An indium gallium oxide channel layer 7 with many oxygen vacancy defects is grown on the ferroelectric layer by atomic layer deposition (ALD). Specifically, indium cyclopentadiene (InCp), triethylgallium (TEGa) and ozone are used as precursors for indium, gallium and oxygen, respectively. The ratio of doped atoms is controlled to be 1:2 by controlling the cycle rate ratio of indium oxide and gallium oxide. The thickness is 4 nm. During the ALD process, the ozone gas is introduced for 6 s and the flow rate is 50 sccm in each cycle to form an oxygen-deficient environment in the reaction chamber and form an indium gallium oxide channel with many oxygen vacancy defects.

[0052] 8) Subsequently, the pattern of the channel layer 7 was defined by ultraviolet lithography, and the indium gallium oxide material in the non-channel region was removed by etching with a 1:20 diluted dilute hydrochloric acid solution, thereby realizing the deposition of a hafnium zirconium ferroelectric layer and an indium gallium oxide channel layer on the inner wall of the vertical trench, as shown in (e).

[0053] 9) Define the source 8 and drain 9 patterned regions by electron beam lithography, and then grow the source and drain metal materials Ti / Pt alloy by electron beam evaporation. Subsequently, remove the metal materials in the non-patterned regions by lift-off technology, and form source and drain metal electrodes on both sides of the indium gallium oxide channel layer respectively. There is a gap between the source and drain metal electrodes, as shown in (f). The channel region is between the source and drain.

[0054] 10) Define the pattern of word line contact holes 10 of gate metal electrode material layer by layer by ultraviolet lithography, and then use photoresist as a barrier layer to remove excess dielectric material in word line contact holes by dry etching and wet etching, so that the bottom of the word line contact hole of each layer of gate metal electrode material contacts the corresponding gate metal electrode 4, as shown in (g). Each layer of gate metal electrode is connected to the word line through different word line contact holes.

[0055] Figure 2 The results are from programming and erasing speed tests conducted on a 3D stacked FeFET fabricated using existing technology and a 3D stacked FeFET fabricated according to this invention. By characterizing the change in the storage window under different write pulse voltage amplitudes and widths, the programming and erasing conditions for the 3D stacked FeFET fabricated using existing technology are +2 V, 20 ns and -2.5 V, 50 ns, respectively; while the programming and erasing conditions for the 3D stacked FeFET device fabricated according to this invention are +2 V, 20 ns and -2 V, 20 ns, respectively. Compared to the 3D stacked FeFET fabricated using existing technology, it requires a lower operating voltage for erasing and has a faster write speed. Furthermore, the write speed is at least 2.5 times faster than other reported similar devices.

[0056] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A method for fabricating a three-dimensional stacked ferroelectric field-effect transistor, comprising the following steps: 1) A silicon dioxide layer is grown on a silicon substrate by wet oxygen oxidation to form a wafer sample; 2) A word line stack is formed by alternating growth of an isolation layer material and a gate metal electrode material on a silicon dioxide layer from bottom to top, wherein the gate metal electrode material is grown by sputtering and the isolation layer material is grown by chemical vapor deposition. 3) Define the pattern of the vertical trench by ultraviolet lithography, use photoresist as a barrier layer, and dry etch the vertical trench on the word line stack to prepare the vertical trench, the bottom of the vertical trench reaching the silicon dioxide layer on the silicon substrate; 4) Ferroelectric layers are grown on wafer samples using atomic layer deposition (ALD). Specifically, one cycle of hafnium oxide layer is grown first, followed by one cycle of zirconium oxide layer. Then, hafnium oxide and zirconium oxide layers are grown alternately in this order to form a hafnium-zirconium ferroelectric layer. 5) A titanium nitride sacrificial layer is grown on the ferroelectric layer by sputtering and then subjected to rapid thermal annealing to activate the ferroelectricity. 6) The titanium nitride sacrificial layer was removed using a wet etching method; 7) An indium gallium oxide channel layer is grown on the ferroelectric layer using atomic layer deposition (ALD); an oxygen-deficient environment is created in the reaction chamber, resulting in a growing indium gallium oxide channel layer with more oxygen vacancy defects. 8) The pattern of the indium gallium oxide channel region is defined by ultraviolet lithography, and the indium gallium oxide material in the non-channel region is removed by etching with diluted dilute hydrochloric acid, thereby realizing the deposition of a hafnium zirconium ferroelectric layer and an indium gallium oxide channel layer on the inner wall of the vertical trench. 9) Define the source and drain metal pattern regions by electron beam lithography, then deposit the source and drain metal materials on the wafer sample by vapor deposition or physical vapor deposition (PVD), and then remove the metal materials in the non-pattern regions by lift-off technology. Source and drain metal electrodes are formed on both sides of the indium gallium oxide channel layer, and the channel region is between the source and drain metal electrodes. 10) Define the pattern of word line contact holes layer by layer by ultraviolet lithography, use photoresist as a barrier layer, and use dry etching and wet etching methods to prepare word line contact holes on different gate metal electrode material layers in the word line stack. The bottom of the word line contact holes is in contact with the surface of the gate metal electrode material.

2. The method for fabricating a three-dimensional stacked ferroelectric field-effect transistor as described in claim 1, characterized in that, The vertical groove has a circular or rectangular shape when viewed from above.

3. The method for fabricating a three-dimensional stacked ferroelectric field-effect transistor as described in claim 1, characterized in that, The thickness of the hafnium zirconium ferroelectric layer is 5~8 nm.

4. The method for fabricating a three-dimensional stacked ferroelectric field-effect transistor as described in claim 1, characterized in that, The thickness of the indium gallium oxide channel layer is 3~5nm.

5. The method for fabricating a three-dimensional stacked ferroelectric field-effect transistor as described in claim 1, characterized in that, In step 6), the wafer sample is immersed in a liquid with a volume ratio of ammonia, hydrogen peroxide and water of 1:1:5, and then the titanium nitride sacrificial layer is removed by wet etching.

6. The method for fabricating a three-dimensional stacked ferroelectric field-effect transistor as described in claim 1, characterized in that, In step 7), when growing the indium gallium oxide channel layer, indium cyclopentadiene, triethyl gallium, and ozone are used as precursors for indium, gallium, and oxygen, respectively.

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