A method for repairing the BOX interface to reduce high-temperature leakage current in PD-SOI MOS devices

Abstract

This invention discloses a BOX interface repair method to reduce high-temperature leakage current in PD-SOI MOS devices. After all high-temperature processes of the PD-SOI MOS device are completed, this invention repairs the interface between the buried oxide layer and the substrate silicon from the back side. The repair process includes back-side laser annealing and / or back-side hydrogen annealing to eliminate or reduce defects, stress damage, and impurity accumulation at this interface generated during the high-temperature processes. Since defects and stress at this interface are the main sources of defects in the neutral region at the bottom of the top silicon layer, repairing this interface can fundamentally block the propagation of defects to the neutral region, improve the minority carrier lifetime in the neutral region, and thus suppress the reverse-biased diffusion leakage current of the PN junction at high temperatures. This invention does not damage the active region and is compatible with standard CMOS processes. Therefore, this invention is applicable to the high-temperature environments of PD-SOI processes in aerospace, automotive electronics, and oil drilling.

Description

Technical Field

[0001] This invention relates to the field of high-temperature semiconductor device technology, and in particular to a BOX interface repair method for reducing high-temperature leakage current in PD-SOI MOS devices. Background Technology

[0002] In long-channel PD-SOI MOS devices, the main component of high-temperature leakage current is the neutral region diffusion current: minority carriers generated by heat in the neutral region at the bottom of the MOS device well (near the top surface of the BOX) diffuse to the depletion region boundary and are swept across the depletion region by an electric field, forming leakage current. The concentration distribution of minority carriers from the generation location to the depletion region boundary depends on the length of the minority carrier lifetime.

[0003] When the minority carrier lifetime is short, minority carriers recombine after diffusing only a short distance within the neutral region. Only minority carriers near the depletion region boundary can reach the depletion region boundary, resulting in a steep concentration gradient between the depth of the neutral region and the depletion region boundary, generating a strong diffusion driving force. Therefore, while simply shortening the minority carrier lifetime can eliminate some minority carriers, it also exacerbates the steepness of the concentration gradient. The two factors compete with each other, limiting the effectiveness of leakage current suppression.

[0004] When the minority carrier lifetime is long enough, minority carriers can diffuse deep into the neutral region all the way to the depletion region boundary without recombination. This makes the minority carrier concentration distribution in the entire neutral region tend to be uniform, and the diffusion driving force naturally weakens. When the concentration gradient approaches zero, even if a large number of minority carriers are generated in the neutral region, they cannot form effective diffusion due to the lack of concentration difference.

[0005] Therefore, improving the minority carrier lifetime in the neutral region is a fundamental and efficient approach to reducing high-temperature leakage current in PD-SOI MOS devices. Its advantages are twofold: firstly, a longer lifetime results in a more even distribution of minority carrier concentration in the neutral region, eliminating the driving force for diffusion and fundamentally weakening the source of leakage current; secondly, this method does not introduce any additional impurities or defects into the device, avoiding reliability risks caused by lattice damage or metal contamination.

[0006] However, in conventional PD-SOI processes, the minority carrier lifetime in the neutral region is often far lower than its intrinsic value. One of the fundamental reasons for this phenomenon is the various stress states and defects present at the interface between the BOX and the back substrate (handle). These stresses and defects directly affect defect formation and minority carrier lifetime in the upper neutral region through mechanical coupling and impurity diffusion channels in the BOX layer. For example, the thermal expansion coefficients of the BOX silicon oxide and the back substrate silicon are mismatched, resulting in significant thermal stress at the BOX-back substrate interface during high-temperature processes. This stress is transmitted through the BOX layer to the bottom of the top silicon layer, inducing dislocations and defects. High temperatures provide diffusion kinetic energy for metallic impurities, causing them to accumulate at low-energy sites such as the BOX interface, forming impurity deposits. In addition to the aforementioned thermal stress and metallic impurities, the BOX / handle interface also exhibits various intrinsic and process-induced defects. For example, silicon and silicon dioxide have different lattice constants, resulting in a large number of dangling bonds and interface states at the interface; bonding processes leave residual microbubbles or voids at the interface; and the BOX layer itself may also have structural defects such as pinholes. The above-mentioned defects make the BOX / handle interface a highly reactive defect source, continuously supplying recombination centers to the neutral region of the top silicon layer. This makes it difficult for minority carriers to maintain a long-lived state even without artificially introduced defects.

[0007] Therefore, if this defect supply channel can be cut off and the negative impact of the BOX / handle interface on the neutral region can be eliminated, the minority carriers in the neutral region can be restored to their intrinsic high lifetime state, thereby achieving autonomous suppression of high-temperature leakage current in PD-SOI MOS devices.

[0008] Based on the above principle analysis, this invention proposes to repair the interface between the BOX and the back substrate to eliminate the continuous degradation effect of defect sources on the minority carrier lifetime in the neutral region, thereby effectively reducing the high-temperature leakage current of PD-SOI MOS devices. Summary of the Invention

[0009] The purpose of this invention is to provide a method for repairing the BOX interface to reduce high-temperature leakage current in PD-SOI MOS devices, thereby solving the problems in the background art.

[0010] To address the aforementioned technical problems, this invention provides a method for repairing the BOX interface to reduce high-temperature leakage current in PD-SOI MOS devices, comprising: Provides a PD-SOI substrate consisting of a silicon substrate, a buried oxide layer, and a top silicon layer; The top silicon layer is etched and HDP filling is performed to form shallow trench isolation, and well implantation is performed in the active region. A gate oxide layer is grown on the top silicon surface, polysilicon is deposited on the gate oxide layer, and the gate pattern is formed by photolithography and etching. Using the gate as a mask, drain and source regions are implanted; a depletion region is formed between the drain and the well regions, and a depletion region is formed between the source and the well regions. The wafer is flipped so that the silicon substrate is facing up, and the silicon substrate is annealed. Localized heating repair is performed at the junction of the buried oxide layer and the back substrate. The device is fabricated using standard back-end processes to form metal silicides, contact holes, and metal interconnect layers.

[0011] In one embodiment, the annealing of the silicon substrate includes laser annealing and / or hydrogen annealing.

[0012] In one embodiment, the laser annealing includes using a pulsed laser to scan and irradiate the back side of a silicon substrate. The laser wavelength penetrates the silicon substrate, and the energy is mainly deposited near the interface between the buried oxide layer and the back substrate.

[0013] In one embodiment, the hydrogen annealing includes placing the wafer in a hydrogen atmosphere annealing furnace and performing hydrogen annealing from the back side of the substrate silicon. The annealing temperature is controlled so that hydrogen atoms penetrate the substrate silicon to reach the junction of the buried oxide layer and the back substrate, combine with dangling bonds, passivate interface defects, and reduce interface state density.

[0014] In one embodiment, the wavelength of the pulsed laser is 200nm~550nm.

[0015] The present invention provides a BOX interface repair method for reducing high-temperature leakage current in PD-SOI MOS devices, which has the following advantages: 1. Address the problem at its source. Target the root cause of damage to the neutral zone in high-temperature processes—defects and stress at the BOX / handle interface—rather than attempting remedies within the neutral zone itself.

[0016] 2. Selective action region, no damage to active region. All repair processes are performed from the back side. Laser energy and hydrogen atoms do not penetrate the BOX layer and will not reach the top silicon layer. It has no effect on the channel region, source / drain region and gate oxide layer of the MOS device and does not sacrifice the on-state characteristics of the device.

[0017] 3. The process steps are designed reasonably. Repair is carried out after all high-temperature processes are completed to avoid the repair effect being destroyed by subsequent high-temperature processes, and at the same time, all accumulated damage is repaired.

[0018] 4. Good process compatibility. Both back-side laser annealing and back-side hydrogen annealing are mature processes in semiconductor manufacturing, requiring no development of new equipment. Attached Figure Description

[0019] Figure 1 This is a schematic cross-sectional view of a PD-SOI substrate.

[0020] Figure 2 This is a cross-sectional schematic diagram of the completed PD-SOI MOS front-end process.

[0021] Figure 3 This is a schematic diagram showing the defects and stresses generated at the BOX / handle interface of a conventional PD-SOI MOS device during high-temperature processing.

[0022] Figure 4 yes Figure 3 The diagram shows the reverse-biased leakage current of the PN junction in the off-state of a conventional PD-SOI MOS device.

[0023] Figure 5 This is a schematic diagram showing the wafer being flipped so that the back substrate faces upwards after all the high-temperature process steps at the front end are completed.

[0024] Figure 6 From Figure 5 A schematic diagram showing the repair treatment of the interface between the buried oxide layer and the back substrate on the back side of the back substrate.

[0025] Figure 7 This is a schematic diagram of the defects and stress at the BOX / handle interface of the PD-SOI MOS device after repair treatment.

[0026] Figure 8 This is a schematic diagram of the reverse-biased leakage current of the off-state PN junction of a PD-SOI MOS device after repair.

[0027] Figure 9 This is a process step to reduce high-temperature leakage current in PD-SOI MOS devices through BOX / handle interface repair treatment. Detailed Implementation

[0028] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for repairing the BOX interface to reduce high-temperature leakage current in PD-SOI MOS devices according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Example 1

[0029] This embodiment provides a method for repairing the BOX / handle interface using back-side laser annealing to reduce high-temperature leakage current in PD-SOI MOS devices. The process is as follows: Figure 9 As shown, it includes the following steps: Step 1: Provide a PD-SOI substrate like Figure 1As shown, a PD-SOI substrate is provided, with a silicon backing (handle) and, from bottom to top, the substrate consists of: a silicon substrate 1, a buried oxide layer (BOX) 2, and a top silicon layer 4.

[0030] Step 2: Complete the PD-SOI MOS front-end process The top silicon layer 4 is etched and HDP filling is performed to form shallow trench isolation (STI) 3; Well injection is performed in the active region (NMOS is P-well; PMOS is N-well); A gate oxide layer 5 is grown on the surface of the top silicon layer 4, and polysilicon 6 is deposited on the gate oxide layer 5. The gate pattern is formed by photolithography and etching. Using the gate as a mask, drain region 7 and source region 8 are implanted. Depletion region 9 is formed between drain region 7 and well region, and depletion region 10 is formed between source region 8 and well region. Thermal annealing is performed to activate the implanted impurities.

[0031] The completed PD-SOI MOS device structure is as follows: Figure 2 As shown.

[0032] At this point, all high-temperature processes at the front end have been completed, and these processes have generated thermal stress damage and defects at the BOX / handle interface. Without additional treatment, these defects and stress at the BOX / handle interface will supply recombination centers to the neutral region of the top silicon layer, reducing the minority carrier lifetime in the neutral region. Figure 3 As shown, Figure 3 The arrows indicate that defects and stress at the BOX / handle interface supply recombination centers to the neutral region of the top silicon layer, reducing the minority carrier lifetime of the neutral region.

[0033] Because the minority carrier lifetime in the neutral region is reduced due to the influence of the BOX / handle interface, the reverse bias leakage current is relatively large. Figure 4 As shown.

[0034] Step 3: Backside laser annealing like Figure 5 As shown, the wafer is flipped so that silicon substrate 1 faces upward; like Figure 6 As shown, a pulsed laser of a certain wavelength is used to scan and irradiate the silicon substrate 1. The laser wavelength penetrates the silicon substrate 1, and the energy is mainly deposited near the BOX / handle interface.

[0035] This localized heating effect can repair defects near the interface, release residual thermal stress, and because the heating time is extremely short, the heat will not diffuse to the top silicon active region.

[0036] Step 4: Complete the downstream process Using standard back-end processes, metal silicides, contact holes, and metal interconnect layers are formed to complete device fabrication, which will not be illustrated here.

[0037] The high-temperature processes involved in the manufacturing of PD-SOI MOS devices can cause accumulated stress damage and defects at the BOX / handle interface. These defects, through the mechanical coupling of the BOX layer, induce recombination centers in the neutral region at the bottom of the top silicon layer, reducing minority carrier lifetime. At high temperatures, the reduced minority carrier lifetime leads to an increase in diffusion leakage current.

[0038] The PD-SOI MOS device fabricated through the above steps, with back-side laser annealing performing localized heating repair of the BOX / handle interface from the substrate side, eliminates defects and stress at the interface and cuts off the source of defect propagation into the neutral region. Figure 7 As shown, with Figure 3 In comparison, defects and stress are significantly reduced. Because laser heating is localized and the heating time is extremely short, it has no thermal impact on the active region. The minority carrier lifetime in the repaired neutral region recovers to near the material's intrinsic value, and high-temperature diffusion leakage is significantly suppressed. Figure 8 As shown, because the BOX / handle interface repair treatment reduces the negative impact of BOX / handle interface defects on the neutral region, it allows minority carriers in the neutral region to recover their intrinsic high lifetime state. Therefore, it is comparable to... Figure 4 In comparison, reverse bias leakage current is significantly reduced. Example 2

[0039] The difference between this embodiment 2 and embodiment 1 is that step 3 uses back-side hydrogen annealing instead of back-side laser annealing.

[0040] Specifically, after all high-temperature processes are completed, the wafer is placed in a hydrogen atmosphere annealing furnace and hydrogen annealed from the back side of the substrate.

[0041] By controlling the annealing temperature, hydrogen atoms can penetrate the substrate and reach the BOX / handle interface to combine with dangling bonds, passivating interface defects and reducing the interface state density. The annealing temperature is also controlled to prevent the introduction of new thermal stress or defects and to avoid affecting the completed doping. Example 3

[0042] This embodiment 3 uses a combination of back laser annealing and back hydrogen annealing.

[0043] In step 3, back-side laser annealing is first performed to repair lattice defects at the interface and release stress; then back-side hydrogen annealing is performed to passivate the remaining interface dangling bonds.

[0044] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for repairing the BOX interface to reduce high-temperature leakage current in PD-SOI MOS devices, characterized in that, include: Provides a PD-SOI substrate consisting of a silicon substrate, a buried oxide layer, and a top silicon layer; The top silicon layer is etched and HDP filling is performed to form shallow trench isolation, and well implantation is performed in the active region. A gate oxide layer is grown on the top silicon surface, polysilicon is deposited on the gate oxide layer, and the gate pattern is formed by photolithography and etching. Using the gate as a mask, drain and source regions are implanted; a depletion region is formed between the drain and the well regions, and a depletion region is formed between the source and the well regions. The wafer is flipped so that the silicon substrate is facing up, and the silicon substrate is annealed. Localized heating repair is performed at the junction of the buried oxide layer and the back substrate. The device is fabricated using standard back-end processes to form metal silicides, contact holes, and metal interconnect layers.

2. The BOX interface repair method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The annealing of the silicon substrate includes laser annealing and / or hydrogen annealing.

3. The BOX interface repair method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 2, characterized in that, The laser annealing process involves using a pulsed laser to scan and irradiate the back side of the silicon substrate. The laser wavelength penetrates the silicon substrate, and the energy is mainly deposited near the interface between the buried oxide layer and the back substrate.

4. The BOX interface repair method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 2, characterized in that, The hydrogen annealing process involves placing the wafer in a hydrogen atmosphere annealing furnace and performing hydrogen annealing from the back side of the substrate silicon. The annealing temperature is controlled to allow hydrogen atoms to penetrate the substrate silicon and reach the interface between the buried oxide layer and the back substrate, where they combine with dangling bonds, passivate interface defects, and reduce the interface state density.

5. The BOX interface repair method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 3, characterized in that, The wavelength of the pulsed laser is 200nm~550nm.

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