LDMOS device and method of manufacturing the same
Patent Information
- Application Number
- CN202611433246.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-16
- Publication Date
- 2026-10-20
Smart Images
Figure FT_1 
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to an LDMOS device and its manufacturing method. Background Technology
[0002] LDMOS (Lateral Double-diffused Metal-Oxide-Semiconductor Transistor) devices are widely used in power semiconductor integrated circuits due to their advantages such as high voltage withstand capability, high integration density, strong driving capability, and low power loss.
[0003] Breakdown voltage and on-resistance are two key performance parameters of LDMOS. Typically, breakdown voltage and on-resistance are contradictory parameters. For example, to ensure a high breakdown voltage, the doping concentration in the drift region or channel formation region (body region) needs to be reduced, or the spacing between them needs to be increased; these methods will increase the on-resistance. Furthermore, in some related technologies, it is possible to simultaneously improve breakdown voltage and on-resistance through complex and cumbersome processes, but this is not conducive to reducing costs and improving yield. Summary of the Invention
[0004] In view of this, this application aims to provide an LDMOS device and a method for manufacturing the same, which can easily and cost-effectively improve both breakdown voltage and on-resistance.
[0005] Based on one aspect of this application, the method for manufacturing an LDMOS device provided in this application includes: A substrate is provided, the substrate including a bulk region and a reserved area for the drift region; Multiple spaced mandrel structures are formed on the reserved area of the body region and the drift region. Each mandrel structure includes a mandrel and a covering layer that covers the outer wall of the mandrel. A gate dielectric layer is formed to cover the surface of the substrate exposed by the mandrel structure and the sidewalls of the cladding layer, and a gate conductive layer is formed to cover the gate dielectric layer and fill the spaces between adjacent mandrel structures; The cladding layer and the core exposed by the gate conductive layer are removed, and the remaining cladding layer is a sidewall structure. The gate dielectric layer, the gate conductive layer and the corresponding sidewall structure located on the body region serve as the gate structure, and the gate dielectric layer, the gate conductive layer and the corresponding sidewall structure located on the reserved area of the drift region serve as the field plate structure. In the gate structure and the field plate structure, the width of the gate conductive layer increases in the direction away from the substrate surface, and the sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, while the sidewalls of the two corresponding sidewall structures that are far from each other are steep. Using the field plate structure as a mask, ion implantation is performed on the exposed drift region reserved area to form a drift region, and the doping concentration of the drift region between the field plate structures is greater than the doping concentration of the drift region under the field plate structure.
[0006] In some embodiments, the step of forming the mandrel structure includes: A sacrificial material layer and a first sidewall material layer are sequentially formed on the substrate; A first patterning is performed on the sacrificial material layer and the first sidewall material layer using a first photomask to form a plurality of spaced mandrels, wherein the remaining sacrificial material layers are formed on the surface of the mandrels and the first sidewall material layer is covered on the surface of the mandrels. A second sidewall material layer is formed to conformally cover the surface of the substrate, the mandrel, and the outer wall of the first sidewall material layer; An anisotropic etching process is performed to etch the second sidewall material layer to expose the surface of the substrate, and the first sidewall material layer and the second sidewall material layer covering the outer wall of the mandrel serve as the cladding layer.
[0007] In some embodiments, the step of forming the gate dielectric layer includes: A first oxide layer is formed on the exposed surface of the substrate using a thermal oxidation process; A second oxide layer is formed by a deposition process to conformally cover the surface of the first oxide layer and the outer wall of the coating layer, wherein the first oxide layer and the second oxide layer serve as the gate dielectric layer.
[0008] In some embodiments, the step of forming the gate conductive layer includes: A conductive material is formed to conformally cover the surface of the gate dielectric layer and fill the spaces between adjacent core structures; Using the surface of the coating layer or the gate dielectric layer as a stop layer, a polishing process is performed, retaining the conductive material between adjacent mandrel structures as the gate conductive layer.
[0009] In some embodiments, the steps of forming the gate structure and the field plate structure include: The first photomask is used to perform a second patterning on the cladding layer and the core, and the cladding layer and the core exposed outside the gate conductive layer are etched away to expose a portion of the surface of the substrate. The second patterning and the pattern of the first patterning are complementary in a plane.
[0010] In some embodiments, the steps of forming the gate structure and the field plate structure include: Using the gate conductive layer as a mask, an anisotropic dry etching process is performed to remove the cladding layer and the mandrel exposed outside the gate conductive layer, thereby exposing part of the surface of the substrate. In the anisotropic dry etching process, the etching selectivity ratio of the cladding layer and the mandrel relative to the gate conductive layer is greater than or equal to 10:1.
[0011] In some embodiments, the step of forming the drift region includes: A patterned photoresist layer is formed on the substrate, the patterned photoresist layer having openings to expose the reserved area of the drift region; Using the patterned photoresist layer and the field plate structure as a mask, ion implantation is performed on the exposed drift region reserved area to form the drift region in the drift region reserved area. The drift region has a first concentration in a first region between the field plate structures and a second concentration in a second region below the field plate structures. The first concentration is greater than the second concentration, and the first region and the second region are alternately distributed in the drift region.
[0012] In some embodiments, the sidewalls of the field plate structure are steep, and inclined ion implantation is employed. During the inclined ion implantation process, the substrate is rotated to change the doping concentration gradient between adjacent first and second regions.
[0013] In some embodiments, after forming the drift region, the method further includes: A patterned photoresist layer is formed on the substrate, the patterned photoresist layer having at least two openings that expose a portion of the surface of the body region and a portion of the surface of the drift region, respectively; Using the patterned photoresist layer, source / drain ion implantation is performed to form source / drain regions in the substrate.
[0014] Based on another aspect of this application, an LDMOS device is also provided, obtained using the manufacturing method described above, the LDMOS device comprising: A substrate having a bulk region and a drift region; The body region is provided with a gate structure; At least one field plate structure is provided on the drift zone; Each of the gate structures and the field plate structures includes a stacked gate dielectric layer and a gate conductive layer, and a sidewall structure located on the sidewall of the gate dielectric layer and the gate conductive layer. The width of the gate conductive layer increases in the direction away from the substrate surface. The sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, and the sidewalls of the two corresponding sidewall structures that are far apart from each other are steep. The doping concentration of the drift region between the field plate structures is greater than the doping concentration of the drift region under the field plate structure.
[0015] In summary, the unexpected effects of this application are as follows: By using a mandrel / sidewall process combined with complementary patterning or self-aligned etching to form an inverted trapezoidal gate conductive layer (with the width increasing in the direction away from the substrate surface), the high electric field region is migrated from the weak gate dielectric region near the substrate surface to the top of the gate conductive layer away from the substrate surface. At the same time, the arc-shaped sidewall structure increases the equivalent dielectric thickness below the high electric field concentration region, thereby reducing the risk of dielectric breakdown and hot carrier injection. The same mandrel structure is used to simultaneously define the positions of the gate structure and the field plate structure, reducing overlay errors and ensuring the relative positional accuracy between the gate structure and the field plate structure. Furthermore, the field plate structure is used as a hard mask for ion implantation, and high and low doping profiles with alternating distribution of the first and second regions are formed in the drift region by tilted rotation implantation. This periodic doping modulation not only optimizes the surface electric field distribution but also effectively modulates the bulk electric field, so that while shortening the drift region length and reducing the on-resistance, a high breakdown voltage can still be maintained. The steep outer walls further enhance the geometric controllability of the shading region, allowing the doping concentration and profile to be accurately predicted during the design phase through TCAD simulation, thereby enabling precise optimization of the electric field distribution. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a stacked structure formed on a substrate in the prior art.
[0017] Figure 2 This is a schematic diagram of forming sidewalls on the sidewalls of a stacked structure in the prior art.
[0018] Figure 3 This is a schematic diagram of forming source / drain doped regions in a substrate in the prior art.
[0019] Figure 4 A flowchart illustrating a method for manufacturing an LDMOS device according to an embodiment of this application.
[0020] Figure 5 This is a schematic diagram of a substrate provided in one embodiment of this application.
[0021] Figure 6 This is a schematic diagram illustrating the formation of a sacrificial material layer and a first sidewall material layer on a substrate and the execution of a pattern, according to an embodiment of this application.
[0022] Figure 7 This is a schematic diagram of a second sidewall material layer formed on a substrate, provided as an embodiment of this application.
[0023] Figure 8This is a schematic diagram illustrating an anisotropic etching process for forming a mandrel structure, provided as an embodiment of this application.
[0024] Figure 9 This is a schematic diagram of a gate dielectric layer formed on a substrate according to an embodiment of this application.
[0025] Figure 10 This is a schematic diagram of forming a conductive material on a substrate according to an embodiment of this application.
[0026] Figure 11 This is a schematic diagram illustrating a grinding process performed with the surface of the gate dielectric layer as a stop layer, according to an embodiment of this application.
[0027] Figure 12 This is a schematic diagram of the formation of a second mask layer provided in an embodiment of this application.
[0028] Figure 13 This is a schematic diagram of the etched coating layer and the core shaft forming the gate structure and field plate structure according to an embodiment of this application.
[0029] Figure 14 This is a schematic diagram illustrating the formation of a first patterned photoresist layer on a substrate and the formation of a drift region by ion implantation, as provided in an embodiment of this application.
[0030] Figure 15 This is a schematic diagram of a source / drain region formed in a substrate according to an embodiment of this application.
[0031] Figure 16 This is a schematic diagram of an LDMOS device provided in an embodiment of this application.
[0032] exist Figures 1-3 In the middle: 10-substrate; 11-body doped region; 12-drift doped region; 13-gate dielectric layer; 14-gate conductive layer; 15-stacked structure; 16-sidewall; 17-gate; 18-source / drain doped region.
[0033] exist Figures 5-16 In the middle: 100-substrate; 110-body region; 101-drift region reserved area; 120-drift region; 121-first region; 123-second region; 210-core; 221-first sidewall material layer; 223-second sidewall material layer; 225-sidewall structure; 220-cladding layer; 230-core structure; 240-gate stack; 241-gate dielectric layer; 243-conductive material; 245-gate conductive layer; 247-second mask layer; 200-gate structure; 300-field plate structure; 401-first patterned photoresist layer; 410-source / drain region. Detailed Implementation
[0034] Figures 1-3This is a schematic diagram of the manufacturing of LDMOS devices in the prior art.
[0035] Figure 1 This is a schematic diagram of a stacked structure formed on a substrate in the prior art. For example... Figure 1 As shown, the substrate 10 has a body doped region 11 and a drift doped region 12. The body doped region 11 and the drift doped region 12 are each doped (e.g., ion implantation) and activated by annealing. A gate dielectric layer 13 and a gate conductive layer 14 are sequentially formed on the substrate 10. The gate conductive layer 14 and the gate dielectric layer 13 are patterned. A portion of the gate dielectric layer 13 and the gate conductive layer 14 located on the body doped region 11 are retained as a stacked structure 15. In the stacked structure 15, the gate conductive layer 14 is rectangular and the gate dielectric layer 13 is a thin planar layer.
[0036] Figure 2 This is a schematic diagram of forming sidewalls on the sidewalls of a stacked structure in the prior art. (Example) Figure 2 As shown, a sidewall 16 is formed on the sidewall of the stacked structure 15, and the stacked structure 15 and the sidewall 16 serve as the gate 17. The sidewall 16 facing outward (away from the gate conductive layer 14) is arc-shaped, and the sidewall 16 facing inward (in contact with the sidewall of the gate conductive layer 14) is steep.
[0037] Figure 3 This is a schematic diagram illustrating the formation of source / drain doped regions in a substrate using existing technology. (Example) Figure 3 As shown, a patterned photoresist layer is formed on the substrate 10. The patterned photoresist layer has openings that expose the surfaces of a portion of the body doped region 11 and a portion of the drift doped region 12. Source and drain ion implantation is performed using the patterned photoresist layer to form source and drain doped regions 18 in the body doped region 11 and the drift doped region 12.
[0038] In view of this, embodiments of this application provide an LDMOS device and a method for manufacturing the same. The manufacturing method includes providing a substrate, the substrate including a body region and a reserved area for a drift region; forming a plurality of spaced-apart spindle structures on the body region and the reserved area for the drift region, each spindle structure including a spindle and a cladding layer covering the outer wall of the spindle; forming a gate dielectric layer covering the surface of the substrate exposed by the spindle structure and the sidewalls of the cladding layer, and forming a gate conductive layer covering the gate dielectric layer and filling the spaces between adjacent spindle structures; removing the cladding layer and spindle exposed by the gate conductive layer, the remaining cladding layer being a sidewall structure, and the gate dielectric layer located on the body region. The gate conductive layer and its corresponding sidewall structure serve as the gate structure, while the gate dielectric layer, gate conductive layer, and their corresponding sidewall structure located on the reserved area of the drift region serve as the field plate structure. In the gate structure and the field plate structure, the width of the gate conductive layer increases in the direction away from the substrate surface. The sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, while the sidewalls of the two corresponding sidewall structures that are far from each other are steep. Using the field plate structure as a mask, ion implantation is performed on the exposed reserved area of the drift region to form the drift region, and the doping concentration of the drift region between the field plate structures is greater than that of the drift region under the field plate structure. An unexpected effect of this application is that, through a mandrel / sidewall process combined with complementary patterning or self-aligned etching to form an inverted trapezoidal gate conductive layer (with the width increasing in the direction away from the substrate surface), the high electric field region is migrated from the weak gate dielectric region near the substrate surface to the top of the gate conductive layer away from the substrate surface. At the same time, the arc-shaped sidewall structure increases the equivalent dielectric thickness below the high electric field concentration region, thereby reducing the risk of dielectric breakdown and hot carrier injection. The same mandrel structure is used to simultaneously define the positions of the gate structure and the field plate structure, reducing overlay errors and ensuring the relative positional accuracy between the gate structure and the field plate structure. Furthermore, the field plate structure is used as a hard mask for ion implantation, and high and low doping profiles with alternating distribution of the first and second regions are formed in the drift region by tilted rotation implantation. This periodic doping modulation not only optimizes the surface electric field distribution but also effectively modulates the bulk electric field, so that while shortening the drift region length and reducing the on-resistance, a high breakdown voltage can still be maintained. The steep outer walls further enhance the geometric controllability of the shading region, allowing the doping concentration and profile to be accurately predicted during the design phase through TCAD simulation, thereby enabling precise optimization of the electric field distribution.
[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0040] One embodiment of this application provides a method for manufacturing an LDMOS device. Figure 4 This is a flowchart illustrating a method for manufacturing an LDMOS device according to an embodiment of this application. Figure 4 As shown, an embodiment of this application provides a method for manufacturing an LDMOS device, including: S100: Provide a substrate, the substrate including a bulk region and a reserved area for the drift region; S200: A plurality of spaced-apart mandrel structures are formed on the reserved area of the body region and the drift region, the mandrel structure including a mandrel and a covering layer covering the outer wall of the mandrel; S300: Forming a gate dielectric layer covering the surface of the substrate exposed by the mandrel structure and the sidewalls of the cladding layer, and forming a gate conductive layer covering the gate dielectric layer and filling the spaces between adjacent mandrel structures; S400: Remove the cladding layer and the core exposed by the gate conductive layer. The remaining cladding layer is a sidewall structure. The gate dielectric layer, the gate conductive layer and the corresponding sidewall structure located on the body region serve as the gate structure. The gate dielectric layer, the gate conductive layer and the corresponding sidewall structure located on the reserved area of the drift region serve as the field plate structure. In the gate structure and the field plate structure, the width of the gate conductive layer increases in the direction away from the substrate surface. The sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, and the sidewalls of the two corresponding sidewall structures that are far apart from each other are steep. S500: Using the field plate structure as a mask, ion implantation is performed on the exposed drift region reserved area to form a drift region, and the doping concentration of the drift region between the field plate structures is greater than the doping concentration of the drift region under the field plate structure.
[0041] Figures 5-15 This is a schematic diagram of the corresponding steps in the manufacturing method of an LDMOS device provided in an embodiment of this application. Next, we will discuss... Figures 5-15 The manufacturing method of the LDMOS device provided in this application will be described in detail.
[0042] First, please refer to Figure 5 Step S100 is executed, providing a substrate 100, which includes a body region 110 and a drift region reserved region 101.
[0043] The substrate 100 can be a substrate suitable for forming power devices, and its material can be, for example, silicon, silicon carbide, gallium nitride, etc. The substrate 100 has a body region 110 and a drift region reserved region 101. The drift region reserved region 101 is the region to be formed into a drift region later. At this time, the doping state of the drift region reserved region 101 is the doping state of the substrate 100.
[0044] In some examples, the conductivity type (channel conductivity type) of the LDMOS device to be formed can be N-type, the conductivity type of the body region 110 can be P-type, and the conductivity type of the substrate 100 and the drift region reserved region 101 can also be P-type, but the doping concentration of the body region 110 is greater than that of the substrate 100.
[0045] In some examples, the surface of substrate 100 is a P-type epitaxial layer, and both the bulk region 110 and the drift region reserved region 101 are located in the P-type epitaxial layer.
[0046] In some examples, the substrate 100 has a P-type doped region, and both the body region 110 and the drift region reserved region 101 are located in the P-type doped region.
[0047] Next, please refer to Figures 6-8 In step S200, a plurality of spaced mandrel structures 230 are formed on the body region 110 and the drift region reserved area 101. The mandrel structure 230 includes a mandrel 210 and a covering layer 220 covering the outer wall of the mandrel 210.
[0048] Specifically, such as Figure 6 As shown, a sacrificial material layer and a first sidewall material layer 221 are sequentially formed on the substrate 100. A first photomask is used to form a first mask layer on the substrate 100. A first patterning is performed on the sacrificial material layer and the first sidewall material layer 221 to form a plurality of spaced mandrels 210. The mandrels 210 are the remaining sacrificial material layers, and the remaining first sidewall material layers 221 are covered on the mandrels 210. The areas on the substrate 100 not covered by the mandrels 210 (exposed areas) can be areas corresponding to the gate structure and the field plate structure. For example, the area on the body region 110 not covered by the mandrels 210 is used to form the gate structure, and the area on the drift region reserved region 101 not covered by the mandrels 210 is used to form the field plate structure. That is, the mandrels 210 cover the surface of the substrate 100 outside the gate structure and the field plate structure. Furthermore, the thicknesses of the sacrificial material layer (core 210) and the first sidewall material layer 221 can be determined based on the thickness of the subsequent gate structure. For example, the sum of the thicknesses of the sacrificial material layer and the first sidewall material layer 221 can be the same as or similar to the thickness of the gate structure. The material of the sacrificial material layer is different from that of the first sidewall material layer 221 and the subsequent second sidewall material layer and gate conductive layer. By adjusting the etching process, a larger etching selectivity ratio of the sidewall material layer (including the first sidewall material layer and the second sidewall material layer) and the sacrificial material layer relative to the gate conductive layer 245 can be achieved when etching the aforementioned materials.
[0049] In some examples, the material of the sacrificial material layer may include silicon oxide, and the material of the first sidewall material layer 221 may include silicon nitride. The sacrificial material layer and the first sidewall material layer 221 may be formed sequentially using a vapor deposition process.
[0050] In some examples, the thickness of the first sidewall material layer 221 may be greater than the thickness of the sacrificial material layer to facilitate subsequent etching to form a sidewall with a smaller curvature.
[0051] like Figure 7 As shown, a second sidewall material layer 223 is formed to conformally cover the surface of the substrate 100, the mandrel 210, and the outer wall of the first sidewall material layer 221. The material of the second sidewall material layer 223 may be the same as or similar to that of the first sidewall material layer 221, and the thickness of the second sidewall material layer 223 may be less than the thickness of the first sidewall material layer 221. At this time, the sidewalls of the mandrel 210 are covered with the second sidewall material layer 223, and the second sidewall material layer 223 on the sidewalls of the mandrel 210 is steeply shaped. The first sidewall material layer 221 and the second sidewall material layer 223 are sequentially stacked on the surface of the mandrel 210.
[0052] like Figure 8 As shown, an anisotropic etching process is performed to etch the second sidewall material layer 223 to expose the surface of the substrate 100. The first sidewall material layer 221 and the second sidewall material layer 223 covering the outer wall of the mandrel 210 serve as a cladding layer 220, and the mandrel 210 and the cladding layer 220 serve as the mandrel structure 230. The anisotropic etching process can be an anisotropic dry etching process. After this etching process, it is feasible for the second sidewall material layer 223 of the first sidewall material layer 221 on the surface of the mandrel 210 to be completely removed or partially retained. At this time, the sidewall of the cladding layer 220 (the side away from the mandrel 210) is arc-shaped.
[0053] Next, please refer to Figures 9-11 In step S300, a gate dielectric layer 241 is formed to cover the surface of the substrate 100 exposed by the core structure 230 and the sidewall of the cladding layer 220, and a gate conductive layer 245 is formed to cover the gate dielectric layer 241 and fill the space between adjacent core structures 230.
[0054] like Figure 9 As shown, a gate dielectric layer 241 is formed to conformally cover the surface of the substrate 100 exposed by the mandrel structure 230 and the outer wall of the cladding layer 220. The gate dielectric layer 241 conformally covers the surface of the cladding layer 220 and the gap between adjacent mandrel structures 230, and forms a plurality of inverted trapezoidal grooves, the sidewalls of which are arc-shaped.
[0055] In some examples, a high-quality first oxide layer can be formed on the exposed substrate 100 surface using a thermal oxidation process. Then, a second oxide layer is formed using a deposition process (chemical vapor deposition) to conformally cover the surface of the first oxide layer and the outer wall of the cladding layer 220. The first oxide layer and the second oxide layer serve as the gate dielectric layer 241.
[0056] like Figure 10As shown, conductive material 243 conformally covers the surface of gate dielectric layer 241 and fills the grooves between adjacent core structures 230. In some examples, the conductive material may be made of polysilicon and may be formed using a deposition process.
[0057] like Figure 11 As shown, the surface of the gate dielectric layer 241 on the cladding layer 220 is used as the stop layer, and a polishing process is performed to retain the conductive material 243 between adjacent core structures 230 as the gate conductive layer 245, that is, the conductive material 243 retained in the groove serves as the gate conductive layer 245. The gate dielectric layer 241 and the gate conductive layer 245 thereon can be gate stacks 240. One gate stack 240 is located on the body region 110, and at least one gate stack 240 is located on the drift region reserved area 101. The gate stacks 240 can all be inverted trapezoidal in shape, that is, the width of the gate conductive layer 245 (gate stack 240) increases along the direction away from the substrate 100 (thickness direction).
[0058] In addition, in other examples, it is also feasible to perform the polishing process using the surface of the coating layer 220 as the stop layer.
[0059] Next, please refer to Figure 12 and Figure 13 In step S400, the cladding layer 220 and core 210 exposed by the gate conductive layer 245 are removed. The remaining cladding layer 220 is a sidewall structure 225. The gate dielectric layer 241, the gate conductive layer 245 and the corresponding sidewall structure 225 on the body region 110 serve as the gate structure 200. The gate dielectric layer 241, the gate conductive layer 245 and the corresponding sidewall structure 225 on the drift region reserved area 101 serve as the field plate structure 300. In the gate structure 200 and the field plate structure 300, the width of the gate conductive layer 245 increases in the direction away from the surface of the substrate 100. The sidewalls of the two corresponding sidewall structures 225 (located on both sides of the same gate conductive layer 245) that are close to each other are arc-shaped, and the sidewalls of the two corresponding sidewall structures 225 (located on both sides of the same gate conductive layer 245) that are far from each other are steep.
[0060] like Figure 12 As shown, a second mask layer 247 is formed on the substrate 100. The second mask layer 247 may be a patterned photoresist layer. The pattern of the second mask layer 247 is complementary to the pattern of the first mask layer in a plane, i.e., the second mask layer 247 covers the surface of the gate conductive layer 245 and exposes the area directly above the mandrel 210 (the surface of the gate dielectric layer 241). In some examples, the second mask layer 247 is formed by performing a photolithography process using a first photomask and a photoresist layer of the opposite type to that used when forming the first mask layer.
[0061] like Figure 13As shown, a second patterning is performed using a second mask layer 247, removing the cladding layer 220 and the core 210 exposed on the surface of the core 210, exposing part of the surface of the substrate 100, and retaining the gate conductive layer 245 and the gate dielectric layer 241 and cladding layer 220 below it. The remaining cladding layer 220 serves as a sidewall structure 225. The gate stack 240 located on the body region 110 and the sidewall structure 225 located on the sidewall of the gate stack 240 serve as a gate structure 200. The gate stack 240 located on the drift region reserved region 101 and the sidewall structure 225 located on the sidewall of the gate stack 240 serve as a field plate structure 300. In other words, the gate structure 200 and the field plate structure 300 formed by the second patterning are complementary to the aforementioned core in the plane, that is, complementary patterns are formed using a first photomask to simultaneously define the boundaries and contours of the gate structure 200 and the field plate structure 300.
[0062] Overall, the longitudinal cross-sectional shape of each gate structure 200 and each field plate structure 300 is rectangular. However, the gate conductive layer 245 is in the shape of an inverted trapezoid, and the sidewall of the inverted trapezoid is a concave arc shape. That is, the width of the gate conductive layer 245 increases along the thickness direction away from the substrate 100, and the rate of increase increases, making the sidewall of the gate conductive layer 245 a concave arc shape. The sidewall structure 225 is wider at the bottom and narrower at the top. The sidewall structure 225 includes a first sidewall facing inward (closer to the gate conductive layer 245) and a second sidewall facing outward (away from the gate conductive layer 245). The first sidewall is arc-shaped and matches the sidewall morphology (longitudinal cross-sectional shape) of the gate conductive layer 245. The second sidewall is steep (vertical). Compared to the rectangular or trapezoidal gate conductive layer 245 (where the electric field is concentrated at the bottom of the gate conductive layer 245), the gate conductive layer 245 in the gate structure 200 and field plate structure 300 of this application is inverted trapezoidal in shape, which allows the high electric field to be concentrated at the top of the gate conductive layer 245. Below this high electric field concentration region is a thicker dielectric layer (gate dielectric layer 241 and sidewall structure 225), which can prevent the high electric field from directly acting on the weakest dielectric layer region. This can significantly reduce the risk of dielectric layer breakdown and hot carrier injection, and improve device reliability.
[0063] It should be noted that in some other embodiments of this application, with Figure 12 and Figure 13The difference is that a second mask layer may not be formed. Instead, an anisotropic dry etching process is performed by utilizing the higher etching selectivity of the cladding layer 220 and the core 210 relative to the gate conductive layer 245 to remove the cladding layer 220 and the core 210 exposed on the surface of the core 210, exposing part of the surface of the substrate 100, and retaining the gate conductive layer 245 and the gate dielectric layer 241 and the cladding layer 220 below it. The remaining cladding layer 220 serves as a sidewall structure 225. The gate stack 240 located on the body region 110 and the sidewall structure 225 located on the sidewall of the gate stack 240 serve as a gate structure 200. The gate stack 240 located on the drift region reserved area 101 and the sidewall structure 225 located on the sidewall of the gate stack 240 serve as a field plate structure 300. Furthermore, in the aforementioned anisotropic dry etching process, the etching selectivity ratio of the cladding layer 220 and the mandrel 210 relative to the gate conductive layer 245 can be greater than or equal to 10:1, so that the exposed sidewalls of the sidewall structure 225 after etching are relatively steep. In other words, using the gate conductive layer 245 as a mask, the cladding layer 220 and the mandrel 210 above the mandrel 210 (not covered by the gate conductive layer 245) are sequentially etched away, i.e., a self-aligned etching process is used to form the gate structure 200 and the field plate structure 300.
[0064] Of course, it is understandable that, in cases like Figure 12 and Figure 13 In the example, the second patterning can also employ the above-mentioned anisotropic dry etching process with a high etching selectivity to ensure that the exposed sidewalls of the sidewall structure 225 after etching are relatively steep.
[0065] In some embodiments, the material of the mandrel 210 and the gate dielectric layer 241 may both include silicon oxide, and the material of the cladding layer 220 may include silicon nitride. The process gas of the above-mentioned anisotropic dry etching process may include fluorocarbon gas, oxidizing gas and inert gas. The fluorine radicals provided by the fluorocarbon gas can rapidly etch silicon nitride and silicon oxide, but basically do not etch polysilicon. During the etching process, the fluorocarbon gas also generates polymer to protect the gate conductive layer 245. The oxidizing gas is used to remove some of the polymer to balance the polymer generated during the etching process. The inert gas may be, for example, argon, to improve the directionality of the etching.
[0066] In a specific example, the cavity pressure can be 100~300mTorr, the power can be 300~500W, the fluorocarbon gas can include CHF3 and CF4, the proportion of CHF3 in the fluorocarbon gas can be 65%~75%, and during the etching process, the etching selectivity ratio of silicon oxide to polysilicon can be greater than or equal to 15:1, and the etching selectivity ratio of silicon nitride to polysilicon can be greater than or equal to 12:1.
[0067] In one specific example, the tilt angle of the sidewalls of the field plate structure 300 and the gate structure 200 exposed (on the side away from the gate conductive layer 245, the second sidewall) is 87~93°.
[0068] Next, please refer to Figures 14-15 In step S500, using the field plate structure 300 as a mask, ion implantation is performed on the exposed drift region reserved area 101 to form a drift region 120, and the doping concentration of the drift region 120 between the field plate structures 300 is greater than the doping concentration of the drift region 120 under the field plate structure 300.
[0069] like Figure 14 As shown, the second mask layer 247 is removed, and a first patterned photoresist layer 401 is formed on the substrate 100. The first patterned photoresist layer 401 has an opening to expose a drift region reserved area 101. Using the first patterned photoresist layer 401 and the field plate structure 300 as masks, ion implantation is performed on the exposed drift region reserved area 101 (the conductivity type of the implanted ions is opposite to that of the body region 110) to form a drift region 120 in the drift region reserved area 101. The first region 121 of the drift region 120 between the field plate structures 300 (including between the field plate structure 300 and the gate structure 200) has a first concentration, and the second region 123 of the drift region 120 below the field plate structure 300 has a second concentration. The first concentration is greater than the second concentration, and the first region 121 and the second region 123 are alternately distributed in the drift region 120. Therefore, the doping concentration in the drift region 120 is periodically distributed with alternating high and low concentrations along the direction away from the gate structure 200. This not only optimizes the surface electric field and improves the breakdown voltage, but also effectively modulates the bulk electric field, allowing for a shorter drift region 120, thereby increasing the breakdown voltage while reducing the on-resistance. Moreover, the capacitive coupling effect of the field plate structure 300 can induce an accumulation layer in the drift region 120 with the same conductivity type as the charge carriers in the drift region 120. For example, an electron accumulation layer is generated in the drift region 120 of an NLDMOS, thereby significantly reducing the effective resistance of the drift region 120 in the on-state.
[0070] In some examples, tilted ion implantation can be used, and the substrate 100 can be rotated during the tilted ion implantation process to ensure that ions can penetrate more fully into the area below the field plate structure 300. This rotating and tilted ion implantation enables multidimensional doping modulation. With each tilted implantation, a periodic concentration distribution is formed within the drift region reserved area 101. In the first region 121 between the field plate structures 300, a first concentration with a high doping concentration is formed due to direct ion implantation. In the second region 123 directly below the field plate structure 300, a second concentration with a low doping concentration is formed due to shading. The varying degrees of shading at and near the boundary between the first and second regions 121 and 123 due to the shading effect allow for a concentration gradient change from the first concentration to the second concentration between the first and second regions 121 and 123, which is beneficial for smoothing the electric field distribution.
[0071] Moreover, and more importantly, although the raised field plate structure 300 exhibits a shadow area (shadowing effect) during tilted ion implantation, in this application, the exposed sidewalls of the sidewall structure 225 are steep, allowing for precise control over the morphology, size, and position of the field plate structure 300, as well as the morphology, size, and position of the gaps between adjacent field plate structures 300. Utilizing this "precise" arrangement, the final doping concentration and doping profile can be accurately predicted during the design phase using TCAD (Technology Computer-Aided Design) simulations, thereby precisely optimizing the electric field distribution. In contrast, when using multiple photoresist patterns as masks for tilted ion implantation, the sidewall morphology of the photoresist patterns exhibits significant random fluctuations, such as different tilt angles or arc shapes with varying curvatures, making it difficult to accurately predict the final doping concentration and doping profile.
[0072] like Figure 15 As shown, the first patterned photoresist layer 401 is removed, and a second patterned photoresist layer is formed on the substrate 100. The second patterned photoresist layer has at least two openings that expose the surfaces of a portion of the body region 110 and a portion of the drift region 120, respectively. Source and drain ion implantation is performed using the second patterned photoresist layer to form source and drain regions 410 in the substrate 100.
[0073] Next, after removing the second patterned photoresist layer, a body contact region can be formed in the body region 110. The body contact region is located in the body region 110 and on the side of the source / drain region 410 away from the gate structure 200.
[0074] An embodiment of this application also provides an LDMOS device, which is obtained by the manufacturing method described above. Figure 16 This is a schematic diagram of an LDMOS device provided in an embodiment of this application.
[0075] like Figure 16 As shown, the LDMOS device provided in this embodiment includes a substrate 100, a body region 110, a drift region 120, a gate structure 200, and a field plate structure 300. The substrate 100 has a body region 110 and a drift region 120. A gate structure 200 is disposed on the body region 110, and at least one field plate structure 300 is disposed on the drift region 120. Each gate structure 200 and field plate structure 300 includes a stacked gate dielectric layer 241 and a gate conductive layer 245, and sidewall structures 225 located on the sidewalls of the gate dielectric layer 241 and the gate conductive layer 245. The width of the gate conductive layer 245 increases in the direction away from the surface of the substrate 100. The sidewalls of two corresponding sidewall structures 225 that are close to each other are arc-shaped, and the sidewalls of two corresponding sidewall structures 225 that are far apart from each other are steep. The doping concentration of the drift region 120 between the field plate structures 300 is greater than the doping concentration of the drift region 120 under the field plate structure 300.
[0076] In summary, this application provides an LDMOS device and a method for manufacturing the same. The manufacturing method includes providing a substrate, the substrate including a body region and a reserved drift region; forming a plurality of spaced-apart spindle structures on the body region and the reserved drift region, each spindle structure including a spindle and a cladding layer covering the outer wall of the spindle; forming a gate dielectric layer covering the surface of the substrate exposed by the spindle structure and the sidewalls of the cladding layer, and forming a gate conductive layer covering the gate dielectric layer and filling the spaces between adjacent spindle structures; removing the cladding layer and spindle exposed by the gate conductive layer, the remaining cladding layer being a sidewall structure, and the gate dielectric layer located on the body region. The gate conductive layer and its corresponding sidewall structure serve as the gate structure, while the gate dielectric layer, gate conductive layer, and their corresponding sidewall structure located on the reserved area of the drift region serve as the field plate structure. In the gate structure and the field plate structure, the width of the gate conductive layer increases in the direction away from the substrate surface. The sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, while the sidewalls of the two corresponding sidewall structures that are far from each other are steep. Using the field plate structure as a mask, ion implantation is performed on the exposed reserved area of the drift region to form the drift region, and the doping concentration of the drift region between the field plate structures is greater than that of the drift region under the field plate structure. An unexpected effect of this application is that, through a mandrel / sidewall process combined with complementary patterning or self-aligned etching to form an inverted trapezoidal gate conductive layer (with the width increasing in the direction away from the substrate surface), the high electric field region is migrated from the weak gate dielectric region near the substrate surface to the top of the gate conductive layer away from the substrate surface. At the same time, the arc-shaped sidewall structure increases the equivalent dielectric thickness below the high electric field concentration region, thereby reducing the risk of dielectric breakdown and hot carrier injection. The same mandrel structure is used to simultaneously define the positions of the gate structure and the field plate structure, reducing overlay errors and ensuring the relative positional accuracy between the gate structure and the field plate structure. Furthermore, the field plate structure is used as a hard mask for ion implantation, and high and low doping profiles with alternating distribution of the first and second regions are formed in the drift region by tilted rotation implantation. This periodic doping modulation not only optimizes the surface electric field distribution but also effectively modulates the bulk electric field, so that while shortening the drift region length and reducing the on-resistance, a high breakdown voltage can still be maintained. The steep outer wall further improves the geometric controllability of the shading region, allowing the doping concentration and profile to be accurately predicted during the design phase through TCAD simulation, thereby enabling precise optimization of the electric field distribution.
[0077] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0078] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
[0079] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0080] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for manufacturing an LDMOS device, characterized in that, include: A substrate is provided, the substrate including a bulk region and a reserved area for the drift region; Multiple spaced mandrel structures are formed on the reserved area of the body region and the drift region. Each mandrel structure includes a mandrel and a covering layer that covers the outer wall of the mandrel. A gate dielectric layer is formed to cover the surface of the substrate exposed by the mandrel structure and the sidewalls of the cladding layer, and a gate conductive layer is formed to cover the gate dielectric layer and fill the spaces between adjacent mandrel structures; The cladding layer and the core exposed by the gate conductive layer are removed, and the remaining cladding layer is a sidewall structure. The gate dielectric layer, the gate conductive layer and the corresponding sidewall structure located on the body region serve as the gate structure, and the gate dielectric layer, the gate conductive layer and the corresponding sidewall structure located on the reserved area of the drift region serve as the field plate structure. In the gate structure and the field plate structure, the width of the gate conductive layer increases in the direction away from the substrate surface, and the sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, while the sidewalls of the two corresponding sidewall structures that are far from each other are steep. Using the field plate structure as a mask, ion implantation is performed on the exposed drift region reserved area to form a drift region, and the doping concentration of the drift region between the field plate structures is greater than the doping concentration of the drift region under the field plate structure.
2. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The steps for forming the mandrel structure include: A sacrificial material layer and a first sidewall material layer are sequentially formed on the substrate; A first patterning is performed on the sacrificial material layer and the first sidewall material layer using a first photomask to form a plurality of spaced mandrels, wherein the remaining sacrificial material layers are formed on the surface of the mandrels and the first sidewall material layer is covered on the surface of the mandrels. A second sidewall material layer is formed to conformally cover the surface of the substrate, the mandrel, and the outer wall of the first sidewall material layer; An anisotropic etching process is performed to etch the second sidewall material layer to expose the surface of the substrate, and the first sidewall material layer and the second sidewall material layer covering the outer wall of the mandrel serve as the cladding layer.
3. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The steps for forming the gate dielectric layer include: A first oxide layer is formed on the exposed surface of the substrate using a thermal oxidation process; A second oxide layer is formed by a deposition process to conformally cover the surface of the first oxide layer and the outer wall of the coating layer, wherein the first oxide layer and the second oxide layer serve as the gate dielectric layer.
4. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The steps for forming the gate conductive layer include: A conductive material is formed to conformally cover the surface of the gate dielectric layer and fill the spaces between adjacent core structures; Using the surface of the coating layer or the gate dielectric layer as a stop layer, a polishing process is performed, retaining the conductive material between adjacent mandrel structures as the gate conductive layer.
5. The method for manufacturing an LDMOS device according to claim 2, characterized in that, The steps for forming the gate structure and the field plate structure include: The first photomask is used to perform a second patterning on the cladding layer and the core, and the cladding layer and the core exposed outside the gate conductive layer are etched away to expose a portion of the surface of the substrate. The second patterning and the pattern of the first patterning are complementary in a plane.
6. The method for manufacturing an LDMOS device according to claim 2, characterized in that, The steps for forming the gate structure and the field plate structure include: Using the gate conductive layer as a mask, an anisotropic dry etching process is performed to remove the cladding layer and the mandrel exposed outside the gate conductive layer, thereby exposing part of the surface of the substrate. In the anisotropic dry etching process, the etching selectivity ratio of the cladding layer and the mandrel relative to the gate conductive layer is greater than or equal to 10:
1.
7. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The steps for forming the drift region include: A patterned photoresist layer is formed on the substrate, the patterned photoresist layer having openings to expose the reserved area of the drift region; Using the patterned photoresist layer and the field plate structure as a mask, ion implantation is performed on the exposed drift region reserved area to form the drift region in the drift region reserved area. The drift region has a first concentration in a first region between the field plate structures and a second concentration in a second region below the field plate structures. The first concentration is greater than the second concentration, and the first region and the second region are alternately distributed in the drift region.
8. The method for manufacturing an LDMOS device according to claim 7, characterized in that, The sidewalls of the field plate structure are steep, and inclined ion implantation is used. During the inclined ion implantation process, the substrate is rotated to change the doping concentration gradient between adjacent first and second regions.
9. The method for manufacturing an LDMOS device according to claim 1, characterized in that, After the drift region is formed, the process further includes: A patterned photoresist layer is formed on the substrate, the patterned photoresist layer having at least two openings that expose a portion of the surface of the body region and a portion of the surface of the drift region, respectively; Using the patterned photoresist layer, source / drain ion implantation is performed to form source / drain regions in the substrate.
10. An LDMOS device, characterized in that, The LDMOS device, obtained by the manufacturing method according to any one of claims 1 to 9, comprises: A substrate having a bulk region and a drift region; A gate structure is provided on the body region; At least one field plate structure is provided on the drift zone; Each of the gate structures and the field plate structures includes a stacked gate dielectric layer and a gate conductive layer, and a sidewall structure located on the sidewall of the gate dielectric layer and the gate conductive layer. The width of the gate conductive layer increases in the direction away from the substrate surface. The sidewalls of the two corresponding sidewall structures that are close to each other are arc-shaped, and the sidewalls of the two corresponding sidewall structures that are far apart from each other are steep. The doping concentration of the drift region between the field plate structures is greater than the doping concentration of the drift region under the field plate structure.