Semiconductor structure and method of manufacturing the same
Patent Information
- Application Number
- CN202611435925.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-16
- Publication Date
- 2026-10-20
AI Technical Summary
此时，需要的工作电压种类越多，制程实现越复杂，从而不利于产量的提升等
[0030]并且，此时多种厚度的栅介质层受同一栅电极的控制。因此，基于同一栅极结构形成的同一晶体管可以同时具有变化的工作电压，从而可以有效提高集成度，且使得晶体管的功能覆盖范围更宽更强大。此时，同一晶体管可以连接多个功能电路。在应用过程中，同一晶体管可以在需要不同工作电压的多个功能电路之间切换连接。
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Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] In existing semiconductor structures, if different operating voltages are required, transistors with gate oxide thicknesses need to be fabricated separately. Fabricating transistors with different gate oxide thicknesses requires different photolithography processes to create the gate oxide layers. Therefore, the more types of operating voltages required, the more complex the manufacturing process becomes, which is detrimental to increasing production yield. Summary of the Invention
[0003] Based on this, this application provides a semiconductor structure and its fabrication method that can effectively reduce the complexity of the manufacturing process.
[0004] A method for fabricating a semiconductor structure, comprising:
[0005] A substrate is provided; a trench isolation structure is formed in the substrate, the trench isolation structure dividing the substrate into multiple active regions;
[0006] A first patterned photoresist with a first opening is formed on one side of the substrate;
[0007] Based on the first opening, the active region is implanted with ions multiple times at different injection angles and with different injection energies to form multiple microbubble regions with different implantation areas in the same active region in the first direction; among the multiple microbubble regions, at least some microbubble regions have different ion implantation depths.
[0008] Remove the first patterned photoresist;
[0009] The substrate after the formation of the microbubble region is subjected to heat treatment to induce peeling cracks in the microbubble region.
[0010] The substrate in which the peeling cracks are generated is cleaned to form a groove in the active region;
[0011] A gate structure is formed on one side of the substrate where the groove is formed; the gate structure includes a gate dielectric layer and a gate electrode, the gate dielectric layer fills the groove, and the surface of the gate dielectric layer away from the substrate is flat, and the gate electrode is located on the side of the gate dielectric layer away from the substrate;
[0012] A source region and a drain region are formed in the active regions on both sides of the gate structure in the second direction, respectively; the second direction intersects the first direction.
[0013] In one embodiment, the implantation direction of the multiple ion implantations is tilted relative to a third direction and toward the same direction as the first direction, and the implantation angle of the multiple ion implantations is positively correlated with the implantation energy, wherein the third direction is the thickness direction of the substrate.
[0014] In one embodiment, during the multiple ion implantations, the implantation direction of some ions is tilted towards the positive direction of the first direction relative to a third direction, while the implantation direction of another portion of ions is tilted towards the negative direction of the first direction relative to the third direction, wherein the third direction is the thickness direction of the substrate.
[0015] In one embodiment, cleaning the substrate from which the peeling cracks occur to form a groove within the active region includes:
[0016] The substrate in which the peeling cracks have occurred is brushed; and / or,
[0017] The substrate from which the peeling cracks occurred is purged with gas; and / or,
[0018] The substrate that developed the peeling cracks was cleaned.
[0019] In one embodiment, before forming the gate structure on the side of the substrate where the groove is formed, the method further includes:
[0020] Repair and / or smooth the surface of the groove.
[0021] In one embodiment, repairing and / or smoothing the surface of the groove includes:
[0022] The surface of the groove is oxidized to form a repair oxide layer;
[0023] Remove the repaired oxide layer.
[0024] In one embodiment, a gate structure is formed on the side of the substrate where the groove is formed, including:
[0025] A gate dielectric material layer is formed that covers the substrate and fills the groove;
[0026] The gate dielectric material layer is subjected to chemical mechanical polishing to form a gate dielectric intermediate layer with a flat surface on the side away from the substrate;
[0027] A gate material layer is formed on the side of the gate dielectric intermediate layer away from the substrate;
[0028] The gate material layer and the gate dielectric intermediate layer are patterned and etched to form the gate structure; after etching, the remaining gate material layer forms the gate electrode, and the remaining gate dielectric intermediate layer forms the gate dielectric layer. The gate dielectric layer includes an effective gate dielectric portion, and the orthogonal projection of the effective gate dielectric portion on the substrate coincides with the orthogonal projection of the gate electrode on the substrate.
[0029] The aforementioned semiconductor structure fabrication method involves forming a first patterned photoresist and performing multiple ion implantations at different implantation angles to form multiple microbubble regions with different implantation depths in the same active region located in a portion of the substrate, each with different implantation areas in the first direction. Then, a heat treatment process is used to generate peeling cracks within the microbubble regions, and the substrate is cleaned along these cracks. At this point, a modified smart cut technique can be used to effectively form grooves of different depths at different locations in the first direction within the active region. Then, a gate dielectric layer is formed that fills the grooves and has a flat surface on the side away from the substrate, thereby effectively enabling the gate dielectric layer of the same gate structure to have different thicknesses at different locations in the first direction. Therefore, this application can simultaneously form multiple gate dielectric layer thicknesses based on the same first patterned photoresist in the same process, effectively reducing process complexity and thus improving yield.
[0030] Furthermore, at this point, gate dielectric layers of varying thicknesses are controlled by the same gate electrode. Therefore, the same transistor formed based on the same gate structure can simultaneously operate at varying voltages, effectively improving integration density and enabling a wider and more powerful functional range. In this scenario, the same transistor can connect to multiple functional circuits. During application, the same transistor can be switched between multiple functional circuits requiring different operating voltages.
[0031] Meanwhile, when using the method of this application for process fabrication, any one or more of the following can be adjusted according to the design requirements of the device: the thickness of the first patterned photoresist, the size of the first opening, the implantation angle of ion implantation, the implantation energy of ion implantation, and the implantation concentration of ion implantation, thereby enabling the fabrication of transistors with different transformer ranges.
[0032] A semiconductor structure, comprising:
[0033] Substrate;
[0034] A trench isolation structure is located within the substrate, dividing the substrate into multiple active regions;
[0035] The groove is located within the active region, and the depth of the groove varies at different positions in the first direction;
[0036] A gate structure, located on the side of the substrate having the groove, includes a gate dielectric layer and a gate electrode, the gate dielectric layer filling the groove, and the surface of the gate dielectric layer away from the substrate being flat, and the gate electrode being located on the side of the gate dielectric layer away from the substrate;
[0037] The source region and drain region are located in the active regions on both sides of the gate structure in a second direction, which intersects with the first direction.
[0038] In one embodiment, the depth of the groove tends to change continuously along the first direction; or, the depth of the groove changes in a wave-like manner along the first direction.
[0039] In one embodiment, the semiconductor structure further includes:
[0040] Multiple functional circuits are connected to transistors formed based on the same gate structure.
[0041] The aforementioned semiconductor structure has grooves of varying depths at different locations along a first direction within the active region. The gate dielectric layer fills these grooves, with its surface flat on the side furthest from the substrate. Therefore, the gate dielectric layer of the same gate structure can have different thicknesses at different locations along the first direction. This allows for the simultaneous formation of multiple gate dielectric layer thicknesses within the same process, reducing process complexity. Furthermore, the multiple gate dielectric layer thicknesses are controlled by the same gate electrode. Consequently, the same transistor formed based on the same gate structure can simultaneously exhibit varying operating voltages, effectively improving integration density and enabling a wider and more powerful functional range for the transistor. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0044] Figure 2 This is a schematic diagram of the cross-sectional structure after the formation of the first patterned photoresist during the fabrication process of the semiconductor structure provided in one embodiment;
[0045] Figure 3 This is a schematic diagram of the cross-sectional structure after one ion implantation during the fabrication process of the semiconductor structure provided in one embodiment;
[0046] Figure 4 This is a schematic diagram of the cross-sectional structure after secondary ion implantation during the fabrication process of the semiconductor structure provided in one embodiment;
[0047] Figure 5 This is a schematic diagram of the cross-sectional structure after three ion implantations during the fabrication process of the semiconductor structure provided in one embodiment;
[0048] Figure 6 This is a schematic diagram of the cross-sectional structure after a groove is formed during the fabrication process of the semiconductor structure provided in one embodiment;
[0049] Figure 7 This is a schematic diagram of the cross-sectional structure after the formation of the repair oxide layer during the fabrication process of the semiconductor structure provided in one embodiment;
[0050] Figure 8 This is a schematic diagram of the cross-sectional structure after the removal and repair of the oxide layer during the fabrication process of the semiconductor structure provided in one embodiment;
[0051] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the gate dielectric material layer is formed during the fabrication process of the semiconductor structure provided in one embodiment;
[0052] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the gate dielectric intermediate layer is formed during the fabrication process of the semiconductor structure provided in one embodiment;
[0053] Figure 11 This is a schematic cross-sectional view of the semiconductor structure after the gate structure is formed during the fabrication process of the semiconductor structure provided in one embodiment;
[0054] Figure 12 This is a schematic diagram of another cross-sectional structure after the gate structure is formed during the fabrication process of the semiconductor structure provided in one embodiment;
[0055] Figure 13 This is a top view of the semiconductor structure after the source and drain regions are formed during the fabrication process of the semiconductor structure provided in one embodiment;
[0056] Figure 14 This is a schematic diagram of the cross-sectional structure after three ion implantations during the fabrication process of the semiconductor structure provided in another embodiment;
[0057] Explanation of reference numerals in the attached figures:
[0058] 100-Substrate, 110-Active region, 111-Microbubble region, 112-Source region, 113-Drain region, 200-Trench isolation structure, 300-First patterned photoresist, 400-Gate structure, 410-Gate dielectric layer, 411-First oxide layer, 412-Second oxide layer, 413-Third dielectric layer, 414-Fourth dielectric layer, 410a-Gate dielectric material layer, 411a-First oxide material layer, 412a-Second oxide material layer, 413a-Third dielectric material layer, 414a-Fourth dielectric material layer, 410b-Gate dielectric intermediate layer, 420-Gate electrode, 500-Repair oxide layer, 10-Groove, 20-First opening, D1-First orientation, D2-Second orientation, D3-Third orientation. Detailed Implementation
[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0061] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0063] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0064] In one embodiment, see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:
[0065] For step S100, please refer to... Figure 2 A substrate 100 is provided; a trench isolation structure 200 is formed in the substrate 100, and the trench isolation structure 200 divides the substrate 100 into a plurality of active regions 110.
[0066] For step S200, please refer to... Figure 2 A first patterned photoresist 300 with a first opening 20 is formed on one side of the substrate 100;
[0067] For step S300, please refer to... Figures 3 to 5 Based on the first opening 20, the active region 110 is implanted with ions multiple times at different implantation angles and with different implantation energies to form multiple microbubble regions 111 with different implantation regions in the first direction D1 within the same active region 110; among the multiple microbubble regions 111, at least some of the microbubble regions 111 have different ion implantation depths.
[0068] Step S400: Remove the first patterned photoresist 300;
[0069] In step S500, the substrate 100 after the formation of the microbubble region 111 is subjected to heat treatment so that peeling cracks are generated in the microbubble region 111.
[0070] For step S600, please refer to... Figure 6 The substrate 100 with peeling cracks is cleaned to form a groove 10 in the active region 110.
[0071] For step S700, please refer to... Figure 11 as well as Figure 12 A gate structure 400 is formed on one side of the substrate 100 where the groove 10 is formed. The gate structure 400 includes a gate dielectric layer 410 and a gate electrode 420. The gate dielectric layer 410 fills the groove 10, and the surface of the gate dielectric layer 410 away from the substrate 100 is flat. The gate electrode 420 is located on the side of the gate dielectric layer 410 away from the substrate 100.
[0072] For step S800, please refer to... Figure 13 In the active regions 110 on both sides of the gate structure 400 in the second direction D2, a source region 112 and a drain region 113 are formed respectively; the second direction D2 intersects the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1.
[0073] In step S100, please refer to Figure 2 The substrate 100 is a semiconductor substrate 100. For example, the substrate 100 may include, but is not limited to, a silicon substrate 100, etc.
[0074] The trench isolation structure 200 is made of an insulating material. When forming the trench isolation structure 200 within the substrate 100, an isolation trench can be formed first. Then, an insulating material is filled into the isolation trench to form the trench isolation structure 200. The trench isolation structure 200 can divide the substrate 100 into multiple active regions 110. The active regions 110 can be used to form semiconductor devices such as transistors.
[0075] In step S200, please refer to Figure 2 First, a first photoresist material layer can be coated on the substrate 100. Then, the first photoresist material layer is exposed and developed based on the first photomask to form the first opening 20, and the remaining first photoresist material layer forms the first patterned photoresist 300.
[0076] For example, before forming the first patterned photoresist 300 on the substrate 100, the active region 110 of the substrate 100 may be ion implanted to form a well region for fabricating transistors within the active region 110.
[0077] In step S300, please refer to Figures 3 to 5The microbubble region 111 is the ion implantation region. The implantation angle can be understood as the angle between the ion implantation direction and the third direction D3. The third direction D3 is the thickness direction of the substrate 100.
[0078] When ion implantation is performed on the same active region 110 using the same first opening 20, different implantation angles result in different blocking areas of the first photoresist, leading to different implantation areas of the microbubble regions 111 formed within the active region 110 along the first direction D1. Therefore, by performing multiple ion implantations at different implantation angles, multiple microbubble regions 111 with different implantation areas along the first direction D1 can be formed within the same active region 110.
[0079] Simultaneously, the ion implantation depth of each microbubble region 111 can be adjusted by changing the implantation energy of each ion implantation, thereby ensuring that at least some of the microbubble regions 111 have different ion implantation depths. The ion implantation depth of the microbubble region 111 is the implantation depth of the ion implantation performed when the microbubble region 111 is formed.
[0080] In step S400, the first patterned photoresist 300 can be removed by a photoresist removal process.
[0081] In steps S500 to S600, the substrate 100 after forming the microbubble regions 111 is heat-treated, which causes the bubbles in each microbubble region 111 to expand and diffuse, thereby forming continuous peeling cracks. The location of the peeling cracks in each microbubble region 111 is related to the injection location of the microbubble region 111.
[0082] Simultaneously, as the heat treatment process proceeds, the implanted ions in each microbubble region 111 within the same active region 110 can diffuse, causing the microbubble regions 111 to gradually approach or connect with each other. At this time, bubbles or cracks can also be generated between the peeling cracks in each microbubble region 111.
[0083] Therefore, after heat treatment, cleaning the substrate 100 can effectively peel off and remove the thin layer of substrate 100 above the peeling cracks in each microbubble region 111, thereby effectively forming the groove 10 in the active region 110 (see [link]). Figure 6 It is understandable that when cleaning the substrate 100, some possible adhesions along the crack can be broken.
[0084] Furthermore, the location of the peeling crack in each microbubble region 111 is related to the implantation location of the microbubble region 111. The implantation location of the microbubble region 111 is related to the ion implantation depth of each microbubble region 111 and its implantation area in the first direction D1. Since the implantation areas of multiple microbubble regions 111 within the same active region 110 are different in the first direction D1, and at least some of the microbubble regions 111 have different ion implantation depths, after effectively peeling away the thin layer of substrate 100 above the peeling crack, the resulting groove 10 can have different depths at different locations in the first direction D1.
[0085] Meanwhile, it should be noted that the difference in ion implantation depth among the various microbubble regions 111 can be controlled to be very small. Furthermore, during the heat treatment process, ions within each microbubble region 111 can diffuse and potentially intersect. Therefore, after heat treatment peeling and cleaning of the peeled-off substrate 100 thin layer, the groove 10 formed in the active region 110 will not exhibit the obvious steps shown in the diagram, but rather tends towards a gradual, continuous change.
[0086] In step S700, please refer to Figure 11 as well as Figure 12 A gate structure 400 covering the recess 10 can be formed. The gate structure 400 includes a gate dielectric layer 410 and a gate electrode 420. The gate dielectric layer 410 may include multiple dielectric layers or a single dielectric layer, depending on actual needs. The material of the gate electrode 420 may include, but is not limited to, a metallic material. For example, the material of the gate electrode 420 may also include polysilicon.
[0087] The gate dielectric layer 410 fills the groove 10, and the surface of the gate dielectric layer 410 away from the substrate 100 is flat. Therefore, the gate dielectric layer 410 can have different thicknesses at different locations in the first direction D1.
[0088] In step S800, please refer to Figure 13 Source region 112 and drain region 113 can be formed in the active regions 110 on both sides of the gate structure 400 in the second direction D2 by ion implantation.
[0089] At this time, the gate structure 400, the source region 112, the drain region 113, and the active region 110 located between the source region 112 and the drain region 113 can form a transistor.
[0090] For example, after forming the source region 112 and the drain region 113, contact hole structures can be formed on the source region 112, the drain region 113 and the gate structure 400 respectively, so as to provide source signal, drain signal and gate signal for the transistor.
[0091] It is understandable that the depth of the groove 10 and the thickness of the gate dielectric layer 410 are different at different positions in the first direction D1. When the position in the first direction D1 is fixed, the depth of the groove 10 and the thickness of the gate dielectric layer 410 can be the same or substantially the same at different positions in the second direction D2.
[0092] In this embodiment, through the formation of a first patterned photoresist 300 and multiple ion implantations at different implantation angles, multiple microbubble regions 111 with different implantation areas in the first direction D1 and at least some microbubble regions 111 with different ion implantation depths are formed in the same active region 110 located in a portion of the substrate 100. Then, by heat treatment, peeling cracks are generated in the microbubble regions 111, and the substrate 100 is cleaned along the peeling cracks. At this time, by using an improved smart cut technique, grooves 10 with different depths at different positions in the first direction D1 can be effectively formed in the active region 110. Then, a gate dielectric layer 410 with a flat surface on the side away from the substrate 100 that fills the grooves 10 is formed, thereby effectively realizing that the gate dielectric layer 410 of the same gate structure 400 can have different thicknesses at different positions in the first direction D1. Therefore, in this embodiment, multiple gate dielectric layer thicknesses can be formed simultaneously based on the same first patterned photoresist 300 in the same process, thereby effectively reducing process complexity and improving yield.
[0093] Furthermore, gate dielectric layers of varying thicknesses are controlled by the same gate electrode 420. Therefore, the same transistor formed based on the same gate structure 400 can simultaneously have varying operating voltages, effectively improving integration density and enabling the transistor to cover a wider and more powerful range of functions. At this time, the same transistor can connect to multiple functional circuits. In application, the same transistor can be switched between multiple functional circuits requiring different operating voltages. For example, when a first voltage is supplied to the transistor, the active region 110 under the gate dielectric layer 410 with a thickness less than or equal to the first thickness forms a channel, at which point the transistor can be connected to the functional circuit requiring the first voltage. When the voltage supplied to the transistor increases from the first voltage to a second voltage, the active region 110 under the gate dielectric layer 410 with a thickness less than or equal to the second thickness forms a channel, at which point the transistor can be switched to the functional circuit requiring the second voltage. The second thickness is greater than the first thickness. It can be understood that when the first voltage is greater than the second voltage, the transistor can cause the active region 110 under the gate dielectric layer 410 of a greater thickness to form a channel under the second voltage, thereby achieving a larger channel width in the first direction D1. At the same time, it can be understood that "more" in this article means two or more.
[0094] Meanwhile, when using the method of this embodiment for processing, any one or more of the following can be adjusted according to the design requirements of the device: the thickness of the first patterned photoresist 300, the size of the first opening 20, the ion implantation angle, the ion implantation energy, and the ion implantation concentration. This allows for the fabrication of transistors with different voltage transformation ranges (e.g., 1V-2.5V, 1.8V-3.3V, 6V-12V, 27V-32V), thus meeting different design requirements. Specifically, by adjusting the thickness of the first patterned photoresist 300, the size of the first opening 20, and the ion implantation angle, the length and position of each microbubble region 111 in the first direction D1 can be adjusted, thereby adjusting the length and position of the groove 10 in the first direction D1, and thus adjusting the channel width of the transistor. By adjusting the ion implantation energy and ion implantation concentration, the ion implantation depth of each microbubble region 111 can be adjusted, thereby affecting the thickness of the gate dielectric layer 410, and thus affecting the voltage value of the transistor's voltage transformation.
[0095] In one embodiment, see Figures 3 to 5 In step S300, when the active region 110 is implanted multiple times at different implantation angles based on the first opening 20, the implantation direction of the multiple ion implantations is tilted relative to the third direction D3 towards the same direction as the first direction D1. The same direction of the first direction D1 can be either the positive direction of the first direction D1 or the negative direction of the first direction D1.
[0096] At this time, during each ion implantation, the first patterned photoresist 300 located on the same side of the first opening 20 in the first direction D1 can be used as a shield, thereby enabling ion implantation of a portion of the active region 110 exposed by the first opening 20.
[0097] Meanwhile, the implantation angle and implantation energy are positively correlated in multiple ion implantations.
[0098] For example, please refer to Figures 3 to 5 The implantation angle increases progressively with each ion implantation. Figure 3 The implantation angle for the first ion implantation is c. Figure 4 The implantation angle for the second ion implantation is b. Figure 5 The implantation angle for the third ion implantation is α. Simultaneously, the implantation energy increases with each subsequent ion implantation, resulting in a progressively greater ion implantation depth.
[0099] At this point, within the same active region 110, the lengths of the multiple microbubble regions 111 formed by multiple ion implantations decrease sequentially along the first direction D1, while the ion implantation depths of the multiple microbubble regions 111 formed by multiple ion implantations increase sequentially. Therefore, the multiple microbubble regions 111 formed within the same active region 110 can be arranged in a stepped manner. Consequently, the depth of the groove 10 subsequently formed within the same active region 110 can vary sequentially along the first direction D1.
[0100] As another example, the implantation angle decreases successively in multiple ion implantations (e.g., Figure 5 The implantation angle decreases sequentially from a to c. At the same time, the implantation energy decreases with each ion implantation, which in turn decreases with each implantation, resulting in a gradual decrease in ion implantation depth.
[0101] At this time, within the same active region 110, the lengths of the multiple microbubble regions 111 formed by multiple ion implantations increase sequentially along the first direction D1, while the ion implantation depths of the multiple microbubble regions 111 formed by multiple ion implantations decrease sequentially. Therefore, the multiple microbubble regions 111 formed within the same active region 110 can be arranged in a stepped manner. Consequently, the depth of the groove 10 subsequently formed within the same active region 110 can vary sequentially along the first direction D1.
[0102] In this embodiment, during multiple ion implantations, the implantation angle and ion implantation depth are positively correlated. The greater the length of each microbubble region 111 in the first direction D1, the smaller the ion implantation depth. The microbubble region 111 with the largest length in the first direction D1 has the smallest ion implantation depth, thereby facilitating the effective removal of the substrate 100 thin layer located on each microbubble region 111.
[0103] Simultaneously, multiple microbubble regions 111 formed within the same active region 110 can be arranged in a stepped manner. Therefore, the depth of the subsequently formed groove 10 within the same active region 110 can vary sequentially along the first direction D1. Furthermore, as explained above, the ion implantation depth difference between each microbubble region 111 can be controlled to be very small, and the depth of the groove 10 formed within the active region 110 tends to change infinitely (continuously). Therefore, the thickness of the gate dielectric layer 410 of the subsequently formed gate structure 400 can tend to change continuously along the first direction D1. This allows the same transistor formed based on the same gate structure 400 to have a continuously varying operating voltage.
[0104] Simultaneously, the depth of the groove 10 formed within the active region 110 tends to change continuously along the first direction D1. This allows the conductive channel formed within the active region 110 surrounding the groove 10 to change continuously along the first direction D1, avoiding the formation of a single transverse current between the source region 112 and the drain region 113 as in traditional channels. This broadens the electron flow direction and significantly reduces the hot carrier injection (HCI) effect. Furthermore, this effectively reduces the off-state leakage current (Ioffleakage) and the drain-induced barrier reduction (DIBL) effect.
[0105] In one embodiment, see Figure 14 In the multiple ion implantations performed in step S300, the implantation direction of some ions is tilted towards the positive direction of the first direction D1 relative to the third direction D3, and the implantation direction of other ions is tilted towards the negative direction of the first direction D1 relative to the third direction D3.
[0106] At this time, multiple ion implantations can be performed on different regions of the active region 110 exposed by the first opening 20 by using the first patterned photoresist 300 located on both sides of the first opening 20 in the first direction D1 as a shield.
[0107] For example, three ion implantations are performed in step S300. The implantation direction of the first ion implantation can be the third direction D3. The implantation depth of the first ion implantation (i.e., the ion implantation depth of the first microbubble region 111 formed by the first ion implantation) is the minimum. The implantation direction of the second ion implantation is inclined in the negative direction of the first direction D1 relative to the third direction D3. The implantation depth of the second ion implantation (i.e., the ion implantation depth of the second microbubble region 111 formed by the second ion implantation) is centered. The implantation direction of the third ion implantation is inclined in the positive direction of the first direction D1 relative to the third direction D3. The implantation depth of the third ion implantation (i.e., the ion implantation depth of the third microbubble region 111 formed by the third ion implantation) is the maximum.
[0108] In this embodiment, the same transistor formed based on the same gate structure 400 can also have a continuously varying operating voltage, which can reduce the hot carrier injection (HCI) effect, etc. Simultaneously, this embodiment can also reduce damage to the first patterned photoresist 300 located on the same side of the first opening 20 during multiple ion implantation processes, thereby improving process control precision. Based on this, the bottom of the subsequently formed groove 10 can be wavy, and the height and undulation of the wavy groove 10 can be set according to requirements.
[0109] In one embodiment, step S600 includes:
[0110] Step S600-1: The substrate 100 with peeling cracks is brushed.
[0111] The substrate 100 with peeling cracks can be cleaned by using a cleaning brush, thereby effectively cleaning and removing the thin layer of substrate 100 above the peeling cracks.
[0112] In one embodiment, step S600 includes:
[0113] Step S600-2: The substrate 100 with peeling cracks is purged with gas.
[0114] The substrate 100 with peeling cracks can be purged with an inert gas, thereby effectively cleaning and removing the thin layer of substrate 100 above the peeling cracks.
[0115] In one embodiment, step S600 includes:
[0116] Step S600-3: Clean the substrate 100 that has developed peeling cracks.
[0117] For example, the substrate 100 can be washed with water. After cleaning the substrate 100 that has peeling cracks, it can be dried.
[0118] In some embodiments, the substrate 100 with peeling cracks can be brushed and purged with gas simultaneously to improve the cleaning effect. After brushing and / or purging, the substrate 100 can also be washed with water, dried, etc.
[0119] In one embodiment, see Figure 8 Before step S700, the following are also included:
[0120] Step S610: Repair and / or smooth the surface of the groove 10.
[0121] Specifically, the groove 10 is formed by creating multiple microbubble regions 111 through ion implantation, followed by a heat treatment process to generate peeling cracks. During this process, ion implantation damages the substrate 100, resulting in defects on the surface of the groove 10. Therefore, repairing the surface of the groove 10 can effectively remove these defects, thus laying a good foundation for the subsequent formation of a high-quality gate dielectric layer 410.
[0122] Meanwhile, since the groove 10 is formed by creating multiple microbubble regions 111 through ion implantation followed by peeling cracks due to a heat treatment process, the surface roughness of the groove 10 is relatively large, making it prone to sharp protrusions or step-like damage. The electric field at these sharp edges will be abnormally concentrated, easily leading to localized breakdown or leakage, thus affecting device reliability. Therefore, smoothing the surface of the groove 10 can effectively improve device reliability.
[0123] In one embodiment, step S610 includes:
[0124] For step S610-1, please refer to [link / reference]. Figure 7 The surface of groove 10 is oxidized to form a repair oxide layer 500;
[0125] For step S610-2, please refer to [link / reference]. Figure 8 Remove and repair the oxide layer 500.
[0126] A repair oxide layer 500 can be formed by oxidizing the damaged and rough portion of the substrate 100 material on the surface of the groove 10 using an in-situ water vapor generation process.
[0127] Subsequently, the repair oxide layer 500 can be removed using etching processes. At this point, the surface defects of the groove 10 after removing the repair oxide layer 500 can be effectively repaired. Simultaneously, the surface of the groove 10 can be effectively smoothed.
[0128] Of course, in other embodiments, when the device requirements are lower, the steps of repairing and / or smoothing the surface of the groove 10 may not be necessary, and the specific steps can be set according to actual needs.
[0129] In one embodiment, step S700 includes:
[0130] For step S700-1, please refer to [link / reference]. Figure 9 A gate dielectric material layer 410a is formed that covers the substrate 100 and fills the groove 10;
[0131] For step S700-2, please refer to [link / reference]. Figure 10 Chemical mechanical polishing is performed on the gate dielectric material layer 410a to form a gate dielectric intermediate layer 410b with a flat surface on the side away from the substrate 100.
[0132] Step S700-3: A gate material layer is formed on the side of the gate dielectric intermediate layer 410b away from the substrate 100;
[0133] For step S700-4, please refer to [link / reference]. Figure 11 as well as Figure 12The gate material layer and the gate dielectric intermediate layer 410b are patterned and etched to form a gate structure 400. After etching, the remaining gate material layer forms a gate electrode 420, and the portion of the remaining gate dielectric intermediate layer 410b opposite to the gate electrode 420 forms a gate dielectric layer 410.
[0134] In step S700-1, please refer to Figure 9 This allows for the formation of a gate dielectric material layer 410a with a relatively large thickness, which facilitates subsequent chemical mechanical polishing and leveling, and makes it easier to achieve the goal of having gate dielectric layers 410 of different thicknesses in the same transistor.
[0135] The gate dielectric material layer 410a may include multiple film layers or a single film layer.
[0136] For example, an in-situ vapor generation (ISSG) process can be first used to oxidize the surface of the groove 10 to form a dense first oxide material layer 411a with a low defect density. This first oxide material layer 411a can serve as the bottom interface layer of the gate dielectric material layer 410a, thereby helping to improve the overall quality and reliability of the gate dielectric material layer 410a.
[0137] Subsequently, a second oxide layer 412a can be formed on the surface of the oxide layer by high-temperature oxidation (HTO) deposition or by using tetraethyl orthosilicate (TEOS) source deposition. The second oxide layer 412a and the first oxide layer 411a can form a gate dielectric material layer 410a.
[0138] In step S700-2, please refer to Figure 10 After performing chemical mechanical polishing on the gate dielectric material layer 410a, the upper surface of the gate dielectric material layer 410a can be made flat.
[0139] For example, after chemical mechanical polishing, polishing repair can be performed, which can effectively avoid reliability problems caused by polishing defects.
[0140] For example, the polished gate dielectric material layer 410a can directly form the gate dielectric intermediate layer 410b. Alternatively, for example, after chemically mechanically polishing the gate dielectric material layer 410a, a third dielectric material layer 413a and a fourth dielectric material layer 414a can be sequentially formed on the upper surface of the polished gate dielectric material layer 410a. The material of the third dielectric material layer 413a may include silicon oxynitride (SiON). The material of the fourth dielectric material layer 414a may include a high dielectric constant material (such as HfO). In this case, the polished gate dielectric material layer 410a, the third dielectric material layer 413a, and the fourth dielectric material layer 414a can be used together to form the gate dielectric intermediate layer 410b.
[0141] In step S700-3, a gate material layer can be formed on the side of the gate dielectric intermediate layer 410b away from the substrate 100 by a deposition process.
[0142] In step S700-4, please refer to Figure 11 as well as Figure 12 First, a second patterned photoresist can be formed on the gate material layer. Then, the gate material layer is etched based on the second patterned photoresist to form the gate electrode 420. During this etching process, a portion of the gate dielectric intermediate layer 410b is over-etched, and the remaining gate dielectric intermediate layer forms the gate dielectric layer 410. The gate dielectric layer 410 includes an effective gate dielectric portion. The orthographic projection of the effective gate dielectric portion on the substrate 100 coincides with the orthographic projection of the gate electrode 420 on the substrate 100. Afterward, the second patterned photoresist is removed. Exemplarily, the portion of the gate dielectric layer 410 other than the effective gate dielectric portion can be removed in subsequent process steps.
[0143] For example, the second oxide layer 412a and the first oxide layer 411a form the gate dielectric material layer 410a. The polished gate dielectric material layer 410a, the third dielectric material layer 413a, and the fourth dielectric material layer 414a form the gate dielectric intermediate layer 410b. After etching away a portion of the gate dielectric intermediate layer 410b, the remaining first oxide layer 411a forms the first oxide layer 411, the remaining second oxide layer 412a forms the second oxide layer 412, the remaining third dielectric layer 413a forms the third dielectric layer 413, and the remaining fourth dielectric layer 414a forms the fourth dielectric layer 414. The first oxide layer 411, the second oxide layer 412, the third dielectric layer 413, and the fourth dielectric layer 414 form the gate dielectric layer 410. It can be understood that the degree and depth of etching of the gate dielectric intermediate layer 410b can be set according to actual needs.
[0144] For example, after forming the gate structure 400, a sidewall structure may also be formed on the sidewall of the gate structure 400.
[0145] Complete the AA and related Well implant processes. Then perform the photo process for the Silicon Recess process. The original different masks for Silicon Recesses with different voltages can be merged into a single mask. If there are no areas that do not require recess or conventional MOS, photoresist is used to cover and block them.
[0146] The thickness of the first patterned photoresist 300 and the size of the first opening 20 can affect the position and size of the subsequently formed microbubble region 111. The thickness of the first patterned photoresist 300 and the size of the first opening 20 can be adjusted according to requirements.
[0147] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0148] In one embodiment, a semiconductor structure is also provided, which includes a substrate 100, a trench isolation structure 200, a recess 10, a gate structure 400, a source region 112, and a drain region 113.
[0149] The substrate 100 is a semiconductor substrate 100. For example, the substrate 100 may include, but is not limited to, a silicon substrate 100, etc.
[0150] The trench isolation structure 200 is located within the substrate 100, dividing the substrate 100 into multiple active regions 110.
[0151] The groove 10 is located within the active region 110. For example, the groove 10 is located within a portion of the active region 110. The depth of the groove 10 varies at different locations along the first direction D1.
[0152] The gate structure 400 is located on the side of the substrate 100 with the recess 10. The gate structure 400 includes a gate dielectric layer 410 and a gate electrode 420. The gate electrode 420 is located on the side of the gate dielectric layer 410 away from the substrate 100.
[0153] The gate dielectric layer 410 may include multiple dielectric layers or a single dielectric layer, depending on actual requirements. The material of the gate electrode 420 may include, but is not limited to, metallic materials. For example, the material of the gate electrode 420 may also include polysilicon.
[0154] The gate dielectric layer 410 fills the groove 10, and the surface of the gate dielectric layer 410 away from the substrate 100 is flat. Therefore, the gate dielectric layer 410 can have different thicknesses at different locations in the first direction D1.
[0155] The source region 112 and the drain region 113 are located in the active regions 110 on both sides of the gate structure 400 in the second direction D2.
[0156] In this embodiment, grooves 10 of varying depths are provided at different positions along the first direction D1 within the active region 110. The gate dielectric layer 410 fills the grooves 10, and its surface away from the substrate 100 is flat. Therefore, the gate dielectric layer 410 of the same gate structure 400 can have different thicknesses at different positions along the first direction D1. Thus, multiple gate dielectric layers 410 of different thicknesses can be formed simultaneously in the same process, thereby reducing process complexity. Furthermore, the gate dielectric layers 410 of various thicknesses are controlled by the same gate electrode 420. Therefore, the same transistor formed based on the same gate structure 400 can simultaneously have varying operating voltages, thereby effectively improving integration density and enabling the transistor to have a wider and more powerful functional range.
[0157] In one embodiment, the depth of the groove 10 tends to change continuously along the first direction D1. In this case, the thickness of the gate dielectric layer 410 of the same gate structure 400 tends to change continuously along the first direction D1.
[0158] In one embodiment, the depth of the groove 10 varies in a wavy shape along the first direction D1. At this time, the thickness of the gate dielectric layer 410 of the same gate structure 400 also varies in a wavy shape along the first direction D1.
[0159] In one embodiment, the semiconductor structure further includes multiple functional circuits. These functional circuits are connected to transistors formed based on the same gate structure 400.
[0160] In application, the same transistor can be switched between multiple functional circuits requiring different operating voltages. For example, when a first voltage is supplied to the transistor, the active region 110 under the gate dielectric layer 410 with a thickness less than or equal to the first thickness forms a channel, allowing the transistor to be connected to a functional circuit requiring the first voltage. When the voltage supplied to the transistor increases from the first voltage to a second voltage, the active region 110 under the gate dielectric layer 410 with a thickness less than or equal to the second thickness forms a channel, allowing the transistor to be switched to a functional circuit requiring the second voltage. The second thickness is greater than the first thickness. It can be understood that when the first voltage is greater than the second voltage, the transistor at the second voltage allows the active region 110 under the gate dielectric layer 410 to form a channel with a greater thickness, thereby achieving a larger channel width in the first direction D1.
[0161] In the description of this specification, references to terms such as "one embodiment," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0162] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0163] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A trench isolation structure is formed in the substrate, which divides the substrate into multiple active regions; A first patterned photoresist with a first opening is formed on one side of the substrate; Based on the first opening, the active region is implanted with ions multiple times at different injection angles and with different injection energies to form multiple microbubble regions with different injection areas in the first direction within the same active region. Among the plurality of microbubble regions, at least some of the microbubble regions have different ion implantation depths; Remove the first patterned photoresist; The substrate after the formation of the microbubble region is subjected to heat treatment to induce peeling cracks in the microbubble region. The substrate in which the peeling cracks are generated is cleaned to form a groove in the active region; A gate structure is formed on one side of the substrate where the groove is formed; the gate structure includes a gate dielectric layer and a gate electrode, the gate dielectric layer fills the groove, and the surface of the gate dielectric layer away from the substrate is flat, and the gate electrode is located on the side of the gate dielectric layer away from the substrate; A source region and a drain region are formed in the active regions on both sides of the gate structure in the second direction, respectively; the second direction intersects the first direction.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The implantation direction of the multiple ion implantations is inclined in the same direction as the first direction relative to the third direction, and the implantation angle of the multiple ion implantations is positively correlated with the implantation energy. The third direction is the thickness direction of the substrate.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the multiple ion implantations, the implantation direction of some ions is tilted towards the positive direction of the first direction relative to the third direction, and the implantation direction of other ions is tilted towards the negative direction of the first direction relative to the third direction, wherein the third direction is the thickness direction of the substrate.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of cleaning the substrate from which the peeling cracks occur to form a groove in the active region includes: The substrate in which the peeling cracks have occurred is brushed; and / or, The substrate from which the peeling cracks occurred is purged with gas; and / or, The substrate that developed the peeling cracks was cleaned.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the gate structure on the side of the substrate where the groove is formed, the method further includes: Repair and / or smooth the surface of the groove.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The repair and / or smoothing of the groove surface includes: The surface of the groove is oxidized to form a repair oxide layer; Remove the repaired oxide layer.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a gate structure on one side of the substrate where the groove is formed includes: A gate dielectric material layer is formed that covers the substrate and fills the groove; The gate dielectric material layer is subjected to chemical mechanical polishing to form a gate dielectric intermediate layer with a flat surface on the side away from the substrate; A gate material layer is formed on the side of the gate dielectric intermediate layer away from the substrate; The gate material layer and the gate dielectric intermediate layer are patterned and etched to form the gate structure; after etching, the remaining gate material layer forms the gate electrode, and the remaining gate dielectric intermediate layer forms the gate dielectric layer. The gate dielectric layer includes an effective gate dielectric portion, and the orthogonal projection of the effective gate dielectric portion on the substrate coincides with the orthogonal projection of the gate electrode on the substrate.
8. A semiconductor structure, characterized in that, include: Substrate; A trench isolation structure is located within the substrate, dividing the substrate into multiple active regions; The groove is located within the active region, and the depth of the groove varies at different positions in the first direction; A gate structure, located on the side of the substrate having the groove, includes a gate dielectric layer and a gate electrode, the gate dielectric layer filling the groove, and the surface of the gate dielectric layer away from the substrate being flat, and the gate electrode being located on the side of the gate dielectric layer away from the substrate; The source region and drain region are located in the active regions on both sides of the gate structure in a second direction, which intersects with the first direction.
9. The semiconductor structure according to claim 8, characterized in that, The depth of the groove tends to change continuously along the first direction; or, the depth of the groove changes in a wave-like shape along the first direction.
10. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: Multiple functional circuits are connected to transistors formed based on the same gate structure.