A semiconductor epitaxial structure and a semiconductor device

Abstract

This invention discloses a semiconductor epitaxial structure and a semiconductor device. The semiconductor epitaxial structure includes a substrate, a channel layer, a cap layer, a barrier layer, and at least two insertion layers. The barrier layer and the at least two insertion layers are located between the channel layer and the cap layer. A barrier layer separates any two adjacent insertion layers. Each insertion layer includes at least a first insertion sub-layer, the material of which includes AlN. Along the direction from the channel layer to the cap layer, the thickness of the first insertion sub-layer decreases in each insertion layer. The technical solution of this invention can optimize the polarization electric field and stress distribution, improving the device's threshold voltage stability, electron mobility, and breakdown voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor epitaxial structure and a semiconductor device. Background Technology

[0002] Gallium nitride (GaN)-based HEMT (High Electron Mobility Transistor) devices are widely used in high-frequency and high-power applications due to their high electron mobility and high breakdown voltage. Traditional HEMT devices typically employ an AlGaN / GaN heterojunction to form a two-dimensional electron gas (2DEG), but uneven polarization electric field and stress distribution lead to problems such as threshold voltage drift and current collapse, limiting improvements in device performance.

[0003] In related technologies, the polarization electric field can be modulated by inserting an AlN layer between the channel layer and the barrier layer to improve device performance. However, this approach is difficult to achieve fine-grained control of the polarization electric field and stress distribution, resulting in limited optimization effects on 2DEG concentration and mobility. A better solution is urgently needed. Summary of the Invention

[0004] This invention provides a semiconductor epitaxial structure and a semiconductor device to optimize the polarization electric field and stress distribution, thereby improving the device's threshold voltage stability, electron mobility, and breakdown voltage.

[0005] According to one aspect of the present invention, a semiconductor epitaxial structure is provided, comprising: Substrate; The channel layer is located on one side of the substrate; the material of the channel layer includes GaN. The cap layer is located on the side of the channel layer away from the substrate; the material of the cap layer includes GaN; The barrier layer is located between the channel layer and the cap layer; the material of the barrier layer includes AlGaN. There are at least two insertion layers, both located between the channel layer and the cap layer; a barrier layer separates any two adjacent insertion layers; the insertion layer includes at least a first insertion sublayer, the material of which includes AlN; Along the direction from the channel layer to the cap layer, the thickness of the first inserted sublayer in each inserted layer decreases.

[0006] Optionally, the channel layer and the cap layer include n barrier layers and n-1 insertion layers; n≥3; Both the cap layer and the channel layer are in contact with the barrier layer.

[0007] Optionally, the channel layer and the cap layer include an m-layer barrier layer and an m+1-layer insertion layer; m ≥ 1; Both the cap layer and the channel layer are in contact with the insertion layer.

[0008] Optionally, the channel layer and the cap layer include a k-layer barrier layer and a k-layer insertion layer; k ≥ 2; One of the cap layer and the channel layer is in contact with the barrier layer, and the other is in contact with the insertion layer.

[0009] Optionally, at least two barrier layers are included between the channel layer and the cap layer; Along the direction from the channel layer to the cap layer, the thickness of each barrier layer decreases.

[0010] Optionally, along the direction from the channel layer to the cap layer, the thickness of the first inserted sublayer in the i-th inserted layer is D. i The thickness of the first inserted sub-layer in the (i+1)th insertion layer is D. i+1 D i+1 =a×D i , 0.3≤a≤0.8.

[0011] Optionally, the sum of the thicknesses of all first inserted sublayers is D, where 1nm ≤ D ≤ 30nm.

[0012] Optionally, at least a portion of the insertion layer further includes a second insertion sub-layer, which is stacked with the first insertion sub-layer; the material of the second insertion sub-layer includes GaN; and / or, At least part of the insertion layer also includes a third insertion sublayer, which is stacked with the first insertion sublayer; the material of the third insertion sublayer includes AlGaN, and the Al composition in the third insertion sublayer is different from the Al composition in the barrier layer.

[0013] Optionally, the first insertion sublayer includes a first surface and a second surface, with the first surface located on the side of the second surface away from the substrate; The first surface is obtained through surface treatment; the surface treatment includes in-situ etching or high-temperature hydrogen annealing.

[0014] According to another aspect of the present invention, a semiconductor device is provided, comprising: The semiconductor epitaxial structure provided in any embodiment of the present invention; The gate, source, and drain are all located on the side of the cap layer away from the channel layer, with the source and drain located between the gate.

[0015] The technical solution of this invention involves setting at least two insertion layers between the channel layer and the cap layer. Each insertion layer includes at least a first insertion sublayer (AlN insertion sublayer), and the thickness of the AlN insertion sublayer in each insertion layer gradually decreases along the direction from the channel layer to the cap layer. This allows for an asymmetric distribution of multiple AlN insertion sublayers between the channel layer and the cap layer, forming a thickness gradient distribution. This allows the superposition of spontaneous polarization and piezoelectric polarization effects of the AlN insertion sublayers to be utilized. By controlling the thickness gradient of the AlN insertion sublayers, a gradient distribution of polarization charge density can be achieved, thereby forming an optimized electric field distribution at the heterojunction interface. This achieves a continuous and gradual change in the polarization electric field from the barrier layer to the cap layer, eliminating... The charge accumulation problem caused by abrupt changes in the electric field in traditional structures can be significantly reduced by lowering the peak value of the channel electric field, thereby suppressing current collapse, reducing threshold voltage drift, and improving breakdown voltage. On the other hand, since the lattice constant of AlN is smaller than that of AlGaN, by setting the insertion layer to include at least one first insertion sublayer made of AlN, and making the insertion layer asymmetrically distributed between the channel layer and the cap layer, compressive stress can be introduced to further modulate the band structure, shift the conduction band bottom energy downward, enhance the quantum confinement effect on the DEG, and improve the electron surface density and DEG mobility. At the same time, multiple AlN insertion sublayers of different thicknesses can form a stepped band structure, suppress the scattering of carriers by interface states, reduce channel resistance, and improve device performance.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a semiconductor epitaxial structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention; Figure 5This is a schematic diagram of an insertion layer in a semiconductor epitaxial structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 8 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 12 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 13 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 14 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 15 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 16 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention; Figure 17 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0021] First, it should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "comprising" and similar terms mean that the element or object preceding the word encompasses the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes. Furthermore, the shapes and sizes of the components in the accompanying drawings do not reflect actual proportions and are only intended to illustrate the content of this invention.

[0022] Figure 1 This is a schematic diagram of a semiconductor epitaxial structure provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the semiconductor epitaxial structure 100 provided in this embodiment of the invention includes a substrate 10, a channel layer 20, a cap layer 30, a barrier layer 40, and at least two insertion layers 50; the channel layer 20 is located on one side of the substrate 10; the material of the channel layer 20 includes GaN; the cap layer 30 is located on the side of the channel layer 20 away from the substrate 10; the material of the cap layer 30 includes GaN; the barrier layer 40 is located between the channel layer 20 and the cap layer 30; the material of the barrier layer 40 includes AlGaN; at least two insertion layers 50 are located between the channel layer 20 and the cap layer 30; a barrier layer 40 is spaced between any two adjacent insertion layers 50; each insertion layer 50 includes at least a first insertion sub-layer 51, the material of the first insertion sub-layer 51 includes AlN; along the direction from the channel layer 20 to the cap layer 30, the thickness of the first insertion sub-layer 51 in each insertion layer 50 decreases.

[0023] The substrate 10 may be made of materials including but not limited to SiC, silicon, or sapphire.

[0024] like Figure 1As shown, the semiconductor epitaxial structure 100 also includes a buffer layer 60, which is located between the channel layer 20 and the substrate 10. The material of the buffer layer 60 includes GaN. By setting the buffer layer 60, it is beneficial to ensure the quality of the subsequently grown channel layer 20.

[0025] In this embodiment, between the channel layer 20 and the cap layer 30, there is not only a barrier layer 40, but also at least two spaced insertion layers 50. Each insertion layer 50 includes at least a first insertion sub-layer 51 made of AlN, and the thickness of the first insertion sub-layer 51 in each insertion layer 50 decreases along the direction from the channel layer 20 to the cap layer 30.

[0026] Specifically, two or more insertion layers 50 are disposed between the channel layer 20 and the cap layer 30, and a barrier layer 40 is separated between any two adjacent insertion layers 50. Each insertion layer 50 can be an AlN layer (in which case, the insertion layer 50 only includes the first insertion sub-layer 51), or it can be a stack of AlN layers and other material layers (in which case, the insertion layer 50 includes both the first insertion sub-layer 51 and other film layers).

[0027] It should be noted that different insertion layers may contain insertion sublayers of the same material or insertion sublayers of different materials. This embodiment of the invention does not limit this, as long as it is ensured that for any insertion layer 50, at least a first insertion sublayer 51 of AlN material is included.

[0028] For example, Figure 1 The illustration is illustrated by an example where two insertion layers 50 are disposed between the channel layer 20 and the cap layer 30, and a barrier layer 40 is located between these two insertion layers 50, with all insertion layers 50 consisting only of a first insertion sublayer 51 made of AlN. (Refer to...) Figure 1 Along the direction from the channel layer 20 to the cap layer 30, the thickness D2 of the upper first insert sublayer 51-2 is less than the thickness D1 of the lower first insert sublayer 51-1.

[0029] It should be noted that in other embodiments, while ensuring that the thickness of the first insertion sub-layer 51 in each insertion layer 50 decreases from bottom to top, regardless of the film structure of each insertion layer 50, the barrier layer 40 and the insertion layer 50 between the channel layer 20 and the cap layer 30 can have other stacking methods. The embodiments of the present invention do not limit this, as long as the number of insertion layers 50 is greater than or equal to two layers, and any two adjacent insertion layers 50 are separated by a barrier layer 40.

[0030] The technical solution of this invention involves setting at least two insertion layers 50 between the channel layer 20 and the cap layer 30. Each insertion layer 50 includes at least an AlN insertion sublayer (first insertion sublayer 51), and the thickness of the AlN insertion sublayer (first insertion sublayer 51) in each insertion layer 50 gradually decreases along the direction from the channel layer 20 to the cap layer 30. This allows for an asymmetric distribution of multiple AlN insertion sublayers (first insertion sublayers 51) between the channel layer 20 and the cap layer 30, forming a thickness gradient distribution. This allows the superposition of the spontaneous polarization and piezoelectric polarization effects of the AlN insertion sublayers (first insertion sublayers 51) to achieve a gradient distribution of polarization charge density by controlling the thickness gradient of the AlN insertion sublayers (first insertion sublayers 51), thereby forming an optimized electric field distribution at the heterojunction interface and achieving a gradient from the barrier layer 40 to the cap layer 30. The polarization electric field of AlN is continuously and gradually changed, eliminating the charge accumulation problem caused by the sudden change in electric field in the traditional structure, significantly reducing the peak value of the channel electric field, thereby suppressing current collapse, reducing threshold voltage drift, and improving breakdown voltage. On the other hand, since the lattice constant of AlN is smaller than that of AlGaN, this embodiment sets the insertion layer 50 to include at least the first insertion sub-layer 51 made of AlN, so that the insertion layer 50 is asymmetrically distributed at the level where the barrier layer 40 is located (between the channel layer 20 and the cap layer 30). This can introduce compressive stress, further modulate the band structure, shift the conduction band bottom energy downward, enhance the quantum confinement effect on 2DEG, and improve the electron surface density and 2DEG mobility. At the same time, the multiple AlN insertion sub-layers (first insertion sub-layer 51) of different thicknesses can form a stepped band structure, suppress the scattering of carriers by interface states, reduce channel resistance, and improve device performance.

[0031] In addition, the semiconductor epitaxial structure of the present invention can be prepared based on the mature metal-organic chemical vapor deposition (MOCVD) process. The thickness gradient of the multilayer AlN insertion sublayer (first insertion sublayer 51) can be achieved by precisely controlling the growth parameters. No complicated equipment modification is required. Moreover, the material system is compatible with traditional epitaxial structures. Only a few process steps need to be added, and mass production is highly feasible.

[0032] Based on the above embodiments, the stacking method of the barrier layer and the insertion layer will be described in detail below.

[0033] Figure 2 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention, as shown below. Figure 2 As shown, as a feasible implementation, optionally, the channel layer 20 and the cap layer 30 include n barrier layers 40 and n-1 insertion layers 50; n≥3; both the cap layer 30 and the channel layer 20 are in contact with the barrier layer 40.

[0034] Specifically, in this embodiment, the insertion layer 50 is located inside the barrier layer 40, dividing the original single barrier layer 40 into multiple barrier layers, with an insertion layer 50 inserted between two adjacent barrier layers 40. At this time, the cap layer 30 is in contact with the top barrier layer 40, and the channel layer 20 is in contact with the bottom barrier layer 40.

[0035] For example, Figure 2 Taking n=4 as an example, the barrier layer 40 includes the first barrier layer 40-1, the second barrier layer 40-2, the third barrier layer 40-3, and the fourth barrier layer 40-4. The insertion layer 50 includes the first insertion layer 50-1, the second insertion layer 50-2, and the third insertion layer 50-3. In the diagram, the numbers following "40-" indicate the sequence number of the barrier layer 40, the numbers following "50-" indicate the sequence number of the insertion layer 50, and the numbers following "51-" indicate the sequence number of the first insertion sub-layer 51. All three are ordered from bottom to top, and the same applies below; further explanation will not follow. Figure 2 In the example, the channel layer 20 is in contact with the first barrier layer 40-1, and the cap layer 30 is in contact with the fourth barrier layer 40-4.

[0036] It should be noted that, Figure 2 The thickness differences of the three first inserted sublayers 51-1, 51-2, and 51-3 are not visually illustrated. However, as explained above, in... Figure 2 In the example shown, the thickness of the first inserted sublayer of the three layers satisfies D1 > D2 > D3. The specific values ​​can be designed by the user, and the embodiments of the present invention do not limit this.

[0037] Figure 3 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention, as shown below. Figure 3 As shown, as another feasible implementation, optionally, the channel layer 20 and the cap layer 30 include an m-layer barrier layer and an m+1-layer insertion layer; m≥1; both the cap layer 30 and the channel layer 20 are in contact with the insertion layer 50.

[0038] Specifically, the insertion layer 50 is located at least before and after the barrier layer 40. When m=1, refer to... Figure 1 Two insertion layers 50 are located on the front and rear layers of the barrier layer 40, respectively. The barrier layer 40 has one insertion layer 50 on the side near the channel layer 20, and another insertion layer 50 on the side near the cap layer 30. When m > 1, refer to... Figure 3 The insertion layers 50 are distributed in the front and rear film layers of the barrier layer 40 and inside the barrier layer 40. At this time, the cap layer 30 is in contact with the top insertion layer 50, and the channel layer 20 is in contact with the bottom insertion layer 50.

[0039] For example, Figure 3The following is an example with m=2, and the channel layer 20 and the cap layer 30 include two barrier layers 40-1 and 40-2, and three insertion layers 50-1, 50-2 and 50-3. Figure 3 In the middle, the thickness of the three first insertion sub-layers (51-1, 51-2 and 51-3) corresponding to the three insertion layers 50 also satisfies D1>D2>D3.

[0040] Figure 4 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention, as shown below. Figure 4 As shown, as another feasible implementation, optionally, a k-layer barrier layer 40 and a k-layer insertion layer 50 are included between the channel layer 20 and the cap layer 30; k ≥ 2; one of the cap layer 30 and the channel layer 20 is in contact with the barrier layer 40, and the other is in contact with the insertion layer 50.

[0041] Specifically, in this embodiment, the barrier layer 40 and the insertion layer 50 are alternately stacked, and their numbers are equal. Referring to the direction from the channel layer 20 to the cap layer 30... Figure 4 The barrier layer 40 and the insertion layer 50 can be stacked in the order of insertion layer 50, barrier layer 40, insertion layer 50, barrier layer 40, etc. In this case, the channel layer 20 is in contact with the bottom insertion layer 50, and the cap layer 30 is in contact with the top barrier layer 40. Alternatively, in other embodiments, the barrier layer 40 and the insertion layer 50 can also be stacked in the order of barrier layer 40, insertion layer 50, barrier layer 40, insertion layer 50, etc. In this case, the channel layer 20 is in contact with the bottom barrier layer 40, and the cap layer 30 is in contact with the top insertion layer 50. These arrangements will not be illustrated further here.

[0042] For example, Figure 4 The following is an example with k=2, and the area between the channel layer 20 and the cap layer 30 includes three barrier layers 40-1, 40-2 and 40-3, and three insertion layers 50-1, 50-2 and 50-3. Figure 4 In the middle, the thickness of the three first insertion sub-layers (51-1, 51-2 and 51-3) corresponding to the three insertion layers 50 also satisfies D1>D2>D3.

[0043] Reference Figure 2 When at least two barrier layers 40 are included between the channel layer 20 and the cap layer 30; optionally, the thickness of each barrier layer 40 decreases along the direction from the channel layer 20 to the cap layer 30.

[0044] For example, Figure 2 Taking an example where four barrier layers 40-1, 40-2, 40-3, and 40-4 are included between the channel layer 20 and the cap layer 30, with thicknesses of H1, H2, H3, and H4 respectively, satisfying H1 > H2 > H3 > H4. As a specific implementation, optionally... Figure 2 In the given values, H1 = 8 nm, H2 = 5 nm, H3 = 3 nm, and H4 = 2 nm.

[0045] In this embodiment, the combination of barrier layer 40 and insertion layer 50 can be understood as a composite barrier layer. When barrier layer 40 is divided into two or more layers by insertion layer 50, along the direction from channel layer 20 to cap layer 30, by setting the thickness of each barrier layer 40 to decrease and the thickness of the first insertion sub-layer 51 in each insertion layer 50 to decrease, the piezoelectric effect can be concentrated near the interface between the composite barrier layer and channel layer 20 to meet the device performance requirements.

[0046] Optionally, along the direction from the channel layer to the cap layer, the thickness of the first inserted sub-layer 51 in the i-th inserted layer 50 is D. i The thickness of the first inserted sub-layer 51 in the (i+1)th inserted layer 50 is D. i+1 D i+1 =a×D i , 0.3≤a≤0.8.

[0047] Specifically, the thickness of any first insertion sublayer 51 is 3 / 10 to 8 / 10 of the thickness of the previous first insertion sublayer 51. This arrangement allows the thickness of multiple first insertion sublayers 51 to be distributed in a certain gradient, which is beneficial for optimizing the electric field distribution. It ensures a continuous and gradual change in the polarization electric field from the barrier layer 40 to the cap layer 30, eliminating the charge accumulation problem caused by abrupt changes in the electric field in traditional structures. This significantly reduces the peak value of the channel electric field, suppresses current collapse, reduces threshold voltage drift, and improves the breakdown voltage.

[0048] It should be noted that the thickness ratio (a) of two adjacent first inserted sublayers 51 can be the same or different, and this embodiment of the invention does not limit this. Optionally, as a specific implementation, Figure 2 D1=1.5nm, D2=1nm, D3=0.5nm.

[0049] Optionally, in the insertion layer 50 closest to the channel layer 20, the thickness of the first insertion sub-layer 51 is D1, where 0.5nm≤D1≤10nm.

[0050] Optionally, the sum of the thicknesses of all the first inserted sublayers 51 is D, where 1nm ≤ D ≤ 30nm.

[0051] Studies have shown that if the total thickness of the first insertion sublayer (AlN layer) is too thin (less than 1 nm), the above optimization effect is almost ineffective. If the total thickness of the first insertion sublayer (AlN layer) is too thick, it is prone to problems such as stress relaxation and a large number of defects, affecting device performance. The embodiments of the present invention avoid the above problems and effectively improve device performance by setting the sum of the thicknesses of all first insertion sublayers to be in the range of 1 nm to 30 nm.

[0052] Optionally, the number of inserted layers 50 between the channel layer 20 and the cap layer 30 is less than 20. This configuration can optimize device performance while reducing the number of process steps and simplifying the manufacturing process.

[0053] It should be noted that, Figures 1-4 The illustration only shows an insertion layer 50 comprising the first insertion sublayer 51. In other embodiments, at least a portion of the insertion layer 50 may optionally include insertion sublayers formed of other materials. Several feasible insertion layer designs are provided below.

[0054] Figure 5 This is a schematic diagram of an insertion layer in a semiconductor epitaxial structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 7 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 8 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention, as shown below. Figures 5-8 As shown, in one embodiment, optionally, at least a portion of the insertion layer 50 further includes a second insertion sublayer 52, which is stacked with the first insertion sublayer 51; the material of the second insertion sublayer 52 includes GaN.

[0055] It should be noted that when the insertion layer 50 includes a first insertion sub-layer 51 and a second insertion sub-layer 52, the embodiments of the present invention do not limit the relationship between the number of layers of the two, as long as the two are stacked.

[0056] Reference Figure 5 Optionally, the second insertion sublayer 52 is located below the first insertion sublayer 51, that is, the second insertion sublayer 52 is located on the side of the first insertion sublayer 51 that is close to the substrate 10.

[0057] Reference Figure 6 Optionally, the second insertion sublayer 52 is located above the first insertion sublayer 51, that is, the second insertion sublayer 52 is located on the side of the first insertion sublayer 51 away from the substrate 10.

[0058] Reference Figure 7 Optionally, the insertion layer 50 includes two second insertion sublayers 52 and one first insertion sublayer 51. Along a direction perpendicular to the plane of the substrate, the two second insertion sublayers 52 are located on opposite sides of the first insertion sublayer 51.

[0059] Reference Figure 8Optionally, the insertion layer 50 includes two first insertion sublayers 51 and one second insertion sublayer 52. Along a direction perpendicular to the plane of the substrate, the two first insertion sublayers 51 are located on opposite sides of the second insertion sublayer 52. It should be noted that in this example, the thickness of the first insertion sublayer in the insertion layer 50 refers to the sum of the thicknesses of the two first insertion sublayers 51.

[0060] In this embodiment, by stacking a first insert sublayer 51 made of AlN and a second insert sublayer 52 made of GaN to form an insert layer 50, the newly introduced second insert sublayer 52 can be used as a stress relief layer to improve the stress problem between the first insert sublayer 51 and other adjacent film layers (such as the channel layer 20, barrier layer 40, or cap layer 30), and reduce the risk of material fracture caused by stress concentration. The insert layers 50 at different locations can be selected according to actual needs. Figures 5-8 The present invention does not limit the structure of any of the provided insertion layers 50.

[0061] Furthermore, the second insert sublayer 52 serves as a stress relief layer, and its thickness does not need to be too thick. Optionally, the thickness of the second insert sublayer 52 is less than the thickness of the channel layer 20.

[0062] Figure 9 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 10 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 11 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 12 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention, as shown below. Figures 9-12 As shown, optionally, at least part of the insertion layer 50 further includes a third insertion sub-layer 53, which is stacked with the first insertion sub-layer 51; the material of the third insertion sub-layer 53 includes AlGaN, and the Al composition in the third insertion sub-layer 53 is different from the Al composition in the barrier layer 40.

[0063] Optionally, the Al composition in the barrier layer 40 can be any value between 0.2 and 0.3, and the Al composition in the third inserted sublayer 53 is not equal to the Al composition in the barrier layer 40. The specific composition can be determined according to actual needs.

[0064] It should be noted that when the insertion layer 50 includes a first insertion sub-layer 51 and a third insertion sub-layer 53, the embodiments of the present invention do not limit the relationship between the number of layers of the two, as long as the two are stacked.

[0065] Reference Figure 9Optionally, the third insertion sublayer 53 is located below the first insertion sublayer 51, that is, the third insertion sublayer 53 is located on the side of the first insertion sublayer 51 that is close to the substrate 10.

[0066] Reference Figure 10 Optionally, the third insertion sublayer 53 is located above the first insertion sublayer 51, that is, the third insertion sublayer 53 is located on the side of the first insertion sublayer 51 away from the substrate 10.

[0067] Reference Figure 11 Optionally, the insertion layer 50 includes two third insertion sublayers 53 and one first insertion sublayer 51. Along a direction perpendicular to the plane of the substrate, the two third insertion sublayers 53 are located on opposite sides of the first insertion sublayer 51.

[0068] Reference Figure 12 Optionally, the insertion layer 50 includes two first insertion sub-layers 51 and one third insertion sub-layer 53. Along a direction perpendicular to the plane of the substrate, the two first insertion sub-layers 51 are located on opposite sides of the third insertion sub-layer 53. It should be noted that in this example, the thickness of the first insertion sub-layer 51 in the insertion layer 50 refers to the sum of the thicknesses of the two first insertion sub-layers 51.

[0069] In this embodiment, by stacking a first insert layer 51 made of AlN and a third insert layer 53 made of AlGaN with an Al composition different from that of the barrier layer 40 to form the insert layer 50, the newly introduced third insert layer 53 can be used as a stress relief layer to improve the stress problem between the first insert layer 51 and other adjacent film layers (such as the channel layer 20, the barrier layer 40, or the cap layer 30), and reduce the risk of material fracture caused by stress concentration. The insert layers 50 at different locations can be selected according to actual needs. Figures 9-12 The present invention does not limit the structure of any of the provided insertion layers 50.

[0070] Furthermore, the third insert sublayer 53 serves as a stress relief layer, and its thickness does not need to be too thick. Optionally, the thickness of the third insert sublayer 53 is less than the thickness of the thinnest barrier layer 40.

[0071] Figure 13 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 14 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 15 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention. Figure 16 This is a schematic diagram of another structure of the insertion layer in the semiconductor epitaxial structure provided in the embodiments of the present invention, as shown below. Figures 13-16As shown, at least part of the insertion layer 50 also includes a second insertion sub-layer 52 and a third insertion sub-layer 53, and the first insertion sub-layer 51, the second insertion sub-layer 52 and the third insertion sub-layer 53 are stacked.

[0072] In this embodiment, a second insert sublayer 52 and a third insert sublayer 53 are added on top of the first insert sublayer 51, and the three are stacked to form the insert layer 50. At this time, both the second insert sublayer 52 and the third insert sublayer 53 serve as stress relief layers.

[0073] Reference Figures 13-16 Optionally, when the insertion layer 50 includes a first insertion sublayer 51, a second insertion sublayer 52, and a third insertion sublayer 53, the second insertion sublayer 52 and the third insertion sublayer 53 do not contact each other. Since both the second insertion sublayer 52 and the third insertion sublayer 53 serve to release stress, if they contact each other, the same side of the first insertion sublayer 51 will have two stress-relieving layers, which will limit the improvement in stress-relieving effect and increase the process flow. In this embodiment, by setting the second insertion sublayer 52 and the third insertion sublayer 53 to not contact each other, it is beneficial to simplify the film structure of the insertion layer 50 while ensuring the stress-relieving effect.

[0074] Reference Figure 13 and Figure 14 Optionally, the second insertion sublayer 52 and the third insertion sublayer 53 are located on opposite sides of the first insertion sublayer.

[0075] Reference Figure 15 Optionally, the insertion layer 50 includes two first insertion sub-layers 51, a third insertion sub-layer 53 located between the two first insertion sub-layers 51, and a second insertion sub-layer 52 located on the side of at least one first insertion sub-layer 51 away from the third insertion sub-layer 53.

[0076] Figure 15 The illustration takes an example where the insertion layer 50 includes two second insertion sub-layers 52, each located on the side of the two first insertion sub-layers 51 away from the third insertion sub-layer 53. In other embodiments, the insertion layer 50 may also include one second insertion sub-layer 52, located on the side of one of the first insertion sub-layers 51 away from the third insertion sub-layer 53, thus removing... Figure 15 One of the second inserted sub-layers 52 in the middle is not shown in detail here.

[0077] Reference Figure 16 Optionally, the insertion layer 50 includes two first insertion sub-layers 51, a second insertion sub-layer 52 located between the two first insertion sub-layers 51, and a third insertion sub-layer 53 located on the side of at least one first insertion sub-layer 51 away from the second insertion sub-layer 52.

[0078] Figure 16The illustration takes an example where the insertion layer 50 includes two third insertion sub-layers 53, each located on the side of the two first insertion sub-layers 51 away from the second insertion sub-layer 52. In other embodiments, the insertion layer 50 may also include one third insertion sub-layer 53, located on the side of one of the first insertion sub-layers 51 away from the second insertion sub-layer 52, thus removing... Figure 16 One of the third inserted sub-layers 53 in the middle is not shown in detail here.

[0079] In summary, at least a portion of the insertion layer 50 can be formed by stacking at least one of AlN insertion sublayer (first insertion sublayer 51), GaN insertion sublayer (second insertion sublayer 52), and AlGaN insertion sublayer (third insertion sublayer 53). In this way, the GaN insertion sublayer (second insertion sublayer 52) and AlGaN insertion sublayer (third insertion sublayer 53) can be used to relieve stress. The specific film structure of the insertion layer 50 at different locations can be selected according to actual needs, and the embodiments of the present invention do not limit this.

[0080] Reference Figure 4 The first inserted sublayer 51 includes a first surface F1 and a second surface F2, with the first surface F1 located on the side of the second surface F2 away from the substrate 10; optionally, the first surface F1 is obtained by surface treatment; the surface treatment includes in-situ etching or high-temperature hydrogen annealing.

[0081] Specifically, when preparing a semiconductor epitaxial layer, after preparing a first insertion sublayer 51, it is first surface treated before growing subsequent film layers, such as barrier layer 40 or cap layer 30. This setup can ensure the flatness and consistency of the interface, form a clear interface, and avoid cracking caused by interdiffusion and stress accumulation.

[0082] The surface treatment can be performed using in-situ etching, such as in-situ thermal etching or Cl2 plasma etching; in addition, high-temperature hydrogen annealing can also be used, but this embodiment of the invention does not limit the specific methods used.

[0083] It should be noted that in some embodiments, when the insertion layer 50 further includes a second insertion sub-layer 52 and / or a third insertion sub-layer 53, and there is a second insertion sub-layer 52 (third insertion sub-layer 53) located on the side of the first insertion sub-layer 51 away from the substrate, the second insertion sub-layer 52 (third insertion sub-layer 53) above the first insertion sub-layer 51 can not only play a role in stress relief, but also play a role in surface modification, which is conducive to forming a flat surface. In this case, it is also possible to choose not to perform surface treatment to simplify the process.

[0084] Exemplary, as a feasible preparation method, optionally, after the preparation of the channel layer is completed, an MOCVD process is used to prepare the channel layer according to the D... i+1 =a×Di The thickness gradient of the AlN insert sublayer is controlled by the rule of 0.3≤a≤0.8. After each AlN insert sublayer is grown, the surface is treated by in-situ etching with Cl2 plasma or high-temperature hydrogen annealing, and then the next layer (e.g., a barrier layer) is grown. After the composite barrier layer is grown, a low-temperature GaN cap layer can be grown for passivation to ensure device performance.

[0085] From a process perspective, the technical solution of this invention, on the one hand, through the design of multiple AlN insertion sub-layers (first insertion sub-layer 51), can disperse the excessive stress and cracking caused by excessive thickness of a single AlN insertion layer, as well as the continuous amplification of the interface roughening of the single AlN insertion layer itself, which leads to device failure; on the other hand, through the multi-layer design, in-situ surface treatment can be performed on each AlN insertion sub-layer (first insertion sub-layer 51) before roughening growth, making the surface smooth and improving the consistency of the device; and on the third hand, through the layer thickness design of AlN insertion sub-layers (first insertion sub-layer 51) decreasing layer by layer from bottom to top, the risk of final material cracking and deformation can be effectively reduced.

[0086] From a structural performance perspective, the technical solution of this invention, on the one hand, through the gradient distribution design of the thickness of the multilayer AlN insert sublayer (first insert sublayer 51) decreasing from bottom to top, can achieve continuous control of the polarization electric field from the barrier layer 40 to the cap layer 30, which can significantly improve device performance compared with the prior art; on the other hand, surface treatment of the AlN insert sublayer or surface modification using a stress relief layer is more conducive to the heteroepitaxial growth of other materials such as GaN or AlGaN, adding more possibilities for composite material design, which is conducive to giving full play to the role of the AlN insert sublayer and effectively improving device performance.

[0087] In summary, the semiconductor epitaxial structure provided by the embodiments of the present invention represents an innovation in both structure and process. Structurally, at least two insertion layers are positioned between the channel layer and the cap layer. Each insertion layer includes an AlN insertion sublayer, and the thickness of the multiple AlN insertion sublayers gradually decreases from bottom to top, forming a gradient-decreasing asymmetric structure. In terms of process, after surface treatments such as in-situ etching or high-temperature hydrogen annealing of the AlN insertion sublayers in the insertion layers, other film layers are grown, which can form a clear interface and avoid material coarsening, interdiffusion, and stress accumulation. Research shows that the technical solution of the embodiments of the present invention can disperse stress, prevent cracking, etch dislocations, improve material performance, optimize band structure, and suppress scattering. Ultimately, in terms of device performance, it achieves a breakdown voltage increase of over 15%, an electron areal density increase of 10%~20%, an electron mobility increase of 5%~10%, and a threshold voltage drift reduction to one-third of that of traditional structures, effectively improving device performance.

[0088] Based on the same inventive concept, embodiments of the present invention also provide a semiconductor device. For example, Figure 17 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 17 As shown, the semiconductor device 200 includes the semiconductor epitaxial structure 100 provided in any of the above embodiments of the invention, and also includes a gate 201, a source 202 and a drain 203, all located on the side of the cap layer 30 away from the channel layer 20, and the source 202 and the drain 203 are located between the gate 201.

[0089] Optionally, the semiconductor devices provided in the embodiments of the present invention include, but are not limited to, HEMT devices.

[0090] In this design, both the source 202 and the drain 203 form ohmic contacts with the heterojunction structure composed of the channel layer and the barrier layer, serving as two current ports for the two-dimensional electron gas conductive channel. The gate 201 is the electrode that controls the operating state of the device, realizing the switching function or radio frequency amplification function of the device.

[0091] Since the semiconductor device provided in the embodiments of the present invention has the semiconductor epitaxial structure provided in any embodiment of the present invention, it possesses the beneficial effects of the aforementioned embodiments related to the semiconductor epitaxial structure. In summary, the embodiments of the present invention improve the device's threshold voltage stability, electron mobility, and breakdown voltage by improving the epitaxial scheme.

[0092] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor epitaxial structure, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; The material of the channel layer includes GaN; A cap layer is located on the side of the channel layer away from the substrate; the material of the cap layer includes GaN; A barrier layer is located between the channel layer and the cap layer; the material of the barrier layer includes AlGaN. At least two insertion layers are located between the channel layer and the cap layer; a barrier layer is spaced between any two adjacent insertion layers; each insertion layer includes at least a first insertion sublayer, the material of which includes AlN; Along the direction from the channel layer to the cap layer, the thickness of the first insert sub-layer in each insert layer decreases.

2. The semiconductor epitaxial structure according to claim 1, characterized in that, The channel layer and the cap layer comprise n layers of the barrier layer and n-1 layers of the insertion layer; n≥3; Both the cap layer and the channel layer are in contact with the barrier layer.

3. The semiconductor epitaxial structure according to claim 1, characterized in that, Between the channel layer and the cap layer, there are m barrier layers and m+1 insertion layers; m≥1; Both the cap layer and the channel layer are in contact with the insertion layer.

4. The semiconductor epitaxial structure according to claim 1, characterized in that, The channel layer and the cap layer comprise k layers of the barrier layer and k layers of the insertion layer; k ≥ 2; One of the cap layer and the channel layer is in contact with the barrier layer, and the other is in contact with the insertion layer.

5. The semiconductor epitaxial structure according to claim 1, characterized in that, At least two barrier layers are included between the channel layer and the cap layer; The thickness of each barrier layer decreases along the direction from the channel layer to the cap layer.

6. The semiconductor epitaxial structure according to claim 1, characterized in that, Along the direction from the channel layer to the cap layer, the thickness of the first insert sub-layer in the i-th insert layer is D. i The thickness of the first inserted sub-layer in the (i+1)th inserted layer is D. i+1 D i+1 =a×D i , 0.3≤a≤0.

8.

7. The semiconductor epitaxial structure according to claim 1, characterized in that, The sum of the thicknesses of all the first inserted sublayers is D, where 1nm ≤ D ≤ 30nm.

8. The semiconductor epitaxial structure according to claim 1, characterized in that, At least a portion of the insertion layer further includes a second insertion sub-layer, the second insertion sub-layer being stacked with the first insertion sub-layer; the material of the second insertion sub-layer includes GaN; and / or, At least part of the insertion layer further includes a third insertion sublayer, which is stacked with the first insertion sublayer; the material of the third insertion sublayer includes AlGaN, and the Al composition in the third insertion sublayer is different from the Al composition in the barrier layer.

9. The semiconductor epitaxial structure according to claim 1, characterized in that, The first insertion sublayer includes a first surface and a second surface, wherein the first surface is located on the side of the second surface away from the substrate; The first surface is obtained through surface treatment; the surface treatment includes in-situ etching or high-temperature hydrogen annealing.

10. A semiconductor device, characterized in that, include: The semiconductor epitaxial structure according to any one of claims 1-9; The gate, source, and drain are all located on the side of the cap layer away from the channel layer, and the source and drain are located between the gate.

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