Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes: providing a substrate; forming a first dummy gate structure and first source / drain regions located in the substrate on both sides of the first dummy gate structure; forming a dielectric layer on the substrate, the dielectric layer exposing the top surface of the first dummy gate structure; removing the first dummy gate structure and forming a first opening in the dielectric layer, the first opening exposing the substrate surface; performing ion implantation on a portion of the substrate at the bottom of the first opening to form a doped region in the substrate at the bottom of the first opening, the doped region being adjacent to at least one of the first source / drain regions on one side of the first dummy gate structure, the conductivity type of the doped region being the same as that of the first source / drain regions. The semiconductor structure formed by the method can increase the saturation drive current (Idsat) of the device, thereby increasing the switching speed, while avoiding an increase in static power consumption, thereby avoiding an increase in off-state leakage current (Ioff).

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] The core performance metric of a FinFET (Fin Field-Effect Transistor) is DC performance, which is the ratio of saturation drive current (Idsat) to off-state leakage current (Ioff). The saturation drive current determines the switching speed, while the off-state leakage current determines the static power consumption. This ratio (DC performance) measures the transistor's switching efficiency and is a key parameter for balancing chip performance and energy efficiency; a higher ratio indicates better performance.

[0003] Improving the DC performance of fin field-effect transistors is a technical problem that needs to be solved continuously. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the DC performance of the fin field-effect transistor.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; a first gate structure located on the substrate; a first lightly doped region located within the substrate on both sides of the first gate structure; a first source / drain region located within the substrate on both sides of the first gate structure, the first source / drain region being adjacent to the first lightly doped region; and a doped region located within the substrate at the bottom of the first gate structure, the doped region being at least adjacent to the first lightly doped region on one side of the first gate structure, the first lightly doped region being located between the first source / drain region and the doped region, the conductivity type of the doped region being the same as that of the first source / drain region, the conductivity type of the doped region being the same as that of the first lightly doped region, and the dopant ion concentration in the doped region being greater than that in the first lightly doped region.

[0006] Optionally, the dopant ion concentration in the doped region is less than the dopant ion concentration in the first source / drain region; the dopant ion concentration in the doped region is less than or equal to twice the dopant ion concentration in the first lightly doped region.

[0007] Optionally, the substrate includes a well region, the first gate structure is located on the well region, the first source / drain region, the first lightly doped region and the doped region are located within the well region, the conductivity type of the doped region is opposite to that of the well region, the dopant ion concentration in the doped region is less than the dopant ion concentration in the well region, and the dopant ion concentration in the well region is less than the dopant ion concentration in the first source / drain region.

[0008] Optionally, the depth of the doped region is less than the depth of the first source / drain region.

[0009] Optionally, the doped region includes a first doped region and a second doped region, the first doped region and the second doped region being adjacent to the first source and drain regions on both sides of the first gate structure, respectively; the length of the first doped region is less than the channel length between the first source and drain regions, and the length of the second doped region is less than the channel length between the first source and drain regions.

[0010] Optionally, the ratio of the length of the doped region to the channel length between the first source and drain regions ranges from 0.1 to 0.6.

[0011] Optionally, it further includes: a second gate structure located on the well region; a second lightly doped region located in the well regions on both sides of the second gate structure; and a second source / drain region located in the well regions on both sides of the second gate structure, wherein the second source / drain region is adjacent to the second lightly doped region, and a well region is spaced between adjacent second lightly doped regions, and the channel length between the second source / drain regions is less than the channel length between the first source / drain regions.

[0012] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dummy gate structure, a first lightly doped region located in the substrates on both sides of the first dummy gate structure, and a first source / drain region located in the substrates on both sides of the first dummy gate structure, wherein the first source / drain region is adjacent to the first lightly doped region; forming a dielectric layer on the substrate, wherein the dielectric layer exposes the top surface of the first dummy gate structure; removing the first dummy gate structure and forming a first opening in the dielectric layer, wherein the first opening exposes the substrate surface; performing ion implantation on a portion of the substrate at the bottom of the first opening to form a doped region in the substrate at the bottom of the first opening, wherein the doped region is at least adjacent to the first lightly doped region on one side of the first dummy gate structure, wherein the first lightly doped region is located between the first source / drain region and the doped region, wherein the conductivity type of the doped region is the same as the conductivity type of the first source / drain region, and the doped ion concentration in the doped region is greater than the doped ion concentration in the first lightly doped region.

[0013] Optionally, the doped region includes a first doped region, which is adjacent to a first source / drain region on one side of the first dummy gate structure; forming the first doped region includes: performing a first ion implantation on a portion of the substrate at the bottom of the first opening to form the first doped region; the doped region further includes a second doped region, which is adjacent to the first source / drain regions on both sides of the first dummy gate structure; forming the second doped region includes: performing a second ion implantation on a portion of the substrate at the bottom of the first opening to form the second doped region, wherein the ion implantation directions of the first ion implantation and the second ion implantation are mirror images of each other.

[0014] Optionally, the first ion implantation has a first incident angle, the value of which is the arctangent of the ratio of the height to the width of the first opening; the second ion implantation has a second incident angle, the value of which is the arctangent of the ratio of the height to the width of the first opening; the first incident angle and the second incident angle are the same.

[0015] Optionally, it further includes: forming a first gate structure within the first opening, wherein the doped region is located at the bottom of the first gate structure.

[0016] Optionally, while forming the first dummy gate structure, the method further includes: forming a second dummy gate structure, a second lightly doped region located in the substrate on both sides of the second dummy gate structure, and a second source / drain region located in the substrate on both sides of the second dummy gate structure, wherein the second source / drain region is adjacent to the second lightly doped region, and a well region is spaced between adjacent second lightly doped regions, and the width of the second dummy gate structure is smaller than the width of the first dummy gate structure; while removing the first dummy gate structure to form the first opening, the method further includes: removing the second dummy gate structure, forming a second opening in the dielectric layer, wherein the aspect ratio of the first opening is smaller than the aspect ratio of the second opening; while forming the first gate structure, a second gate structure is also formed in the second opening.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the semiconductor structure of this invention, the doped region is adjacent to at least one first source / drain region on one side. The conductivity type of the doped region is the same as that of the first source / drain region. The doped region can increase the saturation drive current Idsat of the device, thereby improving the switching speed, while avoiding an increase in static power consumption, and thus avoiding an increase in the off-state leakage current (Ioff). Combining this with the DC performance formula, DC performance is the ratio of the saturation drive current (Idsat) to the off-state leakage current (Ioff). Increasing the saturation drive current Idsat while keeping the off-state leakage current Ioff unchanged improves DC performance.

[0018] Furthermore, the conductivity type of the first doped region is opposite to that of the well region, and the dopant ion concentration in the first doped region is lower than that in the well region. Therefore, after the dopant ions in the first doped region neutralize the dopant ions in the first channel region, the entire first channel region containing the first doped region still exhibits the conductivity type of the well region. The first doped region does not change the overall conductivity type of the first channel region and does not affect the device performance. The dopant ions in the first doped region neutralize some of the dopant ions in the first channel region, thereby relatively increasing the carrier concentration in the first channel region, improving the device's saturation drive current Idsat, and thus increasing the device's switching speed.

[0019] The semiconductor structure formation method of the present invention involves ion implantation into a portion of the substrate at the bottom of the first opening to form a doped region within the substrate at the bottom of the first opening. The doped region is at least adjacent to a first source / drain region on one side of a first dummy gate structure, and the conductivity type of the doped region is the same as that of the first source / drain region. The doped region can increase the saturation drive current (Idsat) of the device, thereby improving the switching speed, while avoiding an increase in static power consumption, and thus avoiding an increase in the off-state leakage current (Ioff). According to the DC performance formula, DC performance is the ratio of the saturation drive current (Idsat) to the off-state leakage current (Ioff). An increase in the saturation drive current (Idsat) without a change in the off-state leakage current (Ioff) results in improved DC performance. Attached Figure Description

[0020] Figures 1 to 7 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0021] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figures 1 to 7 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0023] Please refer to Figure 1 A substrate 200 is provided, the substrate 200 including a well region 201, the well region 201 including a first region I and a second region II.

[0024] The well region 201 contains doped ions, and the conductivity type of the doped ions is N-type or P-type; the N-type doped ions include one or more combinations of phosphorus ions, arsenic ions and antimony ions; the P-type doped ions include one or more combinations of boron ions, boron-fluorine ions and indium ions.

[0025] In this embodiment, the well region 201 contains P-type doped ions. The process for forming the well region 201 includes an ion implantation process.

[0026] In this embodiment, the substrate 200 includes a base and a fin structure located on the base, and the well region 201 is located within the fin structure.

[0027] In other embodiments, the substrate is a planar substrate, and the well region is located within the substrate.

[0028] In this embodiment, the substrate 200 is made of single-crystal silicon.

[0029] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0030] Please continue to refer to this. Figure 1 A first pseudo-gate structure 202 is formed on the first region I; a second pseudo-gate structure 205 is formed on the second region II, and the first pseudo-gate structure 202 and the second pseudo-gate structure 205 are formed simultaneously.

[0031] In this embodiment, the first pseudo-gate structure 202 and the second pseudo-gate structure 205 are different. Specifically, the width of the first pseudo-gate structure 202 is greater than the width of the second pseudo-gate structure 205.

[0032] The first dummy gate structure 202 includes: a first dummy gate dielectric layer 2021 located on the first region I and a first dummy gate layer 2022 located on the first dummy gate dielectric layer 2021; the second dummy gate structure 205 includes: a second dummy gate dielectric layer 2051 located on the second region II and a second dummy gate layer 2052 located on the second dummy gate dielectric layer 2051.

[0033] The method for forming the first dummy gate structure 202 and the second dummy gate structure 205 includes: forming a dummy gate dielectric material layer on a substrate 200; forming a dummy gate material layer on the dummy gate dielectric material layer; forming a patterned mask layer on the dummy gate material layer; etching the dummy gate material layer and the dummy gate dielectric material layer using the patterned mask layer as a mask until the surface of the substrate 200 is exposed, forming the first dummy gate structure 202 on the first region I; and forming the second dummy gate structure 205 on the second region II.

[0034] The first dummy gate dielectric layer 2021 and the second dummy gate dielectric layer 2051 are formed by etching the dummy gate dielectric material layer; the first dummy gate layer 2022 and the second dummy gate layer 2052 are formed by etching the dummy gate material layer.

[0035] The material of the pseudo-gate dielectric material layer includes silicon oxide or a low-K (K less than 3.9) material; the material of the pseudo-gate material layer includes polysilicon.

[0036] Please continue to refer to this. Figure 1 A first lightly doped region 220 is formed in the well regions on both sides of the first pseudo-gate structure 202; and a second lightly doped region 221 is formed in the well regions on both sides of the second pseudo-gate structure 205.

[0037] The first lightly doped region 220 and the second lightly doped region 221 are formed simultaneously, and the process for forming the first lightly doped region 220 and the second lightly doped region 221 includes an ion implantation process.

[0038] In this embodiment, a portion of the first lightly doped region 220 extends to the bottom of the first dummy gate structure 202, and a portion of the second lightly doped region 221 extends to the bottom of the second dummy gate structure 205.

[0039] In this embodiment, the conductivity type of the first lightly doped region 220 and the conductivity type of the second lightly doped region 221 are N-type, and N-type ions are present in the first lightly doped region 220 and the second lightly doped region 221.

[0040] In other embodiments, when the well region has an N-type conductivity, the first lightly doped region and the second lightly doped region have a P-type conductivity, and the first lightly doped region and the second lightly doped region contain P-type ions.

[0041] Please refer to Figure 2 A first sidewall 203 is formed on the sidewall of the first pseudo-gate structure 202, and a second sidewall 206 is formed on the sidewall of the second pseudo-gate structure 205.

[0042] In this embodiment, the first sidewall 203 is located on the first lightly doped region 220, and the second sidewall 206 is located on the second lightly doped region 221.

[0043] The first sidewall 203 and the second sidewall 206 are formed simultaneously. The method for forming the first sidewall 203 and the second sidewall 206 includes: forming a sidewall material layer on the surface of the substrate 200, the top surface and sidewall surface of the first dummy gate structure 202, and the top surface and sidewall surface of the second dummy gate structure 205; etching back the sidewall material layer until the surface of the substrate 200 is exposed; forming the first sidewall 203 on the sidewall of the first dummy gate structure 202; and forming the second sidewall 206 on the sidewall of the second dummy gate structure 205.

[0044] The sidewall material layer comprises a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon oxynitride nitride.

[0045] In this embodiment, the material of the sidewall material layer includes silicon nitride.

[0046] Please continue to refer to this. Figure 2 A first source / drain region 204 is formed in the well region 201 on both sides of the first pseudo-gate structure 202. The first source / drain region 204 is adjacent to the first lightly doped region 220. A second source / drain region 207 is formed in the well region 201 on both sides of the second pseudo-gate structure 205. The second source / drain region 207 is adjacent to the second lightly doped region 221.

[0047] The first sidewall 203 is used to define the distance from the first source / drain region 204 to the bottom channel of the first dummy gate structure 202, so that there is a sufficient distance between the first source / drain region 204 and the channel; the second sidewall 206 is used to define the distance from the second source / drain region 207 to the bottom channel of the second dummy gate structure 205, so that there is a sufficient distance between the second source / drain region 207 and the channel.

[0048] In this embodiment, the first source / drain region 204 and the second source / drain region 207 are formed simultaneously. The material of the first source / drain region 204 is the same as that of the second source / drain region 207, and the conductivity type of the material of the first source / drain region 204 is the same as that of the second source / drain region 207.

[0049] In this embodiment, the materials of the first source / drain region 204 and the second source / drain region 207 include silicon phosphorus. The conductivity type of the first source / drain region 204 and the conductivity type of the second source / drain region 207 are N-type, and N-type ions are present in both the first source / drain region 204 and the second source / drain region 207.

[0050] In other embodiments, when the well region has an N-type conductivity, the materials of the first and second source / drain regions include silicon and germanium. The first and second source / drain regions have a P-type conductivity, and both regions contain P-type ions.

[0051] The N-type ions include one or more combinations of phosphorus ions, arsenic ions, and antimony ions; the P-type ions include one or more combinations of boron ions, borofluorine ions, and indium ions.

[0052] The doped ion concentration in the first source / drain region 204 is greater than the doped ion concentration in the well region 201, the doped ion concentration in the first source / drain region 204 is greater than the doped ion concentration in the first lightly doped region 220, the doped ion concentration in the second source / drain region 207 is greater than the doped ion concentration in the well region 201, and the doped ion concentration in the second source / drain region 207 is greater than the doped ion concentration in the second lightly doped region 221.

[0053] In this embodiment, the conductivity type of the first source / drain region 204 is the same as that of the first lightly doped region 220, and the depth of the first source / drain region 204 is greater than that of the first lightly doped region 220; the conductivity type of the second source / drain region 207 is the same as that of the second lightly doped region 221, and the depth of the second source / drain region 207 is the same as that of the second lightly doped region 221.

[0054] In this embodiment, the method for forming the first source / drain region 204 and the second source / drain region 207 includes: etching the well region 201, forming a first groove in the well region 201 on both sides of the first dummy gate structure 202, and forming a second groove in the well region 201 on both sides of the second dummy gate structure 205; epitaxially growing the first source / drain region 204 inside and outside the first groove, and epitaxially growing the second source / drain region 207 inside and outside the second groove.

[0055] The first source / drain region 204 and the second source / drain region 207 contain N-type ions. When the first source / drain region 204 and the second source / drain region 207 are formed by epitaxial growth process, the first source / drain region 204 and the second source / drain region 207 are in-situ doped with N-type ions by in-situ doping process.

[0056] In other embodiments, after forming the first source / drain region and the second source / drain region, the method further includes: performing N-type ion implantation on the first source / drain region and the second source / drain region.

[0057] In other embodiments, the materials of the first source / drain region and the second source / drain region include silicon; the method of forming the first source / drain region and the second source / drain region includes: ion implantation of the well regions on both sides of the first dummy gate structure to form the first source / drain region; and ion implantation of the well regions on both sides of the second dummy gate structure to form the second source / drain region.

[0058] Please refer to Figure 3 A dielectric layer 208 is formed on a substrate 200, the dielectric layer 208 exposing the top surface of the first dummy gate structure 202 and the top surface of the second dummy gate structure 205.

[0059] The method for forming the dielectric layer 208 includes: forming a dielectric material layer (not shown) on a substrate 200, the top surface of the first dummy gate structure 202 and the sidewall of the first sidewall 203, the top surface of the second dummy gate structure 205 and the sidewall of the second sidewall 206; planarizing the dielectric material layer until the top surface of the first dummy gate structure 202 and the surface of the second dummy gate structure 205 are exposed, thereby forming the dielectric layer 208.

[0060] The dielectric layer 208 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon oxynitride, and silicon oxycarbide. The process for forming the dielectric material layer includes chemical vapor deposition or atomic layer deposition.

[0061] In this embodiment, the dielectric layer 208 is made of silicon oxide; the process for forming the dielectric material layer includes chemical vapor deposition (CVD). CVD can rapidly form a dense and thick dielectric material layer.

[0062] In this embodiment, the process for planarizing the dielectric material layer includes a chemical mechanical polishing process.

[0063] Please refer to Figure 4 Remove the first pseudo-gate structure 202 and the second pseudo-gate structure 205, form a first opening 209 in the dielectric layer 208 of the first region I, and form a second opening 210 in the dielectric layer 208 of the second region II.

[0064] The first pseudo-gate structure 202 and the second pseudo-gate structure 205 are removed simultaneously in one process. The method for removing the first pseudo-gate structure 202 and the second pseudo-gate structure 205 includes: removing the first pseudo-gate layer 2022 and the second pseudo-gate layer 2052; after removing the first pseudo-gate layer 2022 and the second pseudo-gate layer 2052, removing the first pseudo-gate dielectric layer 2021 and the second pseudo-gate dielectric layer 2051.

[0065] The process for removing the first dummy gate layer 2022 and the second dummy gate layer 2052 includes a combination of one or more of the following: dry etching and wet etching. The process for removing the first dummy gate layer 2022 and the second dummy gate layer 2052 causes less damage to the first sidewall 203 and the second sidewall 206, and the process for removing the first dummy gate dielectric layer 2021 and the second dummy gate dielectric layer 2051 causes less damage to the first sidewall 203 and the second sidewall 206.

[0066] The process for removing the first dummy gate dielectric layer 2021 and the second dummy gate dielectric layer 2051 includes a wet etching process. The process for removing the first dummy gate dielectric layer 2021 and the second dummy gate dielectric layer 2051 causes minimal damage to the first sidewall 203 and the second sidewall 206.

[0067] In this embodiment, the width of the first pseudo-gate structure 202 is greater than the width of the second pseudo-gate structure 205, the well region 201 at the bottom of the first pseudo-gate structure 202 is the first channel region, the well region 201 at the bottom of the second pseudo-gate structure 205 is the second channel region, and the length of the first channel region is greater than the length of the second channel region.

[0068] The length of the first channel region is the distance d1 between the first source and drain regions 204 on both sides of the first pseudo-gate structure 202, and the length of the second channel region is the distance d2 between the second source and drain regions 207 on both sides of the second pseudo-gate structure 205, where d1 is greater than d2.

[0069] In this embodiment, the aspect ratio of the first opening 209 is smaller than that of the second opening 210.

[0070] In this embodiment, the first pseudo-gate structure 202 and the second pseudo-gate structure 205 are formed simultaneously, and the first pseudo-gate structure 202 and the second pseudo-gate structure 205 have the same height, so the first opening 209 and the second opening 210 have the same height h.

[0071] Next, ion implantation is performed on a portion of the well region 201 at the bottom of the first opening 209 to form a doped region, which is adjacent to at least one of the first source / drain regions 204. For the process of forming the doped region, please refer to [link to documentation]. Figure 5 and Figure 6 .

[0072] In this embodiment, the doped region includes a first doped region and a second doped region.

[0073] Please refer to Figure 5 A first ion implantation is performed on a portion of the well region 201 at the bottom of the first opening 209 at a first incident angle α1 to form a first doped region 211.

[0074] The first incident angle α1 is the angle between the ion implantation direction and the first normal L1. The first normal L1 is perpendicular to the surface of the substrate 200, that is, the first normal L1 is the end face normal of the first opening 209.

[0075] The first incident angle α1 = arc tan(h / d1), where h is the height of the first opening 209, i.e., the thickness of the dielectric layer 208 (reference). Figure 3 ), d1 is the width of the first opening 209, that is, the length of the first channel region (refer to...). Figure 3 The first incident angle α1 is the angle between the incident direction and the normal to the end face of the first opening 209. The value of the first incident angle α1 is the arctangent of the ratio of the height to the width of the first opening 209.

[0076] In this embodiment, the first incident angle α1 is greater than α, and the first incident angle α1 is greater than β. Where α = arc tan d² / h, that is, α is determined by the height h and width d² of the second opening 210, and β = arc tan 0.5 d1 / h, i.e., β, is determined by the height h and width d1 of the first opening 209. The first incident angle α1 is greater than α to ensure that the region of the first ion implantation will not be implanted into the second channel region; the first incident angle α1 is greater than β to ensure that the region of the first ion implantation is smaller than the length of the entire first channel region.

[0077] A first ion implantation is performed on a portion of the well region 201 at the bottom of the first opening 209 using the arctangent of the ratio of the height to the width of the first opening 209 as the first incident angle α1. This results in a first doped region 211 forming close to a first lightly doped region 220 on one side. The first lightly doped region 220 is located between the first doped region 211 and the first source / drain region 204, in the middle region away from the first channel region. In this embodiment, while performing the first ion implantation on the portion of the well region 201 at the bottom of the first opening 209 using the first incident angle α1, the bottom of the second opening 210 is also implanted with the first ion implantation using the same first incident angle α1. Since the width d2 of the second opening 210 is smaller than the width d1 of the first opening 209, and the aspect ratio of the second opening 210 is greater than that of the first opening 209, when the second opening 210 is implanted with the first incident angle α1, the implanted ions cannot reach the well region 201 at the bottom of the second opening 210 due to the obstruction of the sidewall of the second opening 210. Therefore, a doped region will not be formed in the well region 201 at the bottom of the second opening 210, and the device performance on the second region II will not be affected.

[0078] In this embodiment, the conductivity type of the first doped region 211 is the same as that of the first source / drain region 204, and the conductivity type of the first doped region 211 is opposite to that of the well region 201.

[0079] In this embodiment, the first source / drain region 204 has an N-type conductivity, the first doped region 211 has an N-type conductivity, and the implanted ions for the first ion implantation of the portion of the well region 201 at the bottom of the first opening 209 are N-type ions, which include one or more combinations of phosphorus ions, arsenic ions, and antimony ions.

[0080] In other embodiments, the first source / drain region is P-type in conductivity, the first doped region is P-type in conductivity, and the implanted ions for the first ion implantation of a portion of the well region at the bottom of the first opening are P-type ions, wherein the P-type ions include one or more combinations of boron ions, boron-fluorine ions, and indium ions.

[0081] In this embodiment, the doped ion concentration in the first doped region 211 is less than the doped ion concentration in the first source / drain region 204, and the doped ion concentration in the first doped region 211 is less than the doped ion concentration in the well region 201. The doped ion concentration in the first doped region 211 is less than or equal to twice the doped ion concentration in the first lightly doped region 220.

[0082] The conductivity type of the first doped region 211 is opposite to that of the well region 201, and the dopant ion concentration in the first doped region 211 is lower than that in the well region 201. Therefore, after the dopant ions in the first doped region 211 neutralize the dopant ions in the first channel region, the entire first channel region containing the first doped region 211 still exhibits the conductivity type of the well region 201. The first doped region 211 does not change the overall conductivity type of the first channel region and does not affect the device performance. The dopant ions in the first doped region 211 neutralize some of the dopant ions in the first channel region, thereby relatively increasing the carrier concentration in the first channel region, improving the device's saturation drive current Idsat, and thus improving the device's switching speed.

[0083] The first doped region 211 is located near the first source / drain region 204 on one side, away from the middle region of the first channel region. This allows for improved switching speed while avoiding increased static power consumption, and consequently, avoiding an increase in the off-state leakage current (Ioff). According to the DC performance formula, DC performance is the ratio of saturated drive current (Idsat) to off-state leakage current (Ioff). An increase in the saturated drive current (Idsat) without a change in the off-state leakage current (Ioff) results in improved DC performance.

[0084] In this embodiment, the depth of the first doped region 211 is less than the depth of the first source / drain region 204.

[0085] Please refer to Figure 6 A second ion implantation is performed on a portion of the well region 201 at the bottom of the first opening 209 at a second incident angle α2 to form a second doped region 212.

[0086] The second incident angle α2 is the angle between the ion implantation direction and the first normal L1. The first normal L1 is perpendicular to the surface of the substrate 200, that is, the first normal L1 is the end face normal of the first opening 209.

[0087] In this embodiment, the ion implantation direction of the second ion implantation is a mirror image of the ion implantation direction of the first ion implantation, and the angle of the first incident angle α1 is the same as the angle of the second incident angle α2.

[0088] The second incident angle α2 = arc tan(h / d1), where h is the height of the first opening 209, i.e., the thickness of the dielectric layer 208 (reference). Figure 3 ), d1 is the width of the first opening 209, that is, the length of the first channel region (refer to...). Figure 3 The second incident angle α2 is the angle between the incident direction and the normal to the end face of the first opening 209. The value of the second incident angle α2 is the arctangent of the ratio of the height to the width of the first opening 209.

[0089] In other embodiments, the angle of the first incident angle α1 may be different from the angle of the second incident angle α2.

[0090] In this embodiment, the second incident angle α2 is greater than α, and the second incident angle α2 is greater than β. Where α = arc tan d2 / h, that is, α is determined by the height h and width d2 of the second opening 210, and β = arc tan 0.5 d1 / h, i.e., β, is determined by the height h and width d1 of the first opening 209. The second incident angle α2 is greater than α to ensure that the region of the second ion implantation will not be implanted into the second channel region; the second incident angle α2 is greater than β to ensure that the region of the second ion implantation is smaller than the length of the entire first channel region.

[0091] Using the arctangent of the ratio of the height to the width of the first opening 209 as the second incident angle α2, a second ion implantation is performed on a portion of the well region 201 at the bottom of the first opening 209, so that the formed second doped region 212 is close to the first lightly doped region 220 on the other side. The first lightly doped region 220 is located between the second doped region 212 and the first source / drain region 204, away from the middle region of the first channel region. The second doped region 212 and the first doped region 211 are respectively adjacent to the first source / drain regions 204 on both sides, located on both sides of the middle region of the first channel region.

[0092] In this embodiment, when performing a second ion implantation on a portion of the well region 201 at the bottom of the first opening 209 at a second incident angle α2, a second ion implantation is also performed on the bottom of the second opening 210 at the same second incident angle α2. Since the width d2 of the second opening 210 is smaller than the width d1 of the first opening 209, and the aspect ratio of the second opening 210 is greater than that of the first opening 209, when performing a second ion implantation on the second opening 210 at the second incident angle α2, the implanted ions cannot reach the well region 201 at the bottom of the second opening 210 due to the obstruction of the sidewalls of the second opening 210. Therefore, a doped region will not form within the well region 201 at the bottom of the second opening 210, and the device performance on the second region II will not be affected.

[0093] In this embodiment, the conductivity type of the second doped region 212 is the same as that of the first source / drain region 204, and the conductivity type of the second doped region 212 is opposite to that of the well region 201.

[0094] In this embodiment, the first source / drain region 204 has an N-type conductivity, the second doped region 212 has an N-type conductivity, and the implanted ions for the second ion implantation of the portion of the well region 201 at the bottom of the first opening 209 are N-type ions, which include one or more combinations of phosphorus ions, arsenic ions, and antimony ions.

[0095] In other embodiments, the first source / drain region is P-type, the second doped region is P-type, and the implanted ions for the second ion implantation of a portion of the well region at the bottom of the first opening are P-type ions, wherein the P-type ions include one or more combinations of boron ions, boron-fluorine ions, and indium ions.

[0096] In this embodiment, the doped ion concentration in the second doped region 212 is less than the doped ion concentration in the first source / drain region 204, and the doped ion concentration in the second doped region 212 is less than the doped ion concentration in the well region 201. The doped ion concentration in the second doped region 212 is less than or equal to twice the doped ion concentration in the first lightly doped region 220.

[0097] The conductivity type of the second doped region 212 is opposite to that of the well region 201, and the dopant ion concentration in the second doped region 212 is lower than that in the well region 201. Therefore, after the dopant ions in the second doped region 212 neutralize the dopant ions in the first channel region, the entire first channel region containing the second doped region 212 still exhibits the conductivity type of the well region 201. The second doped region 212 does not change the overall conductivity type of the first channel region and does not affect the device performance. The dopant ions in the second doped region 212 neutralize some of the dopant ions in the first channel region, thereby relatively increasing the carrier concentration in the first channel region, improving the device's saturation drive current Idsat, and thus improving the device's switching speed.

[0098] The second doped region 212 is located near the first source / drain region 204 on the other side. The first doped region 211 and the second doped region 212 are located away from the middle region of the first channel region. This allows for maximizing switching speed while avoiding increased static power consumption, and consequently, preventing an increase in off-state leakage current (Ioff). According to the DC performance formula, DC performance is the ratio of saturated drive current (Idsat) to off-state leakage current (Ioff). An increase in saturated drive current (Idsat) without a change in off-state leakage current (Ioff) results in improved DC performance.

[0099] In this embodiment, the length of the second doped region 212 is the same as the length of the first doped region 211.

[0100] The sum of the length of the second doped region 212 and the length of the first doped region 211 is L, where L = (2d1 - 2H tanα1) / d1, and L ranges from 0.1 to 0.6, i.e., 0.1 ≤ (2d1 - 2H tanα1) / d1 ≤ 0.6.

[0101] In this embodiment, the depth of the second doped region 212 is less than the depth of the first source / drain region 204.

[0102] In this embodiment, the implanted ions of the first ion implantation and the second ion implantation have the same conductivity type, the same type of implanted ions, and the same dosage, so that the doped ion concentrations of the first doped region 211 and the second doped region 212 are the same, and the first doped region 211 and the second doped region 212 are symmetrically distributed on both sides of the middle region of the first channel region, thereby maximizing the switching speed and increasing the saturation drive current Idsat.

[0103] In another embodiment, the types of implanted ions in the first ion implantation and the second ion implantation can be different, and the dopant ion concentrations in the first doped region and the second doped region are the same.

[0104] In another embodiment, the dopant ion concentrations of the first doped region and the second doped region can be different.

[0105] In other embodiments, the first ion implantation and the second ion implantation can be selectively chosen to form only the first doped region or the second doped region. The ratio of the length of the first doped region or the second doped region to the length of the first channel region ranges from 0.1 to 0.6.

[0106] Please refer to Figure 7 A first gate structure 213 is formed in the first opening 209, and a second gate structure 214 is formed in the second opening 210.

[0107] The first gate structure 213 includes: a first gate dielectric layer (not shown) located on the sidewall surface and bottom surface of the first opening 209 and a first gate layer (not shown) located on the first gate dielectric layer.

[0108] In other embodiments, the first gate structure further includes a first work function layer (not shown), which is located between the first gate dielectric layer and the first gate layer.

[0109] The second gate structure 214 includes: a second gate dielectric layer (not shown) located on the sidewall surface and bottom surface of the second opening 210 and a second gate layer (not shown) located on the second gate dielectric layer.

[0110] In other embodiments, the second gate structure further includes a second work function layer (not shown), which is located between the second gate dielectric layer and the second gate layer.

[0111] The first gate structure 213 and the second gate structure 214 are formed simultaneously. The method for forming the first gate structure 213 and the second gate structure 214 includes: forming a gate dielectric material layer on the sidewall surface and bottom surface of the first opening 209, on the dielectric layer 208, and on the sidewall surface and bottom surface of the second opening 210; forming a gate material layer on the gate dielectric material layer, wherein the gate material layer fills the first opening 209 and the second opening 210; planarizing the gate material layer and the gate dielectric material layer until the surface of the dielectric layer 208 is exposed; forming the first gate structure 213 in the first opening 209 and forming the second gate structure 214 in the second opening 210.

[0112] The gate dielectric material layer is a high-k (K greater than 3.9) dielectric material, including hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide; LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, nitrides, or other suitable materials.

[0113] The gate material layer is made of a metal, including tungsten; the first work function layer is made of one or more combinations of N-type and P-type work function materials; the second work function layer is made of one or more combinations of N-type and P-type work function materials, wherein the N-type work function material is titanium aluminum, and the P-type work function material is titanium nitride or tantalum nitride.

[0114] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 7 ,include: Substrate 200; A first gate structure 213 located on substrate 200; The first lightly doped region 220 is located within the substrate 200 on both sides of the first gate structure 213; The first source / drain region 204 is located in the substrate 200 on both sides of the first gate structure 213, and the first source / drain region 204 is adjacent to the first lightly doped region 220. A doped region is located within the bottom substrate 200 of the first gate structure 213. The doped region is adjacent to at least one lightly doped region 220 on one side of the first gate structure 213. The first lightly doped region 220 is located between the first source / drain region 204 and the doped region. The conductivity type of the doped region is the same as that of the first source / drain region 204. The conductivity type of the doped region is the same as that of the first lightly doped region 220. The doped ion concentration in the doped region is greater than that in the first lightly doped region 220.

[0115] In the semiconductor structure, the doped region is adjacent to at least one of the first source / drain regions 204. The conductivity type of the doped region is the same as that of the first source / drain region 204. The doped region can increase the saturation drive current (Idsat) of the device, thereby improving the switching speed, while avoiding an increase in static power consumption, and thus avoiding an increase in the off-state leakage current (Ioff). According to the DC performance formula, DC performance is the ratio of the saturation drive current (Idsat) to the off-state leakage current (Ioff). An increase in the saturation drive current (Idsat) without a change in the off-state leakage current (Ioff) results in improved DC performance.

[0116] In this embodiment, the concentration of doped ions in the doped region is less than the concentration of doped ions in the first source / drain region 204.

[0117] In this embodiment, the concentration of doped ions in the doped region is less than or equal to twice the concentration of doped ions in the first lightly doped region 220.

[0118] In this embodiment, the substrate 200 includes a well region 201, the first gate structure 213 is located on the well region 201, the first source / drain region 204, the first lightly doped region 220 and the doped region are located within the well region 201, the conductivity type of the doped region is opposite to that of the well region 201, and the dopant ion concentration in the doped region is less than that in the well region 201.

[0119] In this embodiment, the doped ion concentration in the well region 201 is less than the doped ion concentration in the first source / drain region 204.

[0120] In this embodiment, the system further includes: a second gate structure 214 located on the well region 201; a second lightly doped region 221 located in the well regions 201 on both sides of the second gate structure 214; and a second source / drain region 207 located in the well regions 201 on both sides of the second gate structure 214. The second source / drain region 207 is adjacent to the second lightly doped region 221, and a well region 201 is spaced between adjacent second lightly doped regions 221. The channel length between the second source / drain regions 207 is less than the channel length between the first source / drain regions 204, that is, the length d1 of the first channel region is greater than the length d2 of the second channel region.

[0121] In this embodiment, the depth of the doped region is less than the depth of the first source / drain region.

[0122] In this embodiment, the doped region includes a first doped region 211 and a second doped region 212, and the first doped region 211 and the second doped region 212 are adjacent to the first source and drain regions 204 on both sides of the first gate structure 213, respectively.

[0123] In this embodiment, the length of the first doped region 211 is less than the channel length between the first source and drain regions 204, and the length of the second doped region 212 is less than the channel length between the first source and drain regions 204.

[0124] In this embodiment, the ratio of the length of the doped region to the channel length between the first source and drain regions ranges from 0.1 to 0.6.

[0125] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The first gate structure located on the substrate; The first lightly doped region is located in the substrate on both sides of the first gate structure; The first source / drain regions are located in the substrates on both sides of the first gate structure, and the first source / drain regions are adjacent to the first lightly doped region. A doped region located within the substrate at the bottom of the first gate structure, the doped region being adjacent at least to a first lightly doped region on one side of the first gate structure, the first lightly doped region being located between the first source / drain region and the doped region, the conductivity type of the doped region being the same as that of the first source / drain region, the conductivity type of the doped region being the same as that of the first lightly doped region, and the dopant ion concentration in the doped region being greater than that in the first lightly doped region.

2. The semiconductor structure as described in claim 1, characterized in that, The concentration of doped ions in the doped region is less than the concentration of doped ions in the first source / drain region; the concentration of doped ions in the doped region is less than or equal to twice the concentration of doped ions in the first lightly doped region.

3. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a well region, the first gate structure is located on the well region, the first source / drain region, the first lightly doped region and the doped region are located within the well region, the conductivity type of the doped region is opposite to that of the well region, the dopant ion concentration in the doped region is less than the dopant ion concentration in the well region, and the dopant ion concentration in the well region is less than the dopant ion concentration in the first source / drain region.

4. The semiconductor structure as described in claim 1, characterized in that, The depth of the doped region is less than the depth of the first source / drain region.

5. The semiconductor structure as described in claim 1, characterized in that, The doped region includes a first doped region and a second doped region, which are respectively adjacent to the first source and drain regions on both sides of the first gate structure; the length of the first doped region is less than the channel length between the first source and drain regions, and the length of the second doped region is less than the channel length between the first source and drain regions.

6. The semiconductor structure as described in claim 1, characterized in that, The ratio of the length of the doped region to the channel length between the first source and drain regions ranges from 0.1 to 0.

6.

7. The semiconductor structure as described in claim 3, characterized in that, Also includes: A second gate structure located on a well region; a second lightly doped region located in the well regions on both sides of the second gate structure; a second source / drain region located in the well regions on both sides of the second gate structure, wherein the second source / drain region is adjacent to the second lightly doped region, and a well region is spaced between adjacent second lightly doped regions, and the channel length between the second source / drain regions is less than the channel length between the first source / drain regions.

8. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first pseudo-gate structure, a first lightly doped region located in the substrate on both sides of the first pseudo-gate structure, and a first source / drain region located in the substrate on both sides of the first pseudo-gate structure are formed on the substrate, wherein the first source / drain region is adjacent to the first lightly doped region. A dielectric layer is formed on the substrate, the dielectric layer exposing the top surface of the first dummy gate structure; Remove the first dummy gate structure and form a first opening in the dielectric layer, the first opening exposing the substrate surface; Ion implantation is performed on a portion of the substrate at the bottom of the first opening to form a doped region within the substrate at the bottom of the first opening. The doped region is at least adjacent to a first lightly doped region on one side of the first pseudo-gate structure. The first lightly doped region is located between the first source / drain region and the doped region. The conductivity type of the doped region is the same as that of the first source / drain region. The doped ion concentration in the doped region is greater than that in the first lightly doped region.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The doped region includes a first doped region, which is adjacent to a first lightly doped region on one side of the first pseudo-gate structure. Forming the first doped region includes: performing a first ion implantation on a portion of the substrate on one side of the bottom of the first opening to form the first doped region; the doped region further includes a second doped region, the first doped region and the second doped region being adjacent to the first lightly doped regions on both sides of the first pseudo-gate structure; forming the second doped region includes: performing a second ion implantation on a portion of the substrate on the other side of the bottom of the first opening to form the second doped region, the ion implantation directions of the first ion implantation and the second ion implantation being mirror images of each other.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first ion implantation has a first incident angle, which is the arctangent of the ratio of the height to the width of the first opening; the second ion implantation has a second incident angle, which is the arctangent of the ratio of the height to the width of the first opening; the first incident angle and the second incident angle are the same.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: A first gate structure is formed within the first opening, and the doped region is located at the bottom of the first gate structure.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, While forming the first dummy gate structure, the method further includes: forming a second dummy gate structure on the substrate, a second lightly doped region located in the substrate on both sides of the second dummy gate structure, and a second source / drain region located in the substrate on both sides of the second dummy gate structure. The second source / drain region is adjacent to the second lightly doped region, and a well region is spaced between adjacent second lightly doped regions. The width of the second dummy gate structure is smaller than the width of the first dummy gate structure. While removing the first dummy gate structure to form the first opening, the method further includes: removing the second dummy gate structure and forming a second opening in the dielectric layer. The aspect ratio of the first opening is smaller than the aspect ratio of the second opening. While forming the first gate structure, a second gate structure is also formed in the second opening.

Images