Trench power semiconductor structure, method of manufacture and power chip

Abstract

This application discloses a trench-type power semiconductor structure, its fabrication method, and a power chip, belonging to the field of power semiconductor technology. The trench-type power semiconductor structure includes: a semiconductor body comprising a first surface, a first region, and a buried region; a gate trench is provided on the first surface, extending from the first surface into the semiconductor body; the buried region is located on the side of the first region away from the first surface and is in contact with the first region; and a gate structure is located within the gate trench; wherein, a first orthographic projection of the buried region on the first surface at least partially overlaps with a second orthographic projection of the first region on the first surface, and does not completely overlap with a third orthographic projection of the gate trench on the first surface; the conductivity type of the buried region is the same as that of the first region. This reduces the electric field strength experienced by the gate structure at the bottom of the gate trench, improving device reliability.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor technology, and particularly relates to a trench-type power semiconductor structure, fabrication method and power chip. Background Technology

[0002] Existing trench MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have a strong gate oxide electric field in the blocking state, which is not well protected by the gate dielectric layer (or gate oxide layer), affecting the long-term reliability of the device. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a trench-type power semiconductor structure, a fabrication method, and a power chip, which reduces the electric field strength borne by the gate structure at the bottom of the gate trench and improves device reliability.

[0004] In a first aspect, this application provides a trench-type power semiconductor structure, comprising: The semiconductor body includes a first surface, a first region, a buried region, and a drift region. The first surface is provided with a gate trench, the drift region is located on the side of the gate trench away from the first surface, the first region is provided on the first surface, the gate trench extends from the first surface into the semiconductor body, and the buried region is located on the side of the first region away from the first surface, and the buried region is arranged in contact with the first region. The gate structure is located within the gate trench; Wherein, the first orthographic projection of the buried region on the first surface at least partially overlaps with the second orthographic projection of the first region on the first surface, and does not completely overlap with the third orthographic projection of the gate trench on the first surface. The third orthographic projection is located within the fourth orthographic projection of the drift region on the first surface. The conductivity type of the buried region is the same as that of the first region, and the conductivity type of the drift region is opposite to that of the buried region. The difference between the doping concentration of the drift region near the gate trench and the doping concentration of the region far from the gate trench is greater than a reference difference.

[0005] According to one embodiment of this application, the doping concentration of the drift region near the gate trench is greater than the doping concentration of the region away from the gate trench.

[0006] According to one embodiment of this application, the drift region includes multiple drift layers, wherein the doping concentration of the drift layer near the gate trench is greater than the doping concentration of the drift layer away from the gate trench.

[0007] According to one embodiment of this application, the bottom of the gate trench extends into the drift region, and the distance between the bottom surface of the gate trench and the first surface is greater than the distance between the buried region and the first surface.

[0008] According to one embodiment of this application, the drift region is located between the buried regions on both sides of the gate trench, and the distance between the drift region and the first surface is equal to the distance between the drift region and the first surface.

[0009] According to one embodiment of this application, the buried regions on both sides of the gate trench are arranged symmetrically.

[0010] According to one embodiment of this application, the doping concentration in the buried area near the first region is less than the doping concentration in the area away from the first region 32.

[0011] According to one embodiment of this application, the first orthographic projection and the third orthographic projection do not overlap, and the distance between the first orthographic projection and the third orthographic projection is smaller than the distance between the second orthographic projection and the third orthographic projection.

[0012] According to one embodiment of this application, the semiconductor body further includes a second surface opposite to the first surface, and a current spreading layer, a first base layer and a second base layer stacked sequentially between the first region and the gate trench, wherein the side surface of the second base layer away from the first base layer is disposed on the first surface; Trench-type power semiconductor structures also include: An interlayer dielectric layer is disposed on the first surface and covers the gate trench; A source electrode is disposed on the first surface, the source electrode covers the interlayer dielectric layer, and is arranged in contact with the first region; The drain electrode is disposed on the second surface; The conductivity type of the current spreading layer is the same as that of the second base layer; the conductivity type of the first base layer is the same as that of the first region; and the conductivity type of the first base layer is opposite to that of the second base layer.

[0013] Secondly, this application provides a method for fabricating a trench-type power semiconductor structure, comprising: A first epitaxial layer is provided, and a drift region and a buried region located on both sides of the drift region are formed in the first epitaxial layer, wherein the conductivity type of the drift region is opposite to that of the buried region; A second epitaxial layer is formed on the first epitaxial layer; A gate trench and a first region are formed on the first surface of the second epitaxial layer on the side away from the first epitaxial layer. The first orthographic projection of the buried region on the first surface at least partially overlaps with the second orthographic projection of the first region on the first surface, and does not completely overlap with the third orthographic projection of the gate trench on the first surface. The buried region is arranged in contact with the first region. The third orthographic projection is located within the fourth orthographic projection of the drift region on the first surface. The conductivity type of the buried region is the same as that of the first region. The difference between the doping concentration of the drift region on the side closer to the gate trench and the doping concentration on the side farther from the gate trench is greater than a reference difference. A gate structure is formed within the gate trench.

[0014] According to one embodiment of this application, the first epitaxial layer includes a first drift layer and multiple second drift layers, wherein a drift region and a burial region located on both sides of the drift region are formed in the first epitaxial layer, including: Provide the first drift layer; Multiple second drift layers are formed on the first drift layer, and the difference between the doping concentration of the second drift layer close to the first drift layer and the doping concentration of the second drift layer far from the first drift layer is greater than a reference difference. Inverse particle injection is performed on the first drift layer and each of the second drift layers to form spaced-apart burial zones, and the second drift layers between the burial zones form drift zones.

[0015] According to one embodiment of this application, a second epitaxial layer is formed on the first epitaxial layer, including: A current spreading layer is formed on the first epitaxial layer, and the conductivity type of the current spreading layer is opposite to that of the buried area. Inversion particle implantation is performed on the side of the current spread layer away from the first epitaxial layer to form the first base layer, and the conductivity type of the first base layer is opposite to that of the current spread layer. Inverted particle injection is performed on the side of the first layer away from the current spread layer to form a second layer, and the conductivity type of the first layer is opposite to that of the second layer.

[0016] Thirdly, this application provides a power chip, including the trench-type power semiconductor structure described above, or including the trench-type power semiconductor structure prepared according to the aforementioned preparation method.

[0017] According to the trench-type power semiconductor structure, fabrication method, and power chip of this application, by setting a buried region that is connected to the first region, the electric field strength in the semiconductor body is reduced when the device is in a blocked state, thereby reducing the electric field strength borne by the gate structure at the bottom of the gate trench and improving the device reliability.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the structural schematic diagrams of the trench-type power semiconductor structure provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the trench-type power semiconductor structure provided in the embodiments of this application; Figure 3 This is the third schematic diagram of the trench-type power semiconductor structure provided in the embodiments of this application; Figure 4 This is a schematic flowchart of the fabrication method of the trench-type power semiconductor structure provided in the embodiments of this application; Figures 5-13 These are one to nine of the stage structures in the preparation method provided in the embodiments of this application.

[0020] Figure label: Semiconductor body 10, first epitaxial layer 11, second epitaxial layer 12, buried region 21, drift region 22, drift layer 23, first drift layer 24, second drift layer 25, gate trench 31, gate dielectric layer 37, gate electrode 38, first region 32, gate structure 33, current spreading layer 34, first base layer 35, second base layer 36, interlayer dielectric layer 40, source electrode 50, drain electrode 60. Detailed Implementation

[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0022] Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. The objects distinguished by "first," "second," etc., are generally of the same class and do not limit the number of objects; for example, the first object may be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0023] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] Reference Figure 1 , Figure 1 This is one of the structural schematic diagrams of the trench power semiconductor structure provided in the embodiments of this application. One embodiment of this application proposes a trench power semiconductor structure.

[0025] In this embodiment, the trench-type power semiconductor structure includes a semiconductor body 10 and a gate structure 33. The semiconductor body 10 includes a first surface S1, a first region 32, a buried region 21, and a drift region 22. The first surface S1 is provided with a gate trench 31, which extends from the first surface S1 into the semiconductor body 10. The buried region 21 is located on the side of the first region 32 away from the first surface S1, and the buried region 21 is arranged in contact with the first region 32. The drift region 22 is located on the side of the gate trench 31 away from the first surface S1. The gate structure 33 is located in the gate trench 31. The first orthographic projection of the buried region 21 on the first surface S1 at least partially overlaps with the second orthographic projection of the first region 32 on the first surface S1, and does not completely overlap with the third orthographic projection of the gate trench 31 on the first surface S1. The third orthographic projection is located within the fourth orthographic projection of the drift region 22 on the first surface S1. The conductivity type of the buried region 21 is the same as that of the first region 32, and the conductivity type of the drift region 22 is opposite to that of the buried region 21. The difference between the doping concentration of the drift region 22 on the side closer to the gate trench 31 and the doping concentration on the side farther from the gate trench 31 is greater than the reference difference.

[0026] The semiconductor body 10 can be made of SiC (silicon carbide) material, which has good electrical conductivity and mechanical strength. Different regions are doped with different particles to form P-type or N-type regions. Of course, the semiconductor body 10 can also be made of materials such as GaN (gallium nitride) or AlN (aluminum nitride).

[0027] As an example, if the conductivity type of the main body of the semiconductor body 10 can be N-type, then the first region 32 and the buried region 21 can be P-type. The doping concentration of the first region 32 can be greater than the doping concentration of the buried region 21; for example, the first region 32 can be a P+ region and the buried region 21 can be a P region. Of course, the above conductivity types can also be designed in reverse.

[0028] The buried region 21 is arranged in contact with the first region 32 and has the same conductivity type. The two regions have good electrical continuity and carrier transport characteristics. The potential of the buried region 21 is basically the same as that of the first region 32, and the buried region 21 forms a PN junction with the epitaxial layer 20.

[0029] As an example, the doping concentration in buried region 21 can range from 2e14 cm⁻¹. -3 ~1e15cm -3 The thickness of the burial area 21 can range from 1.5um to 2um.

[0030] For example, the doping concentration of buried region 21 can be 2e14 cm⁻¹. -3 5e14 cm -3 8e14 cm -3Or 1e15cm -3 The thickness of the burial area 21 can be 1.5um, 1.7um, 1.9um, or 2um, etc.

[0031] In the semiconductor body 10, both the first region 32 and the gate trench 31 are arranged close to the first surface S1, while the buried region 21 is located in the first region 32 and away from the first surface S1. The buried region 21 can adjust the electric field distribution in the region below the gate trench 31 within the semiconductor body 10. In the blocking state, the buried region 21 and the region below the gate trench 31 form a JFET effect (junction field-effect transistor effect), thereby reducing the electric field strength at the bottom of the gate structure 33.

[0032] In this embodiment, a drift region 22 with a gradually varying doping concentration is formed in the region of the epitaxial layer 20 located below the gate trench 31. Taking the main body of the semiconductor body 10 as an example, there is a certain difference between the doping concentration of N-type particles in the drift region 22 near the gate trench 31 and the doping concentration of N-type particles in the region away from the gate trench 31.

[0033] By setting a gradient-doped drift region 22, a JFET effect can be generated with the buried region 21 to reduce the electric field strength below the gate structure 33, while simultaneously reducing the on-resistance and improving reliability.

[0034] According to the trench-type power semiconductor structure of this embodiment, by providing a buried region 21 in the semiconductor body 10 that is in contact with and connected to the first region 32, a JFET effect is formed in the region below the gate trench 31 in the semiconductor body 10 when the device is in a blocked state, thereby reducing the electric field strength borne by the gate structure 33 at the bottom of the gate trench 31 and improving the reliability of the device.

[0035] In some embodiments, the doping concentration of the drift region 22 near the gate trench 31 is greater than the doping concentration of the region away from the gate trench 31.

[0036] In this embodiment, the doping concentration of N-type particles in the drift region 22 near the gate trench 31 is greater than that in the region away from the gate trench 31. This top-down gradient doping concentration structure ensures high breakdown voltage with high doping at the top and reduces the overall on-resistance of the trench-type power semiconductor structure with low doping at the bottom, thus improving conduction performance.

[0037] As an example, the drift region 22 includes multiple drift layers 23, with the doping concentration of the drift layer 23 closer to the gate trench 31 being greater than the doping concentration of the drift layer 23 farther from the gate trench.

[0038] In this example, the semiconductor body 10 is composed of multiple drift layers 23, each with a different doping concentration, thus forming a gradual doping distribution. The doping concentration difference between adjacent drift layers 23 can be the same, thus forming a linearly gradual doping distribution.

[0039] It should be noted that the thickness of the drift region 22 can be approximately the same as the thickness of the buried region 21, and both are less than the overall thickness of the epitaxial layer 20. Therefore, the thickness of the drift layer 23 near the bottom of the semiconductor body 10 can be much greater than the thickness of the other drift layers above it, providing support, and the thickness of the other drift layers above them can be the same. The buried region 21 and the drift region 22 extend to the top of the lowest drift layer 23.

[0040] As an example, the thickness of each drift layer 23 within the drift region 22 can range from 1.5 μm to 2 μm, and the maximum doping concentration of the drift layer 23 can range from 4e16 cm⁻¹. -3 ~6e16cm -3 The minimum doping concentration range can be 9e15 cm⁻¹ -3 ~2e16cm -3 .

[0041] For example, the thickness of the drift layer 23 can be 1.5 μm, 1.7 μm, 1.9 μm, or 2 μm, etc. The maximum doping concentration of the drift layer 23 can be 4e16 cm⁻¹. -3 5e16 cm -3 Or 6e16cm -3 The minimum doping concentration range for drift layer 23 can be 9e15 cm⁻¹. -3 2e16cm -3 Or 2e16cm -3 wait.

[0042] Continue to refer to Figure 1 and Figure 2 In some embodiments, the bottom of the gate trench 31 extends into the drift region 22, and the distance between the bottom surface of the gate trench 31 and the first surface S1 is greater than the distance between the buried region 21 and the first surface S1.

[0043] like Figure 1 and Figure 2 As shown, in the stacking direction between the buried region 21 and the first region 32, the bottom surface of the gate trench 31 is lower than the top surface of the buried region 21. Therefore, the JFET effect generated by the buried region 21 can cover more of the bottom area of ​​the gate trench 31, reducing the electric field strength at the bottom of the gate structure 33. In particular, it can significantly reduce the electric field strength at the bottom corner of the gate trench 31, improving the protection effect.

[0044] Continue to refer to Figure 1 and Figure 2 The drift region 22 is located between the buried regions 21 on both sides of the gate trench 31, and the distance between the drift region 22 and the first surface S1 is equal to the distance between the drift region 22 and the first surface S1.

[0045] The drift region 22 is flanked by buried regions 21, and both are flush with the side closest to the first surface S1. Thus, the buried region 21 and the JFET effect generated by the drift region 22 can more completely cover the side near the gate trench 31, thereby reducing the electric field strength at the bottom of the gate structure 33 to a greater extent.

[0046] In some embodiments, the buried regions 21 on both sides of the gate trench 31 are arranged symmetrically.

[0047] In this embodiment, the buried regions 21 on both sides of the gate structure 33 are symmetrically distributed, which can symmetrically adjust the electric field on both sides of the gate structure 33, so that the electric field intensity at the bottom of the gate structure 33 is symmetrical. In addition, the electric field intensity is stronger at the bottom corner of the gate structure 33, and the symmetrical electric field distribution is beneficial to simultaneously and effectively reduce the electric field intensity at both corners.

[0048] In some embodiments, the doping concentration in the buried region 21 near the first region 32 is less than the doping concentration in the region away from the first region 32.

[0049] In this embodiment, the buried region 21 has a doping concentration that increases from top to bottom, and the electric field shielding effect at deeper depths is greater than that at shallower depths. This helps maintain the conductivity of the surface channel and achieves strong electric field shielding at deeper depths, effectively absorbing high drain voltage.

[0050] In other embodiments, the buried region 21 has a doping concentration that increases from top to bottom, combined with the drift region 22 having a doping concentration that decreases from top to bottom. The dual-gradient doping distribution forms a natural stepped electric field distribution, which can reduce the on-resistance while achieving electric field shielding at the bottom of the gate structure 33, and can also suppress bipolar degradation.

[0051] In some embodiments, the first orthographic projection and the third orthographic projection do not overlap, and the distance between the first orthographic projection and the third orthographic projection is smaller than the distance between the second orthographic projection and the third orthographic projection.

[0052] In this embodiment, such as Figure 1 and Figure 2 In the left-right direction of the diagram shown, the distance between the buried region 21 and the gate trench 31 is smaller than the distance between the first region 32 and the gate trench 31. The closer proximity of the buried region 21 to the gate trench 31 helps to suppress the electric field strength at the bottom of the gate structure 33 and improves the overall reliability of the structure.

[0053] As an example, in the aforementioned left-right direction, the distance between the buried area 21 and the gate trench 31 (i.e., the distance between the first orthographic projection and the third orthographic projection) can range from 0.3 μm to 0.5 μm. For example, this distance can be 0.3 μm, 0.4 μm, or 0.5 μm, etc.

[0054] Reference Figure 3 , Figure 3 This is the third schematic diagram of the trench-type power semiconductor structure provided in this application embodiment. In some embodiments, the semiconductor body 10 further includes a current spreading layer 34, a first base layer 35, and a second base layer 36, which are located between the first region 32 and the gate trench 33 and are stacked sequentially. The side surface of the second base layer 36 away from the first base layer 35 is disposed on the first surface S1. The conductivity type of the current spreading layer 34 is the same as that of the second base layer 36, the conductivity type of the first base layer 35 is the same as that of the first region 32, and the conductivity type of the first base layer 35 is opposite to that of the second base layer 36.

[0055] In this embodiment, the semiconductor body 10 includes a stacked current spreading layer 34, a first base layer 35, and a second base layer 36. The gate trench 31 and the first region 32 can be fabricated based on this stacked structure. For example, the first region 32 can be formed by particle implantation of the current spreading layer 34, the first base layer 35, and the second base layer 36, and then the gate trench 31 can be formed by etching the current spreading layer 34, the first base layer 35, and the second base layer 36.

[0056] As an example, the first region 32 is P-type, the current spreading layer 34 and the second base layer 36 can be N-type, and the first base layer 35 can be P-type. The current spreading layer 34 is used to reduce the on-resistance and provide a current path.

[0057] In some embodiments, the gate structure 33 may include a gate dielectric layer 37 and a gate electrode 38. The gate dielectric layer 37 may be silicon dioxide, and the gate electrode 38 may be polysilicon. The gate dielectric layer 37 is formed on the inner wall of the gate trench 31, and the gate electrode 38 fills the gate trench 31. The gate dielectric layer 37 provides isolation between the gate electrode 38 and the gate trench 31.

[0058] Continue to refer to Figure 3 The semiconductor body 10 also includes a second surface S2 opposite to the first surface S1. The trench-type power semiconductor structure also includes an interlayer dielectric layer 40, a source electrode 50, and a drain electrode 60. The interlayer dielectric layer 40 is disposed on the first surface S1 and covers the gate trench 31. The source electrode 50 is disposed on the first surface S1, and the source electrode 40 covers the interlayer dielectric layer 40 and is arranged in contact with the first region 32. The drain electrode 60 is disposed on the second surface S2.

[0059] The source electrode 50 and drain electrode 60 can be metal. The source electrode 50 is used to collect the source current and serve as the device source for external connection. The drain electrode 60 is used to collect the drain current and serve as the device drain for external connection. The interlayer dielectric layer 40 can be silicon dioxide and is used to achieve insulation between the source electrode 50 and the gate structure 33.

[0060] Reference Figure 4 , Figure 4 This is a schematic flowchart of a method for fabricating a trench-type power semiconductor structure according to an embodiment of this application. Another embodiment of this application also provides a method for fabricating a trench-type power semiconductor structure. The following is a further explanation.

[0061] In this embodiment, the method for fabricating a trench-type power semiconductor structure includes steps 10, 20, and 30.

[0062] Step 10: Provide a first epitaxial layer 11, and form a drift region 22 and a buried region 21 located on both sides of the drift region in the first epitaxial layer 11. The conductivity type of the drift region 22 is opposite to that of the buried region 21. Step 20: Form a second epitaxial layer 12 on the first epitaxial layer 11; Step 30: A gate trench 31 and a first region 32 are formed on the first surface S1 of the second epitaxial layer 12. The first orthographic projection of the buried region 21 on the first surface S1 at least partially overlaps with the second orthographic projection of the first region 32 on the first surface S1, and does not completely overlap with the third orthographic projection of the gate trench 31 on the first surface S1. The third orthographic projection is located within the fourth orthographic projection of the drift region on the first surface. The buried region 21 is arranged in contact with the first region 32. The conductivity type of the buried region 21 is the same as that of the first region 32. The difference between the doping concentration of the drift region 22 on the side closer to the gate trench 31 and the doping concentration on the side farther from the gate trench 31 is greater than the reference difference. Step 40: Form a gate structure 33 within the gate trench 31.

[0063] The structures involved in the preparation method, as well as the functions and principles of each structure, can be found in the foregoing embodiments and... Figure 1 , Figure 2 and Figure 3 The preparation method is explained in conjunction with the staged structures formed in each of the following processes.

[0064] The semiconductor body 10 can be divided into a first epitaxial layer 11 and a second epitaxial layer 12, and is formed in two steps. Both the first epitaxial layer 11 and the second epitaxial layer 12 can be formed by epitaxial growth. The buried region 21 can be formed by inversion particle implantation of the first epitaxial layer 11.

[0065] After the buried region 21 is formed, a second epitaxial layer 12 can be regrowed. The first epitaxial layer 11 and the second epitaxial layer 12 have the same conductivity type. Then, the second epitaxial layer 12 is formed by inversion particle implantation into the first region 32 of the second epitaxial layer 12.

[0066] The gate trench 31 can be formed by etching the second epitaxial layer 12. Alternatively, the second epitaxial layer 12 can be etched through, and a certain depth can be etched into the first epitaxial layer 11, so that the bottom of the gate trench 31 extends to the first epitaxial layer 11. The gate structure 33 can be formed by a deposition process.

[0067] According to the method for fabricating a trench-type power semiconductor structure of this application, by providing a buried region 21 in the semiconductor body 10 that is in contact with and connected to the first region 32, the electric field strength in the semiconductor body 10 is reduced when the device is in a blocking state, thereby reducing the electric field strength borne by the gate structure 33 at the bottom of the gate trench 31 and improving the reliability of the device.

[0068] Reference Figure 5 and Figure 6 , Figure 5 This is one of the stage structures in the preparation method provided in the embodiments of this application. Figure 6 This is the second stage structure in the preparation method provided in the embodiments of this application. In some embodiments, the first epitaxial layer 11 includes a first drift layer 24 and multiple second drift layers 25, wherein the thickness of the first drift layer 24 is greater than the thickness of the second drift layers 25. The first drift layer 24 and each of the second drift layers 25 may be made of SiC, GaN, or AlN, etc.

[0069] In this embodiment, the difference between the doping concentration of the second drift layer 25 near the first drift layer 24 and the doping concentration of the second drift layer 25 far from the first drift layer 23 is greater than a reference difference. For example, the doping concentration of the second drift layer 25 near the first drift layer 24 is less than the doping concentration of the second drift layer 25 far from the first drift layer 24.

[0070] This embodiment is used to form a second drift layer 25 of a first drift layer 24 with a doping concentration gradient to prepare the drift region 22 in the aforementioned embodiment. Figure 2 The drift layer 23 shown includes the portion of the first drift layer 24 located between the burial areas 21 and each second drift layer 25.

[0071] In this embodiment, step 10, forming a drift region 22 in the first epitaxial layer 11 and buried regions 21 located on both sides of the drift region, may include: providing a first drift layer 24; forming multiple layers of second drift layers 25 on the first drift layer 24, wherein the difference between the doping concentration of the second drift layer 25 near the first drift layer 24 and the doping concentration of the second drift layer 25 far from the first drift layer 24 is greater than a reference difference; performing inversion particle implantation on the first drift layer 23 and each of the second drift layers 24 to form spaced-apart buried regions 21, wherein each layer of second drift layers 25 between the buried regions 21 forms a drift region 22.

[0072] As an example, the first drift layer 24 and the second drift layer 25 can be N-type, and the inverse particles in step 20 are P-type particles, such as aluminum ions or boron ions.

[0073] Reference Figure 7 , Figure 7 This is the third stage structure in the preparation method provided in this application embodiment. The buried region 21 can extend downward from the top of the second drift layer 25 to the top of the first drift layer 24. Thus, drift regions 22 with doping concentration decreasing from top to bottom are formed between the buried regions 21.

[0074] Furthermore, since the deeper the inversion particle implantation depth, the smaller the corresponding N-type doping concentration, and the easier it is to complete the inversion, the P-type doping concentration in the deep part of the buried region 21 near the first drift layer 24 is greater than the P-type doping concentration in the shallow part of the buried region 21 far from the first drift layer 24, forming a dual-gradient doping distribution.

[0075] In some embodiments, step 20, forming a second epitaxial layer 12 on the first epitaxial layer 11, may include: forming a current spreading layer 34 on the first epitaxial layer 11, the conductivity type of the current spreading layer 34 being the same as that of the buried region 21; performing inversion particle implantation on the side of the current spreading layer 34 away from the first epitaxial layer 11 to form a first base layer 35, the conductivity type of the first base layer 35 being opposite to that of the current spreading layer 34; and performing inversion particle implantation on the side of the first base layer 35 away from the current spreading layer 34 to form a second base layer 36, the conductivity type of the first base layer 35 being opposite to that of the second base layer 36.

[0076] Reference Figure 8 , Figure 8 This is the fourth stage structure in the preparation method provided in this application embodiment. After preparing the buried region 21, a current spreading layer 34 is formed above the epitaxial layer 20, and the current spreading layer 34 covers the buried region 21.

[0077] Reference Figure 9 , Figure 9This is the fifth stage structure in the preparation method provided in this application. Corresponding inversion particles are injected into the top of the current spreading layer 34 to form the first base layer 35. Taking the current spreading layer 34 as an N-type layer as an example, the inversion particles are P-type particles, such as aluminum ions or boron ions.

[0078] Reference Figure 10 , Figure 10 This is the sixth stage structure in the preparation method provided in this application. A second layer 36 is formed by injecting corresponding inversion particles into the first layer 35. Taking the formation of an N+ type second layer 36 as an example, the inversion particles can be N-type ions such as nitrogen, phosphorus, or arsenic.

[0079] Reference Figure 11 , Figure 11 This is the seventh stage structure in the preparation method provided in this application embodiment. Particle implantation is performed on the current spreading layer 34, the first base layer 35, and the second base layer 36 to form a first region 32. The first region 32 is located above and extends into the buried region 21. The lowest interface of the first region 32 is lower than the highest interface of the buried region 21, enabling effective contact and connection between the first region 32 and the buried region 21.

[0080] Reference Figure 12 , Figure 12 This is the eighth stage structure in the fabrication method provided in this application embodiment. The current spreading layer 34, the first base layer 35, and the second base layer 36 are etched to form a gate trench 31. The depth of the gate trench 31 can also extend into the epitaxial layer, improving the suppression effect of the buried region 21 on the electric field strength at the bottom of the gate trench 31.

[0081] Reference Figure 13 , Figure 13 This is the ninth stage structure in the fabrication method provided in this application embodiment. A gate structure 33 is formed by sequentially depositing a gate dielectric layer 37 and a gate electrode 38 in the gate trench 31. An interlayer dielectric layer 40 is formed on the gate trench 31 to isolate the gate structure 33 from the subsequently formed source electrode 50. Finally, the source electrode 50 is formed on the side of the gate-source layer 30 away from the epitaxial layer 20, and a drain electrode 60 is formed on the second surface S2. The trench-type power semiconductor structure obtained in this embodiment can be referred to... Figure 3 .

[0082] One embodiment of this application also provides a power chip, which includes the trench-type power semiconductor structure described above, or includes a trench-type power semiconductor structure prepared according to the aforementioned preparation method. The trench-type power semiconductor structure and its preparation method can be referred to in the foregoing embodiments. The power chip including this trench-type power semiconductor structure also has corresponding technical effects, which will not be elaborated further in this embodiment.

[0083] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0084] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A trench-type power semiconductor structure, characterized in that, include: A semiconductor body includes a first surface, a first region, a buried region, and a drift region. The first surface is provided with a gate trench, the drift region is located on the side of the gate trench away from the first surface, the first region is disposed on the first surface, and the buried region is located on the side of the first region away from the first surface, and the buried region is arranged in contact with the first region. A gate structure is located within the gate trench; Wherein, the first orthographic projection of the buried region on the first surface at least partially overlaps with the second orthographic projection of the first region on the first surface, and does not completely overlap with the third orthographic projection of the gate trench on the first surface, the third orthographic projection is located within the fourth orthographic projection of the drift region on the first surface, the conductivity type of the buried region is the same as that of the first region, the conductivity type of the drift region is opposite to that of the buried region, and the difference between the doping concentration of the drift region near the gate trench and the doping concentration of the region away from the gate trench is greater than a reference difference.

2. The trench-type power semiconductor structure according to claim 1, characterized in that, The doping concentration in the drift region closer to the gate trench is greater than the doping concentration in the region farther from the gate trench.

3. The trench-type power semiconductor structure according to claim 2, characterized in that, The drift region includes multiple drift layers, with the doping concentration of the drift layer closer to the gate trench being greater than the doping concentration of the drift layer farther from the gate trench.

4. The trench-type power semiconductor structure according to claim 2, characterized in that, The bottom of the gate trench extends into the drift region, and the distance between the bottom surface of the gate trench and the first surface is greater than the distance between the buried region and the first surface.

5. The trench-type power semiconductor structure according to any one of claims 1-4, characterized in that, The drift region is located between the buried regions on both sides of the gate trench, and the distance between the drift region and the first surface is equal to the distance between the drift region and the first surface.

6. The trench-type power semiconductor structure according to claim 5, characterized in that, The buried regions on both sides of the gate trench are arranged symmetrically.

7. The trench-type power semiconductor structure according to any one of claims 1-4, characterized in that, The doping concentration in the buried area closer to the first region is less than the doping concentration in the area farther from the first region.

8. The trench-type power semiconductor structure according to claim 7, characterized in that, The first orthographic projection and the third orthographic projection do not overlap, and the distance between the first orthographic projection and the third orthographic projection is less than the distance between the second orthographic projection and the third orthographic projection.

9. The trench-type power semiconductor structure according to any one of claims 1-4, characterized in that, The semiconductor body also includes a second surface opposite to the first surface, and a current spreading layer, a first base layer and a second base layer stacked sequentially between the first region and the gate trench, wherein the side of the second base layer away from the first base layer is disposed on the first surface; The trench-type power semiconductor structure also includes: An interlayer dielectric layer is disposed on the first surface and covers the gate trench; A source electrode is disposed on the first surface, the source electrode covers the interlayer dielectric layer, and is arranged in contact with the first region; The drain electrode is disposed on the second surface; The conductivity type of the current spreading layer is the same as that of the second base layer, the conductivity type of the first base layer is the same as that of the first region, and the conductivity type of the first base layer is opposite to that of the second base layer.

10. A method for fabricating a trench-type power semiconductor structure, characterized in that, include: A first epitaxial layer is provided, and a drift region and a buried region located on both sides of the drift region are formed in the first epitaxial layer, wherein the conductivity type of the drift region is opposite to that of the buried region; A second epitaxial layer is formed on the first epitaxial layer; A gate trench and a first region are formed on a first surface of the second epitaxial layer on the side away from the first epitaxial layer. The first orthographic projection of the buried region on the first surface at least partially overlaps with the second orthographic projection of the first region on the first surface, and does not completely overlap with the third orthographic projection of the gate trench on the first surface. The buried region is arranged in contact with the first region. The third orthographic projection is located within the fourth orthographic projection of the drift region on the first surface. The conductivity type of the buried region is the same as that of the first region. The difference between the doping concentration of the drift region on the side closer to the gate trench and the doping concentration on the side farther from the gate trench is greater than a reference difference. A gate structure is formed within the gate trench.

11. The preparation method according to claim 10, characterized in that, The first epitaxial layer includes a first drift layer and multiple second drift layers, wherein forming a drift region and a buried region located on both sides of the drift region in the first epitaxial layer includes: Provide the first drift layer; Multiple second drift layers are formed on the first drift layer, and the difference between the doping concentration of the second drift layer close to the first drift layer and the doping concentration of the second drift layer far from the first drift layer is greater than a reference difference. Inverse particle injection is performed on the first drift layer and each of the second drift layers to form spaced-apart buried areas, and the second drift layers between the buried areas form drift areas.

12. The preparation method according to claim 11 or the method described in claim 11, characterized in that, The step of forming a second epitaxial layer on the first epitaxial layer includes: A current spreading layer is formed on the first epitaxial layer, wherein the conductivity type of the current spreading layer is opposite to the conductivity type of the buried region; Inversion particle implantation is performed on the side of the current spread layer away from the first epitaxial layer to form a first base layer, the conductivity type of the first base layer being opposite to that of the current spread layer; A second layer is formed by injecting inverse particles on the side of the first layer away from the current spreading layer, wherein the conductivity type of the first layer is opposite to that of the second layer.

13. A power chip, characterized in that, It includes the trench-type power semiconductor structure according to any one of claims 1-9, or the trench-type power semiconductor structure prepared by the preparation method according to any one of claims 10-12.

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