A silicon carbide junction field effect transistor having double graded continuous superjunctions

Abstract

This invention discloses a silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction, comprising, from bottom to top, a drain metal, an N+ type substrate, an N-type drift region, a current spreading layer, an N-type channel region, and an N+ type source region; a trench extends from the N+ type source region to the N-type channel region; multiple P-type pillars penetrate the N-type drift region, including adjacent first and second P-type pillar segments in the vertical direction, with the second P-type pillar segment located near the top of the current spreading layer, and its width and doping concentration being smaller than those of the first P-type pillar segment; the current spreading layer is located in the lateral space on the side of the second P-type pillar segment and is laterally adjacent to it; P-regions are formed on both sides and within the sidewalls of the N-type channel region; the doping concentration of the N-type drift region increases from bottom to top, forming an inverse complementary gradient with the P-type pillars, and the doping transition between the two pillar segments is smooth. This invention significantly reduces specific on-resistance, ensures charge compensation continuity, eliminates dynamic hysteresis, and improves electromagnetic compatibility and overall stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction. Background Technology

[0002] Silicon carbide (SiC), as a typical representative of wide-bandgap semiconductor materials, possesses excellent physical properties such as a large bandgap, high critical breakdown electric field, and high thermal conductivity, making it a promising candidate for applications in high-temperature, high-frequency, and high-power power electronics. Among SiC power devices, the junction field-effect transistor (JFET), as a voltage-controlled majority carrier device, offers advantages such as high intrinsic reliability, absence of gate oxide reliability issues, and fast switching speed, making it an ideal choice for achieving high-efficiency power conversion. To further break through the one-dimensional silicon limit, applying superjunction theory to SiC JFETs has become a research hotspot in recent years. The superjunction structure introduces alternating P-type and N-type pillars in the drift region, utilizing the charge compensation effect between the P-pillars and N-pillars to make the internal electric field distribution of the device tend towards a rectangle in the reverse blocking state. This allows for a significant increase in the doping concentration in the drift region while maintaining a high breakdown voltage, thereby reducing the specific on-resistance of the device.

[0003] Currently, superjunction structures include traditional equal-width full superjunction structures and discrete floating junction structures. However, in vertical JFET devices, the equal-width P-pillars severely compress the N-type vertical conductive channel throughout the longitudinal depth of the drift region, resulting in a significant reduction in the effective current-carrying cross-sectional area. Because the top space is locked by the equal-width P-pillars, the JFET neck region cannot accommodate an effective high-doped current extension layer while maintaining charge balance, severely limiting the specific on-resistance. Discrete floating junction structures introduce a series of longitudinally arranged, isolated P-type floating islands within the drift region to simulate the superjunction effect. Multiple epitaxial growth processes combined with multiple ion implantation are used to implant aluminum ions onto the surface of each epitaxial layer to form discrete P-type regions. Because these P-type regions are physically isolated, there is a severe discontinuity in charge transport, leading to sluggish dynamic response during high-speed switching. Simultaneously, the floating junction potential is in a suspended state, making it susceptible to leakage current and parasitic capacitance interference, resulting in severe local electric field concentration at interlayer gaps, seriously threatening the stability of the static breakdown voltage. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction, which solves the problems of the existing technology, such as the extremely limited specific on-resistance, the hysteresis of dynamic response during high-speed switching, and the poor stability of the static withstand voltage.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: The first aspect of the present invention provides a silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction, comprising a drain metal, an N+ type substrate, an N-type drift region, an N-type channel region and an N+ type source region arranged sequentially from bottom to top; The trench is formed in the edge regions on both sides of the N+ type source region and extends through the N+ type source region into the N type channel region; The current spreading layer is located between the N-type drift region and the N-type channel region; Multiple P-type pillars are formed on both sides of the edge region of the N-type drift region and penetrate the N-type drift region; the multiple P-type pillars include at least an adjacent first P-type pillar segment and a second P-type pillar segment in the longitudinal direction, the first P-type pillar segment is located near the bottom region of the N+ type substrate, the second P-type pillar segment is located near the top region of the current spreading layer, and the horizontal width of the second P-type pillar segment is smaller than the horizontal width of the first P-type pillar segment; the current spreading layer is located in the lateral space on the side of the second P-type pillar segment and is laterally adjacent to the second P-type pillar segment; The P-region is formed in the two edge regions and sidewalls of the N-type channel region, and is in contact with the upper surface of the current spread layer and the lower surface of the N+ type source region. The source metal is formed on the N+ type source region; Gate metal is formed on the P-region and contacts a portion of the P-region pillar within the sidewall of the N-type channel region; In this system, the doping concentration of multiple P-type pillars decreases from the bottom region to the top region, while the doping concentration of the N-type drift region increases from the bottom region to the top region, forming a vertically complementary reverse gradient; the doping concentration between the first P-type pillar segment and the second P-type pillar segment exhibits a smooth transition.

[0006] Compared to existing technologies, the silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction provided by this invention includes: a drain metal, an N+ type substrate, an N-type drift region, an N-type channel region, and an N+ type source region arranged sequentially from bottom to top; a trench formed in the side edge regions of the N+ type source region and extending through the N+ type source region to the N-type channel region; a current spreading layer located between the N-type drift region and the N-type channel region; and a plurality of P-type pillars formed in the side edge regions of the N-type drift region and extending through the N-type drift region; the plurality of P-type pillars include at least two adjacent first P-type pillar segments and second P-type pillar segments in the longitudinal direction, the first P-type pillar segment being located near the bottom region of the N+ type substrate, the second P-type pillar segment being located near the top region of the current spreading layer, and the first P-type pillar segment being located near the bottom region of the N+ type substrate, and the second P-type pillar segment being located near the top region of the current spreading layer, and the second P-type pillar segment being located near the bottom region of the N+ type substrate. The horizontal width of the second P-type pillar segment is smaller than that of the first P-type pillar segment; the current spreading layer is located in the lateral space on the side of the second P-type pillar segment and is laterally adjacent to the second P-type pillar segment; the P-region is formed in the side edge regions and sidewalls of the N-type channel region and is in contact with the upper surface of the current spreading layer and the lower surface of the N+ type source region; the source metal is formed on the N+ type source region; the gate metal is formed on the P-region and is in contact with a portion of the P-region pillars in the sidewall of the N-type channel region; wherein, the doping concentration of the multiple P-type pillars decreases from the bottom region to the top region, and the doping concentration of the N-type drift region increases from the bottom region to the top region, forming a vertically opposite complementary gradient; the doping concentration between the first P-type pillar segment and the second P-type pillar segment has a smooth transition. In this way, because the horizontal width of the second P-type pillar is smaller than that of the first P-type pillar, lateral space is released in the top region. The current spreading layer is located within this lateral space and is laterally adjacent to the second P-type pillar, allowing electrons to spread rapidly laterally after injection. This achieves strong lateral current expansion at the JFET neck, thereby significantly reducing the specific on-resistance of the device. Since the doping concentration of the multiple P-type pillars decreases from the bottom region to the top region, and the doping concentration of the N-type drift region increases from the bottom region to the top region, forming a vertically opposite complementary gradient, and the doping concentration between the first and second P-type pillars transitions smoothly, the vertical charge compensation channel is free from concentration abrupt changes and potential barriers, ensuring the absolute continuity of the charge compensation channel and eliminating dynamic response hysteresis. Based on the synergistic effect of the stepped morphology and complementary gradient of the multiple P-type pillars, the device forms natural dynamic damping during switching, smoothing the switching waveform and improving the electromagnetic compatibility and overall stability of the device in complex power electronic systems. Attached Figure Description

[0007] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1A schematic diagram of a silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction is shown. Figure 2 A schematic diagram of the fabrication process of the first N-type drift segment is shown. Figure 3 The schematic diagram illustrates the preparation process flow of the first P-type column segment corresponding to the first N-type drift segment; Figure 4 A schematic diagram of the fabrication process for the second N-type drift segment is shown. Figure 5 The schematic diagram illustrates the fabrication process flow of the first P-type column segment corresponding to the second N-type drift segment; Figure 6 A schematic flowchart of the fabrication process of the current spreading layer is shown. Figure 7 A schematic flowchart illustrating the preparation process of the second P-type column segment is shown. Figure 8 A schematic diagram of the deposition process in the N-type channel region is shown. Figure 9 A schematic diagram of the deposition process flow for the N+ type source region is shown. Figure 10 A schematic diagram of the etching process for the trenches is shown. Figure 11 A schematic diagram of the preparation process for the P-region is shown. Figure 12 The fabrication process flow diagram of the drain metal, source metal, and gate metal is schematically shown.

[0008] Explanation of reference numerals in the attached figures 1. Drain metal; 2. N+ type substrate; 3. N-type drift region; 31. First N-type drift segment; 32. Second N-type drift segment; 4. N-type channel region; 5. N+ type source region; 6. Trench; 7. Current spread layer; 8. Multiple P-type pillars; 81. First P-type pillar segment; 82. Second P-type pillar segment; 9. P-region; 10. Source metal; 11. Gate metal. Detailed Implementation

[0009] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0010] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by one of ordinary skill in the art.

[0011] The methods described in the embodiments of the present invention will be explained in detail below.

[0012] Figure 1 A schematic diagram of a silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction is shown, including: drain metal 1, N+ type substrate 2, N type drift region 3, N type channel region 4 and N+ type source region 5 arranged sequentially from bottom to top; The trench 6 is formed in the two edge regions of the N+ source region 5 and extends through the N+ source region 5 into the N-type channel region 4. The current spreading layer 7 is located between the N-type drift region 3 and the N-type channel region 4; Multiple P-type pillars 8 are formed on both sides of the edge region of the N-type drift region 3 and penetrate the N-type drift region 3; the multiple P-type pillars 8 include at least two adjacent first P-type pillar segments 81 and second P-type pillar segments 82 in the longitudinal direction, the first P-type pillar segment 81 is located near the bottom region of the N+ type substrate 2, the second P-type pillar segment 82 is located near the top region of the current spreading layer 7, and the horizontal width of the second P-type pillar segment 82 is smaller than the horizontal width of the first P-type pillar segment 81; the current spreading layer 7 is located in the lateral space on the side of the second P-type pillar segment 82 and is laterally adjacent to the second P-type pillar segment 82; P-region 9 is formed in the two edge regions and sidewalls of the N-type channel region 4, and is in contact with the upper surface of the current spreading layer 7 and the lower surface of the N+ type source region 5. Source metal 10 is formed on N+ type source region 5; Gate metal 11 is formed on P region 9 and contacts a portion of the P region 9 pillar within the sidewall of N-type channel region 4; Among them, the doping concentration of multiple P-type pillars 8 decreases from the bottom region to the top region, and the doping concentration of N-type drift region 3 increases from the bottom region to the top region, forming a vertically opposite complementary gradient; the doping concentration between the first P-type pillar segment 81 and the second P-type pillar segment 82 has a smooth transition.

[0013] As an optional implementation, the N-type drift region 3 includes at least a first N-type drift segment 31 and a second N-type drift segment 32 that are longitudinally adjacent. Both the first N-type drift segment 31 and the second N-type drift segment 32 are located on the side of the first P-type pillar segment 81. The lower surface of the first N-type drift segment 31 is in contact with the N+ type substrate 2, and the upper surface of the second N-type drift segment 32 is in contact with the current spreading layer 7. The donor impurity concentration of the first N-type drift segment 31 is lower than that of the second N-type drift segment 32.

[0014] For example, the first P-type pillar segment 81 includes a first preset P-type pillar segment and a first target P-type pillar segment. The first preset P-type pillar segment 81 includes at least a first preset P-type pillar segment and a first target P-type pillar segment that are longitudinally adjacent. The first preset P-type pillar segment is in contact with the N+ type substrate 2, and the first target P-type pillar segment is in contact with the second P-type pillar segment 82.

[0015] The number of longitudinally adjacent N-type drift segments included in the N-type drift zone 3 is the same as the number of longitudinally adjacent P-type column segments included in the first P-type column segment 81. For example, the N-type drift zone 3 has 3 layers, and correspondingly, the first P-type column segment 81 includes 3 layers of P-type column segments.

[0016] Specifically, the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction of the present invention constructs a three-dimensional synergistic complementary ladder superjunction and localized current spread system based on morphology-space-concentration. The multiple P-type pillars 8 (charge balance regions) in the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction are formed by seamlessly connecting multiple layers of P-type pillars in the vertical direction. From the bottom layer (near the N+ type substrate 2 side) to the top layer (near the N+ type source region 5 side), the horizontal width W of each P-type pillar decreases stepwise (i.e., W1>W2>...>Wn), where n is the number of multiple P-type pillars 8, n≥2, and Wn is the horizontal width of the nth P-type pillar. Within the lateral physical space released by the top layer P-type pillar segment (e.g., the horizontal width of the narrowest P-type pillar segment is W3), a highly doped N+ current spread layer 7 (CSL) is disposed in situ. The lateral width of this current spread layer 7 is strictly matched with the narrowing dimension of the top layer P-type pillar segment.

[0017] The doping distribution of the multiple P-type pillars 8 corresponds to the width gradient. The acceptor doping concentration NA of each P-type pillar decreases synchronously in a stepwise manner from bottom to top (i.e., NA1>NA2>...>NAn), where NAN is the acceptor doping concentration of the nth P-type pillar, and n≥2, achieving a gradient of lower and higher acceptor doping concentrations in the multiple P-type pillars 8. The N-type drift region 3 adopts a complementary reverse gradient, i.e., the donor impurity concentration increases stepwise from bottom to top (ND1>ND2>...>NDm), where m≥2, m is the number of N-type drift segments in the N-type drift region 3, and NDm is the donor impurity concentration of the mth N-type drift segment in the N-type drift region 3. This achieves a gradient of higher and lower donor impurity concentrations in the N-type drift region 3.

[0018] The adjacent P-type pillars 8 and P-regions 9 not only physically overlap in the longitudinal direction, but also form a smooth concentration transition region at their boundaries. That is, a concentration gradient exists between P-region 9 and the top layer of P-type pillars. Furthermore, within the multiple P-type pillars 8, the overlapping of injection energy distributions between P-type pillars in different layers (such as between the bottom layer and the middle layer, and between the middle layer and the top layer) eliminates abrupt doping changes. This uniform concentration gradient distribution across all channels completely eliminates the potential barrier within the longitudinal charge compensation channel, ensuring unimpeded high-speed upward transport of holes during turn-off transients.

[0019] As an optional implementation, the horizontal width of each P-shaped column decreases layer by layer from bottom to top in a ratio of 10% to 60%.

[0020] As an optional implementation, the acceptor impurity concentration of each P-type column decreases layer by layer from bottom to top in increments of 1.5 to 5 times.

[0021] As an alternative implementation, the donor impurity concentration of the current spreading layer 7 is 5 to 50 times that of the highest donor impurity concentration of the N-type drift region 3.

[0022] As an optional implementation, the ratio of the acceptor impurity concentration of the first P-type column segment 81 to the acceptor impurity concentration of the second P-type column segment 82 is 1.2 to 5.

[0023] As an optional implementation, the plurality of P-shaped columns 8 include at least three layers of adjacent P-shaped column segments in the longitudinal direction, and the horizontal width of each P-shaped column segment decreases layer by layer from bottom to top.

[0024] As an optional implementation, the first P-type column segment 81 and the second P-type column segment 82 have a physical overlap region in the longitudinal direction, and the doping concentration of the physical overlap region smoothly transitions from the first P-type column segment 81 to the second P-type column segment 82.

[0025] As an optional implementation, the donor impurity concentration of the first N-type drift segment 31 and the donor impurity concentration of the second N-type drift segment 32 increase continuously from bottom to top, and there is no abrupt change in doping concentration at the junction of the first N-type drift segment 31 and the second N-type drift segment 32.

[0026] As an optional implementation, the horizontal width and acceptor impurity concentration of the first P-type column segment 81 are both greater than the horizontal width and acceptor impurity concentration of the second P-type column segment 82, so that the first P-type column segment 81 forms an electric field anchoring region, which is used to anchor the main electric field peak in the reverse blocking state of the device to the N+ type substrate 2 side.

[0027] Specifically, the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction of the present invention achieves dynamic control of the electric field distribution and current path of the device through the non-uniformity of morphology and concentration, specifically including: In the forward conduction path optimization (i.e., the first quadrant), the current flows from top to bottom through the N-type channel region 4 in the forward conduction state. Since the top P-type pillar segment has the narrowest width, space is freed up, allowing the current spreading layer 7 to quickly spread the current laterally, greatly eliminating the current congestion effect at the JFET neck, increasing the effective current-carrying cross-sectional area, and thus significantly reducing the specific on-resistance of the device.

[0028] The reverse freewheeling path optimization (i.e., the third quadrant) provides a more robust hole injection substrate through a wider and denser P-type pillar in the reverse freewheeling state (source connected to high voltage). This wide substrate structure effectively guides the uniform distribution of reverse current, firmly locking the maximum electric field peak under reverse voltage at the bottom of the device. This protects the upper gate and CSL from high-voltage breakdown, prevents local overheating caused by charge crowding under high-current freewheeling, and improves the device's bidirectional operational robustness.

[0029] Dynamic suppression and electric field anchoring utilize the strong charge compensation effect of the high-concentration P-type pillars at the bottom layer to firmly lock the electric field peak at the bottom of the device in the blocking state, thus keeping the surface gate in a low electric field protection zone. Because the widths of the P-type pillars vary across layers, a physical time difference exists in the charge extraction paths at different depths during switching, creating natural dynamic damping. This smooths the current change rate and effectively suppresses turn-off oscillations and electromagnetic interference.

[0030] The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction of the present invention is a stepped superjunction structure with a complementary dual-gradient distribution of vertical width and concentration. Unlike existing technologies with equal width structures or single-region concentration gradients, this stepped superjunction structure requires not only that the multiple P-type pillars 8 be distributed in a stepped pattern of wider, denser doping at the bottom and narrower, sparser doping at the top, but also that the N-type drift region 3, sandwiched between the multiple P-type pillars 8, exhibit a reverse cross gradient of wider, denser doping at the top and narrower, sparser at the bottom. This complementary design maximizes top conduction and bottom breakdown voltage. The scope of protection should cover all continuous structures with a reverse complementary decreasing / increasing characteristic of P / N type region geometric width and doping concentration.

[0031] The silicon carbide junction field-effect transistor with dual-gradient continuous superjunction of the present invention includes a spatial coordination mechanism that is morphologically and deeply bound to multiple stepped P-type pillars 8. Utilizing the lateral physical space released by the reduction in the horizontal width of the top P-type pillar segment, a highly doped N+ type current spreading layer 7 is filled in situ. The lateral width of the CSL is strictly matched with the width reduction of the top P-type pillar segment. Through the synergy of this morphological clearance and high-density filling, a strong electron current amplification is achieved, completely eliminating the neck current congestion effect.

[0032] This invention emphasizes the physical overlap and electrical continuity of the injection regions in the longitudinal direction, completely eliminating the potential levitation and charge transport discontinuities present in discrete floating junction structures. Furthermore, this invention requires that all boundaries of P-type regions with longitudinal physical overlap (including between P-region 9 and the P-type pillars of the layer, and between the P-type pillars within multiple P-type pillars 8) have a smooth concentration transition throughout the entire longitudinal charge extraction channel. This gradient connection scheme with no concentration step dead zones throughout the channel completely eliminates the hole transport barrier at the microscopic level, a key barrier to ensure low resistance characteristics of the device during high-speed dynamic switching. It mainly includes a continuous compensation pillar structure with longitudinal physical connection and smooth interface concentration transition.

[0033] During forward conduction, the synergistic structure of the wide N-narrow P-column at the top and the current extension layer 7 significantly reduces the specific on-resistance. During reverse freewheeling, the wide P-column structure at the bottom serves as a stable buffer substrate for hole injection. Utilizing the difference in total charge and path formed by the longitudinal stepped topography, this invention introduces a natural charge extraction time difference during switching. The key point lies in using the dynamic damping effect generated by geometric non-uniformity to smooth the turn-off waveform, suppress reverse recovery current spikes and electromagnetic interference. The protection scope should cover all application scenarios that utilize this gradient structure to improve the switching characteristics of the device.

[0034] To ensure that patent rights are not easily circumvented, this invention seeks protection for a set of step-like parameter combinations. These include, but are not limited to: Width gradient: The width Wn of each P-type column segment in the multiple P-type columns 8 decreases from bottom to top in a ratio of 10%-60%; correspondingly, the width of the N-type drift zone 3 increases from bottom to top.

[0035] Concentration gradient: The doping concentration Nn in each layer decreases from bottom to top in increments of 1.5 to 5 times; the doping concentration in the N-type drift region 3 increases from bottom to top in a similar increment.

[0036] Concentration ratio of the cooperating CSL: The donor impurity concentration of the local N+ type current spreading layer 7 is significantly higher than that of the lower N-type drift region 3, preferably 5 to 50 times the highest concentration of the N-type drift region 3, so as to ensure the two-dimensional current spreading effect and prevent the device from being unable to be pinched off.

[0037] Interface concentration smoothing ratio: At the junction of adjacent P-type column segments with longitudinal overlap, the ratio of impurity concentration in the high-concentration region to that in the low-concentration region is controlled between 1.2 and 5 to eliminate the charge transport barrier.

[0038] Layer distribution: Covers all gradient continuous structures with 2 or more layers formed by multiple epitaxial injections.

[0039] This invention utilizes the high charge level at the bottom layer to generate an electric field anchoring effect, pulling the peak value of the main electric field under high voltage conditions down from the surface gate region to a deeper region near the substrate. The key is to use this non-uniform charge distribution to protect the fragile surface structure, thereby improving the overall breakdown reliability of the device.

[0040] In terms of physical characteristics, although Figure 1 An exemplary three-layer stepped reduction design is adopted, but the number of layers of P-type column segments in the multiple P-type columns 8 is not limited to three. Depending on the increase in pressure resistance, it can be flexibly expanded into a stepped structure with two, four, or even more layers. At the same time, in addition to the stepped vertical distribution, the sidewall morphology of each layer of P-type column segments can also be replaced with an inverted cone shape or a smooth slope structure with a continuous slope. Regardless of whether a stepped or continuous slope shape is adopted, as long as it meets the morphological feature of decreasing lateral width from bottom to top and reserving lateral space at the top to embed the local CSL, the spatial synergistic current amplification and bottom electric field anchoring effect of the present invention can be achieved. In addition, the cross-sectional layout of the multiple P-type columns 8 is not limited to strips, but can also be a three-dimensional symmetrical structure such as a cylinder, square, or hexagonal honeycomb.

[0041] Regarding parameter distribution, while maintaining the complementary relationship between the lower-concentration and upper-depletion of multiple P-type pillars 8 and the upper-concentration and lower-depletion of the N-type drift region 3, the concentration variation curve is not limited to a discrete step distribution. Alternatively, the concentrations of the multiple P-type pillars 8 and N-type drift region 3 can be designed as linearly, exponentially, or Gaussianly gradual by precisely controlling the dopant gas flow rate or ion implantation energy / dosage during epitaxial growth. Furthermore, the concentration within the localized N+ type current extension layer 7 located at the JFET neck can also be non-uniform, for example, employing a micro-gradient distribution that is more concentrated near the source and gradually decreases downwards to further smooth the electric field transition.

[0042] In terms of process implementation, besides multiple epitaxy combined with multiple ion implantations, an alternative process can be adopted: deep trench etching combined with multiple tilting ion implantations. By performing gradient implantations at different angles and doses on the etched deep trench sidewalls, a longitudinal concentration and charge gradient can also be constructed in multiple consecutive P-type pillars 8. Alternatively, high-energy ion implantation can be used in a single epitaxial layer to form impurity distributions of different depths. By precisely controlling the projected range and dose of multi-energy implantations, a similar step-like charge balance distribution can be simulated without increasing the number of epitaxial layers. Although these variations of the manufacturing process operate differently, the physical structure formed inside the device and the resulting technical effects are consistent with the present invention, and should be included within the scope of protection of the present invention.

[0043] Regarding the expansion of applicable device types, the stepped topography space release combined with in-situ CSL filling and the core synergistic mechanism combined with complementary dual gradients proposed in this invention essentially represents a fundamental architectural reshaping of the power semiconductor superjunction breakdown layer and conductive neck. Therefore, this alternative is not only applicable to silicon carbide junction field-effect transistors (SiC JFETs), but can also be directly transplanted and applied to silicon carbide superjunction metal-oxide-semiconductor field-effect transistors (SiC SJ-MOSFETs). In MOSFETs, this structure not only significantly reduces the specific on-resistance, but its multiple widened and densed P-type pillars 8 at the bottom also serve as a shielding structure, effectively protecting the fragile gate oxide layer from high-voltage breakdown, producing the same technical effect.

[0044] Compared with existing equal-width superjunction structures and discrete floating junction schemes, this invention achieves a leapfrog performance improvement by introducing a three-dimensional synergistic stepped complementary structure of morphology, space, and concentration. The specific advantages are as follows: First, existing constant-width superjunctions severely compress the FET neck space due to the fixed width of the P-pillars, and due to charge balance limitations, it is impossible to set an effective highly doped current-spreading layer in the neck. This invention, through a stepped narrowing of the top-layer P-type pillar morphology, physically releases lateral space, and utilizes this space to in-situ co-embed a locally highly doped N+ type current-spreading layer 7. This morphological concession combined with a highly concentrated filling two-dimensional co-design allows for rapid lateral spread after electron injection, completely eliminating the current crowding effect in the JFET neck. While maintaining high breakdown voltage, the reduction in on-resistance far exceeds that of traditional single-gradient structures.

[0045] Secondly, this invention proposes a reverse cross-complementary gradient system consisting of multiple P-type pillars 8 (dense at the bottom, thin at the top) and an N-type drift region 3 (dense at the top, thin at the bottom). This invention utilizes the structure of multiple P-type pillars 8 with a widened and denser bottom to generate a strong electric field anchoring effect, forcibly pulling the peak electric field during high-voltage interruption from the fragile surface gate region to a deeper region near the substrate. This design overcomes the defects of existing technologies that easily lead to surface breakdown, greatly enhancing the electrical reliability of the gate and the avalanche robustness of the device. Furthermore, it cleverly utilizes the asymmetry of the geometry. During forward conduction in the first quadrant, extremely low losses are achieved through the synergistic structure of the wide N-type pillars and narrow P-type pillars at the top and the CSL (Continuous Levitational Layer). During reverse freewheeling in the third quadrant, the multiple P-type pillars 8 with a widened and denser bottom act as a stable hole injection buffer layer, effectively improving hole injection efficiency and distribution uniformity, and significantly enhancing the power robustness and heat dissipation characteristics of the device under frequent commutation conditions (such as solid-state circuit breakers and induction heating).

[0046] In terms of dynamic characteristics, this invention utilizes the differences in total charge distribution and path asymmetry formed by the longitudinal stepped topography to create a natural charge extraction / injection time difference during switching operations, generating a physical-level dynamic damping effect. This mechanism can effectively smooth the reverse recovery current waveform, suppress voltage overshoot and high-frequency noise at the moment of turn-off, and improve the electromagnetic compatibility of power electronic systems from the intrinsic structure level of the device.

[0047] Furthermore, this invention significantly enhances the long-term reliability of the surface structure. By anchoring the electric field through the strong charge center at the bottom, the center of gravity of the internal electric field is actively pulled down, causing the peak value of the maximum electric field to deviate from the fragile surface gate region, thus reducing the gate polarization charge stress. In terms of manufacturing process, this invention employs multiple epitaxy combined with gradient window injection to ensure the electrical continuity of multiple P-type pillars 8 in the vertical direction. This not only eliminates the potential drift and electric field distortion hazards commonly found in floating junction structures, but also significantly reduces the dependence on process precision by increasing the fault tolerance window for charge balance, thereby improving the yield of mass production and reducing the manufacturing cost per wafer.

[0048] Finally, by setting multiple combinations of width and concentration parameters, this invention establishes an optimal design matrix covering different voltage levels, ensuring the best compromise performance in various application scenarios. It has strong engineering practical value and deep technical coverage.

[0049] Based on the above Figure 1As can be seen from the implementation method, the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction in this embodiment of the invention includes: a drain metal 1, an N+ type substrate 2, an N-type drift region 3, an N-type channel region 4, and an N+ type source region 5 arranged sequentially from bottom to top; a trench 6 formed in the side edge regions of the N+ type source region 5 and penetrating from the N+ type source region 5 into the N-type channel region 4; a current spreading layer 7 located between the N-type drift region 3 and the N-type channel region 4; a plurality of P-type pillars 8 formed in the side edge regions of the N-type drift region 3 and penetrating the N-type drift region 3; the plurality of P-type pillars 8 include at least two adjacent first P-type pillar segments 81 and second P-type pillar segments 82 in the longitudinal direction, the first P-type pillar segment 81 being located near the bottom region of the N+ type substrate 2, and the second P-type pillar segment 82 being located near the top region of the current spreading layer 7, and... The horizontal width of the second P-type pillar 82 is smaller than the horizontal width of the first P-type pillar 81; the current spreading layer 7 is located in the lateral space on the side of the second P-type pillar 82 and is laterally adjacent to the second P-type pillar 82; the P-region 9 is formed in the side edge regions and sidewalls of the N-type channel region 4 and is in contact with the upper surface of the current spreading layer 7 and the lower surface of the N+ type source region 5; the source metal 10 is formed on the N+ type source region 5; the gate metal 11 is formed on the P-region 9 and is in contact with a portion of the P-region 9 pillars in the sidewall of the N-type channel region 4; wherein, the doping concentration of the multiple P-type pillars 8 decreases from the bottom region to the top region, and the doping concentration of the N-type drift region 3 increases from the bottom region to the top region, forming a vertically opposite complementary gradient; the doping concentration between the first P-type pillar 81 and the second P-type pillar 82 has a smooth transition. Thus, because the horizontal width of the second P-type pillar 82 is smaller than that of the first P-type pillar 81, lateral space is released in the top region. The current spreading layer 7 is located within this lateral space and is laterally adjacent to the second P-type pillar 82, allowing electrons to spread rapidly laterally after injection, achieving strong lateral current expansion at the JFET neck, thereby significantly reducing the specific on-resistance of the device. Since the doping concentration of the multiple P-type pillars 8 decreases from the bottom region to the top region, and the doping concentration of the N-type drift region 3 increases from the bottom region to the top region, forming a vertically opposite complementary gradient, and the doping concentration between the first P-type pillar 81 and the second P-type pillar 82 has a smooth transition, the vertical charge compensation channel has no concentration abrupt changes or potential barriers, ensuring the absolute continuity of the charge compensation channel and eliminating dynamic response hysteresis. Based on the synergistic effect of the stepped morphology and complementary gradient of the multiple P-type pillars 8, the device forms natural dynamic damping during switching, smoothing the switching waveform and improving the electromagnetic compatibility and overall stability of the device in complex power electronic systems.

[0050] The fabrication method of the silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction may include: Step 101: Provide an N+ type substrate 2, and epitaxially grow at least one N-type drift region 3 on the N+ type substrate 2, wherein the donor impurity concentration of each N-type drift region 3 increases from bottom to top.

[0051] Step 102: After the formation of each N-type drift region 3, P-type ion implantation is performed on both sides of the edge region of the N-type drift region 3 to form each P-type implantation region. Adjacent P-type implantation regions have a physical overlap in the vertical direction, and the horizontal width of the upper P-type implantation region is smaller than that of the lower P-type implantation region. The acceptor impurity concentration of the upper P-type implantation region is smaller than that of the lower P-type implantation region. The doping concentration of adjacent P-type implantation regions in the physical overlap region is controlled to have a smooth transition. Each P-type implantation region together constitutes multiple... The bottom part of the P-type column 8 is the first P-type column segment 81. The acceptor impurity concentration of the first P-type column segment 81 decreases from the bottom region to the top region. The N-type drift regions 3 of each layer together constitute the N-type drift region 3. The donor impurity concentration of the N-type drift region 3 increases from the bottom region to the top region, forming a longitudinally opposite complementary gradient with the P-type column. Since the horizontal width of the upper P-type injection region, i.e. the upper first P-type column segment 81, is smaller than the horizontal width of the lower P-type injection region, i.e. the lower first P-type column segment 81, the top region of the P-type column releases lateral space.

[0052] Figure 2 The schematic diagram illustrates the fabrication process flow of the first N-type drift segment 31. Figure 3 The schematic diagram illustrates the fabrication process flow of the first P-type column segment 81 corresponding to the first N-type drift segment 31. Figure 4 The schematic diagram illustrates the fabrication process flow of the second N-type drift segment 32. Figure 5 The schematic diagram illustrates the fabrication process flow of the first P-type column segment 81 corresponding to the second N-type drift segment 32. (See attached diagram.) Figures 2 to 5 As shown, exemplarily, at least one N-type drift region 3 includes two N-type drift regions 3, namely a first N-type drift segment 31 and a second N-type drift segment 32. The first N-type drift segment 31 is epitaxially grown on an N+ type substrate 2, and P-type ion implantation is performed on the two edge regions of the first N-type drift segment 31 to form corresponding P-type implantation regions, i.e., corresponding first P-type pillar segments 81. The second N-type drift segment 32 is epitaxially grown on the first N-type drift segment 31, and P-type ion implantation is performed on the two edge regions of the second N-type drift segment 32 to form corresponding P-type implantation regions, i.e., corresponding first P-type pillar segments 81. The donor impurity concentration of the second N-type drift segment 32 is higher than that of the first N-type drift segment 31, so that the donor impurity concentration of the N-type drift region 3 increases from bottom to top.

[0053] Step 103: Based on the lateral space released at the top of the P-type pillar, a current spreading layer 7 is formed above the N-type drift region 3. During the formation of the current spreading layer 7, the P-type pillar is extended longitudinally from the N-type drift region 3 into the current spreading layer 7, such that the horizontal width of the portion of the P-type pillar within the current spreading layer 7 (i.e., the second P-type pillar segment 82) is smaller than the horizontal width of the portion within the N-type drift region 3. The acceptor impurity concentration of the second P-type pillar segment 82 within the current spreading layer 7 is lower than the acceptor impurity concentration of the P-type pillar portion within the N-type drift region 3. The current spreading layer 7 fills the lateral space and is laterally adjacent to the top region of the P-type pillar. See details. Figure 6 and Figure 7 As shown, Figure 6 A schematic flowchart of the fabrication process of the current spreading layer 7 is shown. Figure 7 A schematic diagram of the preparation process of the second P-type column segment 82 is shown.

[0054] Step 104: Epitaxially grow an N-type channel region 4 on top of the current spreading layer 7. See details... Figure 8 As shown, Figure 8 The deposition process flow diagram of N-type channel zone 4 is schematically shown.

[0055] Step 105: Form an N+ type source region 5 above the N-type channel region 4. See details... Figure 9 As shown, Figure 9 The deposition process flow diagram of N+ type source region 5 is schematically shown.

[0056] Step 106: Trench 6 is etched to form on both sides of the edge region of the N+ source region 5. The trench 6 penetrates the N+ source region 5 and extends into the N-type channel region 4. See details. Figure 10 As shown, Figure 10 The etching process flow diagram of trench 6 is shown schematically.

[0057] Step 107: Based on the location of trench 6, perform P-type ion implantation on both sides of the edge region and sidewall of the N-type channel region 4 to form P-region 9, so that P-region 9 is in contact with the upper surface of the current spreading layer 7 and the lower surface of the N+ type source region 5. See details. Figure 11 As shown, Figure 11 The schematic diagram shows the preparation process flow chart of region P9.

[0058] Step 108: Form source metal 10 on the N+ type source region 5 and gate metal 11 on the P region 9, so that the gate metal 11 contacts a portion of the P region 9 located within the sidewall of the N-type channel region 4. See details. Figure 12 As shown, Figure 12 A schematic diagram of the fabrication process of drain metal 1, source metal 10 and gate metal 11 is shown.

[0059] Step 109: Form drain metal 1 under N+ type substrate 2. See details. Figure 12 As shown, Figure 12 A schematic diagram of the fabrication process of drain metal 1, source metal 10 and gate metal 11 is shown.

[0060] This invention discloses a method for fabricating silicon carbide junction field-effect transistors (JFETs) with a dual-gradient continuous superjunction. Through a two-dimensional synergistic design combining morphology reduction and high-density filling, it achieves strong lateral current expansion of electrons at the JFET neck without disrupting the global charge balance, thereby significantly reducing the specific on-resistance of the device. The method utilizes a reverse-crossing complementary gradient system of multiple P-type pillars 8 (lower denser, upper less dense) formed by the P-type injection regions of each layer and N-type drift regions 3 (upper denser, lower less dense). The high-density N-region at the top (including CSL) ensures extremely fast current flow, while the structure of multiple widened and concentrated P-type pillars 8 at the bottom generates an electric field anchoring effect, forcibly pulling the main electric field peak down to a deeper region near the substrate, achieving physical-level isolation protection for the surface gate. The vertical physical overlap of the injection regions at each level and the smooth transition of interface concentration ensure the absolute continuity of the charge compensation channel, eliminating dynamic response hysteresis. Meanwhile, the charge emission time difference generated by the longitudinal gradient forms a natural dynamic damping, smoothing the switching waveform, suppressing reverse recovery current spikes and oscillations, and improving the electromagnetic compatibility and overall stability of the device in complex power electronic systems.

[0061] It should be noted that the description of the above embodiments of the fabrication method of the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction is similar to the description of the above embodiments of the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction, and has similar beneficial effects. For technical details not disclosed in the embodiments of the fabrication method of the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction of the present invention, please refer to the description of the embodiments of the silicon carbide junction field-effect transistor with dual-gradient continuous superjunction of the present invention for understanding.

[0062] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction, characterized in that, It includes, from bottom to top, a drain metal, an N+ type substrate, an N-type drift region, an N-type channel region, and an N+ type source region; The trench is formed in the edge regions on both sides of the N+ type source region and extends through the N+ type source region into the N type channel region; A current spreading layer is located between the N-type drift region and the N-type channel region; Multiple P-type pillars are formed on both sides of the N-type drift region and penetrate the N-type drift region; the multiple P-type pillars include at least two adjacent first P-type pillar segments and second P-type pillar segments in the longitudinal direction, the first P-type pillar segment is located near the bottom region of the N+ type substrate, the second P-type pillar segment is located near the top region of the current spreading layer, and the horizontal width of the second P-type pillar segment is smaller than the horizontal width of the first P-type pillar segment; the current spreading layer is located in the lateral space on the side of the second P-type pillar segment and is laterally adjacent to the second P-type pillar segment; The P-region is formed in the two edge regions and sidewalls of the N-type channel region, and is in contact with the upper surface of the current spreading layer and the lower surface of the N+ type source region. Source metal is formed on the N+ type source region; Gate metal is formed on the P-region and contacts a portion of the P-region pillar within the sidewall of the N-type channel region; The doping concentration of the plurality of P-type pillars decreases from the bottom region to the top region, while the doping concentration of the N-type drift region increases from the bottom region to the top region, forming a vertically opposite complementary gradient; the doping concentration between the first P-type pillar segment and the second P-type pillar segment has a smooth transition.

2. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The N-type drift region includes at least a first N-type drift segment and a second N-type drift segment that are longitudinally adjacent. Both the first N-type drift segment and the second N-type drift segment are located on the side of the first P-type pillar segment. The lower surface of the first N-type drift segment is in contact with the N+ type substrate, and the upper surface of the second N-type drift segment is in contact with the current spreading layer. The donor impurity concentration of the first N-type drift segment is lower than that of the second N-type drift segment.

3. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The horizontal width of each P-shaped column decreases from bottom to top in a ratio of 10% to 60% for each layer.

4. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The concentration of acceptor impurities in each P-type column decreases layer by layer from bottom to top in increments of 1.5 to 5 times.

5. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The donor impurity concentration of the current spread layer is 5 to 50 times the highest donor impurity concentration of the N-type drift region.

6. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The ratio of the acceptor impurity concentration in the first P-type column segment to the acceptor impurity concentration in the second P-type column segment is 1.2 to 5.

7. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The plurality of P-shaped columns comprises at least three layers of adjacent P-shaped column segments in the longitudinal direction, with the horizontal width of each P-shaped column segment decreasing layer by layer from bottom to top.

8. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The first P-type column segment and the second P-type column segment have a physical overlap region in the longitudinal direction, and the doping concentration of the physical overlap region smoothly transitions from the first P-type column segment to the second P-type column segment.

9. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 2, characterized in that, The donor impurity concentrations of the first N-type drift segment and the second N-type drift segment increase continuously from bottom to top, and there is no abrupt change in doping concentration at the junction of the first N-type drift segment and the second N-type drift segment.

10. The silicon carbide junction field-effect transistor with a dual-gradient continuous superjunction according to claim 1, characterized in that, The horizontal width and acceptor impurity concentration of the first P-type column segment are both greater than those of the second P-type column segment, so that the first P-type column segment forms an electric field anchoring region. The electric field anchoring region is used to anchor the peak value of the main electric field in the reverse blocking state of the device to the N+ type substrate side.

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