JFET device

Abstract

This invention discloses a JFET device. The device cell structure includes: a gate region formed on the side and bottom surfaces of a trench; a source region formed on the top surface of a plateau region between the trenches and divided into a first source region with a width equal to the width of the plateau region and a second source region with a width less than the width of the plateau region; the first and second source regions are in contact along the length of the plateau region; a source contact hole is located on top of the first source region and is in contact with part or all of the first source region; the top of the source contact hole is connected to the source. A first conduction path is formed between the drift region and the source, consisting of a channel region at the bottom of the first source region, the first source region to the source contact hole, and a second conduction path consisting of a channel region at the bottom of the second source region, the second source region, the first source region to the source contact hole; the second conduction path has a first internal source resistance formed by the path from the second source region to the first source region. This invention enables adaptive negative feedback balance of the device current.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a JFET device. Background Technology

[0002] Silicon carbide (SiC) JFETs, with their inherent advantages as wide-bandgap semiconductors, possess characteristics such as low conduction loss, fast switching speed, high temperature resistance, and excellent high-frequency characteristics, making them the core preferred device for high-voltage, high-frequency, and high-power power electronic conversion systems. In engineering scenarios such as new energy, rail transportation, and high-voltage power conversion, the current rating of a single SiC JFET is limited, necessitating the use of multiple chips in parallel to achieve high current and high power capacity expansion. Therefore, the current sharing capability and parallel operation stability of multiple transistors in parallel are key indicators determining the reliability of high-power SiC JFET modules.

[0003] The core bottleneck currently hindering the large-scale application of SiC JFETs in parallel is not peripheral circuit issues such as packaging layout or driver routing, but rather the inconsistency of intrinsic parameters at the wafer and chip levels. The core turn-on and conduction characteristics of SiC JFETs are determined by the gate process, and are affected by wafer material uniformity, gate etching, ion implantation, and junction depth process fluctuations. Within the same wafer and between devices in the same batch, there is a common deviation in the threshold voltage Vth. This intrinsic parameter difference cannot be completely eliminated by conventional device selection, symmetrical PCB layout, or unified drive signals. This directly leads to an imbalance in static and dynamic current distribution when multiple chips are connected in parallel, resulting in a series of problems such as current concentration, single-transistor overload, switching oscillation, and instability under high dv / dt conditions. These issues severely limit the power rating and long-term reliability of SiC JFET parallel modules.

[0004] Existing conventional SiC JFET chip structures rely entirely on the consistency of chip factory parameters to achieve parallel current sharing. However, the Vth non-uniformity caused by gate process fluctuations will continue to amplify the parallel mismatch problem under two core operating conditions: steady-state conduction and high-frequency high dv / dt switching. The specific failure mechanism can be divided into two aspects: 1. Steady-state conduction condition: Discrete Vth leads to current concentration between and within chips, creating a vicious cycle that triggers thermal runaway, including: Due to fluctuations in gate manufacturing processes, the voltage threshold (Vth) of SiC JFET chips connected in parallel within the same batch varies, and local Vth unevenness also exists within the wafer area of ​​a single chip. When operating in parallel, chips / local areas with lower Vth have stronger conduction capabilities and larger conduction currents, naturally creating a current concentration effect.

[0005] Meanwhile, SiC JFET devices inherently exhibit temperature coupling characteristics: power consumption and junction temperature are higher in areas of concentrated current. This high temperature further reduces the local voltage threshold (Vth), leading to increased conductivity and current accumulation in these areas, creating a vicious cycle of current concentration – temperature rise – Vth decrease – further current concentration. This problem ultimately results in some chips in the parallel module operating under prolonged overload, exceeding single-tube stress limits, inconsistent device aging rates, and in severe cases, single-point thermal breakdown, ultimately causing the entire parallel module to fail. Conventional device sorting can only remove extremely abnormal devices; it cannot eliminate the gradual current unevenness caused by small Vth process deviations, nor can it improve the uneven current distribution within a single chip.

[0006] 2. High dv / dt high-frequency switching conditions: Non-uniform gate parameters induce dynamic mismatch and switching instability, including: Under high-frequency switching and high dv / dt transient conditions, the gate process non-uniformity defects of existing SiC JFETs are further amplified. The gate capacitance and gate junction characteristics of each parallel chip and each region of the chip vary with the Vth deviation, resulting in significant differences in the transient response speed and Miller plateau characteristics of the device during turn-on and turn-off.

[0007] Under a unified external drive signal, parallel devices with discrete Vth parameters will exhibit switching timing misalignment and uneven transient current distribution. Some devices will turn on first and turn off later, bearing instantaneous inrush currents far exceeding their rated levels. Simultaneously, under high dv / dt transient excitation, inconsistencies in gate parameters can induce dynamic impedance mismatch in the branches, easily leading to switching oscillations, voltage and current spikes, increased device switching losses and electromagnetic interference, and significantly reduced stability and safety of high-power parallel systems under high-frequency operating conditions.

[0008] like Figure 1 The figure shows the edge of an existing JFET device. Figure 3 A schematic diagram of the cross-sectional structure at line AA1 in the diagram; as shown. Figure 2 The figure shows the edge of an existing JFET device. Figure 3 A schematic diagram of the cross-sectional structure at line AA2 in the middle; as shown. Figure 3 The diagram shown is a top view of an existing JFET device; taking an N-type device as an example, an existing JFET device includes: N-type doped semiconductor substrate 101.

[0009] A platform region 104 is formed in the top region of the semiconductor substrate 101 between two adjacent trenches 103.

[0010] A P-type doped gate region 102 is formed in the semiconductor substrate 101 on the side and bottom surfaces of the trench 103.

[0011] Each of the grooves 103 has a strip-shaped structure and is arranged in parallel, and the platform area 104 also has a strip-shaped structure.

[0012] An N-type heavily doped source region 106 is formed on the top surface of the platform region 104. The source region 106 is formed by ion implantation. Figure 3 In the diagram, the ion implantation region corresponding to the source region 106 is represented by a dashed box 110. The region where the implantation region corresponding to the dashed box 110 intersects with the plateau region 104 is the region corresponding to the source region 106. An N-type lightly doped source side region 107 is also formed on the side of the gate region 102 on the side of the trench 103. The source side region 107 is formed in the semiconductor substrate 101 through light doping implantation on the side of the trench 103. After the impurities implanted by the light doping implantation are superimposed on the semiconductor substrate 101, the doping concentration of the source side region 107 is greater than the doping concentration of the semiconductor substrate 101, but less than the doping concentration of the source region 106.

[0013] Along the width direction of the platform region 104, the width of the source region 106 is equal to the width of the platform region 104.

[0014] The semiconductor substrate 101 located at the bottom of the source region 106 and between the gate region 102 forms a channel region, and the semiconductor substrate 101 at the bottom of the channel region forms a drift region.

[0015] An oxide layer 105 is filled in the trench 103.

[0016] An interlayer film (not shown) covers the surface of the semiconductor substrate 101 of the oxide layer 105 and the platform region 104. Figure 1 and Figure 2 At the corresponding cross-sectional locations, the interlayer membranes were all removed.

[0017] The source contact hole 108, which passes through the interlayer film, is located on top of the source region 106 and contacts the source region 106; the source contact hole 108 is connected to the source composed of the front metal layer 210.

[0018] When the device is turned on, the current conduction path is as shown by the dashed arrow 109. The current enters the channel region from the drift region, and after entering the source region 106, it directly enters the source through the source contact hole 108. Summary of the Invention

[0019] The technical problem to be solved by the present invention is to provide a JFET device that can achieve adaptive negative feedback balance of device current, thereby facilitating current sharing within or between chips, thus improving chip robustness and facilitating chip parallel connection.

[0020] To solve the above-mentioned technical problems, the device cell structure of the JFET device provided by the present invention includes: Semiconductor substrates doped with the first conductivity type.

[0021] A platform region is formed in the top region of the semiconductor substrate between two adjacent trenches.

[0022] A gate region doped with a second conductivity type is formed in the semiconductor substrate on the side and bottom surfaces of the trench.

[0023] Each of the grooves has a strip-shaped structure and is arranged in parallel, and the platform area also has a strip-shaped structure.

[0024] A source region heavily doped with a first conductivity type is formed on the top surface of the platform region.

[0025] The source region is divided into a first source region and a second source region.

[0026] Along the width direction of the platform area, the width of the first source area is equal to the width of the platform area, and the width of the second source area is less than the width of the platform area.

[0027] Along the length of the platform region, the first source region and the second source region are in contact.

[0028] The semiconductor substrate located at the bottom of the first source region and the second source region and between the gate region forms a channel region, and the semiconductor substrate at the bottom of the channel region forms a drift region.

[0029] The trench is filled with a first dielectric layer.

[0030] An interlayer film covers the surface of the semiconductor substrate between the first dielectric layer and the platform region.

[0031] A source contact hole passing through the interlayer film is located at the top of the first source region, and the source contact hole contacts part or all of the first source region; the source contact hole is connected to a source electrode composed of a front-side metal layer. The surface of the second source region is covered by the interlayer film.

[0032] A first conductive path is formed between the drift region and the source electrode, consisting of the channel region at the bottom of the first source region, the first source region to the source contact hole, and a second conductive path consisting of the channel region at the bottom of the second source region, the second source region, the first source region to the source contact hole; the second conductive path has a first internal source resistance formed by the path from the second source region to the first source region, and the first internal source resistance forms an adaptive negative feedback balance structure of the device unit structure.

[0033] A further improvement is that a lightly doped source side region of a first conductivity type is also formed on the side of the gate region on the side of the trench, and the bottom surface of the source side region is located above the bottom surface of the gate region at the bottom of the bottom surface of the trench.

[0034] A further improvement is that the bottom surface of the first source region covers the corresponding gate region and the source side region.

[0035] A further improvement is that, along the width direction of the platform area, the center position of the second source area is aligned with the center position of the platform area, and the second source area and the source side areas on both sides are spaced apart.

[0036] A further improvement is that the JFET device is composed of multiple of the aforementioned device unit structures connected in parallel.

[0037] A further improvement is that, in the JFET device, the platform regions of each of the device unit structures are arranged in parallel.

[0038] Each of the first source regions is formed by implantation of first ions heavily doped with the first conductivity type.

[0039] The area of ​​the first ion implantation includes the first implantation region.

[0040] The width side of the first implantation region is perpendicular to the length side of the platform region. Along the width direction of each platform region, the first implantation region intersects the platform region and the channel region in sequence. The impurities implanted by the first ion in the intersection region of the first implantation region and the platform region form the doped impurities of the first source region.

[0041] A further improvement is that each of the second source regions is formed by second ion implantation with either heavy or light doping of the first conductivity type.

[0042] The second ion implantation region includes the second implantation region; each second implantation region is located in the corresponding platform region, and the doping impurities of the second source region are formed by the impurities implanted by the second ion in the second implantation region.

[0043] A further improvement is that when the second ion implantation is heavily doped with the first conductivity type, the first ion implantation and the second ion implantation are performed in the same ion implantation or are independent of each other; when the second ion implantation is lightly doped with the first conductivity type, the first ion implantation and the second ion implantation are independent of each other.

[0044] A further improvement is that the second injection region is located outside the width side of one side of the first injection region; or, the second injection region is located outside the width sides of both sides of the first injection region.

[0045] A further improvement is that, along the length of the platform region, the length of the source contact hole is less than the length of the first injection region. The width side of the source contact hole is located inside the width side of the first injection region.

[0046] A further improvement is that the implantation dose of the second ion implantation, the width and length of the second implantation region meet the requirements of the first internal source resistance. The smaller the implantation dose of the second ion implantation, the larger the first internal source resistance; the smaller the width of the second implantation region, the larger the first internal source resistance; and the larger the length of the second implantation region, the larger the first internal source resistance.

[0047] A further improvement is that a heavily doped drain region of a first conductivity type is formed on the back side of the drift region.

[0048] A further improvement is that the semiconductor substrate is made of SiC.

[0049] A further improvement is that the material of the first dielectric layer includes an oxide layer.

[0050] A further improvement is that the second conduction path also has a second internal source resistor formed by a distribution path from the bottom channel region to the second source region, and the first internal source resistor and the second internal source resistor are connected in series to form an adaptive negative feedback balance structure of the device unit structure.

[0051] A further improvement is that the JFET device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the JFET device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0052] This invention features a unique design for the source region and source contact hole structure of the device unit structure. The source region is configured as a first source region and a second source region. A source contact hole with a width equal to the width of the plateau region is located at the top of the first source region. The second source region does not have a source contact hole at its top and its width is less than the width of the plateau region. The second and first source regions are connected only along the length of the plateau region to form the source region. This prevents the current in the second source region from directly connecting to the source contact hole. Instead, the current flows along the length of the second source region and enters the first source region before connecting to the source contact hole. Because the second source region is narrower and longer, it possesses a parasitic resistance, namely a first internal source resistance. This first internal source resistance serves as a structural feature of the device unit structure. The adaptive negative feedback balancing structure enables adaptive negative feedback balancing of device current. That is, when the current flowing through the JFET device or its corresponding device cell increases, the voltage across the first internal source resistor also increases, thus increasing the source voltage of the JFET device or device cell while keeping the gate voltage constant. Therefore, the gate-source voltage decreases, resulting in a decrease in the current flowing through the JFET device or device cell. Conversely, when the current flowing through the JFET device or device cell decreases, the current increases after negative feedback through the first internal source resistor. Therefore, this invention ultimately facilitates current sharing within or between chips, improving chip robustness and enabling parallel chip connections.

[0053] In this invention, the width of the second source region is narrower than the width of the first active region. Therefore, the current distribution from the bottom channel region to the second source region is narrower than the current distribution from the channel region to the first source region. This results in an additional parasitic resistance, namely the second internal source resistance, in the current distribution from the channel region to the second source region. The first internal source resistance and the second internal source resistance are connected in series, which will further increase the internal source resistance, thereby further enhancing the effect of adaptive negative feedback balance.

[0054] This invention is particularly suitable for improving the parallel current sharing characteristics of SiC JFET devices, including: firstly, it can accurately offset the Vth dispersion caused by gate process fluctuations, balance the conduction differences between chips in the same batch and within a single chip, automatically distribute the parallel current evenly under steady state, and eliminate the vicious cycle of current concentration and thermal runaway positive feedback; secondly, under high dv / dt high-frequency transient conditions, it can suppress the switching timing mismatch of different devices and different regions, balance the dynamic switching current, weaken transient current spikes and switching oscillations, and significantly improve the working stability of SiC JFET parallel modules in high-frequency and high-power scenarios. Attached Figure Description

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 It is the edge of existing JFET devices Figure 3 A schematic diagram of the cross-sectional structure at line AA1 in the middle; Figure 2 It is the edge of existing JFET devices Figure 3 A schematic diagram of the cross-sectional structure at line AA2 in the middle; Figure 3 This is a top view of an existing JFET device. Figure 4 This is the edge of the JFET device in the embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB1 ​​in the middle; Figure 5 This is the edge of the JFET device in the embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB2 in the middle; Figure 6 This is the edge of the JFET device in the embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB3 in the middle; Figure 7 This is the edge of the JFET device in the embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB4 in the middle; Figure 8 This is a top view structural diagram of the JFET device according to an embodiment of the present invention; Figure 9 This is a circuit structure diagram of the JFET device according to an embodiment of the present invention. Detailed Implementation

[0056] like Figure 4 As shown, this is the edge of the JFET device in an embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB1 ​​in the middle; as shown. Figure 5 As shown, this is the edge of the JFET device in an embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB2 in the middle; as shown. Figure 6 As shown, this is the edge of the JFET device in an embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB3 in the middle; as shown. Figure 7 As shown, this is the edge of the JFET device in an embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at line BB4 in the middle; as shown. Figure 8 The diagram shown is a top view of the JFET device according to an embodiment of the present invention; the device unit structure of the JFET device according to an embodiment of the present invention includes: Semiconductor substrate 201 doped with a first conductivity type.

[0057] A platform region 204 is formed in the top region of the semiconductor substrate 201 between two adjacent trenches 203.

[0058] A gate region 202 doped with a second conductivity type is formed in the semiconductor substrate 201 on the side and bottom surfaces of the trench 203.

[0059] Each of the grooves 203 has a strip-shaped structure and is arranged in parallel, and the platform area 204 also has a strip-shaped structure.

[0060] A source region heavily doped with a first conductivity type is formed on the top surface of the platform region 204.

[0061] The source region is divided into a first source region 206a and a second source region 206b.

[0062] Along the width direction of the platform region 204, the width of the first source region 206a is equal to the width of the platform region 204, and the width of the second source region 206b is less than the width of the platform region 204.

[0063] Along the length of the platform region 204, the first source region 206a and the second source region 206b are in contact.

[0064] The semiconductor substrate 201 located at the bottom of the first source region 206a and the second source region 206b and located between the gate region 202 forms a channel region, and the semiconductor substrate 201 at the bottom of the channel region forms a drift region.

[0065] A first dielectric layer 205 is filled in the trench 203. In this embodiment of the invention, the material of the first dielectric layer 205 includes an oxide layer.

[0066] An interlayer film 209 covers the surface of the semiconductor substrate 201 of the first dielectric layer 205 and the platform region 204.

[0067] A source contact hole 208 passing through the interlayer film 209 is located on top of the first source region 206a, and the source contact hole 208 is in contact with part or all of the first source region 206a; the source contact hole 208 is connected to a source electrode composed of a front metal layer 210. The surface of the second source region 206b is covered by the interlayer film 209.

[0068] A first conductive path is formed between the drift region and the source electrode, consisting of the channel region at the bottom of the first source region 206a, the first source region 206a to the source contact hole 208, and a second conductive path consisting of the channel region at the bottom of the second source region 206b, the second source region 206b, the first source region 206a to the source contact hole 208. The second conductive path has a first internal source resistance R1 formed by the path from the second source region 206b to the first source region 206a. The first internal source resistance R1 forms an adaptive negative feedback balance structure of the device unit structure. Figure 4 The first conductive path is represented by the dashed arrow 211. Figure 6 The dashed arrow 212 in the image represents the second conductive path. Figure 5 The dashed arrow 212a is used to represent the path from the channel region at the bottom of the second source region 206b to the second source region 206b in the second conduction path.

[0069] Compare Figure 5 The dashed arrow 212a in the image corresponds to the path from the channel region to the second source region 206b, and... Figure 4 As can be seen from the path from the channel region to the first source region 206a corresponding to the dashed arrow 211, the second source region 206b is narrower and the current is more concentrated, thus increasing the resistance. Therefore, in this embodiment of the invention, the second conduction path also includes a second internal source resistor R2 formed by the distribution path from the bottom channel region to the second source region. The first internal source resistor R1 and the second internal source resistor R2 are connected in series to form an adaptive negative feedback balance structure of the device unit structure.

[0070] In this embodiment of the invention, a lightly doped source side region 207 of a first conductivity type is further formed on the side of the gate region 202 on the side of the trench 203. The bottom surface of the source side region 207 is located above the bottom surface of the gate region 202 at the bottom of the bottom surface of the trench 203. The source side region 207 is formed in the semiconductor substrate 201 by lightly doping implantation on the side of the trench 203. After the impurities implanted by the light doping implantation are superimposed on the semiconductor substrate 201, the doping concentration of the source side region 207 is greater than the doping concentration of the semiconductor substrate 201, but less than the doping concentration of the first source region 206a.

[0071] The bottom surface of the first source region 206a covers the corresponding gate region 202 and the source side region 207.

[0072] In this embodiment of the invention, the center position of the second source region 206b is aligned with the center position of the platform region 204 along the width direction of the platform region 204, and the second source region 206b and the source side regions 207 on both sides are spaced apart.

[0073] In this embodiment of the invention, the JFET device is composed of multiple device unit structures connected in parallel. For example... Figure 8 As shown, each of the platform regions 204 forms a device unit structure, and the device unit structures in the multiple platform regions 204 form a parallel structure.

[0074] In the JFET device, the platform regions 204 of each device unit structure are arranged in parallel.

[0075] Each of the first source regions 206a is formed by first ion implantation with heavy doping of the first conductivity type.

[0076] The area of ​​the first ion implantation includes the first implantation region. Figure 8 In the diagram, the first injection region is represented by a dashed box 213.

[0077] The width side of the first implantation region is perpendicular to the length side of the platform region 204. Along the width direction of each platform region 204, the first implantation region intersects the platform region 204 and the channel region in sequence. The impurities implanted by the first ion in the intersection region of the first implantation region and the platform region 204 form the doped impurities of the first source region 206a.

[0078] In this embodiment of the invention, each of the second source regions 206b is formed by second ion implantation with heavy doping of the first conductivity type. In other embodiments, each of the second source regions 206b can also be formed by second ion implantation with light doping of the first conductivity type.

[0079] The second ion implantation region includes the second implantation region; each second implantation region is located in the corresponding platform region 204, and the doping impurities of the second source region 206b are formed by the impurities implanted by the second ion implantation in the second implantation region. Figure 8 In this context, the range of the second injection region is the same as the range of the second source region 206b.

[0080] In this embodiment of the invention, the first ion implantation and the second ion implantation are performed in the same ion implantation. Since it is necessary to ensure that the first ion implantation is a heavily doped implantation of the first conductivity type, the second ion implantation is also a heavily doped implantation of the first conductivity type. In other embodiments, the first ion implantation and the second ion implantation can be independent of each other. In this case, the first ion implantation and the second ion implantation need to be combined with an additional photomask pattern. In this case, the first internal source resistance R1 can be adjusted by adjusting the second ion implantation. In this case, the second ion implantation can be heavily or lightly doped of the first conductivity type, and the specific implantation dose can be set according to actual needs.

[0081] In this embodiment of the invention, the second injection region is located outside the width side of one side of the first injection region. Figure 8 The diagram shows a structure where the second injection region is located outside the width edge of one side of the first injection region. In other embodiments, the second injection region may also be located outside the width edges of both sides of the first injection region.

[0082] In this embodiment of the invention, the length of the source contact hole 208 is less than the length of the first injection region along the length direction of the platform region 204. The width side of the source contact hole 208 is located inside the width side of the first injection region. Figure 8 In the diagram, the area where the source contact hole 208 is formed is represented by a dashed box 214.

[0083] In this embodiment of the invention, the implantation dose of the second ion implantation, the width and length of the second implantation region meet the size requirements of the first internal source resistance R1. The smaller the implantation dose of the second ion implantation, the larger the first internal source resistance R1; the smaller the width of the second implantation region, the larger the first internal source resistance R1; and the larger the length of the second implantation region, the larger the first internal source resistance R1.

[0084] A heavily doped drain region of the first conductivity type (not shown) is formed on the back side of the drift region.

[0085] In this embodiment of the invention, the semiconductor substrate 201 is made of SiC. The JFET device is a SiC JFET device. In other embodiments, the semiconductor substrate 201 may also be made of other semiconductor materials, such as silicon, germanium-silicon, etc.

[0086] In this embodiment of the invention, the JFET device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the JFET device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0087] like Figure 9 The diagram shown is a circuit structure diagram of a JFET device according to an embodiment of the present invention. Figure 9 In the diagram, the JFET device can be split into a first JFET (shown by dashed box 301) and a second JFET (shown by dashed box 302) connected in parallel. The source S1 of the second JFET is also connected to the source S2 of the first JFET through an internal source resistor R, which is the series resistance of the first internal source resistor R1 and the second internal source resistor R2. The first JFET and the second JFET share a common gate G and a common drain D. The drain current is divided into two paths: the current in the first conduction path (shown by dashed arrow 211) and the current in the second conduction path (shown by dashed arrow 212). For the second conduction path, when the current increases, the voltage across the internal source resistor R increases, and the corresponding gate-source voltage Vgs decreases, thus reducing the current and suppressing the increase in current.

[0088] Figure 9 Source S1 corresponds to the second source region 206b, and source S2 corresponds to the first source region 206a. It can be seen that if the current of a local chip or a chip in a parallel circuit is large, then V... S2 =I*R will increase, V S2 This indicates the voltage at the source S2. A decrease in Vgs suppresses current. If a local area of ​​the chip or a chip in a parallel circuit has a higher temperature, increasing R1 will similarly reduce Vgs. s2 This negative feedback process promotes current sharing within or between chips, improving chip robustness and facilitating parallel connection. Simultaneously, the second source region 206b in the R-channel, i.e., the second conduction path, expands the current from the drain, which helps reduce Rdson, the source-drain on-resistance.

[0089] In this embodiment of the invention, the structure of the source region and the source contact hole 208 of the device unit structure is specially configured. The source region is set as a first source region 206a and a second source region 206b. The first source region 206a has a source contact hole 208 at its top with a width equal to the width of the plateau region 204. The second source region 206b does not have a source contact hole 208 at its top and its width is less than the width of the plateau region 204. The second source region 206b and the first source region 206a are connected only in the length direction of the plateau region 204 to form the source region. In this way, the current in the second source region 206b cannot be directly connected to the source contact hole 208. Instead, it flows along the length direction of the second source region 206b and enters the first source region 206a before connecting to the source contact hole 208. Because the second source region 206b is narrower and longer, it has parasitic characteristics. The resistor is the first internal source resistor R1. The first internal source resistor R1 can serve as an adaptive negative feedback balancing structure for the device cell structure and can achieve adaptive negative feedback balancing of the device current. That is, when the current flowing through the JFET device or the corresponding device cell structure of the JFET device increases, the voltage across the first internal source resistor R1 will also increase. Thus, the source voltage of the JFET device or the corresponding device cell structure will also increase, while the gate voltage remains unchanged, so the gate-source voltage will decrease, thereby reducing the current of the JFET device or the device cell structure. Conversely, when the current of the JFET device or the device cell structure decreases, the current will also increase after the negative feedback of the first internal source resistor R1. Therefore, the embodiments of the present invention ultimately facilitate current sharing within the chip or between chips, thereby improving the robustness of the chip and facilitating chip parallel connection.

[0090] In this embodiment of the invention, the width of the second source region 206b is narrower than the width of the first active region 206a. Therefore, the current distribution from the bottom channel region to the second source region 206b is narrower than the current distribution from the channel region to the first source region. This results in an additional parasitic resistance, namely the second internal source resistance R2, in the current distribution from the channel region to the second source region 206b. The series connection of the first internal source resistance R1 and the second internal source resistance R2 will further increase the internal source resistance R, thereby further enhancing the effect of adaptive negative feedback balance.

[0091] The embodiments of the present invention are particularly suitable for improving the parallel current sharing characteristics of SiC JFET devices, including: firstly, accurately offsetting the Vth dispersion caused by gate process fluctuations, balancing conduction differences between chips in the same batch and within a single chip, automatically sharing the parallel current in steady state, and eliminating the vicious cycle of current concentration and thermal runaway positive feedback; secondly, under high dv / dt high-frequency transient conditions, suppressing the switching timing mismatch of different devices and different regions, balancing dynamic switching current, weakening transient current spikes and switching oscillations, and significantly improving the working stability of SiC JFET parallel modules in high-frequency and high-power scenarios.

[0092] To address the inherent technical defects of existing SiC JFETs, such as Vth dispersion, poor parallel current sharing, and insufficient stability under high and low operating conditions due to gate process fluctuations, this invention abandons the passive improvement schemes of traditional external circuit optimization and device selection. Instead, it innovates and improves from the internal chip structure level. By introducing a functional resistor structure, namely the internal source resistor R, into the device source path, a built-in current-temperature negative feedback self-balancing mechanism can be constructed. This fundamentally suppresses the current concentration problem inside and between chips, significantly improving the parallel compatibility and operational stability of SiC JFETs.

[0093] In this embodiment of the invention, a dedicated resistor structure, namely the internal source resistor R, is added to the source current path of the SiC JFET chip, so that the source potential of the device can adaptively and dynamically shift with the changes in the path current and local temperature. This is a built-in passive control unit of the device, which does not rely on external driving, detection and control circuits, and has a simple structure and high reliability.

[0094] The negative feedback self-balancing mechanism implemented in this embodiment of the invention includes: When a chip or a local area of ​​a chip in a parallel system experiences current accumulation and increased current flow due to a low Vth, the voltage drop across the source path resistance (i.e., the internal source resistance R) increases synchronously, causing the source bias potential of that local area to rise. With the gate drive voltage Vge relatively fixed, this increase in source potential directly leads to a passive decrease in the effective gate-source bias voltage Vgs of that region.

[0095] This process forms a stable negative feedback regulation mechanism: abnormal current increase → increased voltage drop across the internal source resistor R → decreased effective bias Vgs → suppressed device conduction capability → automatic limitation of local overcurrent. Conversely, for chips / regions with high Vth and low current, the source resistor voltage drop is small and the bias Vgs is relatively sufficient, so the conduction capability is not suppressed and the current carrying ratio can be automatically increased.

[0096] This invention addresses the core pain points of existing JFET devices by utilizing the adaptive negative feedback effect of the internal source resistor R: First, it precisely offsets the Vth dispersion caused by gate process fluctuations, balances conduction differences between chips in the same batch and within a single chip, and automatically distributes parallel current evenly under steady-state conditions, preventing the vicious cycle of current concentration and thermal runaway positive feedback. Second, under high dv / dt high-frequency transient conditions, it can suppress switching timing mismatches between different devices and regions, balance dynamic switching current, weaken transient current spikes and switching oscillations, and significantly improve the working stability of SiC JFET parallel modules in high-frequency, high-power scenarios.

[0097] Compared to existing traditional external optimization solutions, the embodiments of the present invention are native optimizations at the chip structure level, which do not require increasing the cost of peripheral circuits or selecting high-precision devices. They are highly adaptable and reliable, solving the industry technical problems of poor current sharing and insufficient stability under operating conditions of SiCJFETs in parallel from the device's original level.

[0098] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A JFET device, characterized in that, The device unit structure includes: Semiconductor substrates doped with the first conductivity type; A platform region is formed in the top region of the semiconductor substrate between two adjacent trenches; A gate region doped with a second conductivity type is formed in the semiconductor substrate on the side and bottom surfaces of the trench; Each of the grooves has a strip-shaped structure and is arranged in parallel, and the platform area also has a strip-shaped structure; A heavily doped source region of the first conductivity type is formed on the top surface of the platform region; The source region is divided into a first source region and a second source region; Along the width direction of the platform area, the width of the first source area is equal to the width of the platform area, and the width of the second source area is less than the width of the platform area; Along the length of the platform region, the first source region and the second source region are in contact with each other; The semiconductor substrate located at the bottom of the first source region and the second source region and between the gate region forms a channel region, and the semiconductor substrate at the bottom of the channel region forms a drift region; The trench is filled with a first dielectric layer; An interlayer film covers the surface of the semiconductor substrate between the first dielectric layer and the platform region; The source contact hole passing through the interlayer film is located at the top of the first source region, and the source contact hole is in contact with part or all of the first source region; the source contact hole is connected to the source electrode composed of the front metal layer; the surface of the second source region is covered by the interlayer film; A first conductive path is formed between the drift region and the source electrode, consisting of the channel region at the bottom of the first source region, the first source region to the source contact hole, and a second conductive path consisting of the channel region at the bottom of the second source region, the second source region, the first source region to the source contact hole; the second conductive path has a first internal source resistance formed by the path from the second source region to the first source region, and the first internal source resistance forms an adaptive negative feedback balance structure of the device unit structure.

2. The JFET device as described in claim 1, characterized in that: A lightly doped source side region of a first conductivity type is also formed on the side of the gate region on the side of the trench, and the bottom surface of the source side region is located above the bottom surface of the gate region at the bottom of the bottom surface of the trench.

3. The JFET device as described in claim 2, characterized in that: The bottom surface of the first source region covers the corresponding gate region and the source side region.

4. The JFET device as described in claim 2, characterized in that: Along the width direction of the platform area, the center position of the second source area is aligned with the center position of the platform area, and the second source area and the source side areas on both sides are spaced apart.

5. The JFET device as described in claim 1, characterized in that: A JFET device is composed of multiple such device unit structures connected in parallel.

6. The JFET device as described in claim 5, characterized in that: In the JFET device, the plateau regions of each of the device unit structures are arranged in parallel. Each of the first source regions is formed by implantation of first ions heavily doped with the first conductivity type; The area of ​​the first ion implantation includes the first implantation region; The width side of the first implantation region is perpendicular to the length side of the platform region. Along the width direction of each platform region, the first implantation region intersects the platform region and the channel region in sequence. The impurities implanted by the first ion in the intersection region of the first implantation region and the platform region form the doped impurities of the first source region.

7. The JFET device as described in claim 6, characterized in that: Each of the second source regions is formed by implanting second ions that are heavily or lightly doped with the first conductivity type. The second ion implantation region includes the second implantation region; each second implantation region is located in the corresponding platform region, and the doping impurities of the second source region are formed by the impurities implanted by the second ion in the second implantation region.

8. The JFET device as claimed in claim 7, characterized in that: When the second ion implantation is a heavily doped first conductivity type, the first ion implantation and the second ion implantation are performed in the same ion implantation or are independent of each other; when the second ion implantation is a lightly doped first conductivity type, the first ion implantation and the second ion implantation are independent of each other.

9. The JFET device as claimed in claim 7, characterized in that: The second injection region is located outside the width side of one side of the first injection region; or, the second injection region is located outside the width sides of both sides of the first injection region.

10. The JFET device as claimed in claim 6, characterized in that: Along the length of the platform region, the length of the source contact hole is less than the length of the first injection region, and the width side of the source contact hole is located inside the width side of the first injection region.

11. The JFET device as claimed in claim 7, characterized in that: The implantation dose of the second ion implantation, the width and length of the second implantation region meet the requirements of the first internal source resistance. The smaller the implantation dose of the second ion implantation, the larger the first internal source resistance. The smaller the width of the second implantation region, the larger the first internal source resistance. The larger the length of the second implantation region, the larger the first internal source resistance.

12. The JFET device as claimed in claim 1, characterized in that: A heavily doped drain region of the first conductivity type is formed on the back side of the drift region.

13. The JFET device as claimed in claim 1, characterized in that: The semiconductor substrate is made of SiC.

14. The JFET device as claimed in claim 1, characterized in that: The material of the first dielectric layer includes an oxide layer.

15. The JFET device as claimed in claim 1, characterized in that: The second conduction path also includes a second internal source resistor formed by a distribution path from the bottom channel region to the second source region. The first internal source resistor and the second internal source resistor are connected in series to form an adaptive negative feedback balance structure of the device unit structure.

16. The JFET device according to any one of claims 1 to 15, characterized in that: The JFET device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the JFET device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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