Normally open transistor and its fabrication method

Abstract

This application relates to a normally-on transistor and its fabrication method. The normally-on transistor includes: a substrate having a first conductivity type; a first drift region, a source region, and a drain region located within the substrate, wherein the portion of the first drift region between the source and drain regions forms a channel; and the first drift region, source region, and drain region each having a second conductivity type different from the first conductivity type; a gate structure located between the source and drain regions for controlling the conduction and cutoff of the channel; and a second drift region located within the first drift region and at a distance from the source region less than the distance from the drain region, having a second conductivity type, and with an ion doping concentration greater than that of the first drift region. Thus, while maintaining a high breakdown voltage, it ensures that in practical applications, when the drain voltage increases, the source voltage change is small, thereby ensuring the normal operation of the circuit.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a normally open transistor and a method for fabricating the same. Background Technology

[0002] Normally-on transistors (NOTs) are semiconductor devices in which a conductive channel exists between the source and drain when the gate-source voltage is zero. Due to their normally-on characteristic, these devices are often integrated into BCD (Bipolar Discrete Transistor) process platforms as core high-voltage components. BCD platforms integrate high-voltage power devices such as bipolar transistors (BMTs), CMOS (Complementary Metal-Oxide-Semiconductor), and DMOS (Diffused Metal-Oxide-Semiconductor) devices, along with various resistors, capacitors, and diodes, onto a single chip. They are currently widely used in mobile devices, home appliances, displays, automobiles, data centers, and other fields.

[0003] In the design of high-voltage normally open transistors, breakdown voltage (BV) is a core performance indicator. To achieve a higher breakdown voltage, it is typically necessary to reduce the doping concentration of the drift region, i.e., using lower ion implantation conditions during drift region formation. However, while a lower doping concentration in the drift region improves the breakdown voltage, it also leads to a larger voltage change at the source terminal when the drain voltage increases. Ultimately, this affects the practical circuit functionality. Summary of the Invention

[0004] In view of this, the present application provides a normally open transistor and a method for fabricating the same to solve at least one problem existing in the prior art.

[0005] In a first aspect, embodiments of this application provide a normally open transistor, including:

[0006] The substrate has a first type of conductivity;

[0007] A first drift region, a source region, and a drain region are located within the substrate. The portion of the first drift region located between the source region and the drain region is used to form a channel. The first drift region, the source region, and the drain region all have a second conductivity type different from the first conductivity type.

[0008] A gate structure, located between the source region and the drain region, is used to control the conduction and turn-off of the channel;

[0009] The second drift region is located within the first drift region and its distance from the source region is less than its distance from the drain region. The second drift region has a second conductivity type, and the ion doping concentration of the second drift region is greater than that of the first drift region.

[0010] In conjunction with a first aspect of this application, in an alternative embodiment, the second drift region is adjacent to the source region below the source region and extends toward the drain region to the bottom of the gate structure.

[0011] In conjunction with a first aspect of this application, in an optional embodiment, the gate structure includes a gate doped region located within the substrate, the gate doped region having a first conductivity type; the second drift region includes a portion located below the gate doped region; and along the thickness direction of the substrate, the area of ​​the portion of the second drift region that projects onto the gate doped region is less than or equal to 2 / 3 of the projected area of ​​the gate doped region.

[0012] In conjunction with a first aspect of this application, in an optional embodiment, the second drift region includes a first sub-region and a second sub-region; the ion doping concentration of the first sub-region is greater than the ion doping concentration of the second sub-region; and the first sub-region is closer to the source region than the second sub-region.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, the second drift region and the first drift region are formed by a second ion implantation process and a first ion implantation process, respectively, wherein the implantation dose of the second ion implantation process is 1.5 to 2.5 times that of the implantation dose of the first ion implantation process.

[0014] Secondly, embodiments of this application provide a method for fabricating a normally-on transistor, comprising:

[0015] Provide a substrate having a first conductivity type;

[0016] A first ion implantation process is performed to form a first drift region having a second conductivity type different from the first conductivity type within the substrate;

[0017] A second ion implantation process is performed to form a second drift region having a second conductivity type within the first drift region, wherein the ion doping concentration of the second drift region is greater than that of the first drift region;

[0018] A gate structure, a source region, and a drain region are formed; wherein the source region and the drain region are spaced apart, the portion of the first drift region located between the source region and the drain region is used as a channel, and both the source region and the drain region have a second conductivity type; the gate structure is located between the source region and the drain region and is used to control the conduction and turn-off of the channel; the distance between the second drift region and the source region is less than the distance between the second drift region and the drain region.

[0019] In conjunction with a second aspect of this application, in an alternative embodiment, the second drift region is adjacent to the source region below the source region and extends toward the drain region to the bottom of the gate structure.

[0020] In conjunction with a second aspect of this application, in an alternative embodiment, forming the gate structure includes performing a third ion implantation process to form a gate doped region having a first conductivity type within the substrate;

[0021] The second drift region includes a portion located below the gate doped region; along the thickness direction of the substrate, the area of ​​the portion of the second drift region that overlaps with the projected area of ​​the gate doped region is less than or equal to 2 / 3 of the projected area of ​​the gate doped region.

[0022] In conjunction with a second aspect of this application, in an optional embodiment, the second drift region includes a first sub-region and a second sub-region; the ion doping concentration of the first sub-region is greater than the ion doping concentration of the second sub-region; and the first sub-region is closer to the source region than the second sub-region.

[0023] In conjunction with a second aspect of this application, in an optional embodiment, the implantation dose of the second ion implantation process is 1.5 to 2.5 times that of the implantation dose of the first ion implantation process.

[0024] Compared with the prior art, this application has the following beneficial effects: In the normally open transistor and its fabrication method provided in the embodiments of this application, by setting a second drift region with a higher ion doping concentration within the first drift region, and the distance between the second drift region and the source region is smaller than its distance from the drain region, the on-resistance of the channel near the source region is reduced, resulting in a smaller voltage change at the source terminal when the drain terminal voltage increases. Since the second drift region is essentially still a drift region, its ion doping concentration is necessarily lower than that of the source region, and its position is closer to the source region, thus reducing the on-resistance at the source terminal while having a smaller impact on the device breakdown voltage. In summary, the embodiments of this application can maintain a high breakdown voltage on the one hand, and ensure that in practical applications, the voltage change at the source terminal is small when the drain terminal voltage increases, thereby ensuring the normal operation of the circuit.

[0025] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This is a schematic cross-sectional view of a normally open transistor in related technologies.

[0028] Figure 2 This is a schematic cross-sectional view of the normally open transistor in the first embodiment of this application;

[0029] Figure 3 A schematic flowchart illustrating the fabrication method of a normally open transistor provided in an embodiment of this application;

[0030] Figures 4 to 13 This is a schematic cross-sectional view of the normally open transistor corresponding to the first embodiment of this application during the fabrication process;

[0031] Figure 14 This is a schematic cross-sectional view of the normally open transistor in the second embodiment of this application;

[0032] Figure 15 In the first embodiment of this application, the normally open transistor and Figure 1 A comparison of the source voltage versus drain voltage curves of normally open transistors in related technologies is shown.

[0033] Figure 16 For the normally open transistor in the first embodiment of this application, Figure 1 The diagram shows a comparison of the breakdown voltage test curves of normally open transistors in the related technologies and normally open transistors in the comparative examples. Detailed Implementation

[0034] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0036] In the accompanying drawings, for clarity, the dimensions of the structures and their relative dimensions may be exaggerated. The same reference numerals denote the same structural features throughout.

[0037] When structures are referred to as being "on," "adjacent to," "connected to," or "coupled to" other structures, they may be directly on, adjacent to, connected to, or coupled to other structures, or there may be intervening structures. Conversely, when a structure is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other structures, there are no intervening structures. Although the terms first, second, third, etc., may be used to describe structures or parts, these terms are only used to distinguish one structure or part from another. Therefore, without departing from the teachings of this application, the first structure or part discussed below may be referred to as the second structure or part. And the discussion of the second structure or part does not imply that the first structure or part necessarily exists in this application.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated feature but do not exclude the presence or addition of one or more other features. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0041] This application provides a normally-on transistor and its fabrication method. Specifically, the normally-on transistor is, for example, a junction field-effect transistor (JFET). JFETs have very high input impedance, allowing for high isolation between the input and output circuits; they lack the inherent noise of vacuum tubes and transistors; and due to their negative temperature coefficient, they avoid the risk of thermal runaway. Furthermore, JFETs have very high power gain, thus eliminating the need for a driver stage. Of course, this application is not limited to this; the normally-on transistor can also be other devices with the same or similar structures, such as a depletion-mode MOSFET.

[0042] The following section, using the JFET structure as an example and in conjunction with the accompanying drawings, introduces the normally open transistor and its fabrication method provided in the embodiments of this application.

[0043] First, please refer to Figure 2 The normally open transistor includes: a substrate 100; a first drift region 120, a source region (see 161 and 181 in the figure) and a drain region (see 162 and 182 in the figure) located within the substrate 100; a gate structure (see 151, 191, 171 and 172 in the figure); and a second drift region 140.

[0044] The substrate 100 has a first conductivity type. A portion of the first drift region 120 located between the source and drain regions is used to form a channel. The first drift region 120, the source region, and the drain region all have a second conductivity type different from the first conductivity type. A gate structure is located between the source and drain regions and is used to control the channel's on / off state. A second drift region 140 is located within the first drift region 120 and its distance from the source region is less than its distance from the drain region. The second drift region has a second conductivity type, and its ion doping concentration is greater than that of the first drift region.

[0045] Figure 1 This is a schematic cross-sectional view of a normally open transistor in related technologies. Please refer to... Figure 1 and Figure 2Compared with related technologies, the normally open transistor provided in this application embodiment has a second drift region 140 with a higher ion doping concentration within the first drift region 120. Furthermore, the distance between the second drift region 140 and the source region is smaller than its distance from the drain region, thereby reducing the on-resistance of the channel near the source region. This results in a smaller voltage change at the source terminal when the drain voltage increases. Since the second drift region 140 is essentially still a drift region, its ion doping concentration is necessarily lower than that of the source region, and its position is closer to the source region. Therefore, while reducing the on-resistance at the source terminal, it has a smaller impact on the device breakdown voltage. In summary, this application embodiment can maintain a high breakdown voltage on the one hand, and ensure that in practical applications, when the drain voltage increases, the voltage change at the source terminal is small, thereby ensuring the normal operation of the circuit.

[0046] In this embodiment, the substrate 100 is a semiconductor substrate, and its material includes at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or the substrate 100 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form the substrate 100 have been described herein, any material that can be used as the substrate 100 falls within the spirit and scope of this application.

[0047] In a specific application, substrate 100 may include a growth substrate and an epitaxial layer formed on the growth substrate. Optionally, the growth substrate and the epitaxial layer have the same conductivity type. For example, substrate 100 has a first conductivity type, which is P-type; providing substrate 100 specifically includes epitaxially growing a P-type epitaxial layer on a P-type growth substrate. Furthermore, the first conductivity type can obviously also be N-type. Accordingly, for the normally open transistor being a JFET, it can be either an NJFET or a PJFET.

[0048] The first drift region 120 is formed using a first ion implantation process. When the first conductivity type is P-type and the second conductivity type is N-type, the first drift region 120 is an N-type drift region. Taking a normally open transistor (NJFET) as an example, the first drift region 120 can specifically be a high-voltage N-type drift region (HV-Ndrift, HNDR). Correspondingly, when the first conductivity type is N-type, the second conductivity type is P-type, which will not be elaborated further.

[0049] The source region may include a source-well region 161 and a source contact region 181. The ion doping concentration of the source contact region 181 is greater than that of the source-well region 161. Taking N-type as an example, the source contact region 181 is an N+ region; the source-well region 161 can also be called an NW (N-Well) region. The source contact region 181 is located within the source-well region 161 and is located on the surface of the substrate 100.

[0050] The drain region may include a drain well region 162 and a drain contact region 182. The ion doping concentration of the drain contact region 182 is greater than that of the drain well region 162. Taking N-type as an example, the drain contact region 182 is an N+ region; the drain well region 162 can also be called an NW (N-Well) region. The drain contact region 182 is located within the drain well region 162 and is located on the surface of the substrate 100.

[0051] The gate structure may include a gate doped region located within the substrate 100. The gate doped region may include a gate well region 151 and a gate contact region 191. The ion doping concentration of the gate contact region 191 is greater than that of the gate well region 151. The gate doped region has a first conductivity type. Taking P-type as an example, the gate contact region 191 is a P+ region; the gate well region 151 can also be referred to as a PW (P-Well) region. The gate contact region 191 is located within the gate well region 151 and is located on the surface of the substrate 100.

[0052] When the gate-source voltage is zero, the channel is in the on state. When a reverse bias voltage is applied to the gate structure and the substrate, a depletion layer is formed below the gate well region 151 and the depletion layer gradually widens until the channel is pinched off, and the device is also in the pinch-off state.

[0053] In a specific example, the device may further include a first field oxide layer 131 and a second field oxide layer 132. The first field oxide layer 131 is located between the gate doped region and the drain region; the second field oxide layer 132 is located between the gate doped region and the source region. The gate structure may further include a first gate field plate 171 and a second gate field plate 172. The second gate field plate 172 is located on the first field oxide layer 131 and partially extends onto the first drift region 120, specifically, for example, extending onto the gate contact region 191; the first gate field plate 171 is located on the first field oxide layer 131 and is located on the side of the second gate field plate 172 closest to the drain region.

[0054] Both the first gate field plate 171 and the second gate field plate 172 may include a gate layer and sidewalls located on both sides of the gate layer. Exemplarily, the gate layer is composed of polysilicon material; alternatively, metals, metal nitrides, metal silicides, or similar compounds may be used as the material for the gate layer. Exemplarily, the sidewalls are made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the sidewalls may be a single-layer or multi-layer structure.

[0055] Optionally, the gate contact region 191 and the second gate field plate 172 are electrically connected to the same wiring layer via conductive plugs to form a gate. That is, the gate contact region 191 and the second gate field plate 172 are electrically connected via conductive plugs, so that when a bias voltage is applied to the gate, the second gate field plate 172 and the first field oxide layer 131 can form a bias field plate structure to increase the average electric field of the first drift region 120 and reduce the electric field peak value, thereby achieving the purpose of suppressing hot carrier effects and improving breakdown voltage. Exemplarily, the first gate field plate 171 is a floating gate structure, meaning that the first gate field plate 171 does not need to be connected to external electrodes. The first gate field plate 171 can form a floating field plate structure with the first field oxide layer 131, making the electric field distribution in the first drift region 120 more uniform and ensuring that the corners where the electric field is concentrated are not easily broken down, thereby further improving the breakdown voltage.

[0056] The second drift region 140 is located within the first drift region 120. The depth of the second drift region 140 is less than the depth of the first drift region 120. The second drift region 140 has a second conductivity type; that is, the conductivity type of the second drift region 140 is the same as that of the first drift region 120, but opposite to that of the substrate 100. When the first conductivity type is N-type, the second drift region 140 is an N-Drift region, also known as an NDRF region. The ion doping concentration of the second drift region 140 is greater than that of the first drift region 120. This increases the on-resistance and reduces the voltage drop change. Understandably, the second drift region 140, as a drift region, has a lower ion doping concentration than the ion doping concentration of the source-well region 161 to be formed.

[0057] As an optional specific implementation, the second drift region 140 is adjacent to the source region below the source region. Further, the second drift region 140 is adjacent to the source-well region 161 below the source-well region 161.

[0058] Furthermore, the second drift region 140 may also include a portion extending downward toward the drain region and below the gate structure. Specifically, in embodiments where the gate structure includes a gate doped region, the second drift region 140 includes a portion located below the gate doped region.

[0059] Furthermore, along the thickness direction of the substrate 100, the area of ​​the portion where the second drift region 140 overlaps with the projected area of ​​the gate doped region is less than or equal to 2 / 3 of the projected area of ​​the gate doped region. Even further, the area of ​​the portion where the second drift region 140 overlaps with the projected area of ​​the gate doped region accounts for 1 / 2 to 2 / 3 of the projected area of ​​the gate doped region.

[0060] Please combine Figure 2 The second drift region 140 is adjacent to the source region, thus minimizing the on-resistance of the channel near the source region and reducing the voltage variation range at the source. The second drift region 140 extends further below the gate doped region, further reducing the on-resistance; the improvement is significant when the area of ​​the overlapping portion of the second drift region 140 and the gate doped region is more than half the projected area of ​​the gate doped region. When the area of ​​the overlapping portion of the second drift region 140 and the gate doped region exceeds two-thirds of the projected area of ​​the gate doped region, especially when extending close to the drain, pull-bias tests reveal a decrease in breakdown voltage, making it difficult to maintain a high breakdown voltage.

[0061] As an optional specific implementation, the second drift region 140 and the first drift region 120 are formed using a second ion implantation process and a first ion implantation process, respectively. The implantation dose of the second ion implantation process is 1.5 to 2.5 times that of the first ion implantation process. Further, the implantation dose of the second ion implantation process is, for example, twice that of the first ion implantation process. Here, implantation dose refers to the total number of ions implanted into the substrate 100 per unit area by the ion beam. The inventors have found that when the implantation dose of the second ion implantation process is within the range of 1.5 to 2.5 times that of the first ion implantation process, the second drift region 140 can improve the problem of large changes in the source voltage with increasing drain voltage, while maintaining a high breakdown voltage.

[0062] Figure 15 In the first embodiment of this application, the normally open transistor and Figure 1The accompanying graph shows a comparison of the source voltage versus drain voltage curves of normally open transistors in related technologies. Specifically, the normally open transistor in the first embodiment of this application is an NJFET. The second drift region 140 is located below the source region, adjacent to it, and extends below the gate well region 151. The area of ​​the overlapping portion of the second drift region 140 and the gate well region 151 is equal to half the projected area of ​​the gate well region 151. The implantation dose of the second ion implantation process is twice that of the first ion implantation process. During the test, a constant current of 0.1 μA is applied to the source terminal, and both the gate voltage VG and the substrate voltage VB are 0V. As shown in the figure, when the drain voltage increases from 0V to 150V, the change in source voltage does not exceed 1V. In contrast, Figure 1 The normally open transistor in the related technology shown has essentially the same fabrication conditions as the normally open transistor in the first embodiment of this application, the only difference being that the second ion implantation process is not performed, resulting in a structure as shown... Figure 1 The diagram does not include the second drift region 140. (By...) Figure 15 It can be seen that during the process of increasing the drain voltage from 0V to 150V, the source voltage changes by approximately 3V in related technologies. Therefore, the improvements in this application ensure that in practical applications, when the drain voltage increases, the source voltage change is relatively small, thus guaranteeing the normal operation of the circuit.

[0063] Figure 16 For the normally open transistor in the first embodiment of this application, Figure 1 The diagram shows a comparison of breakdown voltage test curves for normally open transistors in related technologies and normally open transistors in comparative examples. The normally open transistor in the comparative example is fabricated under essentially the same conditions as the normally open transistor in the first embodiment of this application, the only difference being that the second drift region 140 extends into the drain region. Figure 16 As can be seen, compared to related technologies, the breakdown voltage of the normally open transistor in the first embodiment can still reach 140V, thus maintaining a high breakdown voltage while improving the problem of large voltage changes at the source terminal. In contrast, the breakdown voltage of the comparative embodiment drops significantly and no longer meets the device requirements. Therefore, by adding a second drift region 140 and ensuring that the distance between the second drift region 140 and the source region is less than the distance between the second drift region 140 and the drain region, it is possible to reduce the impact on the device breakdown voltage while lowering the source terminal on-resistance.

[0064] Next, please refer to Figure 14 . Figure 14This is a cross-sectional view of the normally open transistor in the second embodiment of this application. The structure of the normally open transistor in the second embodiment is basically the same as that in the first embodiment. The main difference is that the second drift region 140 includes a first sub-region 141 and a second sub-region 142; the ion doping concentration of the first sub-region 141 is greater than that of the second sub-region 142; and the first sub-region 141 is closer to the source region than the second sub-region 142.

[0065] This application is not limited to this; the second drift region 140 may also include a third sub-region, or even more sub-regions (not shown in the figure), each with a different ion doping concentration. Furthermore, the ion doping concentration of each sub-region decreases in the direction away from the source region. Thus, by forming multiple sub-regions with different ion doping concentrations, greater design flexibility can be achieved between maintaining a higher breakdown voltage and a smaller source voltage variation.

[0066] Next, please refer to Figure 3 The method for fabricating a normally open transistor provided in this application includes:

[0067] Step S01: Provide a substrate having a first conductivity type;

[0068] Step S02: Perform a first ion implantation process to form a first drift region with a second conductivity type in the substrate, the second conductivity type being different from the first conductivity type;

[0069] Step S03: Perform a second ion implantation process to form a second drift region with a second conductivity type within the first drift region. The ion doping concentration of the second drift region is greater than that of the first drift region.

[0070] Step S04: Forming a gate structure, a source region, and a drain region; wherein the source region and the drain region are spaced apart, the portion of the first drift region located between the source region and the drain region is used as a channel, and both the source region and the drain region have a second conductivity type; the gate structure is located between the source region and the drain region and is used to control the conduction and turn-off of the channel; the distance between the second drift region and the source region is less than the distance between the second drift region and the drain region.

[0071] Understandably, the normally open transistor fabrication method provided in this application, by performing a second ion implantation process, forms a second drift region with a higher ion doping concentration within the first drift region. Furthermore, the distance between the second drift region and the source region is smaller than its distance from the drain region, thereby reducing the on-resistance of the channel near the source region. This results in a smaller voltage change at the source terminal when the drain voltage increases. Since the second drift region is essentially still a drift region, its ion doping concentration is necessarily lower than that of the source region, and its location is closer to the source region. Therefore, while reducing the on-resistance at the source terminal, it has a smaller impact on the device breakdown voltage. In summary, this embodiment can maintain a high breakdown voltage on the one hand, and ensure that in practical applications, when the drain voltage increases, the voltage change at the source terminal is small, thus guaranteeing the normal operation of the circuit.

[0072] Below, in conjunction with Figures 4 to 13 The normally open transistor and its fabrication method provided in the embodiments of this application will be further described in detail.

[0073] Please refer to Figure 4 Substrate 100 is provided.

[0074] The substrate 100 is a semiconductor substrate, and its material includes, for example, at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or the substrate 100 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form the substrate 100 have been described herein, any material that can serve as the substrate 100 falls within the spirit and scope of this application.

[0075] In a specific application, substrate 100 may include a growth substrate and an epitaxial layer formed on the growth substrate. Optionally, the growth substrate and the epitaxial layer have the same conductivity type. Exemplarily, substrate 100 has a first conductivity type, which is P-type; providing substrate 100 specifically includes epitaxially growing a P-type epitaxial layer on a P-type growth substrate. Furthermore, the first conductivity type can obviously also be N-type.

[0076] Next, please refer to Figure 5 Prior to performing the first ion implantation process, a step of forming a shallow trench isolation structure 110 (STI) may also be included.

[0077] In the actual fabrication process, an etching process can first be performed on one side of the upper surface of the substrate 100 to form shallow trenches extending into the interior of the substrate 100; then, an insulating layer, specifically a silicon oxide layer, is formed in the shallow trenches, thereby forming a shallow trench isolation structure 110. Exemplarily, the shallow trench isolation structure 110 is located between the active regions of the device.

[0078] Next, please refer to Figure 6 A first ion implantation process is performed to form a first drift region 120 having a second conductivity type within the substrate 100.

[0079] The second conductivity type differs from the first conductivity type. When the first conductivity type is P-type, the second conductivity type is N-type, and the first drift region 120 is an N-type drift region. Correspondingly, when the first conductivity type is N-type, the second conductivity type is P-type, which will not be elaborated further.

[0080] In the actual fabrication process, the first drift region 120 can be formed through the following steps: a patterned first mask layer 210 is formed on the upper surface of the substrate 100; an ion implantation process is performed using the first mask layer 210 as a mask to form the first drift region 120; and finally, the first mask layer 210 is removed. Exemplarily, the first mask layer 210 includes a photoresist (PR) layer. Exemplarily, the first drift region 120 is located within the active region of the device. Taking a conventional high-voltage NJFET as an example, to improve the breakdown voltage, the HNDR region is typically formed using lower dose ion implantation conditions.

[0081] Next, please refer to Figure 7 The method may further include forming a first field oxide layer 131 and a second field oxide layer 132 on the substrate 100 in the region where the first drift region 120 is located.

[0082] The first field oxide layer 131 is located between a predetermined formation site of the gate doped region and a predetermined formation site of the drain region; the second field oxide layer 132 is located between a predetermined formation site of the gate doped region and a predetermined formation site of the source region. Exemplarily, the first field oxide layer 131 and the second field oxide layer 132 can be formed using a LOCOS (Local Oxidation of Silicon) process, i.e., an oxide layer is grown on the surface of the substrate 100 as a field oxide isolation layer through selective thermal oxidation. Of course, any suitable method well known to those skilled in the art can also be used to form the first field oxide layer 131 and the second field oxide layer 132; this application does not specifically limit this method.

[0083] Next, please refer to Figure 8 A second ion implantation process is performed to form a second drift region 140 within the first drift region 120.

[0084] The second drift region 140 has a second conductivity type; that is, the conductivity type of the second drift region 140 is the same as that of the first drift region 120, but opposite to that of the substrate 100. When the first conductivity type is N-type, the second drift region 140 is an N-Drift region, also known as an NDRF region.

[0085] In the actual fabrication process, the second drift region 140 can be formed by the following steps: forming a patterned second mask layer 220 on the upper surface of the substrate 100; performing an ion implantation process using the second mask layer 220 as a mask to form the second drift region 140; and finally removing the second mask layer 220.

[0086] It should be noted that the second drift region 140 is located on the side of the channel near the preset formation position of the source region. Its injection can be selective injection (i.e., slot injection) or a large-area injection of an entire continuous region (i.e., block injection).

[0087] The ion doping concentration of the second drift region 140 is greater than that of the first drift region 120. This increases the concentration, thereby reducing the on-resistance and decreasing the voltage drop. Understandably, the second drift region 140, as a drift region, has a lower ion doping concentration than the source-well region 161 to be formed.

[0088] As an optional specific implementation, the implantation dose of the second ion implantation process is 1.5 to 2.5 times that of the first ion implantation process. Further, the implantation dose of the second ion implantation process is, for example, twice that of the first ion implantation process. Here, implantation dose refers to the total number of ions implanted into the substrate 100 per unit area by the ion beam. The inventors have found that when the implantation dose of the second ion implantation process is within the range of 1.5 to 2.5 times that of the first ion implantation process, the second drift region 140 can improve the problem of large changes in the source terminal voltage with increasing drain terminal voltage, while maintaining a high breakdown voltage.

[0089] The depth of the second drift region 140 is greater than the depth of the source-well region 161 to be formed but less than the depth of the first drift region 120.

[0090] Although the figure only shows the fabrication process of the normally open transistor corresponding to the first embodiment, it should be understood that for the second embodiment of this application, in order to form a second drift region 140 including a first sub-region 141 and a second sub-region 142, two second ion implantation processes can be used to form the first sub-region 141 and the second sub-region 142 respectively. The implantation region and implantation dose of the two second ion implantation processes can be set independently according to actual needs. After performing the two second ion implantation processes, the ion doping concentration of the first sub-region 141 is greater than the ion doping concentration of the second sub-region 142.

[0091] This application is not limited to this; the second drift region 140 may also include a third sub-region, or even more sub-regions (not shown in the figure), each with a different ion doping concentration. Furthermore, the ion doping concentration of each sub-region decreases in the direction away from the source region. By forming multiple sub-regions with different ion doping concentrations, greater design flexibility can be achieved between maintaining a higher breakdown voltage and a smaller source voltage variation.

[0092] Next, the gate structure, source region, and drain region are formed. The following description uses only one exemplary fabrication process, but it should be understood that the formation order of the structures in this application is not limited to this.

[0093] Please refer to Figure 9 An ion implantation process is performed to form the gate well region 151.

[0094] The gate well region 151 has a first conductivity type. In the actual fabrication process, the gate well region 151 can be formed by the following steps: forming a patterned third mask layer 230 on the upper surface of the substrate 100; performing an ion implantation process using the third mask layer 230 as a mask to form the gate well region 151; and finally removing the third mask layer 230.

[0095] The depth of the second drift region 140 is greater than the depth of the gate well region 151 to ensure that a second drift region 140 still exists below the gate well region 151 after its formation. The second drift region 140 is adjacent to the gate well region 151 below it. Along the thickness direction of the substrate 100, the area of ​​the portion of the projection overlap between the second drift region 140 and the gate well region 151 is less than or equal to 2 / 3 of the projected area of ​​the gate well region 151. Further, the area of ​​the portion of the projection overlap between the second drift region 140 and the gate well region 151 accounts for 1 / 2 to 2 / 3 of the projected area of ​​the gate well region 151.

[0096] Furthermore, the implantation region 152 can also be formed simultaneously in this step. Accordingly, the implantation region 152 also has a first conductivity type. The implantation region 152 is located in the region of the substrate 100 where the first drift region 120 has not been formed. In a subsequent process, a substrate contact region will be formed within the implantation region 152.

[0097] Next, please refer to Figure 10 An ion implantation process is performed to form source-well region 161 and drain-well region 162.

[0098] The source-well region 161 and drain-well region 162 have a second conductivity type. In the actual fabrication process, the source-well region 161 and drain-well region 162 can be formed by the following steps: forming a patterned fourth mask layer 240 on the upper surface of the substrate 100; performing an ion implantation process using the fourth mask layer 240 as a mask to form the source-well region 161 and drain-well region 162; and finally removing the fourth mask layer 240.

[0099] The depth of the second drift region 140 is greater than the depth of the source-well region 161, so as to ensure that after the source-well region 161 is formed, the second drift region 140 still exists below the source-well region 161. The second drift region 140 is adjacent to the source-well region 161 below the source-well region 161.

[0100] Please combine Figure 2 As an optional specific implementation, gate structures and drain regions can be respectively provided on both sides of the source region. The second drift region 140 extends from below the gate structure on one side (specifically below the gate well region 151), covers the bottom of the source region (specifically the bottom of the source well region 161), and extends to below the gate structure on the other side (specifically below the gate well region 151).

[0101] Next, please refer to Figure 11 A first gate field plate 171 and a second gate field plate 172 are formed.

[0102] The second gate field plate 172 is located on the first field oxide layer 131 and extends partially to the first drift region 120, specifically extending to the gate contact region 191; the first gate field plate 171 is located on the first field oxide layer 131 and is located on the side of the second gate field plate 172 near the drain region.

[0103] Both the first gate field plate 171 and the second gate field plate 172 may include a gate layer and sidewalls located on both sides of the gate layer. Exemplarily, the gate layer is composed of polysilicon material; alternatively, metals, metal nitrides, metal silicides, or similar compounds may be used as the material for the gate layer. Exemplarily, the sidewalls are made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the sidewalls may be a single-layer or multi-layer structure.

[0104] Next, please refer to Figure 12 An ion implantation process is performed to form source contact region 181 and drain contact region 182.

[0105] Source contact region 181 and drain contact region 182 have a second conductivity type, and their ion doping concentrations are both higher than those of source-well region 161 and drain-well region 162. In actual fabrication, source contact region 181 and drain contact region 182 can be formed through the following steps: a patterned fifth mask layer 250 is formed on the upper surface of substrate 100; ion implantation is performed using the fifth mask layer 250 as a mask to form source contact region 181 and drain contact region 182; finally, the fifth mask layer 250 is removed. Source contact region 181 and drain contact region 182 are located within source-well region 161 and drain-well region 162, respectively, and are both located on the surface of substrate 100 to achieve ohmic contact with conductive plugs in subsequent processes, thereby forming conductive leads in the source and drain regions.

[0106] Next, please refer to Figure 13 An ion implantation process is performed to form the gate contact region 191 and the substrate contact region 192.

[0107] Gate contact region 191 and substrate contact region 192 have a first conductivity type, and their ion doping concentrations are both higher than those of gate well region 151 and implantation region 152. In actual fabrication, gate contact region 191 and substrate contact region 192 can be formed through the following steps: a patterned sixth mask layer 260 is formed on the upper surface of substrate 100; an ion implantation process is performed using the sixth mask layer 260 as a mask to form gate contact region 191 and substrate contact region 192; and finally, the sixth mask layer 260 is removed. Gate contact region 191 and substrate contact region 192 are located within gate well region 151 and implantation region 152, respectively, and are both located on the surface of substrate 100 to achieve ohmic contact with conductive plugs in subsequent processes, thereby forming conductive leads for the gate and substrate.

[0108] The gate contact region 191 and the gate well region 151 can be collectively referred to as the gate doped region. Although in actual processes, the gate contact region 191 and the gate well region 151 are formed in different ion implantation processes, for ease of description, the process of forming the gate doped region within the substrate 100 will be collectively referred to as the third ion implantation process. Since the gate contact region 191 is located within the gate well region 151, the area of ​​the portion of the projection of the second drift region 140 overlapping with the gate doped region along the thickness direction of the substrate 100 is less than or equal to 2 / 3 of the projected area of ​​the gate doped region. Specifically, the area of ​​the portion of the projection of the second drift region 140 overlapping with the gate well region 151 is less than or equal to 2 / 3 of the projected area of ​​the gate well region 151.

[0109] Finally, please refer to Figure 2 A conductive interconnect structure 310 is formed. The conductive interconnect structure 310 specifically includes conductive plugs and wiring layers.

[0110] Gate contact region 191 and second gate field plate 172 are electrically connected to the same wiring layer via conductive plugs to form a gate. Exemplarily, the first gate field plate 171 is a floating gate structure, meaning it does not need to be connected to an external electrode. Source contact region 181 is electrically connected to another wiring layer via another conductive plug to form a source. Drain contact region 182 is electrically connected to yet another wiring layer via yet another conductive plug to form a source. Furthermore, substrate contact region 192 is also electrically connected to a separate wiring layer via a separate conductive plug to form a substrate end.

[0111] It should be noted that the normally open transistor embodiments and the normally open transistor fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the normally open transistor provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the normally open transistor provided in the embodiments of this application is not limited to the fabrication method of the normally open transistor provided in the embodiments of this application, and any normally open transistor prepared by a fabrication method that can form the normally open transistor structure provided in the embodiments of this application is within the scope of protection of this application.

[0112] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A normally open transistor, characterized in that, include: The substrate has a first type of conductivity; A first drift region, a source region, and a drain region are located within the substrate. The portion of the first drift region located between the source region and the drain region is used to form a channel. The first drift region, the source region, and the drain region all have a second conductivity type different from the first conductivity type. A gate structure, located between the source region and the drain region, is used to control the conduction and turn-off of the channel; The second drift region is located within the first drift region and its distance from the source region is less than its distance from the drain region. The second drift region has a second conductivity type, and the ion doping concentration of the second drift region is greater than that of the first drift region.

2. The normally open transistor according to claim 1, characterized in that, The second drift region is adjacent to the source region below the source region and extends toward the drain region to the bottom of the gate structure.

3. The normally open transistor according to claim 1 or 2, characterized in that, The gate structure includes a gate doped region located within the substrate, the gate doped region having a first conductivity type; the second drift region includes a portion located below the gate doped region; along the thickness direction of the substrate, the area of ​​the portion of the second drift region that overlaps with the projection of the gate doped region is less than or equal to 2 / 3 of the projected area of ​​the gate doped region.

4. The normally open transistor according to claim 1, characterized in that, The second drift region includes a first sub-region and a second sub-region; the ion doping concentration of the first sub-region is greater than that of the second sub-region; the first sub-region is closer to the source region than the second sub-region.

5. The normally open transistor according to claim 1, characterized in that, The second drift region and the first drift region are formed by a second ion implantation process and a first ion implantation process, respectively. The implantation dose of the second ion implantation process is 1.5 to 2.5 times that of the first ion implantation process.

6. A method for fabricating a normally open transistor, characterized in that, include: Provide a substrate having a first conductivity type; A first ion implantation process is performed to form a first drift region having a second conductivity type different from the first conductivity type within the substrate; A second ion implantation process is performed to form a second drift region having a second conductivity type within the first drift region, wherein the ion doping concentration of the second drift region is greater than that of the first drift region; A gate structure, a source region, and a drain region are formed; wherein the source region and the drain region are spaced apart, the portion of the first drift region located between the source region and the drain region is used as a channel, and both the source region and the drain region have a second conductivity type; the gate structure is located between the source region and the drain region and is used to control the conduction and turn-off of the channel; the distance between the second drift region and the source region is less than the distance between the second drift region and the drain region.

7. The method for fabricating a normally open transistor according to claim 6, characterized in that, The second drift region is adjacent to the source region below the source region and extends toward the drain region to the bottom of the gate structure.

8. The method for fabricating a normally open transistor according to claim 6 or 7, characterized in that, The formation of the gate structure includes performing a third ion implantation process to form a gate doped region having a first conductivity type within the substrate; The second drift region includes a portion located below the gate doped region; along the thickness direction of the substrate, the area of ​​the portion of the second drift region that overlaps with the projected area of ​​the gate doped region is less than or equal to 2 / 3 of the projected area of ​​the gate doped region.

9. The method for fabricating a normally open transistor according to claim 6, characterized in that, The second drift region includes a first sub-region and a second sub-region; the ion doping concentration of the first sub-region is greater than that of the second sub-region; the first sub-region is closer to the source region than the second sub-region.

10. The method for fabricating a normally open transistor according to claim 6, characterized in that, The implantation dose of the second ion implantation process is 1.5 to 2.5 times that of the first ion implantation process.

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