Wafer extension Pt process method
Patent Information
- Application Number
- CN202610780962.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-01
- Publication Date
- 2026-10-20
AI Technical Summary
[0002]目前超结（SJ）扩Pt工艺，因wafer边缘位置的硅（silicon）裸露浅表层存在Pt元素富集，在后续的W刻蚀（etch）和AL etch过程中，Pt因物理轰击不断累积使刻蚀腔体氛围改变，腔体表面覆盖（coating）Pt元素导致刻蚀速率降低，终点（end point）时间持续趋势上升（trend up）并最终导致超标（OOS）并致使设备宕机，无法继续作业
[0025]本发明在沉积Pt层之前，在晶圆的周边边缘处裸露的半导体衬底表面形成保护层，且保护层沿半导体衬底的倾斜表面向下延伸后底部位置低于后续Pt扩散深度，也即位于后续的Pt扩散区的底部表面之下；这样就能防止在晶圆的周边边缘处Pt和半导体衬底直接接触并进而防止在扩Pt工艺完成后Pt扩散并残留在晶圆的周边边缘处的半导体衬底材料中；而晶圆的周边边缘处的半导体衬底的表面会在后续工艺中暴露，当进行金属刻蚀时，金属刻蚀时会轰击到晶圆的周边边缘处的半导体衬底的表面，由于晶圆的周边边缘处的半导体衬底的表面没有Pt，故本发明能防止在后续的金属刻蚀中将Pt轰击出来，从而能防止轰击出来的Pt沉积并不断累积在金属刻蚀腔的内壁表面，从而能防止金属刻蚀腔的刻蚀速率降低以及由此产生的刻蚀终点时间的不断增加，所以，本发明能防止在晶圆的周边边缘处的半导体衬底表面产生Pt残留，从而能防止Pt残留对后续工艺中的金属刻蚀工艺的不利影响。
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Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a wafer platinum dilution (Pt) process. Background Technology
[0002] Currently, in the superjunction (SJ) Pt expansion process, Pt enrichment exists in the shallow surface layer of exposed silicon at the edge of the wafer. During subsequent W etching and AL etching processes, the Pt continuously accumulates due to physical bombardment, altering the etching chamber atmosphere. The coating of Pt on the chamber surface leads to a decrease in etching rate, a continuously increasing end-point time trend, and ultimately results in exceeding the time limit (OOS), causing equipment shutdown and preventing further operation. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a wafer Pt expansion process method that can prevent Pt residue from being generated on the surface of the semiconductor substrate at the peripheral edge of the wafer, thereby preventing the adverse effects of Pt residue on the metal etching process in subsequent processes.
[0004] To solve the above-mentioned technical problems, the wafer Pt expansion process method provided by the present invention includes the following steps: Step 1: Provide a wafer for which Pt expansion process is required. The wafer includes a semiconductor substrate, and the surface of the semiconductor substrate is exposed and has a tilted morphology at the peripheral edge of the wafer.
[0005] Step 2: Form a protective layer that covers the exposed surface of the semiconductor substrate around the wafer, and the lowest point of the protective layer extending downward along the surface of the semiconductor substrate with an inclined morphology is lower than the Pt diffusion depth of the subsequent Pt diffusion process.
[0006] Step 3: Deposit a Pt layer on the surface of the wafer. At the peripheral edge of the wafer, the protective layer prevents the Pt layer from contacting the surface of the semiconductor substrate.
[0007] Step 4: Annealing is performed to diffuse Pt from the Pt layer into the semiconductor substrate and form a Pt diffusion region. At the peripheral edge of the wafer, the protective layer prevents Pt from diffusing into the semiconductor substrate.
[0008] Step 5: Remove the Pt layer and form a Pt-free semiconductor substrate surface at the peripheral edge of the wafer.
[0009] A further improvement is that the material of the protective layer includes an oxide layer.
[0010] A further improvement is that, in step one, the wafer further includes an interlayer film formed on the surface of the semiconductor substrate, and a contact hole opening is formed in the interlayer film that passes through the interlayer film.
[0011] A further improvement is that the contact hole opening is formed by a patterned etching process, which also removes the interlayer film on the surface of the semiconductor substrate at the peripheral edge of the wafer.
[0012] A further improvement is that, in step three, the Pt layer fills the contact hole opening and extends to the surface of the interlayer film outside the contact hole opening.
[0013] A further improvement is that, after step five, it also includes: A first layer of metallic material is filled into the contact hole opening to form a contact hole.
[0014] A further improvement is that the steps for forming the contact hole include: The first metal material layer is deposited, which fills the contact hole opening and extends beyond the contact hole opening.
[0015] A first metal etching is performed to remove the first metal material layer outside the contact hole opening. Taking advantage of the fact that there is no Pt residue on the surface of the semiconductor substrate at the peripheral edge of the wafer, Pt is prevented from being ejected during the first metal etching and thus Pt contamination of the metal etching cavity is prevented.
[0016] A further improvement is that the material of the first metal material layer includes tungsten.
[0017] Further improvements include: A front-side metal layer is formed.
[0018] Photolithography is used to define the patterning area of the front metal layer.
[0019] A second metal etching is performed to form the pattern of the front metal layer. Taking advantage of the fact that there is no Pt residue on the surface of the semiconductor substrate at the peripheral edge of the wafer, Pt is prevented from being ejected during the second metal etching, thereby preventing Pt from contaminating the metal etching cavity.
[0020] A further improvement is that the material of the front metal layer includes Al.
[0021] A further improvement is that a semiconductor epitaxial layer is formed on the top surface of the semiconductor substrate, and in step one, the exposed surface of the semiconductor substrate is the surface of the semiconductor epitaxial layer.
[0022] A further improvement is to form a superjunction device in the semiconductor epitaxial layer.
[0023] A further improvement is that the semiconductor substrate is made of silicon.
[0024] The material of the semiconductor epitaxial layer includes silicon.
[0025] This invention forms a protective layer on the exposed semiconductor substrate surface at the periphery of the wafer before depositing the Pt layer. This protective layer extends downwards along the inclined surface of the semiconductor substrate, with its bottom position below the subsequent Pt diffusion depth, i.e., below the bottom surface of the subsequent Pt diffusion region. This prevents direct contact between Pt and the semiconductor substrate at the wafer periphery, and consequently prevents Pt from diffusing and remaining in the semiconductor substrate material at the wafer periphery after the Pt diffusion process. The surface of the semiconductor substrate at the wafer periphery is exposed in subsequent processes, and during metal etching, the metal... During etching, the metal substrate at the periphery of the wafer is bombarded. Since there is no Pt on the surface of the semiconductor substrate at the periphery of the wafer, this invention can prevent Pt from being ejected during subsequent metal etching. This prevents the ejected Pt from depositing and accumulating on the inner wall surface of the metal etching cavity, thereby preventing a decrease in the etching rate of the metal etching cavity and a continuous increase in the etching endpoint time. Therefore, this invention can prevent Pt residue from forming on the surface of the semiconductor substrate at the periphery of the wafer, thereby preventing the adverse effects of Pt residue on the subsequent metal etching process. Attached Figure Description
[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of the wafer Pt expansion process method according to an embodiment of the present invention; Figures 2-6 This is a schematic diagram of the device structure in each step of the wafer Pt expansion process method according to an embodiment of the present invention. Detailed Implementation
[0027] like Figure 1 The diagram shown is a flowchart of the wafer Pt expansion process according to an embodiment of the present invention; as shown... Figures 2 to 6 The diagram shown is a schematic representation of the device structure in each step of the wafer Pt expansion process according to an embodiment of the present invention. The wafer Pt expansion process according to an embodiment of the present invention includes the following steps: Step 1, such as Figure 2 As shown, a wafer for Pt expansion process is provided, the wafer including a semiconductor substrate 101, the surface of the semiconductor substrate 101 being exposed and having a tilted morphology at the peripheral edge of the wafer. Figure 2 The peripheral edge of the wafer described herein is shown in dashed box 104.
[0028] In this embodiment of the invention, the wafer further includes an interlayer film 102 formed on the surface of the semiconductor substrate 101, and a contact hole opening 103 is formed in the interlayer film 102, penetrating the interlayer film 102. That is, in this embodiment of the invention, the Pt expansion process is performed after the contact hole opening 103 is formed. In other embodiments, the Pt expansion process can also be set at other suitable times as needed; that is, this embodiment of the invention does not limit the pre-layer conditions of the wafer.
[0029] The contact hole opening 103 is formed by a patterned etching process, which also removes the interlayer film 102 on the surface of the semiconductor substrate 101 at the peripheral edge of the wafer. This exposes the surface of the semiconductor substrate 101 at the peripheral edge of the wafer.
[0030] Preferably, a semiconductor epitaxial layer is also formed on the top surface of the semiconductor substrate 101, and the exposed surface of the semiconductor substrate 101 is the surface of the semiconductor epitaxial layer.
[0031] In some embodiments, a superjunction device is formed in the semiconductor epitaxial layer.
[0032] The semiconductor substrate 101 is made of silicon.
[0033] The material of the semiconductor epitaxial layer includes silicon.
[0034] Step 2, as follows Figure 3 As shown, a protective layer 105 is formed, which covers the surface of the semiconductor substrate 101 exposed around the wafer periphery, and the lowest position of the protective layer 105 extending downward along the surface of the semiconductor substrate 101 with an inclined morphology is lower than the Pt diffusion depth of the subsequent Pt diffusion process. Figure 3 In the diagram, the lowest position of the protective layer 105 is shown as dashed line AA. The Pt diffusion depth of the subsequent Pt diffusion process corresponds to the depth of the bottom surface of the subsequently formed Pt diffusion region 107, and the corresponding position of the bottom surface of the Pt diffusion region 107 is shown as dashed line BB. Therefore, in this embodiment of the invention, the structure of the protective layer 105 can be adjusted according to the subsequent formation process of the Pt diffusion region 107, which can completely avoid subsequent contamination and related side effects caused by Pt element enrichment at the wafer edge.
[0035] In this embodiment of the invention, the protective layer 105 is made of an oxide layer. In other embodiments, the material of the protective layer 105 can also be set according to actual needs.
[0036] Step 3, as follows Figure 4 As shown, a Pt layer 106 is deposited on the surface of the wafer, and at the peripheral edge of the wafer, the protective layer 105 prevents the Pt layer 106 from contacting the surface of the semiconductor substrate 101.
[0037] In this embodiment of the invention, the Pt layer 106 fills the contact hole opening 103 and extends to the surface of the interlayer film 102 outside the contact hole opening 103.
[0038] In some embodiments, the deposition process of the Pt layer 106 includes sputtering and evaporation.
[0039] Step 4, as follows Figure 5 As shown, annealing diffuses Pt from the Pt layer 106 into the semiconductor substrate 101 and forms a Pt diffusion region 107. At the peripheral edge of the wafer, the protective layer 105 prevents Pt from diffusing into the semiconductor substrate 101.
[0040] Step 5, as follows Figure 6 As shown, the Pt layer 106 is removed and a Pt-free surface of the semiconductor substrate 101 is formed at the peripheral edge of the wafer.
[0041] In this embodiment of the invention, after step five, the method further includes: A first metal material layer is filled into the contact hole opening 103 to form a contact hole. The steps for forming the contact hole include: A first metal material layer is deposited, which fills the contact hole opening 103 and extends beyond it. The material of the first metal material layer includes tungsten.
[0042] A first metal etching is performed to remove the first metal material layer outside the contact hole opening 103. Taking advantage of the fact that there is no Pt residue on the surface of the semiconductor substrate 101 at the peripheral edge of the wafer, Pt is prevented from being ejected during the first metal etching and thus Pt contamination of the metal etching cavity is prevented.
[0043] Also includes: A front-side metal layer is formed. The material of the front-side metal layer includes Al.
[0044] Photolithography is used to define the patterning area of the front metal layer.
[0045] A second metal etching is performed to form the pattern of the front metal layer. Taking advantage of the fact that there is no Pt residue on the surface of the semiconductor substrate 101 at the peripheral edge of the wafer, Pt is prevented from being ejected during the second metal etching and thus Pt contamination of the metal etching cavity is prevented.
[0046] In this embodiment of the invention, before depositing the Pt layer 106, a protective layer 105 is formed on the surface of the exposed semiconductor substrate 101 at the peripheral edge of the wafer. The protective layer 105 extends downwards along the inclined surface of the semiconductor substrate 101, and its bottom position is lower than the subsequent Pt diffusion depth, i.e., below the bottom surface of the subsequent Pt diffusion region 107. This prevents direct contact between Pt and the semiconductor substrate 101 at the peripheral edge of the wafer, and thus prevents Pt from diffusing and remaining in the semiconductor substrate 101 material at the peripheral edge of the wafer after the Pt diffusion process. The surface of the semiconductor substrate 101 at the peripheral edge of the wafer will be exposed in subsequent processes, such as when metallization is performed. During etching, the metal etching process bombards the surface of the semiconductor substrate 101 at the peripheral edge of the wafer. Since there is no Pt on the surface of the semiconductor substrate 101 at the peripheral edge of the wafer, this embodiment of the invention can prevent Pt from being bombarded out in subsequent metal etching, thereby preventing the bombarded Pt from depositing and accumulating on the inner wall surface of the metal etching cavity. This prevents the etching rate of the metal etching cavity from decreasing and the resulting increase in the etching endpoint time. Therefore, this embodiment of the invention can prevent Pt residue from being generated on the surface of the semiconductor substrate 101 at the peripheral edge of the wafer, thereby preventing the adverse effects of Pt residue on the subsequent metal etching process.
[0047] This invention embodiment deposits an oxide film at the edge to isolate the subsequent Pt from the bare silicon, i.e., the semiconductor substrate 101, thereby avoiding the adverse effects of Pt accumulation during subsequent metal etching (tungsten, aluminum, etc.) and has the advantages of strong operability and good effect.
[0048] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A wafer Pt expansion process method, characterized in that, Including the following steps: Step 1: Provide a wafer for Pt expansion process, the wafer including a semiconductor substrate, the surface of the semiconductor substrate being exposed and having a tilted morphology at the peripheral edge of the wafer; Step 2: Form a protective layer that covers the exposed surface of the semiconductor substrate around the wafer, and the lowest point of the protective layer extending downward along the surface of the semiconductor substrate with an inclined morphology is lower than the Pt diffusion depth of the subsequent Pt diffusion process. Step 3: Deposit a Pt layer on the surface of the wafer. At the peripheral edge of the wafer, the protective layer prevents the Pt layer from contacting the surface of the semiconductor substrate. Step 4: Annealing is performed to diffuse Pt from the Pt layer into the semiconductor substrate and form a Pt diffusion region. At the peripheral edge of the wafer, the protective layer prevents Pt from diffusing into the semiconductor substrate. Step 5: Remove the Pt layer and form a Pt-free semiconductor substrate surface at the peripheral edge of the wafer.
2. The wafer Pt expansion process method as described in claim 1, characterized in that: The material of the protective layer includes an oxide layer.
3. The wafer Pt expansion process method as described in claim 2, characterized in that: In step one, the wafer also includes an interlayer film formed on the surface of the semiconductor substrate, and a contact hole opening is formed in the interlayer film that passes through the interlayer film.
4. The wafer Pt expansion process method as described in claim 3, characterized in that: The contact hole opening is formed by a patterned etching process, which also removes the interlayer film on the surface of the semiconductor substrate at the peripheral edge of the wafer.
5. The wafer Pt expansion process method as described in claim 3, characterized in that: In step three, the Pt layer fills the contact hole opening and extends to the surface of the interlayer film outside the contact hole opening.
6. The wafer Pt expansion process method as described in claim 3, characterized in that: After step five, the following also includes: A first layer of metal material is filled into the contact hole opening to form a contact hole.
7. The wafer Pt expansion process method as described in claim 6, characterized in that: The steps for forming the contact hole include: A first metal material layer is deposited, which fills the contact hole opening and extends beyond the contact hole opening; A first metal etching is performed to remove the first metal material layer outside the contact hole opening. Taking advantage of the fact that there is no Pt residue on the surface of the semiconductor substrate at the peripheral edge of the wafer, Pt is prevented from being ejected during the first metal etching and thus Pt contamination of the metal etching cavity is prevented.
8. The wafer Pt expansion process method as described in claim 7, characterized in that: The material of the first metallic layer includes tungsten.
9. The wafer Pt expansion process method as described in claim 6, characterized in that, Also includes: Form a front metal layer; Photolithography is performed to define the patterning area of the front metal layer; A second metal etching is performed to form the pattern of the front metal layer. Taking advantage of the fact that there is no Pt residue on the surface of the semiconductor substrate at the peripheral edge of the wafer, Pt is prevented from being ejected during the second metal etching, thereby preventing Pt from contaminating the metal etching cavity.
10. The wafer Pt expansion process method as described in claim 9, characterized in that, The material of the front metal layer includes Al.
11. The wafer Pt expansion process method as described in claim 1, characterized in that: A semiconductor epitaxial layer is also formed on the top surface of the semiconductor substrate. In step one, the exposed surface of the semiconductor substrate is the surface of the semiconductor epitaxial layer.
12. The wafer Pt expansion process method as described in claim 11, characterized in that: A superjunction device is formed in the semiconductor epitaxial layer.
13. The wafer Pt expansion process method as described in claim 11, characterized in that: The semiconductor substrate is made of silicon; The material of the semiconductor epitaxial layer includes silicon.