Super junction transistor with orthogonal shield layer

Abstract

A superjunction transistor with an orthogonal shielding layer is disclosed. The transistor includes a source region having a first conductivity type, a well region below the source region having a second conductivity type, and a current spreading layer below the well region having a first conductivity type. The transistor includes a gate formed in a trench and arranged in a striped gate pattern. The transistor also includes a transition region having a first conductivity type and a shielding region having a second conductivity type located below the current spreading layer. The transition region and the shielding region are alternately arranged in a striped transition region pattern that is angularly offset from the striped gate pattern. The transistor also includes a superjunction region below the shielding region and the transition region. The superjunction region includes n-type pillars and p-type pillars arranged in an alternating striped superjunction pattern that is angularly offset from the striped transition region pattern.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more particularly to techniques for improving the area utilization of power transistors. Background Technology

[0002] Power electronics can be used to control the conversion and distribution of electricity. For example, a switching power converter can be used to form a direct current (DC) voltage from an alternating current (AC) voltage by switching the current flowing through a magnetic element, such as an inductor. Conversely, an inverter can be used to convert a DC voltage to an AC voltage. In these and other forms of power electronics, power switches can be used to control the conversion and flow of power through the power conversion system and to the electronic circuitry powered by the device.

[0003] Power switches used in such power conversion systems may need to handle high currents and withstand large voltages. The inventors of the embodiments of this disclosure have recognized that optimizing certain performance parameters of the power switch may come at the expense of degrading other performance parameters of the power switch. For example, the inventors of the embodiments of this disclosure have recognized that reducing the on-state resistance (RON) of a power transistor to reduce conduction losses may come at the expense of reducing the short-circuit withstand time (SCWT). As another example, the inventors of the embodiments of this disclosure have also recognized that certain techniques for reducing the on-state resistance (RON) of a power transistor may come at the further expense of reducing the breakdown voltage (BV) of the power transistor. The embodiments of this disclosure can address one or more of these challenges. Attached Figure Description

[0004] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0005] Figure 1 A perspective view of a transistor according to an embodiment of the present disclosure is illustrated.

[0006] Figure 2A A cross-sectional view of a transistor according to an embodiment of the present disclosure is illustrated.

[0007] Figure 2B A cross-sectional view of a transistor according to an embodiment of the present disclosure is illustrated.

[0008] Figure 2C A top cross-sectional view of a transistor according to an embodiment of the present disclosure is illustrated.

[0009] Figure 2D A top cross-sectional view of a transistor according to an embodiment of the present disclosure is illustrated.

[0010] Figure 3AA perspective view of a transistor according to an embodiment of the present disclosure is illustrated.

[0011] Figure 3B A perspective view of a transistor according to an embodiment of the present disclosure is illustrated.

[0012] Figure 3C A perspective view of a transistor according to an embodiment of the present disclosure is illustrated.

[0013] Figure 3D and Figure 3E A top view of a link area injection pattern according to an embodiment of the present invention is shown.

[0014] Figure 4 A top layout diagram of a transistor according to an embodiment of the present disclosure is illustrated.

[0015] Figure 5 A method for manufacturing a superjunction transistor according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0016] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0017] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component, and this disclosure is not intended to distinguish between components with different names but the same form and function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including but not limited to". Additionally, the term "coupled" is intended to indicate an indirect or direct connection. Thus, if a first device is coupled to or is coupled to a second device, the connection between the first and second devices can be achieved through a direct connection or through an indirect connection via other elements and connectors.

[0018] The embodiments disclosed herein may include a transistor. The transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the transistor may be a silicon carbide transistor formed on a silicon carbide substrate. In other embodiments, the transistor may be implemented in silicon, gallium nitride, or any other suitable semiconductor material. As described in further detail below, the transistor may include a superjunction region and may therefore also be referred to as a superjunction transistor.

[0019] The transistor may include a source region having a first conductivity type, a well region below the source region having a second conductivity type, and a current spreading layer below the well region having a first conductivity type. The transistor may also include a vertical gate formed in a trench extending through the source region, well region, and current spreading layer. The vertical gate may be arranged in a striped pattern in a first direction along a first axis. The transistor may include a transition region below the current spreading layer having a first conductivity type, and a shielding region below the current spreading layer having a second conductivity type. The transition region and shielding region may be arranged in an alternating striped transition region pattern that is angularly offset from the striped gate pattern. For example, the transition region and shielding region may be arranged in an alternating striped transition region pattern in a second direction along a second axis orthogonal to the first axis. The transistor may also include a superjunction region below the shielding region and transition region. The superjunction region may include n-type pillars and p-type pillars. The n-type pillars and p-type pillars may be arranged in an alternating striped superjunction pattern that is angularly offset from the striped transition region pattern. For example, the n-type pillars and p-type pillars may be arranged in an alternating striped superjunction pattern in a direction along a first axis orthogonal to the second axis. The transistor may also include an epitaxial region of a first conductivity type located below the superjunction region and above the drain contact layer.

[0020] In some implementations, the transistor may be an n-channel MOSFET (“NMOS” or “NMOS transistor”). For example, the first conductivity type may be n-type, and each of the source region, current spreading layer, transition region, and epitaxial region may be an n-type doped region. In such implementations, the second conductivity type may be p-type, and both the well region and the shielding region may be p-type doped regions.

[0021] Certain parameters of a transistor can depend on the size and doping of individual regions, including the source region, well region, current spreading layer, transition region, shielding region, and superjunction region. For example, the gate pitch may affect how many fingers of the transistor can be implemented in parallel in a given region of the semiconductor substrate, thus potentially affecting the transistor's on-resistance (RON). Furthermore, the width of the transition region within the striped transition region pattern and the transition region spacing of the striped transition region pattern may affect the transistor's saturation current, thereby affecting the transistor's short-circuit withstand time. Additionally, the doping of the n-type pillars in the superjunction region and the superjunction spacing may affect the transistor's on-resistance (RON) and breakdown voltage (BV). As described in further detail below, arranging the individual regions with striped patterns that are angularly offset (e.g., orthogonal) to the patterns of the adjacent regions above and / or below allows the size and doping of each region to be determined independently of each other. For example, by patterning the transition and shielding regions with striped transition region patterns orthogonal to (or otherwise angularly offset from) the striped gate pattern, the corresponding widths and spacings of the shielding and transition regions can be determined separately from the gate spacing of the striped gate pattern. Therefore, the width and spacing of the shielding region and the transition region can be selected based on the target saturation current value, and are not limited to the same spacing of the striped gate pattern. Furthermore, by patterning the first and second pillars of the superjunction region with a stripe pattern orthogonal to (or otherwise angularly offset from) the striped transition region pattern, the spacing and doping of the superjunction region can be determined separately from the striped transition region pattern and separately from the striped gate pattern. Therefore, the spacing of the superjunction region and the doping of the n-type and p-type pillars therein can be selected based on the target on-resistance (RON) and breakdown voltage (BV) values, and are not limited to the same spacing of the striped gate pattern or the striped transition region pattern.

[0022] Figure 1 A perspective view of a transistor 100 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 1 A perspective view of a portion of transistor 100 cut out from a semiconductor substrate is shown. Although Figure 1 The transistor 100 is illustrated with three finger-like portions, but the transistor 100 may include portions of the semiconductor substrate not present in the image. Figure 1 The other portions shown in the diagram repeat with additional fingers (e.g., 10, 100, 1000, or more) in a similar pattern. In some embodiments, transistor 100 may be a silicon carbide transistor formed on a silicon carbide substrate. In other embodiments, transistor 100 may be implemented in silicon, gallium nitride, or any other suitable semiconductor material. As described in further detail below, transistor 100 may include a superjunction region and may therefore also be referred to as a superjunction transistor.

[0023] like Figure 1As shown, transistor 100 may include a source contact layer 120 located above source region 124. Source contact layer 120 may include, for example, a silicide that can improve the connection between source region 124 and the metal layer above the source terminals coupled to transistor 100. Figure 1 The conductivity of the contacts between (not shown in the diagram). The source region 124 may have a first conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, the source region 124 may be a heavily doped n-type region. Transistor 100 may also include a well region 128 located below the source region 124. The well region 128 may have a second conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, the well region 128 may be a doped p-type region. Transistor 100 may also include a current spreading layer 130 located below the well region 128. The current spreading layer 130 may have a first conductivity type, similar to that of the source region 124. For example, in an embodiment where transistor 100 is an NMOS transistor, the current spreading layer 130 may be a doped n-type region.

[0024] Transistor 100 may further include a gate 116 formed in a trench. Gate 116 may be a vertical gate, whereby the trench extends from the upper surface of the semiconductor substrate (on...). Figure 1 (As shown in the x-axis direction) it extends downwards. In some embodiments, the trench may extend through the source region 124 and the well region 128. For example, as Figure 1 As shown, the trench can extend through the source region 124 and the well region 128, further through the current spreading layer 130, and into the shielding region 138. During fabrication, the trench can be formed by etching a pattern on the upper surface of the semiconductor substrate. After etching, a gate oxide 114 can be grown or deposited along the sidewalls and bottom of the trench. The gate oxide 114 can include, for example, silicon dioxide or any other oxide suitable for forming a gate dielectric. A gate 116 can then be deposited to fill the remaining area of ​​the trench. In some embodiments, the gate 116 can be formed of, for example, heavily doped polysilicon. The gate 116 can also be formed of any other conductive material (such as a metal or metal alloy) suitable for forming the physical gate of the transistor 100. An interlayer dielectric 110 can be formed over the gate 116. The interlayer dielectric 110 can electrically isolate the gate 116 from the source contact layer 120 and the overlying metal layer coupled to the source terminals of the transistor 100. Although Figure 1 Not shown, but each instance of gate 116 can be coupled to the upper gate metal layer via a contact through the interlayer dielectric 110 for routing and coupling to the gate terminal of transistor 100 at different locations on the semiconductor die.

[0025] like Figure 1 As shown, gate 116 can be located on the first axis (e.g., Figure 1 The striped gate pattern is arranged in the first direction (shown along the z-axis). Specifically, as shown... Figure 1 As shown, the stripes of gate 116 can extend along the length in the z-axis direction, with the stripes repeating along the y-axis at gate spacing 117. Gate 116 can be separated from well region 128 by gate oxide 114. Thus, a vertical channel can be formed in well region 128 adjacent to gate oxide 114 and gate 116, extending from source region 124 through well region 128 to current spreading layer 130. As described in further detail below, during operation of transistor 100 in the on-state, current can flow from drain contact layer 180 through epitaxial region 170, through n-type pillars 152 of superjunction region 150, through transition region 140, and through current spreading layer 130, and then from this current spreading layer through various channels opened in well region 128 by applying sufficient gate voltage to gate 116 to source region 124. For a given semiconductor die region, the on-resistance of transistor 100 can depend in part on the number of instances of gate 116 that can be formed in the striped gate pattern. Therefore, reducing the gate spacing 117 of the striped gate pattern can produce more instances of gate 116 for a given semiconductor region, thus resulting in lower on-resistance.

[0026] like Figure 1 As shown, transistor 100 may further include a shielding region 138 located below the current spreading layer 130. Shielding region 138 may have a second conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, shielding region 138 may be a doped p-type region. When a high voltage is applied across the drain and source of transistor 100, shielding region 138 can provide shielding to protect the upper gate structure (including gate oxide 114) from the electric field in superjunction region 150, thereby increasing the breakdown voltage (BV) of transistor 100. Transistor 100 may further include a transition region 140 located below the current spreading layer 130. Transition region 140 may have a first conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, transition region 140 may be a moderately doped n-type region. In some embodiments, transition region 140 and shielding region 138 may be disposed at the same depth (e.g., along...). Figure 1 At the same depth as the x-axis illustrated in the example. The transition region 140 and the shielding region 138 can be arranged alternately in a stripe transition region pattern that is angularly offset from the stripe gate pattern. For example, the transition region 140 and the shielding region 138 can be in a second direction orthogonal to the first axis (e.g., in a second direction orthogonal to the z-axis, such as...). Figure 1 As shown, the striped transition area pattern is set in an alternating manner. Figure 1As shown, the alternating stripes of the transition region 140 and the shielding region 138 can extend along the length, for example, in the direction of the y-axis, wherein the widths of the stripes in the transition region 140 and the shielding region 138 repeat in an alternating manner in the direction of the z-axis. Figure 2A , Figure 2B and Figure 2C The cross-sectional view further reveals a striped transition zone pattern including transition zone 140 and shielding zone 138.

[0027] The orientations of the z-axis, y-axis, and x-axis described in this article Figure 1 , Figures 2A to 2D and Figures 3A to 3D Each of these axes shall be kept consistent. For the purposes of this disclosure and to aid in the description and illustration of the embodiments included herein, the z-axis may also be referred to as the first axis, the y-axis as the second axis, and the x-axis as the third axis. However, the designation of which axis is “first,” which axis is “second,” and which axis is “third” may be modified without departing from the scope of this disclosure.

[0028] Figure 2A A cross-sectional view of a transistor 100 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 2A An example of transistor 100 in compliance with Figure 1 The x-axis and z-axis shown are on the xz plane and in particular along the x-axis and z-axis. Figure 1 The cross-sectional view of the cutting line 2A shown. Figure 2B A cross-sectional view of a transistor 100 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 2B An example of transistor 100 in compliance with Figure 1 The x-axis and y-axis shown are on the xy-plane and in particular along the xy-axis. Figure 1 The cross-sectional view of cutting line 2B shown.

[0029] like Figure 2A and Figure 2B As shown in the diagram, shielding region 138 and transition region 140 may be located between current spreading layer 130 and superjunction region 150, which may include n-type pillars 152 and p-type pillars 154. In some embodiments, shielding region 138 may have the same (along the x-axis) thickness as transition region 140 and be located at the same depth as transition region. In some embodiments, transition region 140 may have a different doping level than current spreading layer 130. For example, in an embodiment where transistor 100 is an NMOS transistor, transition region 140 may have a lighter n-type doping than current spreading layer 130. In other embodiments, transition region 140 may have the same doping concentration as current spreading layer 130. In such embodiments, transition region 140 may be considered as an extension of current spreading layer 130 through shielding region 138.

[0030] As described above, transition region 140 can collect current traveling vertically through n-type pillar 152 into current spread layer 130, where the current can then travel horizontally through current spread layer 130 toward the various channels formed in well region 128 by applying a gate voltage to gate 116. Shielding region 138, combined with well region 128, can help provide a JFET-like effect for the current flowing through current spread layer 130. As described above, well region 128 and shielding region 138 can be p-type regions. And refer to below... Figures 3A to 3E As described, the well region 128 and the shield region 138 can be coupled to the source contact layer 120 to maintain the p-type region coupled to the source of the transistor 100 and thus to the lowest voltage potential (e.g., ground) within the transistor 100. Therefore, the well region 128 and the shield region 138 can form the gate of a depletion-mode junction field-effect transistor (JFET) that clamps the current channel through the current spread layer 130. Similarly, the opposite portions of the shield region 138 on the opposite side of the transition region 140 can also form the gate of a depletion-mode JFET that clamps the current through the transition region 140. However, the width of the channel through the transition region 140 can be greater than the width of the channel through the current spread layer 130, so the JFET effect within the transistor 100 can be dominated by the JFET-like structure formed by the well region 128 and the shield region 138 above and below the current spread layer 130.

[0031] The JFET effect provided by the well region 128 and shield region 138 above and below the current spreading layer 130 can help improve the short-circuit withstand time (SCWT) of transistor 100. For example, the JFET effect can provide a flatter saturation current for transistor 100 across a certain drain-source voltage range, which in turn limits the drain-source current of transistor 100 under short-circuit conditions. In such short-circuit conditions, the power system in which transistor 100 is implemented may fail, whereby transistor 100 is turned on by a gate voltage higher than the gate-source threshold of transistor 100 while the entire system supply voltage is applied across the drain-source of transistor 100. During such conditions, the JFET effect can limit the current flowing through transistor 100, thus extending the short-circuit withstand time (SCWT) during which transistor 100 can withstand faulty short-circuit conditions without failure. The saturation current for a given embodiment of transistor 100 can depend in part on the length of the JFET channel flowing through the current spreading layer 130, the dimensions of which are referenced below. Figure 2C It was described in further detail.

[0032] Figure 2C A top cross-sectional view of a transistor 100 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 2C Examples are given in accordance with Figure 1 A cross-sectional view of transistor 100 shown on the yz plane of the y-axis and z-axis, and particularly at the depth along the x-axis where it intersects with shielding region 138 and transition region 140.

[0033] like Figure 2C As shown, the transition region 140 and the shielding region 138 can be arranged in an alternating manner with a stripe transition region pattern that is angularly offset from the stripe gate pattern. For example, the transition region 140 and the shielding region 138 can be arranged in a second direction orthogonal to the first axis (e.g., in the second direction of the y-axis orthogonal to the first direction of the z-axis, such as...). Figure 2C As shown, the stripe transition zone pattern is arranged in an alternating manner. That is, the stripes can extend in the y-axis direction and repeat in an alternating manner along the z-axis. Although in Figure 2C A single stripe of transition region 140 is illustrated, but other stripes of transition region 140 may repeat in an alternating manner with the stripes of shielding region 138. (See above reference) Figure 2A and Figure 2B The length of the JFET channel along the z-axis through the current spreading layer 130 can be determined by the width of the shielding region 138 along the z-axis. The width of the stripes of the shielding region 138 along the z-axis can be equal to the transition region spacing 141 (the alternating stripes of the shielding region 138 and the transition region 140 repeat along the z-axis at this transition region spacing) minus the width of the transition region 140. Therefore, the length of the JFET channel through the current spreading layer 130 can also be described as depending on the transition region spacing 141 and the width of the transition region 140 along the z-axis.

[0034] like Figure 1 and Figures 2A to 2C As shown in the diagram, the transition region 140 and the shielding region 138 can be arranged in an alternating manner with a stripe transition region pattern that is angularly offset from the stripe gate pattern. For example, the transition region 140 and the shielding region 138 can be arranged in an alternating manner with a stripe transition region pattern in a second direction of a second axis orthogonal to the first axis (e.g., in a second direction of the y-axis orthogonal to the z-axis). By patterning the transition region 140 and the shielding region 138 with a stripe transition region pattern along a second axis (e.g., the y-axis) orthogonal to or otherwise angularly offset from the first axis (e.g., the z-axis) (along which the stripe gate pattern extends), the width and spacing of the transition region 140 and the shielding region 138 can be determined separately from the gate spacing 117 of the stripe gate pattern. Therefore, in some embodiments, the gate spacing 117 of the stripe gate pattern can be different from the transition region spacing 141 of the stripe transition region pattern. Therefore, the width of the shielding region 138 and the transition region 140 and the transition region spacing 141 can be selected based on a target saturation current value, and are not limited to the same gate spacing 117 of the stripe gate pattern.

[0035] Return to reference Figure 1 The transistor 100 may include a superjunction region 150 located below the shielding region 138 and the transition region 140. The superjunction region 150 may include n-type pillars 152 and p-type pillars 154. The n-type pillars 152 and p-type pillars 154 may be arranged in an alternating manner with a striped superjunction pattern that is angularly offset from the striped transition region pattern. For example, the n-type pillars 152 and p-type pillars 154 may be arranged in a first direction orthogonal to the second axis (in the direction of the first axis). Figure 1 The striped superjunction pattern shown is arranged in an alternating manner in the first direction (orthogonal to the z-axis). Figure 2D The top sectional view further reveals a striped superjunction pattern including n-type column 152 and p-type column 154. Figure 2D A top cross-sectional view of a transistor 100 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 2D Examples are given in accordance with Figure 1 The top cross-sectional view of transistor 100 is shown on the yz plane, which represents the y-axis and z-axis, and particularly at the depth along the x-axis where it intersects with n-type pillar 152 and p-type pillar 154. (See diagram) Figure 1 and Figure 2D As shown in the diagram, alternating stripes of n-type pillars 152 and p-type pillars 154 can extend along the length in the z-axis direction, wherein the widths of the stripes of n-type pillars 152 and p-type pillars 154 repeat in an alternating manner in the y-axis direction. The superjunction spacing 151 can define the width of the stripe pattern including instances of n-type pillars 152 and p-type pillars 154. Although in Figure 1 and Figure 2D A single example of n-type pillar 152 and p-type pillar 154 is illustrated, but it should be understood that other examples of superjunction region 150 may be repeated along the y-axis, wherein there are alternating stripes of n-type pillar 152 and p-type pillar 154 in other regions of the semiconductor die (not shown).

[0036] The superjunction region 150 can be configured to increase the breakdown voltage (BV) of the transistor 100. For example, the n-type pillar 152 and the p-type pillar 154 can be charge-balanced. Figure 1 As shown, in some embodiments, the n-type pillar 152 and the p-type pillar 154 may have the same width as each other. In such embodiments, the n-type doping concentration of the n-type pillar 152 may be equal to the p-type doping concentration of the p-type pillar 154 to maintain charge balance. In other embodiments, the n-type pillar 152 may have a smaller or larger width along the y-axis than the p-type pillar 154, and therefore may have a proportionally larger or smaller doping concentration than the p-type pillar 154 to maintain the overall charge balance of the superjunction region 150. Compared to a fully n-type drift layer, the charge balance of the p-type pillar 154 and the n-type pillar 152 allows the superjunction region 150 to provide a higher blocking voltage and therefore a higher breakdown voltage (BV).

[0037] As described above, during operation of transistor 100 in the on-state, current can flow from drain contact layer 180 through epitaxial region 170, through n-type pillars 152 of superjunction region 150, through transition region 140, and through current spread layer 130. Current can then flow from this current spread layer through various channels opened in well region 128 by applying sufficient gate voltage to gate 116 to source region 124. Higher n-type doping of n-type pillars 152 can provide lower resistance through n-type pillars 152, thus contributing to lower on-resistance (RON) of transistor 100. However, higher n-type doping of n-type pillars 152 can also increase the total charge within n-type pillars 152, thus reducing the breakdown voltage (BV) of transistor 100. Another factor affecting the total charge within n-type pillars 152 is the width of n-type pillars 152 and the superjunction spacing 151 of the striped superjunction pattern. For example, reducing the superjunction spacing 151 and, in particular, reducing the width of the n-type pillar 152 can reduce the total charge in a single stripe of the n-type pillar 152, thus providing a higher breakdown voltage (BV) for the transistor 100 as a whole.

[0038] like Figure 1 and Figure 2D As shown in the diagram, the n-type pillars 152 and p-type pillars 154 can be arranged in an alternating manner with a stripe superjunction pattern that is angularly offset from the stripe transition region pattern. For example, the n-type pillars 152 and p-type pillars 154 can be arranged in a first direction orthogonal to the second axis (e.g., in a direction similar to...). Figure 1 The striped superjunction pattern is arranged alternately along a first direction (orthogonal to the y-axis and z-axis) shown. The n-type pillars 152 and p-type pillars 154 are patterned with a striped superjunction pattern along a first axis (e.g., the z-axis) orthogonal to or otherwise angularly offset from a second axis (e.g., the y-axis) (along which the striped transition region pattern extends). The width and spacing of the n-type pillars 152 and p-type pillars 154 can be determined separately from the transition region spacing 141 of the striped transition region pattern, which includes the shielding region 138 and the transition region 140. Therefore, in some embodiments, the transition region spacing 141 of the striped transition region pattern may differ from the superjunction spacing 151 of the striped superjunction pattern. Furthermore, the gate spacing 117 of the striped gate pattern may differ from the superjunction spacing 151 of the striped superjunction pattern. Therefore, the widths of the n-type pillar 152 and the p-type pillar 154, as well as the superjunction spacing 151, can be selected based on the target on-resistance (RON) and breakdown voltage (BV) values, without being limited to the same gate spacing 117 of the striped gate pattern or the same transition spacing 141 of the striped transition pattern.

[0039] Refer again Figure 1Transistor 100 may include an epitaxial region 170 located below superjunction region 150. In some embodiments, epitaxial region 170 may have a first conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, epitaxial region 170 may be an n-doped region. Transistor 100 may also include a drain contact layer 180 adjacent to epitaxial region 170. Drain contact layer 180 may include, for example, silicide, which may improve the connection between epitaxial region 170 and an additional metal layer added to the bottom of semiconductor substrate and coupled to the drain terminal of transistor 100. Figure 1 The conductivity of the contacts between (not shown). As described above, during operation when transistor 100 is in the on state, current can flow from drain contact layer 180 through epitaxial region 170, through n-type pillar 152 of superjunction region 150, through transition region 140, and through current spread layer 130. Current can then flow from this current spread layer through various channels opened in well region 128 by applying sufficient gate voltage to gate 116 to source region 124.

[0040] Figure 3A A perspective view of a transistor 300 according to an embodiment of the present disclosure is illustrated. Transistor 300 may represent the above reference. Figure 1 and Figures 2A to 2D An embodiment of transistor 100 is described. Transistor 300 may include certain elements similar to those of transistor 100, which may be arranged and operated in a manner similar to that described above with reference to transistor 100. For example, similar to transistor 100, transistor 300 may include an interlayer dielectric 110, a gate oxide 114, a gate 116, a source contact layer 120, a source region 124, a well region 128, a current spreading layer 130, a shielding region 138, a transition region 140, a superjunction region 150 including n-type pillars 152 and p-type pillars 154, an epitaxial region 170, and a drain contact layer 180.

[0041] Transistor 300 may also include multiple link regions 315. The multiple link regions 315 may have a second conductivity type. For example, in an embodiment where transistor 300 is an NMOS transistor, each of the multiple link regions 315 may be a p-type doped region, similar to the well region 128 and the shield region 138. Figure 3AAs shown, a plurality of link regions 315 may extend in the x-axis direction from the source contact layer 120 through the source region 124, the well region 128, and the current spreading layer 130 to the shielding region 138. Each of the plurality of link regions 315 may couple the well region 128 and the shielding region 138 to the source contact layer 120 to keep the p-type well region 128 and the shielding region 138 coupled to the source of the transistor 300 and thus to the lowest voltage potential (e.g., ground) within the transistor 300.

[0042] In some implementations, the multiple link areas 315 can each be formed in an island-like pattern. For example, as... Figure 3A As shown, each link region 315 may be surrounded by a region of source region 124, well region 128, and current spreading layer 130. In some embodiments, such as Figure 3A As shown, each link region 315 may have a circular shape relative to the z-axis and y-axis zy-plane. In other embodiments, each link region 315 may have an ellipse, a square, a rectangle, or any other shape suitable for forming a repeating island pattern relative to the z-axis and y-axis zy-plane.

[0043] In some implementations, multiple link areas 315 can be arranged in rows and columns along the z-axis and y-axis. For example, multiple link areas 315 can be arranged along an axis parallel to the first axis (e.g., along an axis parallel to...). Figure 3A The z-axis shown is the axis. Furthermore, multiple link areas 315 can also be set along an axis orthogonal to the first axis (e.g., along an axis perpendicular to the first axis). Figure 3A The z-axis shown is orthogonal to and parallel to the y-axis. For example, multiple link areas 315 can be arranged along an axis parallel to the second axis (e.g., along an axis parallel to the y-axis) and centered with respect to the width of the stripes of the shielding area 138.

[0044] In some implementations, each link region 315 may be positioned at a distance (e.g., 40µm, 20µm, 10µm, 5µm or less) from another instance of link region 315 to maintain sufficiently strong coupling between each region of source contact layer 120 to well region 128 and to each region of shield region 138. The spacing of link regions 315 along the y-axis ensures, for example, that at least one instance of link region 315 is coupled to each corresponding region of well region 128 between corresponding gates 116. The spacing of link regions 315 along the z-axis also ensures, for example, that at least one instance of link region 315 is coupled to each instance of shield region 138 between corresponding instances of transition region 140.

[0045] Figure 3B A perspective view of a transistor 301 according to an embodiment of the present disclosure is illustrated. Transistor 301 may represent the transistor referenced above. Figure 3AAlternative embodiments of the described transistor 300. Transistor 301 may include certain elements similar to those of transistors 100 and 300, which may be arranged and operated in a manner similar to that described above with reference to transistors 100 and 300. For example, similar to transistors 100 and 300, transistor 301 may include an interlayer dielectric 110, a gate oxide 114, a gate 116, a source contact layer 120, a source region 124, a well region 128, a current spreading layer 130, a shielding region 138, a transition region 140, a superjunction region 150 including n-type pillars 152 and p-type pillars 154, an epitaxial region 170, and a drain contact layer 180.

[0046] Transistor 301 may also include a plurality of link regions 325. The plurality of link regions 325 may have a second conductivity type. For example, in an embodiment where transistor 301 is an NMOS transistor, each of the plurality of link regions 325 may be a p-type doped region, similar to the well region 128 and the shield region 138. Figure 3B As shown, a plurality of link regions 325 may extend in the x-axis direction from the source contact layer 120 through the source region 124, the well region 128, and the current spreading layer 130 to the shielding region 138. Each of the plurality of link regions 325 may couple the well region 128 and the shielding region 138 to the source contact layer 120 to keep the p-type well region 128 and the shielding region 138 coupled to the source of the transistor 301 and thus to the lowest voltage potential (e.g., ground) within the transistor 301.

[0047] In some implementations, the multiple link areas 325 may each be formed with a striped pattern. For example, as... Figure 3B As shown, the plurality of link areas 325 may be arranged along an axis parallel to the second axis (e.g., along an axis parallel to the y-axis) and centered with respect to the width of the stripes of the shielding area 138. As another example, the plurality of link areas 325 may be arranged in a stripe pattern, wherein the stripes extend along the length parallel to the second axis (e.g., along an axis parallel to the y-axis).

[0048] In some implementations, each link region 325 may be positioned at a distance (e.g., 40µm, 20µm, 10µm, 5µm or less) from another instance of link region 325 to maintain sufficiently strong coupling between each region of source contact layer 120 to well region 128 and to each region of shield region 138. At least one instance of link region 325 may be coupled to each corresponding region of well region 128 between corresponding gates 116. Furthermore, the spacing of link regions 325 along the z-axis may also ensure, for example, that at least one instance of link region 325 is coupled to each instance of shield region 138 between corresponding instances of transition region 140.

[0049] Figure 3C A perspective view of a transistor 302 according to an embodiment of the present disclosure is illustrated. Transistor 302 may represent the above reference. Figure 3A Alternative embodiments of the described transistor 300. Transistor 302 may include certain elements similar to those of transistors 100 and 300, which may be arranged and operated in a manner similar to that described above with reference to transistors 100 and 300. For example, similar to transistors 100 and 300, transistor 302 may include an interlayer dielectric 110, a gate oxide 114, a gate 116, a source contact layer 120, a source region 124, a well region 128, a current spreading layer 130, a shielding region 138, a transition region 140, a superjunction region 150 including n-type pillars 152 and p-type pillars 154, an epitaxial region 170, and a drain contact layer 180.

[0050] Transistor 302 may also include a plurality of link regions 335. The plurality of link regions 335 may have a second conductivity type. For example, in an embodiment where transistor 302 is an NMOS transistor, each of the plurality of link regions 335 may be a p-type doped region, similar to the well region 128 and the shield region 138. Figure 3C As shown, a plurality of link regions 335 may extend in the x-axis direction from the source contact layer 120 through the source region 124, the well region 128, and the current spreading layer 130 to the shielding region 138. Each of the plurality of link regions 335 may couple the well region 128 and the shielding region 138 to the source contact layer 120 to keep the p-type well region 128 and the shielding region 138 coupled to the source of the transistor 302 and thus to the lowest voltage potential (e.g., ground) within the transistor 302.

[0051] like Figure 3C As shown, the plurality of link regions 335 can each be formed with a stripe pattern. For example, the plurality of link regions 335 can be arranged with a stripe pattern, wherein the stripes extend along the length at an angle 336 to the first axis (at an angle 336 to the z-axis). In some embodiments, each link region 335 can be arranged with a linear pattern that is angularly offset from the stripe gate pattern at an angle in the range of 20 degrees to 70 degrees.

[0052] In some implementations, each linear pattern of the link region 335 may be positioned at a distance (e.g., 40µm, 20µm, 10µm, 5µm or less) from another instance of the link region 335 to maintain sufficiently strong coupling between each region of the source contact layer 120 to the well region 128 and to each region of the shield region 138. At least one instance of the link region 335 may be coupled to each corresponding region of the well region 128 between corresponding gates 116. Furthermore, the spacing of the link regions 335 along the z-axis may also ensure, for example, that at least one instance of the link region 335 is coupled to each instance of the shield region 138 between corresponding instances of the transition region 140.

[0053] By intersecting the gate structures formed by gate oxide 114 and gate 116, link region 335 can sacrifice a portion of the channel formed in well region 128. However, the increase in on-resistance (RON) due to sacrificing a portion of the channel can be offset by eliminating the significant effect of the constraint of maintaining a minimum spacing between the link region and the gate structure to prevent gate misalignment. Therefore, the trenches in which gate oxide 114 and gate 116 are formed can be disposed in the semiconductor substrate with a smaller gate pitch, thereby increasing the number of transistor fingers and reducing the on-resistance (RON) for a given semiconductor die region.

[0054] Figure 3D and Figure 3E A top view of a link area injection pattern according to an embodiment of the present invention is illustrated. (Refer to the above text.) Figure 3A As described, the link area 315 can be arranged in an island pattern, with rows arranged along an axis parallel to the z-axis and columns arranged along an axis parallel to the y-axis. In some embodiments, the rows and columns can be offset at an angle from the z-axis and y-axis. For example, as... Figure 3D As shown, the rows of link areas 315 can be arranged along an axis offset from the z-axis by an angle 336. In some embodiments, the angle 336 can be, for example, in the range of 20 degrees to 70 degrees. In other embodiments, multiple link areas 315 can be, for example, arranged in a manner such as... Figure 3D The hexagonal pattern shown is configured as follows. Figure 3D and Figure 3EIn any of these embodiments shown, each link region 315 may be located at a distance (e.g., 40µm, 20µm, 10µm, 5µm or less) from another instance of link region 315 to maintain sufficiently strong coupling between each region of source contact layer 120 to well region 128 and to each region of shield region 138. The spacing of link regions 315 along the yz plane can ensure, for example, that at least one instance of link region 315 is coupled to each corresponding region of well region 128 between corresponding gates 116, and can also ensure that at least one instance of link region 315 is coupled to each instance of shield region 138 between corresponding instances of transition region 140.

[0055] Figure 4 A top layout view of a transistor 400 according to an embodiment of the present disclosure is illustrated. Transistor 400 may include certain elements similar to those of transistors 100 and 300, which may be configured similarly to those of transistor 100 (referenced above). Figure 1 The transistor 400 is laid out and operated in a manner similar to that described for transistors 100 and 300 (Figure 3). For example, similar to transistors 100 and 300, transistor 400 may include an interlayer dielectric, a gate oxide, a gate, a source contact layer, a source region, a well region, a current spreading layer, a shielding region, a transition region, a superjunction region including n-type and p-type pillars, an epitaxial region, and a drain contact layer. However, Figure 4 The top layout diagram shown includes only certain layers to illustrate the corresponding angular relationships of the striped gate pattern of the gate, the striped transition region pattern of the shielding region and the transition region, and the striped superjunction patterns of the n-type pillars and p-type pillars. For example, Figure 4 The top layout diagram illustrates gate oxide 414, gate 416, link region 415, shielding region 438, n-type pillar 452, and p-type pillar 454, but the included interlayer dielectric, source contact layer, source region, well region, current spread layer, and transition region (as well as epitaxial region and drain contact layer) are omitted from the view, so that the corresponding patterns of gate 416, shielding region 438, n-type pillar 452, and p-type pillar 454 can be observed relative to each other.

[0056] like Figure 4 As shown, the gate 416 of transistor 400 can be configured with a striped gate pattern. For example, the gate 416 of the transistor can be configured with a striped gate pattern in a first direction 481 parallel to the z-axis. Although from Figure 4The transition region is omitted in the view to show the underlying layer, but the shielding region 438 can be arranged in an alternating manner with a striped transition region pattern that is angularly offset from the striped gate pattern. For example, the shielding region 438 can be arranged in an alternating manner with a striped transition region pattern in a second direction 482, which is offset by an angle 490 from the first direction 481 of the striped gate pattern. By forming the striped transition region pattern along the second direction 482 that is angularly offset from the first direction 481 of the striped gate pattern, the width and spacing of the transition region and the shielding region can be determined separately from the gate spacing of the striped gate pattern. Therefore, in some embodiments, the gate spacing of the striped gate pattern can be different from the transition region spacing of the striped transition region pattern. Therefore, the width of the shielding region and the transition region, as well as the transition region spacing, can be selected based on a target saturation current value, and are not limited to the same gate spacing of the striped gate pattern.

[0057] For example Figure 4 As shown, the n-type pillars 452 and p-type pillars 454 can be arranged alternately in a stripe superjunction pattern that is angularly offset from the stripe transition region pattern. For example, the n-type pillars 452 and p-type pillars 454 can be arranged alternately in a stripe superjunction pattern on a third direction 483, which is offset by an angle 495 from the second direction 482 of the stripe transition region pattern. By patterning the n-type pillars 452 and p-type pillars 454 in a stripe superjunction pattern on a third direction 483 that is angularly offset from the second direction 482 of the stripe transition region pattern, the width and spacing of the n-type pillars 452 and p-type pillars 454 can be determined separately from the transition region spacing of the stripe transition region pattern. Therefore, in some embodiments, the transition region spacing of the stripe transition region pattern can be different from the superjunction spacing of the stripe superjunction pattern. Furthermore, the gate spacing of the stripe gate pattern can be different from the superjunction spacing of the stripe superjunction pattern. Therefore, the widths of the n-type pillar 452 and the p-type pillar 454, as well as the superjunction spacing, can be selected based on the target on-resistance (RON) and breakdown voltage (BV) values, without being limited to the same gate spacing of the striped gate pattern or the same transition spacing of the striped transition region pattern.

[0058] Figure 5 A method 500 for manufacturing a superjunction transistor according to an embodiment of the present disclosure is illustrated. Method 500 can be performed by any suitable mechanism. Method 500 can utilize... Figure 5 The steps shown are performed in fewer or more steps. Furthermore, steps in method 500 can be omitted, repeated, executed in parallel, or combined with... Figure 5 The order shown may differ from the sequential execution or recursive execution. Although shown sequentially, one or more steps of method 500 may be executed simultaneously or in a reordered manner. For example, although... Figure 5The steps illustrated herein generally address forming a layer in a direction from the bottom of the semiconductor substrate toward the upper surface of the semiconductor substrate, but the regions described herein can be formed in any suitable order by using different doping implantations at different depths.

[0059] Step 502 may include forming a superjunction region comprising n-type pillars and p-type pillars arranged in an alternating pattern of striped superjunctions. For example, as referenced above. Figure 1 and Figure 2D As described, the superjunction region 150 can be formed in a semiconductor substrate and can be included in a first direction orthogonal to the second axis (in relation to...). Figure 1 The n-type pillars 152 and p-type pillars are arranged in an alternating pattern in the first direction (orthogonal to the z-axis shown) as a striped superjunction pattern. Although described herein as forming part of the superjunction region 150, the n-type pillars 152 and p-type pillars 154 can be formed by different doping routines. For example, as Figure 1 As illustrated, an n-type pillar 152 can be formed in a semiconductor substrate by applying patterned n-type doping implantation at a depth extending above the epitaxial region 170. Similarly, a p-type pillar 154 can be formed in a semiconductor substrate by applying patterned p-type doping implantation at a depth extending above the epitaxial region 170. Figure 1 and Figure 2D As shown in the figure, the alternating stripes of n-type column 152 and p-type column 154 can be patterned to extend along the length in the z-axis direction, wherein the width of the stripes of n-type column 152 and p-type column 154 repeats in an alternating manner in the y-axis direction.

[0060] Step 504 may include forming a transition region having a first conductivity type and a shielding region having a second conductivity type in an alternating pattern and with a stripe transition region pattern offset at an angle to the stripe superjunction pattern. For example, the transition region having the first conductivity type and the shielding region having the second conductivity type may be formed in an alternating pattern and with a stripe transition region pattern in a second direction along a second axis orthogonal to the first axis or otherwise offset at an angle to it. (Refer to the above...) Figure 1 and Figures 2A to 2C As described, transition region 140 and shielding region 138 can be formed in the semiconductor substrate above superjunction region 150. Transition region 140 is an n-type region, while shielding region 138 can be a p-type region. Figure 1 and Figures 2A to 2C As illustrated, a transition region 140 can be formed in the semiconductor substrate by applying patterned n-type doping implantation at a depth extending above the superjunction region 150. Similarly, a shielding region 138 can be formed in the semiconductor substrate by applying patterned p-type doping implantation at a depth also extending above the superjunction region 150. Figure 1 and Figures 2A to 2CAs shown in the diagram, the alternating stripes of the transition region 140 and the shielding region 138 can be patterned to extend along the length, for example, in the direction of the y-axis and orthogonal to the z-axis. The stripe pattern of the transition region 140 and the shielding region 138 can be repeated alternately in the direction of the z-axis.

[0061] Step 506 may include forming a current-spreading layer having a first conductivity type over the transition region and the shielding region. For example, as referenced above. Figure 1 As described, the current spreading layer 130 can be formed over the transition region 140 and the shielding region 138. The current spreading layer 130 can be an n-type region. Figure 1 and Figures 2A to 2B As illustrated, an n-type doping implantation can be applied to a depth extending above the transition region 140 and the shielding region 138 to form a current spreading layer 130 in the semiconductor substrate.

[0062] Step 508 may include forming a well region having a second conductivity type above the current spreading layer. For example, as referenced above. Figure 1 As described, well region 128 can be formed in the semiconductor substrate above current spreading layer 130. Well region 128 can be a p-type region. For example, as... Figure 1 and Figures 2A to 2B As illustrated, a well region 128 can be formed in a semiconductor substrate by applying p-type doping implantation at a depth extending above the current spreading layer 130.

[0063] Step 510 may include forming a source region having a first conductivity type above the well region. For example, as referenced above. Figure 1 As described, source region 124 can be formed in the semiconductor substrate above well region 128. Source region 124 can be a heavily doped n-type region. For example, as... Figure 1 and Figures 2A to 2B As illustrated, a source region 124 can be formed in a semiconductor substrate by applying heavy n-type doping implantation at a depth extending above the well region 128.

[0064] Step 512 may include forming a gate in a trench extending through the source and well regions, the gate being configured with a striped gate pattern angularly offset from the stripe transition region pattern. For example, the gate may be configured with a striped gate pattern in a first direction of a first axis orthogonal to the second axis. (Refer to the above text.) Figure 1 As described, trenches can be formed by etching a pattern on the upper surface of a semiconductor substrate. After etching, a gate oxide 114 can be grown or deposited along the sidewalls and bottom of the trench. The gate oxide 114 can include, for example, silicon dioxide or any other oxide suitable for forming a gate dielectric. A gate 116 can then be deposited to fill the remaining area of ​​the trench. In some embodiments, the gate 116 can be formed of, for example, heavily doped polysilicon. Figure 1 As shown, the gate 116 may be configured in a striped gate pattern in a first direction orthogonal to or otherwise angularly offset from a first axis (e.g., the z-axis). Specifically, the stripes of the gate 116 may extend along the length in the z-axis direction, wherein the stripes repeat along the y-axis with a gate spacing 117.

[0065] Step 514 may include forming a plurality of link regions having a second conductivity type and extending through the source region, well region, and current spread layer to reach the shielding region. For example, as referenced above. Figures 3A to 3C As described, multiple link areas (such as link area 315) Figure 3A ), Link Area 325 ( Figure 3B ) or link area 335 ( Figure 3C ()) can be formed in a semiconductor substrate, extending from the source contact layer 120, through the source region 124, the well region 128, and the current spreading layer 130, to reach the shielding region 138. Such as link region 315 ( Figure 3A ), Link Area 325 ( Figure 3B ) or link area 335 ( Figure 3C The link region can be a p-type region. For example, a link region such as 315 can be formed in the semiconductor substrate by applying p-type doping implantation to a depth extending through the source region 124, the well region 128, and the current spreading layer 130 to the shielding region 138. Figure 3A ), Link Area 325 ( Figure 3B ) or link area 335 ( Figure 3C The link regions of the plurality of link regions can couple the well region 128 and the shield region 138 to the source contact layer 120 to keep the p-type well region 128 and the shield region 138 coupled to the source of the transistor and thus coupled to the lowest voltage potential (e.g., ground) within the transistor.

[0066] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A transistor, the transistor comprising: A source region having a first conductivity type; A well region located below the source region and having a second conductivity type; A current spreading layer, located below the well region and having the first conductivity type; A gate, formed in a trench extending through the source region and the well region, the gate being arranged in a striped gate pattern; A transition region located below the current spreading layer and having the first conductivity type; A shielding region located below the current spreading layer and having the second conductivity type, wherein the transition region and the shielding region are arranged alternately in a striped transition region pattern that is angularly offset from the striped gate pattern; and A superjunction region, located below the shielding region and the transition region, includes n-type pillars and p-type pillars arranged in an alternating manner with striped superjunction patterns that are angularly offset from the striped transition region pattern.

2. The transistor according to claim 1, wherein: The gate is arranged in the striped gate pattern in a first direction of the first axis; and The transition zone and the shielding zone are arranged alternately in the striped transition zone pattern in a second direction of a second axis orthogonal to the first axis.

3. The transistor according to claim 1, wherein: The n-type pillars and the p-type pillars are arranged alternately in the striped superjunction pattern along a first direction of the first axis; and The transition zone and the shielding zone are arranged alternately in the striped transition zone pattern in a second direction of a second axis orthogonal to the first axis.

4. The transistor of claim 1, wherein the gate spacing of the striped gate pattern is different from the transition spacing of the striped transition pattern.

5. The transistor of claim 1, wherein the gate spacing of the striped gate pattern is different from the superjunction spacing of the striped superjunction pattern.

6. The transistor of claim 1, wherein the transition region spacing of the striped transition region pattern is different from the superjunction spacing of the striped superjunction pattern.

7. The transistor according to claim 1, further comprising: A source contact layer, wherein the source contact layer is located above the source region; and Multiple link regions having the second conductivity type and extending from the source contact layer through the source region, the well region, and the current spreading layer to the shielding region.

8. The transistor of claim 7, wherein each link region is arranged in a linear pattern, the linear pattern being angularly offset from the striped gate pattern at an angle ranging from 20 degrees to 70 degrees.

9. The transistor according to claim 7, wherein: The gate is arranged in the striped gate pattern in a first direction of the first axis; and The plurality of link areas are arranged in an island pattern along an axis parallel to the first axis.

10. The transistor according to claim 7, wherein: The gate is arranged in the striped gate pattern in a first direction of the first axis; and The plurality of link areas are arranged in an island pattern along an axis orthogonal to the first axis.

11. The transistor of claim 1, wherein the transistor is a silicon carbide transistor.

12. The transistor of claim 1, wherein the transistor is an NMOS transistor.

13. A superjunction transistor, the superjunction transistor comprising: A source region having a first conductivity type; A well region located below the source region and having a second conductivity type; A current spreading layer, located below the well region and having the first conductivity type; A gate, the gate being formed in a trench extending through the source region and the well region, the gate being arranged in a striped gate pattern in a first direction of a first axis; A transition region located below the current spreading layer and having the first conductivity type; A shielding region located below the current spreading layer and having the second conductivity type, wherein the transition region and the shielding region are arranged alternately in a striped transition region pattern in a second direction of a second axis orthogonal to the first axis; and The superjunction region is located below the shielding region and the transition region, and the superjunction region includes n-type pillars and p-type pillars arranged in an alternating striped superjunction pattern in the first direction of the first axis.

14. The superjunction transistor according to claim 13, wherein: The gate spacing of the striped gate pattern is different from the transition spacing of the striped transition region pattern. The gate spacing of the striped gate pattern is different from the superjunction spacing of the striped superjunction pattern; and The transition zone spacing of the striped transition zone pattern is different from the superjunction spacing of the striped superjunction pattern.

15. The superjunction transistor of claim 13, wherein the superjunction transistor is a silicon carbide transistor.

16. A method, the method comprising: A superjunction region is formed, the superjunction region comprising n-type pillars and p-type pillars arranged in an alternating pattern of striped superjunction patterns; A transition region having a first conductivity type and a shielding region having a second conductivity type are formed in an alternating manner and with a stripe transition region pattern that is angularly offset from the stripe superjunction pattern. A current spreading layer having the first conductivity type is formed above the transition region and the shielding region; A well region having the second conductivity type is formed above the current spreading layer; A source region having the first conductivity type is formed above the well region; as well as A gate is formed in a trench extending through the source region and the well region, the gate being configured with a striped gate pattern that is angularly offset from the striped transition region pattern.

17. The method of claim 16, wherein: The gate is arranged in the striped gate pattern in a first direction of the first axis; and The transition zone and the shielding zone are arranged alternately in the striped transition zone pattern in a second direction of a second axis orthogonal to the first axis.

18. The method of claim 16, wherein: The n-type pillars and the p-type pillars are arranged alternately in the striped superjunction pattern along a first direction of the first axis; and The transition zone and the shielding zone are arranged alternately in the striped transition zone pattern in a second direction of a second axis orthogonal to the first axis.

19. The method of claim 16, wherein the transition region spacing of the stripe transition region pattern is different from the gate spacing of the stripe gate pattern and the superjunction spacing of the stripe superjunction pattern.

20. The method of claim 16, further comprising: Multiple link regions are formed, the multiple link regions having the second conductivity type, and extending through the source region, the well region and the current spreading layer to reach the shielding region.

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