A termination structure of super junction device and a preparation method thereof

Abstract

This invention discloses a termination structure for a superjunction device and its fabrication method. The termination structure includes an active region, a transition region, and a termination region, each having doped pillars of a first and second conductivity type distributed sequentially along a horizontal direction. No first conductivity type impurities are implanted at the body region where the transition region and the termination region intersect. The first and second conductivity type doped pillars in both the transition and termination regions are vertically divided into upper and lower portions. The upper and lower portions of the second conductivity type doped pillars are staggered horizontally. The size of the second conductivity type doped pillars on the side of the termination region furthest from the transition region is smaller than that on the side of the termination region closest to the transition region. The middle portion of the termination region and the upper portion of the second conductivity type doped pillars near the transition region are both covered with second conductivity type doped implantation regions. This termination structure can adjust the electric field distribution in the termination region, optimize the performance of the device termination structure, improve the overall utilization rate of the termination, and reduce costs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a terminal structure of a superjunction device and its fabrication method. Background Technology

[0002] In the field of power devices, VDMOSFET (Vertical Double-diffused MOSFET) is a traditional MOSFET device with a long history of development. However, due to the "silicon limit", there is always a contradiction between the voltage withstand capability and the on-resistance of VDMOSFET. Therefore, improving the voltage withstand capability and reducing the on-resistance of the device has become a major limitation to the continued development of VDMOSFET. The introduction of the superjunction MOSFET structure breaks the "silicon limit". Compared with VDSMOSFET, it can significantly reduce the on-resistance at the same voltage withstand level.

[0003] The formation of superjunction structures generally involves two processes: multiple epitaxy and trench etching. Multiple epitaxy involves growing epitaxial layers multiple times, with P-type impurities implanted during each growth to form staggered PN-doped pillars. Trench etching involves growing thicker epitaxial layers in fewer steps, etching the epitaxial layer after each growth to form trenches, and then filling them with P-type epitaxial layers to form staggered PN-doped pillars. The two processes are completely different. Multiple epitaxy has greater variability, while trench etching has less variability and is limited by device size.

[0004] The superjunction structure comprises an active region, a transition region, and a termination region. The design of the transition and termination regions is particularly important, affecting the overall device performance, reliability, stability, and the trade-off between chip area and cost. Therefore, how to design the transition and termination regions to improve the performance of the terminated device of the superjunction MOSFET structure has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a termination structure for a superjunction device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a termination structure for a superjunction device, comprising: An active region, a transition region, and a terminal region are distributed sequentially along a horizontal direction, wherein the active region, the transition region, and the terminal region each have a first conductivity type doped pillar and a second conductivity type doped pillar; In this configuration, no first conductivity type impurities are implanted at the body region where the transition region and the terminal region intersect. Both the first conductivity type doped pillars and the second conductivity type doped pillars in the transition region and the terminal region are vertically divided into upper and lower portions. Horizontally, the upper and lower portions of the second conductivity type doped pillars are staggered. Furthermore, along the horizontal direction, the size of the second conductivity type doped pillar on the side of the terminal region furthest from the transition region is smaller than the size of the second conductivity type doped pillar on the side of the terminal region closest to the transition region. The middle portion of the terminal region and the upper portion of the second conductivity type doped pillars near the transition region are both covered with second conductivity type doped implantation regions.

[0006] In a second aspect, the present invention provides a method for fabricating a termination structure of a superjunction device, used to fabricate the termination structure of the superjunction device described in the first aspect, the method comprising: S1. An epitaxial layer of the first conductivity type is grown on a substrate layer of the first conductivity type with doping, and a first conductivity type impurity is implanted. A second conductivity type impurity is implanted using a first photomask, and an active region, a transition region and a terminal region are formed at the same time. S2. Based on step S1, continue to grow the first conductivity type epitaxial layer, implant the first conductivity type impurity, and use the first photomask to implant the second conductivity type impurity. Then, repeat step S2 N times to form the first conductivity type doped pillar and the second conductivity type doped pillar in the active region, as well as the lower part of the first conductivity type doped pillar and the lower part of the second conductivity type doped pillar in the transition region and the terminal region. S3. Based on step S2, grow the first conductivity type epitaxial layer again and implant the first conductivity type impurity. Use the second photomask to implant the second conductivity type impurity. Then, repeat step S3 once more to continue forming the first conductivity type doped pillar and the second conductivity type doped pillar in the active region, as well as the upper part of the first conductivity type doped pillar and the upper part of the second conductivity type doped pillar in the transition region and the terminal region. The first conductivity type doped pillar and the second conductivity type doped pillar are alternately distributed along the horizontal direction and have different sizes. Furthermore, the upper part of the second conductivity type doped pillar and the lower part of the second conductivity type doped pillar are staggered along the horizontal direction. S4. Based on step S3, a first conductivity type epitaxial layer is grown again and a first conductivity type impurity is implanted. A second conductivity type impurity within a preset dose range is selectively implanted in a portion of the transition region and the terminal region to form a second conductivity type implantation region. S5. Activate the impurities in the device body prepared in step S4 through thermal processing, and form and etch a thick oxide layer on the upper surface of the first conductivity type epitaxial layer through thermal oxidation to distinguish the active region and the terminal region. S6. Based on step S5, a first type of conductivity impurity is implanted on the surface of the first conductivity type epitaxial layer, and then a gate oxide layer is formed by a dry oxidation process. Polysilicon is deposited on the upper surface of the gate oxide layer, and the polysilicon and the gate oxide layer are etched to form polysilicon layers of different sizes in the active region and the terminal region. S7. Based on step S6, implant impurities of the second conductivity type to form a body region, and then implant impurities of the first conductivity type to form the Nsource source region located in the active region and part of the terminal region. S8. Based on step S7, deposit an interlayer dielectric layer, etch out the contact hole area, and implant impurities of the second conductivity type to form a low-resistance contact hole. Then, deposit metal and pattern the metal to distinguish the active area metal and the gate metal. After that, prepare and thin the back metal to obtain the back metal.

[0007] Compared with the prior art, the beneficial effects of the present invention are as follows: The superjunction device termination structure proposed in this invention does not perform first conductivity type impurity implantation at the body region where the transition region and termination region meet, and therefore does not form an Nsource source region at the body region where the active region and transition region meet. Thus, when the device is in an avalanche state, the failure risk in the transition region can be reduced. Furthermore, the termination structure of the superjunction device proposed in this invention divides the second conductivity type doped pillars in the transition region and termination region into upper and lower parts of different sizes and horizontal staggered arrangement. The size of the second conductivity type doped pillar on the side of the termination region farther from the transition region is smaller than the size of the second conductivity type doped pillar on the side closer to the transition region. Additionally, a second conductivity type impurity implantation region is formed in a portion of the termination region. This allows for adjustment of the electric field distribution in the termination region, optimization of the device termination structure performance, improvement of the overall termination utilization rate, and reduction of cost.

[0008] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0009] Figure 1 This is a schematic flowchart of the method for fabricating the terminal structure of the superjunction device provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the side cross-section of the device structure prepared in step S1 according to the embodiment of the present invention; Figure 3 This is a schematic diagram of the side cross-section of the device structure prepared in step S2 according to the embodiment of the present invention; Figure 4 This is a schematic diagram of the side cross-section of the device structure prepared in step S3 according to the embodiment of the present invention; Figure 5This is a schematic diagram of the side cross-section of the device structure prepared in step S4 of the present invention. Figure 6 This is a schematic diagram of the side cross-section of the device structure prepared in step S5 of the present invention; Figure 7 This is a schematic diagram of the side cross-section of the device structure prepared in step S6 of the present invention; Figure 8 This is a schematic diagram of the side cross-section of the device structure prepared in step S7 of the present invention; Figure 9 This is a schematic diagram of the side cross-section of the device structure prepared in step S8 of the present invention. Detailed Implementation

[0010] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0011] In a first aspect, embodiments of the present invention provide a method for fabricating a terminal structure of a superjunction device. Please refer to... Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for fabricating a terminal structure of a superjunction device according to an embodiment of the present invention. Figure 1 As shown, the preparation method includes: S1. An epitaxial layer of the first conductivity type is grown on a substrate layer of the first conductivity type with doping, and a first conductivity type impurity is implanted. A second conductivity type impurity is implanted using a first photomask, and an active region, a transition region and a termination region are formed at the same time.

[0012] For example, Figure 2 This is a schematic diagram of the side cross-section of the device structure prepared in step S1. In this diagram, 2 represents a doped substrate layer of the first conductivity type, 3 represents a first conductivity type epitaxial layer, and 4 represents a second conductivity type doped pillar formed in step S1 by implanting a second conductivity type impurity into the first conductivity type epitaxial layer 3. The blank area between every two adjacent second conductivity type doped pillars 4 is a first conductivity type doped pillar. 1a represents the active region, 1b represents the transition region, and 1c represents the termination region. In this invention, the first conductivity type is N-type, and the second conductivity type is P-type. This invention does not specifically limit the first and second conductivity type impurities.

[0013] It should be noted that the first conductivity type substrate 2 can be a silicon substrate, and the first conductivity type substrate 2 is a heavily doped first conductivity type substrate, wherein heavy doping means that the impurity concentration in the silicon single crystal is greater than 10¹. 8 / cm -3 One atom.

[0014] In step S1, the same photolithography size is used when implanting the second conductivity type impurity in region 1a. However, from region 1b to region 1c, the photolithography size changes in a gradual decreasing manner from left to right. This results in a gradual distribution of the second conductivity type doped pillars 4 along the horizontal direction. It should be noted that the photolithography size from region 1b to region 1c can be based on the photolithography size of the second conductivity type impurity implanted in region 1a, decreasing gradually from left to right; or it can be based on a photolithography size larger than the photolithography size of the second conductivity type impurity implanted in region 1a, decreasing gradually from left to right. For example, as shown... Figure 1 As shown, along the horizontal direction, the widths of the second conductivity type doped pillars 4 in region 1a are the same, the widths of the three second conductivity type doped pillars 4 in region 1b are the same, and the widths of the three second conductivity type doped pillars 4 in region 1b are greater than the widths of the second conductivity type doped pillars 4 in region 1a. Furthermore, the widths of the three second conductivity type doped pillars 4 in region 1b are greater than the widths of the 14 second conductivity type doped pillars 4 in region 1c. The widths of the 14 second conductivity type doped pillars 4 in region 1c also decrease from left to right; the first three second conductivity type doped pillars 4 have the same width, the middle five have the same width, and the last six have the same width. In summary, as... Figure 1 As shown, the width distribution of the 17 second conductivity type doped pillars 4 in regions 1b and 1c, from left to right, is: 3, 3, 5, 6. It should be noted that... Figure 1 The number of second conductivity type doped pillars in each region shown, as well as the specific distribution of the width of the second conductivity type doped pillars, are preferred exemplary illustrations. These can vary with the size of the device, and the present invention does not specifically limit them.

[0015] S2. Based on step S1, continue to grow the first conductivity type epitaxial layer, implant the first conductivity type impurity, and implant the second conductivity type impurity using the first photomask. Then, repeat step S2N times to form the first conductivity type doped pillar and the second conductivity type doped pillar in the active region, as well as the lower part of the first conductivity type doped pillar and the lower part of the second conductivity type doped pillar in the transition region and the terminal region.

[0016] In step S2, the same photolithography size is used when implanting the second type of conductivity impurity in region 1a, and the photolithography size used in regions 1b and 1c gradually decreases from left to right in the direction from region 1b to region 1c.

[0017] It should be noted that N is a positive integer greater than 1. For example, N can be 4, and the value of N is determined by the size of the device; this invention does not impose specific limitations on this. Figure 3 This is a schematic diagram of the side cross-section of the device structure prepared in step S2. For example... Figure 3 As shown, after performing step S2 five times based on step S1, alternating first and second conductivity type doped pillars along the horizontal direction can be formed. The first and second conductivity type doped pillars in region 1b can be referred to as the lower part of the first conductivity type doped pillar and the lower part of the second conductivity type doped pillar in region 1b; similarly, the first and second conductivity type doped pillars in region 1c can be referred to as the lower part of the first conductivity type doped pillar and the lower part of the second conductivity type doped pillar in region 1c.

[0018] S3. Based on step S2, grow the first conductivity type epitaxial layer again and implant the first conductivity type impurity. Use the second photomask to implant the second conductivity type impurity. Then, repeat step S3 once more to continue forming the first conductivity type doped pillar and the second conductivity type doped pillar in the active region, as well as the upper part of the first conductivity type doped pillar and the upper part of the second conductivity type doped pillar in the transition region and the terminal region. The first conductivity type doped pillar and the second conductivity type doped pillar are alternately distributed in the horizontal direction and have different sizes. Furthermore, the upper part of the second conductivity type doped pillar and the lower part of the second conductivity type doped pillar are staggered in the horizontal direction.

[0019] Here, the width of the upper second conductivity type doped pillar is different from the width of the lower second conductivity type doped pillar, and the widths of both the upper and lower second conductivity type doped pillars gradually change along the horizontal direction from left to right; specifically, the widths of both the upper and lower second conductivity type doped pillars decrease from left to right. Furthermore, the width of the formed upper second conductivity type doped pillar varies based on 1 / 2 or 1 / 3 of the width of the lower second conductivity type doped pillar. The number of upper second conductivity type doped pillars is grouped the same as that of the lower second conductivity type doped pillars. The upper second conductivity type doped pillars in regions 1b and 1c are staggered at the top of the lower second conductivity type doped pillars, with two upper second conductivity type doped pillars distributed on either side of the top of each lower second conductivity type doped pillar. For example, Figure 4 This is a schematic diagram of the side cross-section of the device structure prepared in step S3. For example... Figure 4 As shown, 5 represents the upper part of the second conductivity type doped pillar. From Figure 4As can be seen, in regions 1a, 1b, and 1c, the first conductivity type doped pillars and the second conductivity type doped pillars are alternately distributed horizontally, and their widths are different. Furthermore, in regions 1b and 1c, the upper portion of the second conductivity type doped pillars 5 and the lower portion of the second conductivity type doped pillars 4 are staggered horizontally. Each lower portion of the second conductivity type doped pillar has one upper portion of the second conductivity type doped pillar distributed on each of its top left and right sides. The width of each lower portion of the second conductivity type doped pillar is greater than the width of the upper portion of the second conductivity type doped pillar distributed on each of its top left and right sides; for example, the width of each upper portion of the second conductivity type doped pillar is 1 / 2 or 1 / 3 of the width of the lower portion of the second conductivity type doped pillar below it. (Continue to refer to...) Figure 4 Two upper second-conductivity type doped pillars distributed on the left and right sides of the top of a lower second-conductivity type doped pillar constitute a group of upper second-conductivity type doped pillars. The number of lower second-conductivity type doped pillars is the same as the number of upper second-conductivity type doped pillar groups. For example, there are 14 lower second-conductivity type doped pillars and 14 groups of upper second-conductivity type doped pillars in region 1c. The 14 lower second-conductivity type doped pillars and the 14 groups of upper second-conductivity type doped pillars are in a one-to-one correspondence.

[0020] In this invention, throughout the entire process from steps S1 to S3, the dosage of the second conductivity type impurity is different each time it is injected, but the energy is the same. Furthermore, from the first injection of the second conductivity type impurity to the last injection, the injection dosage of the second conductivity type impurity gradually increases. For example, when N is 4, a total of 8 injections of the second conductivity type impurity are performed throughout the entire process from steps S1 to S3. The dosage of these 8 injections is different, but the energy is the same, and from the 1st to the 8th injection, the injection dosage changes in a gradually increasing manner.

[0021] S4. Based on step S3, a first conductivity type epitaxial layer is grown again and a first conductivity type impurity is implanted. A second conductivity type impurity within a preset dose range is selectively implanted in a portion of the transition region and the terminal region to form a second conductivity type implantation region.

[0022] Specifically, based on step S3, a first conductivity type epitaxial layer is grown again and a first conductivity type impurity is implanted; a second conductivity type impurity is implanted on the surface of a portion of the first conductivity type epitaxial layer in regions 1b and 1c, forming a second conductivity type doped implantation region that simultaneously covers the top of the upper portion of the second conductivity type doped pillars on the side of region 1b closest to region 1c and the top of the upper portion of the second conductivity type doped pillars on the side of region 1c closest to region 1b; and a second conductivity type impurity is implanted on the surface of the first conductivity type epitaxial layer in the middle portion of region 1c, forming multiple second conductivity type doped implantation regions that respectively cover the top of each upper portion of the second conductivity type doped pillars in the middle portion of region 1c, while no low-concentration second conductivity type impurity implantation is performed in the peripheral region of region 1c. It should be noted that the formed second conductivity type doped implantation regions are low-concentration second conductivity type implantation regions, and the implantation dose of the second conductivity type impurity within the second conductivity type implantation regions ranges from 1.0e12 to 2.5e12 cm⁻¹. -2 .

[0023] For example, Figure 5 This is a schematic diagram of the side cross-section of the device structure prepared in step S4. For example... Figure 5 As shown, the second conductivity type doped implantation region 6 simultaneously covers the top of one upper portion of the second conductivity type doped pillar 5 on the side of region 1b near region 1c, as well as the tops of six upper portions of the second conductivity type doped pillar 5 on the side of region 1c near region 1b. Furthermore, the top of each upper portion of the second conductivity type doped pillar 5 in the middle portion of region 1c is also covered by a second conductivity type doped implantation region 6. However, the tops of the six upper portions of the second conductivity type doped pillar 5 on the side of region 1c away from region 1b are not covered by the second conductivity type doped implantation region 6. It should be noted that... Figure 5 This is merely an illustrative example. The number of second conductivity type dopants 5 in the upper part of region 1c that is not covered by the second conductivity type doping implantation region 6 on the side away from region 1b can also be 2, 4 or 8, etc. The present invention does not specifically limit the specific number.

[0024] S5. The impurities in the device body prepared in step S4 are activated by thermal processing, and a thick oxide layer is formed and etched on the upper surface of the first conductivity type epitaxial layer by thermal oxidation to distinguish the active region and the terminal region.

[0025] Specifically, impurities within the device are activated through a thermal process, and a thick oxide layer is formed on the upper surface of the first conductivity type epitaxial layer 3 of the device prepared in S4 using a thermal oxidation process. For example, the thickness of the thick oxide layer ranges from 1.2 to 1.8 μm. Subsequently, the thick oxide layer in regions 1a, part of 1b, and part of the peripheral areas of region 1c is etched away using a photolithography process. For example, Figure 6This is a schematic diagram of the side cross-section of the device structure prepared in step S5, as shown below. Figure 6 As shown, 7 represents a thick oxide layer.

[0026] S6. Based on step S5, first conductivity type impurities are implanted on the surface of the first conductivity type epitaxial layer, and then a gate oxide layer is formed by a dry oxidation process. Polysilicon is deposited on the upper surface of the gate oxide layer, and the polysilicon and the gate oxide layer are etched to form polysilicon layers of different sizes in the active region and the terminal region.

[0027] Specifically, a predetermined amount of first-conductivity type impurities is implanted onto the surface of the first-conductivity type epitaxial layer 3 of the device prepared in step S5. Specifically, the implantation dose ranges from 1.0e12 to 2.0e12 cm. -2 Then, a gate oxide layer is formed using a dry oxidation process. Next, polysilicon is deposited on the upper surface of the gate oxide layer. Subsequently, a portion of the polysilicon and gate oxide layer in the peripheral areas of regions 1a, 1b, and 1c are etched away using a photolithography process to form polysilicon layers of different sizes in regions 1a, 1b, and 1c. Figure 7 This is a schematic diagram of the side cross-section of the device structure prepared in step S6, as shown below. Figure 7 As shown, 8 represents the gate oxide layer, and 9-1, 9-2, and 9-3 all represent polysilicon layers. Specifically, 9-1 represents the polysilicon layer in region 1a, 9-2 represents the polysilicon layer in region 1b and at the boundary with region 1c, and 9-3 represents the polysilicon layer in the peripheral region of region 1c. (Continue to refer to...) Figure 7 The two polysilicon layers 9-1 have the same width, and the width of polysilicon layer 9-2 is greater than the width of polysilicon layer 9-1. Polysilicon layer 9-2 is used to connect to the gata electrode.

[0028] S7. Based on step S6, implant impurities of the second conductivity type to form a body region, and then implant impurities of the first conductivity type to form the Nsource source region located in the active region and part of the terminal region.

[0029] Specifically, using a self-aligned implantation method, second conductivity type impurities are implanted into the unmasked area of ​​the surface of the first conductivity type epitaxial layer 3 of the device prepared in step S5, forming body regions located in the peripheral regions of region 1a, part of region 1b, and region 1c, respectively. Then, first conductivity type impurities are implanted at the body region locations in region 1a and the body region locations in the peripheral regions of region 1c to form Nsource source regions. However, first conductivity type impurities are not implanted in the body region portion of region 1b near region 1a and the middle body region portion of region 1b, so that Nsource source regions are not formed at the body region location where region 1a and region 1b intersect. For example, Figure 8 This is a schematic diagram of the side cross-section of the device structure prepared in step S7, as shown below. Figure 8As shown, 10 represents the body region and 11 represents the Nsource source region. It should be noted that step S7 injects a high concentration of first conductivity type impurities, with the injection dose ranging from 3e15 to 5e15 cm⁻¹. -2 .

[0030] S8. Based on step S7, deposit an interlayer dielectric layer, etch out the contact hole area, and implant impurities of the second conductivity type to form a low-resistance contact hole. Then, deposit metal and pattern the metal to distinguish the active area metal and the gate metal. After that, prepare and thin the back metal to obtain the back metal.

[0031] Specifically, an interlayer dielectric layer is deposited on the upper surface of the device prepared in step S7, and the interlayer dielectric layer is etched to etch out the contact hole region. Then, a high concentration of second conductivity type impurities is implanted into the unmasked area. The implantation dose of the high concentration of second conductivity type impurities ranges from 1.0e15 to 2.5e15 cm⁻¹. -2 To form low-resistance contact holes in the etched contact hole region, metal is deposited and patterned to distinguish the active metal and gate metal. Finally, a metal layer is deposited on the back side of the doped first conductivity type substrate 2, and the metal layer is thinned to obtain the back metal. In this way, a superjunction device (i.e., a terminal device of a superjunction MOSFET structure) can be fabricated, and the side cross-sectional view of the terminal structure of the superjunction device is shown below. Figure 9 As shown, 12 represents the interlayer dielectric layer, 13 represents the active region metal, 14 represents the metal connected to the gate electrode, and the back metal is not shown. Figure 9 middle.

[0032] For the terminal structure of the superjunction device prepared by the method proposed in this invention, since no Nsource source region is formed at the body region where the 1a and 1b regions meet, the avalanche current flows out from the contact hole when the device is in an avalanche state, which can reduce the failure risk of the device in the 1b region. The distribution of the second conductivity type doped pillars in the middle part of the 1b and 1c regions and the low concentration of second conductivity type impurity implantation region covering part of the 1b region can ensure the withstand voltage capability of the device in the Nrich direction. In addition, since the size of the second conductivity type doped pillars on the outside of the 1c region gradually decreases and the upper part of the second conductivity type doped pillars are subdivided and staggered along the horizontal direction, the body electric field on the outside of the terminal can converge towards the inside of the terminal, making the surface electric field distribution more uniform, thereby improving the utilization rate of the device terminal. In particular, for the Prich direction, the electric field will more easily converge towards the inside of the terminal, thereby reducing the electric field on the outside of the terminal and improving the device performance. Therefore, when manufacturing high-voltage or ultra-high-voltage superjunction devices, under the same withstand voltage capability, compared with traditional superjunction structures, the device structure prepared by the above-mentioned preparation method of this invention can improve device performance while reducing terminal size and chip area, thereby reducing costs.

[0033] In the description of this invention, it should be understood that the terms "width", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0036] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A termination structure for a superjunction device, characterized in that, include: An active region, a transition region, and a terminal region are distributed sequentially along a horizontal direction, wherein the active region, the transition region, and the terminal region each have a first conductivity type doped pillar and a second conductivity type doped pillar; In this configuration, no first conductivity type impurities are implanted at the body region where the transition region and the terminal region intersect. Both the first conductivity type doped pillars and the second conductivity type doped pillars in the transition region and the terminal region are vertically divided into upper and lower portions. Horizontally, the upper and lower portions of the second conductivity type doped pillars are staggered. Furthermore, along the horizontal direction, the size of the second conductivity type doped pillar on the side of the terminal region furthest from the transition region is smaller than the size of the second conductivity type doped pillar on the side of the terminal region closest to the transition region. The middle portion of the terminal region and the upper portion of the second conductivity type doped pillars near the transition region are both covered with second conductivity type doped implantation regions.

2. The termination structure of the superjunction device according to claim 1, characterized in that, Along the horizontal direction, the size of the upper part of the second conductivity type doped pillar is different from that of the lower part of the second conductivity type doped pillar, and the size of both the upper and lower parts of the second conductivity type doped pillar exhibits a gradual distribution along the horizontal direction.

3. The termination structure of the superjunction device according to claim 2, characterized in that, Along the horizontal direction from left to right, the size of both the upper and lower second conductivity type doped pillars decreases from large to small.

4. The termination structure of the superjunction device according to claim 2, characterized in that, Each lower portion of the second conductivity type doped pillar has an upper portion of the second conductivity type doped pillar distributed on its left and right sides at the top, and the size of each lower portion of the second conductivity type doped pillar is larger than the size of the upper portion of the second conductivity type doped pillar distributed on its left and right sides at the top.

5. The termination structure of the superjunction device according to claim 4, characterized in that, Two upper second-conductivity type doped pillars distributed on the left and right sides of the top of a lower second-conductivity type doped pillar constitute a group of upper second-conductivity type doped pillars, wherein the number of lower second-conductivity type doped pillars is the same as the number of upper second-conductivity type doped pillar groups.

6. The termination structure of the superjunction device according to claim 1, characterized in that, The top of the upper portion of the second conductivity type doped pillars on the side of the terminal region closest to the transition region and the space between adjacent upper portion second conductivity type doped pillars are covered with a second conductivity type doped injection region; the top of each upper portion of the second conductivity type doped pillar in the middle portion of the terminal region is covered with a second conductivity type doped injection region, but the space between two adjacent upper portion second conductivity type doped pillars is not covered with a second conductivity type doped injection region. The implantation dose range for the second conductivity type doped implantation region is 1.0e¹² to 2.5e¹² cm⁻¹. -2 .

7. A method for fabricating a terminal structure of a superjunction device, characterized in that, The method for fabricating a termination structure for a superjunction device as described in any one of claims 1-6 includes: S1. A first conductivity type epitaxial layer (3) is grown on a first conductivity type substrate layer (2) with doping, and first conductivity type impurities are implanted. Second conductivity type impurities are implanted using a first photomask, and an active region, a transition region and a terminal region are formed at the same time. S2. Based on step S1, continue to grow the first conductivity type epitaxial layer (3), implant the first conductivity type impurity, use the first photomask to implant the second conductivity type impurity, and then repeat step S2 N times to form the first conductivity type doped pillar and the second conductivity type doped pillar in the active region, as well as the lower part of the first conductivity type doped pillar and the lower part of the second conductivity type doped pillar in the transition region and the terminal region (4). S3. Based on step S2, grow the first conductivity type epitaxial layer (3) again and implant the first conductivity type impurity. Use the second photomask to implant the second conductivity type impurity. Then, repeat step S3 once more to continue forming the first conductivity type doped pillar and the second conductivity type doped pillar in the active region, and to form the upper part of the first conductivity type doped pillar and the upper part of the second conductivity type doped pillar (5) in the transition region and the terminal region. The first conductivity type doped pillar and the second conductivity type doped pillar are alternately distributed along the horizontal direction and have different sizes. Furthermore, the upper part of the second conductivity type doped pillar and the lower part of the second conductivity type doped pillar are staggered along the horizontal direction. S4. Based on step S3, grow a first conductivity type epitaxial layer (3) again and inject a first conductivity type impurity, and selectively inject a second conductivity type impurity within a preset dose range into a portion of the transition region and the terminal region to form a second conductivity type injection region (6). S5. The impurities in the device body prepared in step S4 are activated by thermal process treatment, and a thick oxide layer (7) is formed and etched on the upper surface of the first conductivity type epitaxial layer (3) by thermal oxidation to distinguish the active region and the terminal region. S6. Based on step S5, first conductivity type impurities are implanted on the surface of the first conductivity type epitaxial layer (3), and then a gate oxide layer (8) is formed by dry oxidation process. Polysilicon is deposited on the surface of the gate oxide layer (8), and the polysilicon and the gate oxide layer (8) are etched to form polysilicon layers (9) of different sizes in the active region and the terminal region. S7. Based on step S6, implant impurities of the second conductivity type to form a body region (10), and then implant impurities of the first conductivity type to form an Nsource source region (11) located in the active region and part of the terminal region. S8. Based on step S7, deposit an interlayer dielectric layer (12), etch out the contact hole area, and implant impurities of the second conductivity type to form a low resistance contact hole. Then deposit metal and pattern the metal to distinguish the active area metal (13) and the gate metal (14). After that, prepare and thin the back metal to obtain the back metal (1).

8. The method for fabricating the terminal structure of the superjunction device according to claim 7, characterized in that, In step S1, the same photolithography size is used when implanting the second type of conductivity impurity in the active region, while when implanting the second type of conductivity impurity in the transition region and the terminal region, the photolithography size used from the transition region to the terminal region is based on the photolithography size used in the active region and gradually decreases from left to right. In step S2, the same photolithography size is used when implanting the second type of conductivity impurity in the active region, and when implanting the second type of conductivity impurity in the transition region and the terminal region, the photolithography size used gradually decreases from left to right in the direction from the transition region to the terminal region.

9. The method for fabricating the terminal structure of the superjunction device according to claim 7, characterized in that, During steps S1 to S3, the dosage of the second conductivity type impurity is different each time it is injected, but the energy is the same. Furthermore, from the first injection of the second conductivity type impurity to the last injection of the second conductivity type impurity, the injection dosage of the second conductivity type impurity gradually increases.

10. The method for fabricating the terminal structure of the superjunction device according to claim 7, characterized in that, S4 specifically includes: S41. Based on step S3, grow the first conductivity type epitaxial layer (3) again and implant the first conductivity type impurity; S42. On the surface of the first conductivity type epitaxial layer (3) in the transition region and the terminal region, a second conductivity type impurity is implanted to form a second conductivity type doping implantation region (6) that simultaneously covers the top of the upper part of the second conductivity type doped pillar (5) on the side of the transition region near the terminal region and the top of the upper part of the second conductivity type doped pillar (5) on the side of the terminal region near the transition region; and on the surface of the first conductivity type epitaxial layer (3) in the middle part of the terminal region, a second conductivity type impurity is implanted to form a plurality of second conductivity type doping implantation regions (6) that respectively cover the top of each upper part of the second conductivity type doped pillar (5) in the middle part of the terminal region.

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