Transistor, electronic device and method for manufacturing a transistor

Abstract

This invention provides a transistor, an electronic device, and a method for fabricating a transistor, comprising: a gate, a gate dielectric layer, a ferroelectric material layer, a channel layer, and an electrode layer, wherein the gate, gate dielectric layer, ferroelectric material layer, and channel layer are sequentially stacked; the electrode layer includes: a first source, a first drain, a second source, and a second drain, respectively connected to the channel layer; the line connecting the first source and the first drain is a first reference line, and the line connecting the second source and the second drain is a second reference line; the first reference line and the second reference line intersect each other; the overlap length of the projection of the first reference line and the ferroelectric material layer onto the gate dielectric layer is greater than the overlap length of the projection of the second reference line and the ferroelectric material layer onto the gate dielectric layer. By relying on the arrangement design of the ferroelectric material layer, the dependence on anisotropic materials for transistor anisotropy is eliminated, thereby ensuring high stability and electrical performance of the transistor and improving its electrical anisotropy.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more particularly to a transistor, electronic device, and method for manufacturing a transistor. Background Technology

[0002] In transistors, intrinsically anisotropic two-dimensional semiconductor materials are typically used as the channel layer to achieve electrical anisotropy. With two sets of source and drain electrodes positioned differently, the conductivity of the intrinsically anisotropic two-dimensional semiconductor material varies along different directions, resulting in different resistances in the corresponding regions of each source and drain electrode, and consequently, different output signals. However, most existing intrinsically anisotropic two-dimensional semiconductor materials typically have low anisotropy ratios, resulting in smaller differences in the signals output through different source and drain electrodes. Materials with high anisotropy ratios are often prone to oxidation and degradation, while more stable materials often suffer from lower on / off ratios and carrier mobility. Therefore, limited by the material properties of existing intrinsically anisotropic two-dimensional semiconductor materials, it is difficult to simultaneously achieve optimal performance in transistors across the three dimensions of anisotropy ratio, stability, and electrical properties. Summary of the Invention

[0003] This invention provides a transistor, an electronic device, and a method for fabricating a transistor, which not only ensures the transistor has high stability and electrical performance, but also improves the anisotropy ratio of the transistor.

[0004] In a first aspect, embodiments of the present invention provide a transistor, comprising: a gate, a gate dielectric layer, a ferroelectric material layer, a channel layer, and an electrode layer, wherein the gate, the gate dielectric layer, the ferroelectric material layer, and the channel layer are stacked sequentially; the electrode layer comprises: a first source, a first drain, a second source, and a second drain respectively connected to the channel layer, wherein the line connecting the first source and the first drain is a first reference line, the line connecting the second source and the second drain is a second reference line, and the first reference line and the second reference line intersect each other; the overlap length between the first reference line and the projection of the ferroelectric material layer on the gate dielectric layer is a first length, and the overlap length between the second reference line and the projection of the ferroelectric material layer on the gate dielectric layer is a second length, wherein the first length is greater than the second length.

[0005] In a second aspect, embodiments of the present invention provide an electronic device including the transistor mentioned in the first aspect above.

[0006] Thirdly, embodiments of the present invention provide a method for fabricating a transistor, comprising: A gate is formed; a gate dielectric layer is formed on the gate; a ferroelectric material layer and a channel layer are formed on the gate dielectric layer, the channel layer covering the ferroelectric material layer; a first source, a first drain, a second source, and a second drain are formed on the second surface of the gate dielectric layer; the first source, the first drain, the second source, and the second drain are all connected to the channel layer; the line connecting the first source and the first drain is a first reference line, the line connecting the second source and the second drain is a second reference line, and the first reference line and the second reference line intersect each other; the distance at which the first reference line and the projection of the ferroelectric material layer on the gate dielectric layer overlap is a first distance, the distance at which the second reference line and the projection of the ferroelectric material layer on the gate dielectric layer overlap is a second distance, and the first distance is greater than the second distance.

[0007] The beneficial effects of this invention are as follows: This invention provides a transistor, electronic device, and a method for fabricating a transistor. A ferroelectric material layer is disposed between the channel layer and the gate dielectric layer. Since the polarized ferroelectric material layer can consume the carriers in the overlapping channel layer or induce the enrichment of carriers in the overlapping channel layer, the conductivity difference between the channel layer in the overlapping region and the channel layer in other regions is large. Therefore, by relying on the arrangement design of the ferroelectric material layer, the resistance difference of the transistor in different directions can be large. For example, the overlap length of the projection of the first reference line and the ferroelectric material layer on the gate dielectric layer is the first length, and the overlap length of the projection of the second reference line and the ferroelectric material layer on the gate dielectric layer is the second length. When the first length is greater than the second length, the difference between the resistance between the first source and the first drain and the resistance between the second source and the second drain can be set to be large. Compared to existing technologies where intrinsically anisotropic two-dimensional semiconductors exhibit resistance differences along different directions due to varying carrier mobility, this new approach breaks away from the conventional methods for achieving resistance differences in different directions. It employs a novel approach that not only achieves resistance differences across directions but also amplifies these differences through the arrangement of ferroelectric material layers, thereby improving the transistor's anisotropy ratio. Furthermore, since electrical anisotropy is achieved through the arrangement of ferroelectric material layers, independent of the channel layer's material properties, the channel layer can be made of a more stable material with superior electrical properties, ensuring the transistor exhibits high stability and electrical performance. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a transistor structure provided in an embodiment of the present invention; Figure 2 This is a partial structural diagram of a transistor provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another partial structure of a transistor provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a transistor fabrication method provided in an embodiment of the present invention; Figure 5 This is a test diagram of the anisotropy ratio provided in an embodiment of the present invention; Figure 6 This is a test diagram of another anisotropy ratio provided in an embodiment of the present invention. Detailed Implementation

[0009] The specific embodiments of a transistor, electronic device, and transistor fabrication method provided by the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0010] This invention provides a transistor 1, such as Figure 1 As shown, the structure may include: a gate 20, a gate dielectric layer 30, a ferroelectric material layer 40, a channel layer 50, and an electrode layer 60. The gate 20, the gate dielectric layer 30, the ferroelectric material layer 40, and the channel layer 50 are stacked sequentially. The electrode layer 60 includes: a first source 61, a first drain 62, a second source 63, and a second drain 64, which are respectively connected to the channel layer 50. The line connecting the first source 61 and the first drain 62 is a first reference line L1, and the line connecting the second source 63 and the second drain 64 is a second reference line L2. The first reference line L1 and the second reference line L2 intersect each other. The overlap length of the projection of the first reference line L1 and the ferroelectric material layer 40 onto the gate dielectric layer 30 is a first length d1, and the overlap length of the projection of the second reference line L2 and the ferroelectric material layer 40 onto the gate dielectric layer 30 is a second length d2. The first length d1 is greater than the second length d2.

[0011] When the first reference line L1 and the second reference line L2 intersect each other, the term "intersect each other" can mean either perpendicular or not perpendicular, and is not limited here.

[0012] In this embodiment, the ferroelectric material layer 40 can regulate the carrier concentration in the overlapping channel layer 50. Therefore, the carrier concentration in the channel layer 50 regulated by the ferroelectric material layer 40 differs from that in the unregulated region, resulting in different conductivity and resistance. In the above embodiment, the first length d1 is greater than the second length d2, so the area of ​​the channel layer 50 between the first source 61 and the first drain 62 that is regulated by the ferroelectric material layer 40 is larger, while the area of ​​the channel layer 50 between the second source 63 and the second drain 64 that is regulated by the ferroelectric material layer 40 is smaller. Therefore, the resistance between the first source 61 and the first drain 62 is different from the resistance between the second source 63 and the second drain 64, achieving electrical anisotropy in transistor 1.

[0013] Furthermore, a ferroelectric material layer is disposed between the channel layer and the gate dielectric layer. Since the polarized ferroelectric material layer can consume the charge carriers in the channel layer that overlaps with it, or induce the enrichment of charge carriers in the channel layer that overlaps with it, the conductivity of the channel layer in the overlapping region with the ferroelectric material layer is significantly different from that of the channel layer in other regions. Therefore, by relying on the arrangement design of the ferroelectric material layer, the resistance of the transistor can be significantly different in different directions. For example, the overlap length of the projection of the first reference line and the ferroelectric material layer on the gate dielectric layer is the first length, and the overlap length of the projection of the second reference line and the ferroelectric material layer on the gate dielectric layer is the second length. When the first length is greater than the second length, the difference between the resistance between the first source and the first drain and the resistance between the second source and the second drain can be set to be larger. Compared to existing technologies where intrinsically anisotropic two-dimensional semiconductors exhibit resistance differences along different directions due to varying carrier mobility, this new approach breaks away from the conventional methods for achieving resistance differences in different directions. It employs a novel approach that not only achieves resistance differences across directions but also amplifies these differences through the arrangement of ferroelectric material layers, thereby improving the transistor's anisotropy ratio. Furthermore, since electrical anisotropy is achieved through the arrangement of ferroelectric material layers, independent of the channel layer's material properties, the channel layer can be made of a more stable material with superior electrical properties, ensuring the transistor exhibits high stability and electrical performance.

[0014] It should be understood that existing intrinsically anisotropic semiconductor materials, due to the anisotropy of their crystal structure, result in anisotropy of their band structure, leading to different carrier mobilities along different directions. This manifests macroscopically as anisotropy in the material's conductivity. However, since the difference in carrier mobility along different directions is limited, the effectiveness of achieving electrical anisotropy in transistors relying on intrinsically anisotropic materials is limited. As shown in Table 1 below, the anisotropy ratios of transistors made from commonly used intrinsically anisotropic semiconductor materials are all within the range of 2 to 15. In other words, for transistors made using the material properties of existing intrinsically anisotropic semiconductors, the same current input passing through the source and drain electrodes arranged in different directions will result in output currents that differ by at most a factor of 15.

[0015] Table 1

[0016] The ferroelectric material layer provided in this embodiment of the invention can consume the charge carriers in the overlapping channel layer after polarization. If the charge carriers in the channel layer are depleted, a near-insulating effect can be achieved. Therefore, the resistance of the channel layer in the overlapping region with the ferroelectric material layer differs significantly from the resistance of the channel layer in other regions. The anisotropy ratio varies depending on the shape and arrangement of the ferroelectric material layer. In some embodiments, as shown in the last row of Table 1 above, transistors fabricated using the principle of controlling the channel layer with a ferroelectric material layer can achieve an anisotropy ratio of 200, which is far greater than the anisotropy ratio achievable by transistors fabricated with intrinsically anisotropic materials in Table 1 above. Therefore, using a ferroelectric material layer to control the channel layer can enable transistors to obtain a superior anisotropy ratio.

[0017] In some embodiments, the transistor is fabricated on a substrate. When the substrate is made of silicon, the substrate is a silicon substrate. When a silicon oxide layer is formed on the surface of the silicon substrate, the silicon oxide layer can serve as a gate dielectric layer, and the silicon substrate itself can serve as the gate. Of course, the substrate can also be made of other non-conductive materials, in which case the gate can be located between the substrate and the gate dielectric layer.

[0018] In some embodiments, taking the first source as an example, a portion of the first source is located above the channel layer, while the remaining portion of the first source may be located above the gate dielectric layer, such as... Figure 1 As shown; or, the entire first source is located above the channel, but no diagram is provided. The first drain, second source, and second drain can also be configured similarly, which will not be detailed here.

[0019] In some embodiments, the channel layer is made of an intrinsically anisotropic semiconductor material.

[0020] In the above embodiments of the present invention, by setting a ferroelectric material layer overlapping with the channel layer, intrinsic anisotropic semiconductor materials are no longer required to achieve electrical anisotropy in the transistor, thus removing material limitations. Therefore, preferably, the channel layer can be made of an intrinsic anisotropic semiconductor to obtain a higher on / off ratio and carrier mobility. Furthermore, since research on intrinsic anisotropic semiconductor materials is relatively comprehensive, there are many materials to choose from. Therefore, selection and combination can be made according to actual conditions to obtain better transistor performance.

[0021] In some embodiments, such as Figure 2 As shown, the gate 20 is used to: apply a first gate voltage pulse V1, making the polarization direction of the ferroelectric material layer 40 a first direction F1, and adjusting the resistance of the overlapping region of the channel layer 50 with the ferroelectric material layer 40 to a first resistance; as shown Figure 3 As shown, a second gate voltage pulse V2 is applied, causing the polarization direction of the ferroelectric material layer 40 to be the second direction F2, and the resistance of the overlapping region of the channel layer 50 with the ferroelectric material layer 40 is adjusted to the second resistance; the first resistance is less than the second resistance; the first direction F1 is the gate dielectric layer 30 ( Figure 2 and Figure 3 (Not shown in the image) points in the direction of the channel layer 50, and the second direction F2 is opposite to the first direction F1.

[0022] in, Figure 2 and Figure 3 for Figure 1 The diagram shows a partial structural schematic of the transistor along a cross-section of the first reference line L1.

[0023] It should be understood that the polarization direction of a ferroelectric material layer refers to the direction in which the charge centers in the ferroelectric material layer separate, for example, the polarization direction is the direction in which the separated negative charge points to the positive charge.

[0024] Among them, such as Figure 2 As shown, the first gate voltage pulse V1 can be a positive voltage. When the first gate voltage pulse V1 acts on the ferroelectric material layer 40, the ferroelectric material layer 40 is regulated by the first gate voltage pulse V1, and its polarization direction is the first direction F1. At this time, due to charge separation in the polarized ferroelectric material layer 40, positive charges accumulate on the surface of the ferroelectric material layer 40 away from the gate 20, thereby attracting electrons (negative charges) to accumulate in the channel layer 50, thus increasing the concentration of free electrons in the channel layer 50, which in turn increases the concentration of charge carriers in the channel layer 50. Consequently, the conductivity of the region overlapping with the ferroelectric material layer 40 in the channel layer 50 increases, and the resistance decreases. When the ferroelectric material layer 40 and the electrode layer 60 are arranged as follows... Figure 1As shown, the channel layer 50 between the first source 61 and the first drain 62 has a larger area controlled by the ferroelectric material layer 40, so its resistance is smaller. The channel layer 50 between the second source 63 and the second drain 64 has a smaller area controlled by the ferroelectric material layer 40, so its resistance is larger.

[0025] like Figure 3 As shown, the second gate voltage pulse V2 can be a negative voltage. When the second gate voltage pulse V2 acts on the ferroelectric material layer 40, the ferroelectric material layer 40 is regulated by the second gate voltage pulse V2, and its polarization direction is the second direction F2. At this time, due to the charge separation of the polarized ferroelectric material layer 40, negative charges accumulate on the surface of the ferroelectric material layer 40 away from the gate 20, thereby consuming electrons in the channel layer 50, thus reducing the concentration of free electrons in the channel layer 50, that is, reducing the concentration of charge carriers in the channel layer 50. Consequently, the conductivity of the region of the channel layer 50 overlapping with the ferroelectric material layer 40 decreases, and the resistance increases. When the ferroelectric material layer 40 and the electrode layer 60 are arranged as follows... Figure 1 As shown, the channel layer 50 between the first source 61 and the first drain 62 has a larger area controlled by the ferroelectric material layer 40, resulting in a larger resistance. The channel layer 50 between the second source 63 and the second drain 64 has a smaller area controlled by the ferroelectric material layer 40, resulting in a smaller resistance.

[0026] In summary, by inputting different gate voltage pulses into the gate 20, the resistance of the region overlapping the ferroelectric material layer 40 in the channel layer 50 can be increased or decreased, thereby forming different anisotropic characteristics. The resistance between the first source 61 and the first drain 62 can be greater than or less than the resistance between the second source 63 and the second drain 64. This achieves the anisotropy of the transistor.

[0027] In some embodiments, the non-intrinsic anisotropic semiconductor material includes at least one of molybdenum disulfide, tungsten disulfide, tungsten diselenide, molybdenum diselenide, indium selenide, or gallium selenide.

[0028] The materials mentioned above are all intrinsically anisotropic two-dimensional semiconductor materials, thus facilitating film transfer during transistor fabrication and experimentation. Of course, depending on the specific circumstances, the choice of materials is not limited to two-dimensional materials; other non-two-dimensional intrinsically anisotropic semiconductor materials can be selected, such as germanium and germanium-silicon. The choice of materials is also not limited to intrinsically anisotropic materials; intrinsically anisotropic semiconductor materials, such as rhenium disulfide and black phosphorus, can also be chosen. By combining the anisotropy of the channel layer itself with the ferroelectric material layer, a higher anisotropy ratio can be achieved.

[0029] In some embodiments, the material used to fabricate the ferroelectric material layer includes at least one of copper indium sulfide, copper chromium sulfide, indium α-selenide, hafnium dioxide, or polyvinylidene fluoride-based ferroelectric polymers.

[0030] It should be understood that the materials used to fabricate the aforementioned ferroelectric material layers all possess the characteristic of non-volatile polarization under gate voltage regulation, enabling the transistor to maintain this characteristic for a long time after being regulated by a specific gate voltage pulse and exhibiting specific anisotropic characteristics. Of course, the materials used to fabricate the ferroelectric material layers can also be other materials that can undergo non-volatile polarization under gate voltage regulation; this is not a limitation.

[0031] In some embodiments, such as Figure 1 As shown, the projection pattern of the ferroelectric material layer 40 onto the gate dielectric layer 30 is rectangular.

[0032] Thus, since the rectangle has a long side and a wide side, when the source and drain of transistor 1 are arranged in different directions, the length of the corresponding region in the channel layer 50 that is controlled by the ferroelectric material layer 40 is different, thereby realizing the anisotropy of transistor 1.

[0033] Of course, the projection pattern of the ferroelectric material layer 40 onto the gate dielectric layer 30 can also be elliptical or other patterns with different lengths along different directions, which is not limited here.

[0034] In some embodiments, such as Figure 1 As shown, the longer side of the projected pattern is parallel to the first reference line. Thus, the extension direction of the channel layer 50 between the first source 61 and the first drain 62 is consistent with the extension direction of the rectangular projection pattern, and the area of ​​the channel layer 50 controlled by the ferroelectric material layer 40 is larger; the extension direction of the channel layer 50 between the second source 63 and the second drain 64 is perpendicular to the extension direction of the rectangular projection pattern, and the area of ​​the channel layer 50 controlled by the ferroelectric material layer 40 is smaller, achieving a higher anisotropy ratio.

[0035] Of course, different anisotropy ratios can also be obtained by adjusting the extension direction of the ferroelectric layer 40 so that the long side of the projection pattern of the ferroelectric layer 40 on the gate dielectric layer 30 intersects with the first reference line L1, which is not limited here.

[0036] In some embodiments, such as Figure 1 As shown, the area of ​​the channel layer 50 is larger than the area of ​​the ferroelectric material layer 40.

[0037] Thus, the ferroelectric material layer 40 only regulates a portion of the channel layer 50, while the remaining portion of the channel layer 50 is not regulated by the ferroelectric material layer 40. This results in an uneven distribution of charge carriers in the channel layer 50. This uneven distribution of charge carriers causes different resistances when current flows through the channel layer 50 in different directions, achieving anisotropy of the transistor 1. Furthermore, because the area of ​​the channel layer 50 is larger than that of the ferroelectric material layer 40, the arrangement of the ferroelectric material layer 40 has a certain degree of freedom. The placement position of the ferroelectric material layer 40 can be changed during the fabrication of the transistor 1 according to actual conditions, thereby changing the anisotropy ratio of the transistor 1.

[0038] Based on the same inventive concept, this embodiment of the invention also provides an electronic device. The implementation principle of this electronic device is basically similar to that of the transistor described in the foregoing embodiments. The specific implementation method of this electronic device can be found in the specific embodiments of the foregoing transistor, and the repeated parts will not be described again.

[0039] Specifically, this invention provides an electronic device including a transistor as described in any of the embodiments above.

[0040] In some embodiments, anisotropic transistors are used in electronic devices, resulting in different signal processing weights for signals transmitted in different directions, and enabling parallel signal transmission and processing. Furthermore, due to the non-volatile storage characteristics of ferroelectric materials, the electronic devices can be pre-programmed without the need for an electric field, improving device stability and reducing power consumption. In summary, the electronic devices provided in these embodiments, by applying the transistors described above, ensure electrical performance and stability while improving anisotropy. These electronic devices can be used as synapses, and synapses fabricated from these devices can be applied in various fields such as neuromorphic computing, multi-task visual recognition, intelligent sensing, and artificial intelligence hardware.

[0041] Based on the same inventive concept, this embodiment of the invention also provides a method for fabricating a transistor. The implementation principle of this method is basically similar to that of the transistor described in the foregoing embodiments. For the specific implementation of this method, please refer to the specific embodiments of the transistor described above. Repeated details will not be repeated.

[0042] Specifically, the present invention provides a method for fabricating a transistor, comprising: Forming a gate; A gate dielectric layer is formed above the gate; A ferroelectric material layer and a channel layer are formed on top of the gate dielectric layer, with the channel layer covering the ferroelectric material layer; A first source, a first drain, a second source, and a second drain are formed on the second surface of the gate dielectric layer. The first source, the first drain, the second source, and the second drain are all connected to the channel layer. The line connecting the first source and the first drain is a first reference line, and the line connecting the second source and the second drain is a second reference line. The first reference line and the second reference line intersect each other. The distance at which the first reference line overlaps with the projection of the ferroelectric material layer on the gate dielectric layer is a first distance, and the distance at which the second reference line overlaps with the projection of the ferroelectric material layer on the gate dielectric layer is a second distance. The first distance is greater than the second distance.

[0043] In the above technical solution, by setting a ferroelectric material layer, the transistor can have high electrical anisotropy while ensuring electrical performance and stability.

[0044] To facilitate understanding, the following detailed description is provided in conjunction with specific examples.

[0045] First, combined Figure 4 As shown, taking silicon substrate 21 as gate 20 and silicon oxide layer on the surface of silicon substrate 21 as gate dielectric layer 30 as an example, the method of transistor fabrication is described in detail.

[0046] Step 1: Provide a silicon substrate 21 with a silicon oxide layer to obtain the following... Figure 4 The structure shown in (a) is shown in the image.

[0047] A heavily doped p-type silicon wafer can be selected as the silicon substrate 21.

[0048] Thermal oxidation can be used. Figure 4 In (a) shown, a silicon oxide layer is formed on the upper surface of the silicon substrate 21 as a gate dielectric layer 30. Of course, the material of the gate dielectric layer 30 is not limited to silicon oxide, and the method of forming the gate dielectric layer 30 is not limited to thermal oxidation. Other methods such as vapor deposition can also be used.

[0049] After the gate dielectric layer 30 is formed, the structure obtained in step 1 is cleaned sequentially with acetone, isoacetone and deionized water, and then dried with nitrogen gas for later use.

[0050] Step 2: Using a mechanical exfoliation method, CIPS thin films are exfoliated from the bulk single crystal of copper indium sulfide compound (chemical formula CuInP2S6, abbreviated as CIPS). After the shape of the CIPS thin films is modified, they are used as ferroelectric material layer 40. The ferroelectric material layer 40 is then placed on the surface of the first carrier 71 to obtain the following result: Figure 4 The structure shown in (b) is shown in the image.

[0051] Step 3, as follows Figure 4As shown in (c), the ferroelectric material layer 40 on the surface of the first carrier 71 is oriented toward the gate dielectric layer 30; the ferroelectric material layer 40 on the surface of the first carrier 71 is transferred to the gate dielectric layer 30 using a dry transfer method, resulting in the following... Figure 4 The structure shown in (d) is shown in the diagram.

[0052] Step 4: Using a mechanical peeling method, a molybdenum disulfide sheet is peeled off from the molybdenum disulfide block single crystal. After the shape of the molybdenum disulfide sheet is modified, it is used as the channel layer 50. The channel layer 50 is placed on the surface of the second carrier 72.

[0053] Step 5, as follows Figure 4 As shown in (e), the channel layer 50 on the surface of the second carrier 72 is oriented toward the ferroelectric material layer 40; the channel layer 50 is transferred onto the ferroelectric material layer 40 and the partially exposed gate dielectric layer 30 using a dry transfer method, resulting in the following... Figure 4 The structure shown in (f) is shown in the diagram.

[0054] Step 6: Using electron beam evaporation, deposit a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode on another silicon wafer to form an electrode layer 60; Figure 4 As shown in (g), after transferring the electrode layer 60 on the silicon wafer to the third carrier 73, the electrode layer 60 on the surface of the third carrier 73 is oriented towards the channel layer 50; the electrode layer 60 is transferred onto the channel layer 50 using a dry transfer method, so that it forms an electrical contact with the channel layer 50, resulting in the following... Figure 4 The structure shown in (h) is as described above. The specific arrangement of the electrode layer 60 can be found in the embodiments described above, and will not be repeated here.

[0055] The first carrier 71, the second carrier 72 and the third carrier 73 mentioned above can be made of polydimethylsiloxane (PDMS) or other materials that can achieve the same effect, which are not limited here.

[0056] It should be understood that although the electrode layer 60 can be formed directly by metal deposition, in order to avoid damage to the ferroelectric material layer 40 or the channel layer 50 during the metal deposition process, a dry transfer method is used to transfer the electrode layer 60 deposited on the third carrier 73 to the channel layer.

[0057] The fabricated transistors were dried in a vacuum oven to remove residual moisture at the interface and improve the contact quality between the layers.

[0058] Secondly, the polarization programming method of the ferroelectric material layer of the transistor is explained in detail.

[0059] Taking the transistor prepared in the above embodiment as an example, the ferroelectric material layer is made of CIPS, the channel layer is made of molybdenum disulfide, the transistor is placed in the probe station test system, the source is grounded, and a voltage pulse is applied to the ferroelectric material layer through the gate.

[0060] like Figure 2 As shown, when the applied first gate voltage pulse V1 has a voltage of +40V to +80V and a duration of 30s to 120s, the ferroelectric dipole polarization direction of the CIPS ferroelectric material layer 40 is the first direction F1 (from the gate dielectric layer 30 to the channel layer 50). At this time, the ferroelectric material layer 40 induces electron accumulation in the overlapping molybdenum disulfide channel layer 50, forming a region with high conductivity. The polarization state of the transistor programmed by the first gate voltage pulse V1 is called the upward polarization state. The anisotropy ratio of this transistor is tested, and the test results are as follows: Figure 5 As shown. The current between the first source 61 and the first drain 62 arranged along the first reference line L1 is recorded as the first current I1, and the current between the second source 63 and the second drain 64 arranged along the second reference line L2 is recorded as the second current I2. The first current I1 is approximately 8 times the second current I2. Therefore, the anisotropy ratio of the transistor fabricated using the above material and programmed to be in the upward polarization state is 8.

[0061] like Figure 3 As shown, when the applied second gate voltage pulse V2 has a voltage level of -40V to -80V and a duration of 30s to 120s, the ferroelectric dipole polarization direction of the CIPS ferroelectric material layer 40 is the second direction F2 (opposite to the first direction). At this time, the ferroelectric material layer 40 depletes the electrons in the overlapping molybdenum disulfide channel layer 50, forming a region with low conductivity. The polarization state of the transistor programmed by the second gate voltage pulse V2 is called the downward polarization state. The anisotropy ratio of this transistor is tested, and the test results are as follows. Figure 6 As shown. The current between the first source 61 and the first drain 62 arranged along the first reference line L1 is recorded as the first current I1, and the current between the second source 63 and the second drain 64 arranged along the second reference line L2 is recorded as the second current I2. The second current I2 is approximately 200 times the first current I1. Therefore, using the above material, the anisotropy ratio of the transistor programmed to the downward polarization state is 200.

[0062] Based on this, different anisotropy ratios can be obtained by polarizing the ferroelectric material layer 40 with different gate voltage pulses.

[0063] Furthermore, to obtain a higher anisotropy ratio, the applied voltage may vary depending on the channel material used, so it can be determined according to the actual situation. This explanation is based on just one example.

[0064] In summary, the technical solutions provided in the embodiments of the present invention have the following advantages: 1. This invention solves the problems associated with existing technologies that rely on intrinsically anisotropic semiconductor materials, namely, the low switching ratio and poor stability of intrinsically anisotropic semiconductors. By introducing a ferroelectric material layer into the channel layer made of anisotropic semiconductor material, the residual polarization effect of the ferroelectric material is used to spatially selectively control the channel carrier concentration, thereby constructing a transistor with direction-dependent transport characteristics. This eliminates the dependence of electrical anisotropy on intrinsically anisotropic materials, achieving ultra-high electrical anisotropy while maintaining excellent semiconductor performance.

[0065] 2. Since ferroelectric materials have non-volatile polarization characteristics, the transistor constructed in this invention can maintain its position for a long time without a continuous external electric field, which is beneficial to reduce transistor power consumption and improve stability.

[0066] 3. In this embodiment of the invention, by utilizing the directional correlation transport characteristics of transistors, multiple signal transmission channels with different response intensities and learning behaviors are formed within a single transistor. Thus, such transistors can be used to simulate the axon-multisynaptic connection structure in biological neural networks, providing new implementation methods for neuromorphic computing, multi-task visual recognition, intelligent perception, and edge artificial intelligence hardware.

[0067] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A transistor, characterized in that, include: The system comprises a gate, a gate dielectric layer, a ferroelectric material layer, a channel layer, and an electrode layer, wherein the gate, the gate dielectric layer, the ferroelectric material layer, and the channel layer are stacked sequentially. The electrode layer includes a first source, a first drain, a second source, and a second drain, which are respectively connected to the channel layer. The line connecting the first source and the first drain is a first reference line, and the line connecting the second source and the second drain is a second reference line. The first reference line and the second reference line intersect each other. The overlap length between the projection of the first reference line and the ferroelectric material layer onto the gate dielectric layer is a first length, and the overlap length between the projection of the second reference line and the ferroelectric material layer onto the gate dielectric layer is a second length. The first length is greater than the second length.

2. The transistor as claimed in claim 1, characterized in that, The gate is used to: apply a first gate voltage pulse to make the polarization direction of the ferroelectric material layer a first direction, and adjust the resistance of the overlapping region of the channel layer with the ferroelectric material layer to a first resistance; A second gate voltage pulse is applied to make the polarization direction of the ferroelectric material layer a second direction, and the resistance of the overlapping region of the channel layer and the ferroelectric material layer is adjusted to a second resistance. The first resistor is smaller than the second resistor; The first direction is the direction from the gate dielectric layer to the channel layer, and the second direction is opposite to the first direction.

3. The transistor as claimed in claim 1, characterized in that, The channel layer is made of an intrinsic anisotropic semiconductor material.

4. The transistor as claimed in claim 3, characterized in that, The intrinsic anisotropic semiconductor material includes at least one of molybdenum disulfide, tungsten disulfide, tungsten diselenide, molybdenum diselenide, indium selenide, or gallium selenide.

5. The transistor as claimed in claim 1, characterized in that, The materials used to fabricate the ferroelectric material layer include at least one of the following: copper indium sulfide, copper chromium sulfide, indium α-selenide, hafnium dioxide, or polyvinylidene fluoride-based ferroelectric polymers.

6. The transistor as claimed in claim 1, characterized in that, The projection pattern of the ferroelectric material layer on the gate dielectric layer is rectangular.

7. The transistor as claimed in claim 6, characterized in that, The longer side of the projected pattern is parallel to the first reference line.

8. The transistor according to any one of claims 1-7, characterized in that, The area of ​​the channel layer is larger than the area of ​​the ferroelectric material layer.

9. An electronic device, characterized in that, Includes the transistor as described in any one of claims 1-8.

10. A method for fabricating a transistor, characterized in that, include: Forming a gate; A gate dielectric layer is formed on the gate; A ferroelectric material layer and a channel layer are formed on the gate dielectric layer, wherein the channel layer covers the ferroelectric material layer; A first source, a first drain, a second source, and a second drain are formed on the second surface of the gate dielectric layer. The first source, the first drain, the second source, and the second drain are all connected to the channel layer. The line connecting the first source and the first drain is a first reference line, and the line connecting the second source and the second drain is a second reference line. The first reference line and the second reference line intersect each other. The distance at which the first reference line overlaps with the projection of the ferroelectric material layer on the gate dielectric layer is a first distance, and the distance at which the second reference line overlaps with the projection of the ferroelectric material layer on the gate dielectric layer is a second distance. The first distance is greater than the second distance.

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