Gate oxide mass optimization method

Abstract

This invention discloses a method for optimizing gate oxide quality, comprising: providing a semiconductor substrate and forming a silicon-containing consumable layer on the surface of the semiconductor substrate, wherein the semiconductor substrate contains silicon and elements that cannot be completely oxidized, and all elements contained in the silicon-containing consumable layer can be completely oxidized; performing thermal oxidation to form a gate oxide layer, wherein the thermal oxidation completely oxidizes the silicon-containing consumable layer and leaves the surface of the semiconductor substrate unoxidized or partially oxidized, thereby eliminating interface defects formed at the interface between the semiconductor substrate and the gate oxide layer by elements in the semiconductor substrate that cannot be completely oxidized when the semiconductor substrate is directly thermally oxidized; and annealing the gate oxide layer in a NO atmosphere, thereby diffusing N to the interface between the semiconductor substrate and the gate oxide layer to partially decompose the interface defects. This invention can reduce interface defects, thereby optimizing gate oxide quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for optimizing gate oxide quality. Background Technology

[0002] The ability to directly form a SiO2 oxide layer through thermal oxidation is a unique advantage of SiC compared to other third-generation semiconductors. However, due to the presence of carbon in SiC materials, during actual oxidation, the newly formed oxide film blocks oxygen from entering the SiC / SiO2 interface, resulting in incomplete oxidation of carbon atoms. Some carbon remains at the interface, forming carbon clusters.

[0003] This high density of defects increases the probability of carrier scattering during transport and reduces the channel carrier mobility, which in turn severely affects device performance and stability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a gate oxide quality optimization method that can reduce interface defects and thus optimize gate oxide quality.

[0005] To solve the above-mentioned technical problems, the gate oxide quality optimization method provided by the present invention includes the following steps: A semiconductor substrate is provided and a silicon-containing consumption layer is formed on the surface of the semiconductor substrate, the semiconductor substrate containing silicon and elements that cannot be completely oxidized in subsequent thermal oxidation, and the elements contained in the silicon-containing consumption layer can be completely oxidized.

[0006] A gate oxide layer is formed by thermal oxidation, wherein the thermal oxidation completely oxidizes the silicon-containing consumption layer and leaves or partially oxidizes the surface of the semiconductor substrate. The thermal oxidation of the silicon-containing consumption layer eliminates the interface defects formed at the interface between the semiconductor substrate and the gate oxide layer when the semiconductor substrate is directly thermally oxidized, which are caused by elements in the semiconductor substrate that are not completely oxidized. The gate oxide layer is annealed in a NO atmosphere, and the annealing diffuses N to the interface between the semiconductor substrate and the gate oxide layer to partially decompose the interface defects.

[0007] A further improvement is that the semiconductor substrate is made of SiC; and the interface defects include C clusters.

[0008] A further improvement is that the semiconductor substrate is used to form a semiconductor device, the semiconductor device including a trench gate device; and that the process further includes the following steps before forming the silicon-containing consumption layer: A trench is formed in the trench gate formation region of the semiconductor substrate.

[0009] The silicon-containing consumption layer is formed on the inner surface of the trench and extends to the surface of the semiconductor substrate outside the trench.

[0010] A further improvement is that the trench is formed by a photolithography definition and etching process.

[0011] A further improvement is that, after the trench etching is completed, the process further includes: forming a sacrificial oxide layer, and then removing the sacrificial oxide layer to eliminate etching defects.

[0012] A further improvement is that the silicon-containing consumption layer is an epitaxially grown intrinsic silicon layer or a polycrystalline silicon layer.

[0013] A further improvement is that the thickness of the silicon-containing consumption layer is 100 Å to 150 Å.

[0014] A further improvement is that the temperature of the thermal oxidation is 1100℃ or 1150℃.

[0015] When the semiconductor substrate contains elements that cannot be completely oxidized, this invention adds a step of forming a silicon-containing consumption layer on the surface of the semiconductor substrate before thermal oxidation. The elements contained in the silicon-containing consumption layer can be completely oxidized. In this way, the gate oxide layer can be formed by completely oxidizing the silicon-containing consumption layer or by superimposing a small amount of oxidation on the semiconductor substrate on the basis of complete oxidation of the silicon-containing consumption layer. During the thermal oxidation of the silicon-containing consumption layer, interface defects formed by elements in the semiconductor substrate that cannot be completely oxidized can be completely eliminated. This invention also further addresses the interface defects that may exist during thermal oxidation by adding annealing in a NO atmosphere. Annealing diffuses N elements to the interface to decompose interface defects, thereby further reducing interface defects. Therefore, this invention can reduce interface defects and thus optimize gate oxide quality. Attached Figure Description

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of the gate oxide quality optimization method according to an embodiment of the present invention; Figures 2-6 This is a schematic diagram of the device structure in each step of the gate oxide quality optimization method according to an embodiment of the present invention. Detailed Implementation

[0017] like Figure 1 The diagram shown is a flowchart of the gate oxide quality optimization method according to an embodiment of the present invention; as shown Figures 2 to 6 The diagram shown is a schematic representation of the device structure in each step of the gate oxide quality optimization method according to an embodiment of the present invention. The gate oxide quality optimization method according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 5As shown, a semiconductor substrate 101 is provided and a silicon-containing consumption layer 104 is formed on the surface of the semiconductor substrate 101. The semiconductor substrate 101 contains silicon and elements that cannot be completely oxidized in subsequent thermal oxidation. All elements contained in the silicon-containing consumption layer 104 can be completely oxidized.

[0018] In this embodiment of the invention, the semiconductor substrate 101 is made of SiC; C cannot be completely oxidized in the subsequent thermal oxidation, and the subsequent interface defects include C clusters.

[0019] The semiconductor substrate 101 is used to form a semiconductor device, the semiconductor device including a trench gate device; prior to forming the silicon-containing consumption layer 104, the following is also included: like Figure 2 As shown, a trench 102 is formed in the trench gate formation region of the semiconductor substrate 101. The trench 102 is formed by photolithography and etching processes.

[0020] After the etching of the trench 102 is completed, the process also includes: like Figure 3 As shown, a sacrificial oxide layer 103 is formed.

[0021] like Figure 4 As shown, the sacrificial oxide layer 103 is then removed to eliminate etching defects.

[0022] Back Figure 5 As shown, the silicon-containing consumption layer 104 is formed on the inner surface of the trench 102 and extends to the surface of the semiconductor substrate 101 outside the trench 102.

[0023] In other embodiments, the semiconductor device may include a planar gate device. In this case, it is not necessary to form the trench 102, and the silicon-containing consumption layer 104 can be formed directly on the surface of the semiconductor substrate 101.

[0024] In this embodiment of the invention, the silicon-containing consumption layer 104 is an epitaxially grown intrinsic silicon layer or a polycrystalline silicon layer.

[0025] Preferably, the thickness of the silicon-containing consumption layer 104 is preset based on the thickness of the subsequent gate oxide layer 105, so that the thickness of the oxide layer obtained after the silicon-containing consumption layer 104 is completely oxidized is exactly the designed thickness of the gate oxide layer 105; in this case, the semiconductor substrate 101 will not be oxidized during the subsequent thermal oxidation. In other embodiments, the thickness of the silicon-containing consumption layer 104 can also be set smaller to ensure that the subsequent thermal oxidation can completely consume the silicon-containing consumption layer 104. In some embodiments, the thickness of the silicon-containing consumption layer 104 is 100 Å to 150 Å.

[0026] Step S102, as follows Figure 6 As shown, a gate oxide layer 105 is formed by thermal oxidation. The thermal oxidation completely oxidizes the silicon-containing consumption layer 104 and leaves the surface of the semiconductor substrate 101 unoxidized or partially oxidized. The thermal oxidation of the silicon-containing consumption layer 104 eliminates interface defects formed at the interface between the semiconductor substrate 101 and the gate oxide layer 105 when the semiconductor substrate 101 is directly thermally oxidized, which are caused by elements in the semiconductor substrate 101 that are not completely oxidized.

[0027] Since the silicon-containing consumption layer 104 is completely oxidized, the gate oxide layer 105 directly contacts the semiconductor substrate 101 to form an interface, resulting in a channel region being formed on the surface region of the semiconductor substrate 101. Because the surface of the semiconductor substrate 101 is not oxidized or only partially oxidized, compared to existing methods that form a gate oxide layer by oxidizing the surface of the semiconductor substrate 101, this embodiment of the invention can completely eliminate interface defects caused by unoxidized elements related to the thermal oxidation of the semiconductor substrate 101, or reduce interface defects to a negligible level.

[0028] In some embodiments, the temperature of the thermal oxidation is 1100°C or 1150°C.

[0029] Step S103, as follows Figure 6 As shown, the gate oxide layer 105 is annealed under a NO atmosphere. This annealing diffuses N to the interface between the semiconductor substrate 101 and the gate oxide layer 105, partially decomposing the interface defects. That is, if some interface defects still form at the interface between the semiconductor substrate 101 and the gate oxide layer 105 in step S102, the annealing process can decompose these interface defects, further reducing them. Fewer interface defects result in higher carrier mobility, thereby improving device performance.

[0030] When the semiconductor substrate 101 contains elements that cannot be completely oxidized, this embodiment of the invention adds a step of forming a silicon-containing consumption layer 104 on the surface of the semiconductor substrate 101 before thermal oxidation. The elements contained in the silicon-containing consumption layer 104 can be completely oxidized. In this way, the gate oxide layer 105 can be formed by completely oxidizing the silicon-containing consumption layer 104 or by superimposing a small amount of oxidation on the semiconductor substrate 101 on the basis of completely oxidizing the silicon-containing consumption layer 104. During the thermal oxidation of the silicon-containing consumption layer 104, interface defects formed by elements in the semiconductor substrate 101 that cannot be completely oxidized can be completely eliminated. This embodiment of the invention also provides annealing in a NO atmosphere to address interface defects that may exist during thermal oxidation. Annealing diffuses N elements to the interface to decompose interface defects, thereby further reducing interface defects. Therefore, this embodiment of the invention can reduce interface defects and thus optimize gate oxide quality.

[0031] To avoid carbon clusters formed at the interface due to direct oxidation of SiC surface and interface defects generated during precipitation, this embodiment of the invention first deposits a layer of polycrystalline silicon or intrinsic silicon at the surface-treated trench, then oxidizes the deposited polycrystalline silicon to form a SiO2 layer, and finally anneals in a NO environment, where N atoms diffuse to the interface, decompose some carbon clusters, help reduce the interface state density, and thus reduce interface state defects.

[0032] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for optimizing gate oxide quality, characterized in that, Includes the following steps: A semiconductor substrate is provided and a silicon-containing consumption layer is formed on the surface of the semiconductor substrate, wherein the semiconductor substrate contains silicon and elements that cannot be completely oxidized in subsequent thermal oxidation, and the elements contained in the silicon-containing consumption layer can be completely oxidized. A gate oxide layer is formed by thermal oxidation, wherein the thermal oxidation completely oxidizes the silicon-containing consumption layer and leaves or partially oxidizes the surface of the semiconductor substrate. The thermal oxidation of the silicon-containing consumption layer eliminates the interface defects formed at the interface between the semiconductor substrate and the gate oxide layer when the semiconductor substrate is directly thermally oxidized, which are caused by elements in the semiconductor substrate that are not completely oxidized. The gate oxide layer is annealed in a NO atmosphere, and the annealing diffuses N to the interface between the semiconductor substrate and the gate oxide layer to partially decompose the interface defects.

2. The gate oxide quality optimization method as described in claim 1, characterized in that: The semiconductor substrate is made of SiC; the interface defects include C clusters.

3. The gate oxide quality optimization method as described in claim 2, characterized in that: The semiconductor substrate is used to form a semiconductor device, the semiconductor device including a trench gate device; prior to forming the silicon-containing consumption layer, the following is also included: A trench is formed in the trench gate formation region of the semiconductor substrate; The silicon-containing consumption layer is formed on the inner surface of the trench and extends to the surface of the semiconductor substrate outside the trench.

4. The gate oxide quality optimization method as described in claim 3, characterized in that: The trenches are formed by a combination of photolithography and etching processes.

5. The gate oxide quality optimization method as described in claim 4, characterized in that: After the trench etching is completed, the process further includes: forming a sacrificial oxide layer, and then removing the sacrificial oxide layer to eliminate etching defects.

6. The gate oxide quality optimization method as described in claim 2, characterized in that: The silicon-containing consumption layer is an epitaxially grown intrinsic silicon layer or a polycrystalline silicon layer.

7. The gate oxide quality optimization method as described in claim 6, characterized in that: The thickness of the silicon-containing consumption layer is 100 Å to 150 Å.

8. The gate oxide quality optimization method as described in claim 1, characterized in that: The temperature of the thermal oxidation is 1100℃ or 1150℃.

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