Electrical structure comprising mos transistors

Abstract

This disclosure provides an electrical structure and a method for fabricating the same. The electrical structure includes a substrate and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is disposed on a first surface of the substrate and includes a gate structure. The gate structure has a top surface and a bottom surface opposite to the top surface. The width of the top surface is smaller than the width of the bottom surface.

Description

Technical Field

[0001] This disclosure relates to an electrical structure and a method for fabricating the same. In particular, it relates to an electrical structure including a MOS transistor and a method for fabricating the same.

[0002] This application claims priority to U.S. Application No. 19 / 175,196, filed on April 10, 2025, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Semiconductor structures are used in a wide range of electronic applications, and their dimensions are constantly shrinking to meet current application requirements. However, various problems arise during the miniaturization process, affecting the final electrical characteristics, quality, cost, and yield. Typical memory elements (such as dynamic random access memory (DRAM) elements) include signal lines, such as word lines and bit lines that intersect with them. As DRAM element sizes shrink and signal line sizes and / or spacing decrease, parasitic capacitance becomes a critical issue.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides an electrical structure including a substrate and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is disposed on a first surface of the substrate and includes a gate structure. The gate structure has a top surface and a bottom surface opposite to the top surface. The width of the top surface is smaller than the width of the bottom surface.

[0006] Another aspect of this disclosure provides an electrical structure including a substrate, a metal-oxide-semiconductor (MOS) transistor, and an electrical contact. The MOS transistor is disposed on a first surface of the substrate and includes a gate structure. The electrical contact is disposed adjacent to the MOS transistor and electrically connected to the first surface of the substrate. The distance between the gate structure of the MOS transistor and the electrical contact decreases toward the first surface of the substrate.

[0007] Another aspect of this disclosure provides a method for fabricating an electrical structure. The method includes forming a gate structure on a first surface of a substrate. The method also includes removing a portion of the gate structure such that the width of a top surface of the gate structure is smaller than the width of a bottom surface of the gate structure. The method further includes forming a spacer on one side surface of the gate structure.

[0008] The technical features and advantages of this disclosure have been broadly summarized above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages forming the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0009] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the accompanying drawings, wherein similar reference numerals represent similar elements throughout the drawings, and: Figure 1 A method for preparing an electrical structure is shown in the form of a flowchart according to an embodiment of this disclosure.

[0010] Figure 2 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0011] Figure 3 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0012] Figure 4 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0013] Figure 5 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0014] Figure 6 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0015] Figure 7 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0016] Figure 8 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0017] Figure 9An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0018] Figure 10 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0019] Figure 11 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0020] Figure 12 A cross-sectional schematic diagram of an electrical structure is shown according to an embodiment of the present disclosure.

[0021] Figure 13 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0022] Figure 14 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0023] Figure 15 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0024] Figure 16 An embodiment of this disclosure shows a stage of a method for preparing an electrical structure.

[0025] Figure 17 A cross-sectional schematic diagram of an electrical structure is shown according to an embodiment of the present disclosure.

[0026] Figure 18 A cross-sectional schematic diagram of an electrical structure is shown according to an embodiment of the present disclosure.

[0027] The annotations in the attached figures are explained as follows: 1: Electrical Structure 1a: Electrical Structure 1b: Electrical Structure 1c: Electrical Structure 2:Substrate 3: First MOS transistor 3a: Second MOS transistor 3b: First MOS transistor 3c: Second MOS transistor 3d: First MOS transistor 3e: Second MOS transistor 3f: First MOS transistor 3g: Second MOS transistor 4: First insulating layer 5: Second insulation layer 6: Electrical contact 6a: Electrical contact 13: Hole Structure 13': Hole structure 21: First Surface 22: Drain 23: Source 24: Source 25: Depressed area 26: Low-resistivity layer 28: Part 30: First gate structure 30a: Second gate structure 30c: Second gate structure 30d: First gate structure 30f: First gate structure 31: Gate oxide layer 31a: Gate oxide layer 31b: Gate oxide layer 31c: Gate oxide layer 32: First gate conductor layer 32a: First gate conductor layer 32b: First gate conductor layer 32c: First gate conductor layer 33: Second gate conductor layer 33a: Second gate conductor layer 33b: Second gate conductor layer 33c: Second gate conductor layer 34: Upper level 34a: Upper layer 34b: Upper layer 34c: Upper layer 35: First spacer 35a: Second spacer 35b: First spacer 35c: Second spacer 36: First floor 36a: First layer 36b: First layer 36c: First layer 37: Second layer 37a: Second layer 37b: Second layer 37c: Second layer 38: Third Floor 38a: Third layer 38b: Third layer 38c: Third layer 41: First Surface 43: First through hole 43': Through hole 51: First Surface 53: Second through hole 53': Through hole 60: Central Materials 61: Part One 62: Part Two 63: Part Three 65: Peripheral layer 67: Side surface 80: Cleaning agent 82: Cobalt 301: Top surface 302: Bottom surface 303: Side surface 322: Bottom surface 323: Side surface 331: Top surface 333: Side surface 353: Side surface 354: Depressed portion 380: Protective layer 653: Center Hole 900: Preparation Method D: Distance D1: Distance D2: Distance S901: Steps S902: Steps S903: Steps W1: Width W1': Width W2: Width W2': Width W3: Width W4: Width W4': Width W5: Width W6: Width W7: Width W11: First width W12: Second width. Detailed Implementation

[0028] The embodiments or examples of this disclosure shown in the accompanying drawings are described below using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the embodiments, and any further application of the principles set forth herein, are to be regarded as normal occurrences by those skilled in the art related to this disclosure. Reference numerals may be repeated in all embodiments, but this does not necessarily mean that a component of one embodiment is applicable to another embodiment, even if they use the same reference numerals.

[0029] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited to these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part.

[0030] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the concepts of this disclosure. As used herein, unless the context explicitly indicates otherwise, the singular forms “a / an” and “the” also include the plural forms. It should be understood that the terms “comprises” and “comprising” as used in this specification indicate the presence of said components, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more components, integers, steps, operations, elements, components, or combinations thereof.

[0031] Figure 1 According to an embodiment of this disclosure, a method 900 for preparing an electrical structure 1 is shown in the form of a flowchart. Figures 2 to 12 According to an embodiment of this disclosure, a method for preparing electrical structure 1 includes several stages. For a better understanding of various aspects of this disclosure, at least some of the figures have been simplified.

[0032] Reference Figure 1 and Figure 2 In step S901, a gate structure (including a first gate structure 30 and a second gate structure 30a) is formed on a first surface 21 of a substrate 2.

[0033] In some embodiments, substrate 2 may have a first surface 21 (e.g., a top surface). Substrate 2 may include a drain 22, a source 23, and a source 24. Substrate 2 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0034] The first gate structure 30 may include a gate oxide layer 31, a first gate conductor layer 32, a second gate conductor layer 33, and an upper layer 34. The formation of the first gate structure 30 may include the following steps: First, a gate oxide layer 31 may be formed or disposed on a first surface 21 of the substrate 2, and the gate oxide layer may include an oxide material for electrical insulation. The gate oxide layer 31 may have a substantially constant width.

[0035] Then, a first gate conductor layer 32 may be formed or disposed on the gate oxide layer 31, and the first gate conductor layer may include a polysilicon material. Therefore, the first gate conductor layer 32 may be formed or disposed on the first surface 21 of the substrate 2. The first gate conductor layer 32 may have a first width W11. The first width W11 may be substantially constant. Therefore, the cross-sectional view of the first gate conductor layer 32 may be rectangular.

[0036] A second gate conductor layer 33 may then be formed or disposed on the first gate conductor layer 32, and the second gate conductor layer may include tungsten silicide (WSix) material. The second gate conductor layer 33 may have a second width W12. The second width W12 may be substantially constant. Therefore, the cross-sectional view of the second gate conductor layer 33 may present a rectangular shape. The second width W12 of the second gate conductor layer 33 may be substantially equal to the first width W11 of the first gate conductor layer 32.

[0037] Then, an upper layer 34 may be formed or disposed on the second gate conductor layer 33, and the upper layer may include a nitride material. The upper layer 34 may have a substantially constant width. Therefore, the cross-sectional view of the upper layer 34 may present a rectangular shape. The substantially constant width of the upper layer 34 may be substantially equal to the second width W12 of the second gate conductor layer 33.

[0038] The first gate structure 30 may have a top surface 301, a bottom surface 302 opposite to the top surface 301, and a side surface 303 extending between the top surface 301 and the bottom surface 302. The bottom surface 302 of the first gate structure 30 may contact the first surface 21 of the substrate 2. The top surface 301 of the upper layer 34 may be the top surface 301 of the first gate structure 30. The bottom surface 302 of the gate oxide layer 31 may be the bottom surface 302 of the first gate structure 30.

[0039] In some embodiments, the first gate conductor layer 32 and the second gate conductor layer 33 may be defined together as a gate contact or a gate electrode. The top surface 331 of the second gate conductor layer 33 may be the top surface 331 of the gate electrode (including the first gate conductor layer 32 and the second gate conductor layer 33). The bottom surface 322 of the first gate conductor layer 32 may be the bottom surface 322 of the gate electrode (including the first gate conductor layer 32 and the second gate conductor layer 33).

[0040] The second gate structure 30a may include a gate oxide layer 31a, a first gate conductor layer 32a, a second gate conductor layer 33a, and an upper layer 34a. The structure of the second gate structure 30a may be the same as that of the first gate structure 30. That is, the dimensions and materials of the gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, and the upper layer 34a of the second gate structure 30a may be the same as those of the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, and the upper layer 34a of the first gate structure 30, respectively.

[0041] Reference Figure 1 and Figure 3 In step S902, a portion of the gate structure (e.g., the first gate structure 30) is removed, such that the width W4 of the top surface 301 of the gate structure (e.g., the first gate structure 30) is smaller than the width W5 of the bottom surface 302 of the gate structure (e.g., the first gate structure 30).

[0042] A portion of the second gate conductor layer 33 and a portion of the first gate conductor layer 32 can be removed simultaneously, for example, by etching. The second gate conductor layer 33 and the first gate conductor layer 32 can be etched at different etching rates. Alternatively, the second gate conductor layer 33 and the first gate conductor layer 32 can be etched using a specific selective etching ratio. Therefore, both the first gate conductor layer 32 and the second gate conductor layer 33 can taper gradually from the first surface 21 of the substrate 2. Both the first gate conductor layer 32 and the second gate conductor layer 33 can taper upwards.

[0043] Each of the first gate conductor layer 32 and the second gate conductor layer 33 can be trapezoidal. The side surface 323 of the first gate conductor layer 32 can be aligned with the side surface 333 of the second gate conductor layer 33. In the gate electrode (including the first gate conductor layer 32 and the second gate conductor layer 33), the width W6 of the top surface 331 of the second gate conductor layer 33 is smaller than the width W7 of the bottom surface 322 of the first gate conductor layer 32. Figure 3 The width W6 of the top surface 331 of the second gate conductor layer 33 can be less than Figure 2 The second width W12 in the middle. Figure 3 The width W7 of the bottom surface 322 of the first gate conductor layer 32 in the middle can be less than Figure 2 The first width is W11.

[0044] Simultaneously, a portion of the gate oxide layer 31 and a portion of the upper layer 34 can be removed, for example, by etching together with the second gate conductor layer 33 and the first gate conductor layer 32. The upper layer 34, the second gate conductor layer 33, the first gate conductor layer 32, and the gate oxide layer 31 can be etched at different etching rates. Alternatively, the upper layer 34, the second gate conductor layer 33, the first gate conductor layer 32, and the gate oxide layer 31 can be etched using a specific etching selectivity. Therefore, both the upper layer 34 and the gate oxide layer 31 can gradually taper from the first surface 21 of the substrate 2. Both the upper layer 34 and the gate oxide layer 31 can gradually taper upwards.

[0045] Each of the upper layer 34 and the gate oxide layer 31 can be trapezoidal. The side surface of the upper layer 34 can be substantially aligned with the side surface 333 of the second gate conductor layer 33, the side surface 323 of the first gate conductor layer 32, and the side surface of the gate oxide layer 31. Therefore, the width W4 of the top surface 301 of the first gate structure 30 can be smaller than the width W5 of the bottom surface 302 of the first gate structure 30. The first gate structure 30 can be trapezoidal.

[0046] The first gate structure 30 can gradually taper from the first surface 21 of the substrate 2. The first gate structure 30 can taper upwards. In some embodiments, the ratio of the width W4 of the top surface 301 of the first gate structure 30 to the width W5 of the bottom surface 302 of the first gate structure 30 can be 1 / 4 to 1 / 2, or 1 / 4 to 3 / 4, or 1 / 3 to 2 / 3. The entire side surface 303 of the first gate structure 30 can be a flat slope. The tilt angle between the side surface 303 of the first gate structure 30 and the first surface 21 of the substrate 2 can be less than 90 degrees.

[0047] Similarly, the second gate structure 30a can also be etched. Therefore, the outline of the second gate structure 30a can be the same as the outline of the first gate structure 30.

[0048] Reference Figure 1 and Figure 4 In step S903, a spacer (e.g., a first spacer 35 or a second spacer 35a) is formed on the side surface 303 of the gate structure (e.g., a first gate structure 30 or a second gate structure 30a). The formation of the first spacer 35 and the second spacer 35a may include the following steps: First, a first layer 36 is conformally formed or disposed on the side surface 303 of the first gate structure 30. A first layer 36a is conformally formed or disposed on the side surface of the second gate structure 30a. The material of the first layers 36 and 36a may include a nitride material. Then, a second layer 37 may be formed or disposed on the side surface of the first layer 36 and a portion of the first surface 21 of the substrate 2. A second layer 37a may be formed or disposed on the side surface of the first layer 36a and a portion of the first surface 21 of the substrate 2. The second layers 37 and 37a may taper upwards and may include an oxide material.

[0049] Then, a protective layer 380 can be formed on the first layers 36, 36a and the second layers 37, 37a by deposition, for example. The protective layer 380 may include a nitride material. The protective layer 380 may include a third layer 38 located on the second layer 37 of the first spacer 35, and a third layer 38a located on the second layer 37a of the second spacer 35a. Therefore, the first spacer 35 may include the first layer 36, the second layer 37, and the third layer 38. The second spacer 35a may include the first layer 36a, the second layer 37a, and the third layer 38a. Simultaneously, a first MOS transistor 3 and a second MOS transistor 3a may be formed, and they may be separable from each other. The first MOS transistor 3 may include a first gate structure 30 and a first spacer 35 disposed on the side surface 303 of the first gate structure 30. The second MOS transistor 3a may include a second gate structure 30a and a second spacer 35a disposed on the side surface of the second gate structure 30a.

[0050] Reference Figure 5 A first insulating layer 4 may be formed or disposed on the first surface 21 of the substrate 2. In some embodiments, the first insulating layer 4 may be disposed on the first surface 21 of the substrate 2 and may cover the first MOS transistor 3 (including the first gate structure 30 and the first spacer 35) and the second MOS transistor 3a (including the second gate structure 30a and the second spacer 35a). The first surface 41 (e.g., the top surface) of the first insulating layer 4 may be higher than the top surface of the third layer 38 of the first MOS transistor 3 and the top surface of the third layer 38a of the second MOS transistor 3a. The first insulating layer 4 may include an oxide material, such as silicon dioxide (SiO2).

[0051] Reference Figure 6The first insulating layer 4 can be thinned from the first surface 41, for example, by grinding. Therefore, a higher portion of the first insulating layer 4 can be removed, and the first surface 41 of the first insulating layer 4 can be aligned with the top surface of the third layer 38 of the first MOS transistor 3 and the top surface of the third layer 38a of the second MOS transistor 3a. Thus, the top surfaces of the third layer 38 of the first MOS transistor 3 and the third layer 38a of the second MOS transistor 3a can be exposed from the first surface 41 of the first insulating layer 4.

[0052] Reference Figure 7 A second insulating layer 5 may be formed or disposed on the first insulating layer 4. The second insulating layer 5 may cover and contact the first surface 41 of the first insulating layer 4. The material of the second insulating layer 5 may be different from the material of the first insulating layer 4. The second insulating layer 5 may include a nitride material, such as silicon nitride (Si3N4, or SiN).

[0053] At the same time, an electrical structure 1 (or a stacked structure or a semiconductor structure) can be formed.

[0054] like Figure 8 As shown, at least one first hole structure 13' can be formed from the first surface 51 of the second insulating layer 5 by, for example, dry etching, to expose a portion 28 of the substrate 2. The first hole structure 13' can extend through the first insulating layer 4 to form a through hole 43' having a width W1'. The first hole structure 13' can extend through the second insulating layer 5 to form a through hole 53' having a width W2'. The width W1' can be substantially equal to the width W2'. The first hole structure 13' can be disposed on both sides of the first MOS transistor 3. For example, the first hole structure 13' can be disposed between the first MOS transistor 3 and the second MOS transistor 3a.

[0055] In some embodiments, the first hole structure 13' may further extend through the protective layer 380 and into the substrate 2 to form a recessed portion 25 recessed from the first surface 21 of the substrate 2. The recessed portion 25 has a width W3. The width W3 may be the maximum width of the recessed portion 25 and may be less than the width W1'.

[0056] Reference Figure 9The exposed portion 28 of the substrate 2 can be cleaned by applying a cleaning agent 80 to the first hole structure 13'. Simultaneously, the cleaning agent 80 can etch the first insulating layer 4 and the second insulating layer 5, expanding the first hole structure 13' into a second hole structure 13. Therefore, the fabrication technique for the second hole structure 13 can include, for example, wet etching. The cleaning agent 80 can include water and hydrofluoric acid (HF), with the weight ratio of water to HF between 500:1 and 2500:1. Alternatively, the weight ratio of water to HF can be between 1800:1 and 2200:1, 1000:1 and 2000:1, or 1500:1 and 2100:1. This cleaning agent 80 can also be referred to as "ultra-diluted hydrofluoric acid (HF)".

[0057] The second hole structure 13 may extend through the first insulating layer 4 to form a first through hole 43 (or a first enlarged through hole) having a first width W1. The second hole structure 13 may extend through the second insulating layer 5 to form a second through hole 53 (or a second enlarged through hole) having a second width W2. Since the etching rate of the cleaning agent 80 on the first insulating layer 4 is greater than the etching rate on the second insulating layer 5, the first width W1 may be greater than the second width W2.

[0058] In some embodiments, the difference between the first width W1 and the second width W2 may be less than one-tenth of the first width W1. That is, the ratio (W1-W2) / W1 may be less than 0.1, 0.09, 0.08, 0.07, or 0.06. Therefore, the gap (or tolerance) between the sidewall of the first through hole 43 and the sidewall of the second through hole 53 can be very small. The sidewalls of the first through hole 43 and the second through hole 53 can be substantially aligned.

[0059] Reference Figure 10 A low-resistivity layer 26 can be formed on the cleaned exposed portion 28 of the substrate 2 by, for example, sputtering and annealing. In some embodiments, the low-resistivity layer 26 can be formed by sputtering cobalt (Co) 82 and annealing, such that the low-resistivity layer 26 may include cobalt disilicide (CoSi2). In this disclosure, the ultra-dilute hydrofluoric acid (HF) as described above does not affect the formation of the low-resistivity layer 26. Residual cobalt (Co) can then be removed by, for example, wet cleaning.

[0060] Reference Figure 11 A peripheral layer 65 can be formed or disposed on the sidewall of the second pore structure 13, for example, by deposition. The peripheral layer 65 may define a central pore 653. The peripheral layer 65 may include titanium nitride (TiN). Figure 11 As shown, this can reduce the difference between the first width W1 of the first through-hole 43 and the second width W2 of the second through-hole 53. Therefore, the sidewalls of the second hole structure 13 can be substantially flat to facilitate the deposition process of the peripheral layer 65.

[0061] Reference Figure 12 A central material 60 can be used to fill a central hole 653 defined by a peripheral layer 65, thereby forming an electrical contact 6 and an electrical contact 6a. The central material 60 may include tungsten (W). The electrical contacts 6 and 6a may extend through the second insulating layer 5 and the first insulating layer 4.

[0062] Figure 12 A cross-sectional schematic diagram of an electrical structure 1 is shown according to an embodiment of the present disclosure. In some embodiments, the electrical structure 1 may be a semiconductor structure or semiconductor element including circuitry (such as a memory cell). In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

[0063] Furthermore, electrical structure 1 may be or include part of an integrated circuit (IC) wafer, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0064] The electrical structure 1 may include a substrate 2, a first MOS transistor 3, a second MOS transistor 3a, a first insulating layer 4, a second insulating layer 5, an electrical contact 6, and an electrical contact 6a.

[0065] In some embodiments, substrate 2 may have a first surface 21 (e.g., a top surface). Substrate 2 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, group III-V, or group II-VI semiconductor materials. In some other embodiments, substrate 2 may include a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0066] Depending on the IC manufacturing stage, substrate 2 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof).

[0067] like Figure 12 As shown, substrate 2 may include a drain 22, a source 23, and a source 24. Substrate 2 may define a recessed portion 25 recessed from its first surface 21 (e.g., the top surface). The recessed portion 25 may be disposed in the drain 22 or the source 23. The recessed portion 25 has a third width W3. The third width W3 may be the maximum width of the recessed portion 25. Furthermore, substrate 2 may include a low-resistivity layer 26 disposed on the bottom wall of the recessed portion 25. The low-resistivity layer 26 may include cobalt (Co), such as cobalt disilicide (CoSi2).

[0068] The first MOS transistor 3 and the second MOS transistor 3a may be part of a word line. The first MOS transistor 3 and the second MOS transistor 3a may be disposed on the first surface 21 of the substrate 2. The first MOS transistor 3 may correspond to a drain 22 and a source 23. The first MOS transistor 3 may include a first gate structure 30 and a first spacer 35 located on the first gate structure 30. The first gate structure 30 may include a gate oxide layer 31, a first gate conductor layer 32, a second gate conductor layer 33, and an upper layer 34. The gate oxide layer 31 may be formed or disposed on the first surface 21 of the substrate 2 and may include an oxide material for electrical insulation. The first gate conductor layer 32 may be formed or disposed on the gate oxide layer 31 and may include a polysilicon material. The second gate conductor layer 33 may be formed or disposed on the first gate conductor layer 32 and may include a tungsten silicide (WSix) material. The first gate conductor layer 32 and the second gate conductor layer 33 may together define a gate electrode or a gate contact. The upper layer 34 may be disposed on the second gate conductor layer 33 and may include a nitride material. In some embodiments, the gate electrode may include an upper layer 34.

[0069] The first gate structure 30 may have a top surface 301, a bottom surface 302 opposite to the top surface 301, and a side surface 303 extending between the top surface 301 and the bottom surface 302. The bottom surface 302 of the first gate structure 30 may contact the first surface 21 of the substrate 2. The top surface 301 of the upper layer 34 may be the top surface 301 of the first gate structure 30. The bottom surface 302 of the gate oxide layer 31 may be the bottom surface 302 of the first gate structure 30. Furthermore, the top surface 331 of the second gate conductor layer 33 may be the top surface 331 of the gate electrode (including the first gate conductor layer 32 and the second gate conductor layer 33). The bottom surface 322 of the first gate conductor layer 32 may be the bottom surface 322 of the gate electrode (including the first gate conductor layer 32 and the second gate conductor layer 33).

[0070] Both the first gate conductor layer 32 and the second gate conductor layer 33 can gradually taper from the first surface 21 of the substrate 2. Both the first gate conductor layer 32 and the second gate conductor layer 33 can gradually taper upwards. Each of the first gate conductor layer 32 and the second gate conductor layer 33 can be trapezoidal. The side surface 323 of the first gate conductor layer 32 can be aligned with the side surface 333 of the second gate conductor layer 33. In the gate electrode (including the first gate conductor layer 32 and the second gate conductor layer 33), the width W6 of the top surface 331 of the second gate conductor layer 33 can be smaller than the width W7 of the bottom surface 322 of the first gate conductor layer 32.

[0071] Furthermore, both the upper layer 34 and the gate oxide layer 31 can gradually taper from the first surface 21 of the substrate 2. Both the upper layer 34 and the gate oxide layer 31 can taper upwards. Each of the upper layer 34 and the gate oxide layer 31 can be trapezoidal. The side surface of the upper layer 34 can be substantially aligned with the side surface 333 of the second gate conductor layer 33, the side surface 323 of the first gate conductor layer 32, and the side surface of the gate oxide layer 31. Therefore, the width W4 of the top surface 301 of the first gate structure 30 can be smaller than the width W5 of the bottom surface 302 of the first gate structure 30. The first gate structure 30 can be trapezoidal.

[0072] The first gate structure 30 can gradually taper from the first surface 21 of the substrate 2. The first gate structure 30 can taper upwards. In some embodiments, the ratio of the width W4 of the top surface 301 of the first gate structure 30 to the width W5 of the bottom surface 302 of the first gate structure 30 can be 1 / 4 to 1 / 2, or 1 / 4 to 3 / 4, or 1 / 3 to 2 / 3. The entire side surface 303 of the first gate structure 30 can be a flat slope. The tilt angle between the side surface 303 of the first gate structure 30 and the first surface 21 of the substrate 2 can be less than 90 degrees.

[0073] The first spacer 35 may include a first layer 36, a second layer 37 disposed on the first layer 36, and a third layer 38 disposed on the second layer 37. The first layer 36 may cover the side surface 303 of the first gate structure 30. The material of the first layer 36 may include a nitride material. The second layer 37 may be formed or disposed on the first layer 36. The second layer 37 may include an oxide material. The third layer 38 may cover the first layer 36 and the second layer 37. For example, the third layer 38 may cover the outer surface of the second layer 37 and the top surface of the first layer 36. Therefore, the second layer 37 may be sandwiched between the first layer 36 and the third layer 38. The bottom end of the third layer 38 may be disposed on the first surface 21 of the substrate 2.

[0074] The second MOS transistor 3a may correspond to the drain 22 and the source 24. The second MOS transistor 3a may include a second gate structure 30a and a second spacer 35a located on the second gate structure 30a. The second gate structure 30a may include a gate oxide layer 31a, a first gate conductor layer 32a, a second gate conductor layer 33a, and an upper layer 34a. The structure of the second gate structure 30a may be the same as the structure of the first gate structure 30. That is, the dimensions and materials of the gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, and the upper layer 34a of the second gate structure 30a may be the same as the dimensions and materials of the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, and the upper layer 34a of the first gate structure 30, respectively.

[0075] The second spacer 35a may include a first layer 36a, a second layer 37a disposed on the first layer 36a, and a third layer 38a disposed on the second layer 37a. The first layer 36a may cover the side surface of the second gate structure 30a. The material of the first layer 36a may include a nitride material. The second layer 37a may be formed or disposed on the first layer 36a. The second layer 37a may include an oxide material. The third layer 38a may cover the first layer 36a and the second layer 37a. For example, the third layer 38a may cover the outer surface of the second layer 37a and the top surface of the first layer 36a. Therefore, the second layer 37a may be sandwiched between the first layer 36a and the third layer 38a. The bottom end of the third layer 38a may be disposed on the first surface 21 of the substrate 2.

[0076] A first insulating layer 4 may be disposed on a first surface 21 of a substrate 2. In some embodiments, the first insulating layer 4 may be disposed on a first surface 21 of a substrate 2 and may cover a first MOS transistor 3 and a second MOS transistor 3a. The first insulating layer 4 may include an oxide material, such as silicon dioxide (SiO2). The first surface 41 (e.g., the top surface) of the first insulating layer 4 may be aligned with the top surface of the third layer 38 of the first MOS transistor 3 and the top surface of the third layer 38a of the second MOS transistor 3a.

[0077] The first insulating layer 4 may define a first through-hole 43 extending through the first insulating layer 4. The first through-hole 43 has a width W1. The width W1 is the maximum width of the first through-hole 43. The recessed portion 25 of the substrate 2 may communicate with the first through-hole 43 of the first insulating layer 4. The width W3 of the recessed portion 25 may be smaller than the width W1 of the first through-hole 43.

[0078] A second insulating layer 5 may be disposed on the first insulating layer 4. The second insulating layer 5 may cover and contact the first surface 41 of the first insulating layer 4. The material of the second insulating layer 5 may be different from the material of the first insulating layer 4. The second insulating layer 5 may include a nitride material, such as silicon nitride (Si3N4, or SiN). The second insulating layer 5 may define a second through-hole 53 extending through the second insulating layer 5. The second through-hole 53 of the second insulating layer 5 may communicate with the first through-hole 43 of the first insulating layer 4, thereby forming a hole structure 13 (or contact hole). The central axis of the first through-hole 43 may be substantially aligned with the central axis of the second through-hole 53. Therefore, the hole structure 13 may extend through the first insulating layer 4 and the second insulating layer 5, and may include the first through-hole 43 and the second through-hole 53. In some embodiments, the hole structure 13 may further extend into the substrate 2 and may include a recessed portion 25.

[0079] The second through hole 53 has a width W2. The width W2 can be the maximum width of the second through hole 53. The width W2 of the second through hole 53 can be smaller than the width W1 of the first through hole 43. The width W3 of the recessed portion 25 can be smaller than the width W2 of the second through hole 53.

[0080] Electrical contact 6 may be disposed in the hole structure 13 and may extend through the first insulating layer 4 and the second insulating layer 5 to electrically connect to the first surface 21 of the substrate 2. Furthermore, electrical contact 6 may extend further into the substrate 2. Electrical contact 6 may include a peripheral layer 65 and a central material 60. Peripheral layer 65 may be disposed on the sidewall of hole structure 13 and may define a central hole. The central hole defined by peripheral layer 65 may be filled with central material 60. Peripheral layer 65 may include titanium nitride (TiN), and central material 60 may include tungsten (W).

[0081] The electrical contact 6 may include a first portion 61, a second portion 62, and a third portion 63. The first portion 61 may be disposed in the first through-hole 43 of the first insulating layer 4 and may have a width W1. It should be noted that the width W1 of the first portion 61 may be the maximum width of the first portion 61 and may be substantially equal to the width W1 of the first through-hole 43 of the first insulating layer 4. The first portion 61 may include a portion of the peripheral layer 65 and a portion of the central material 60.

[0082] The second portion 62 may be disposed in the second through-hole 53 of the second insulating layer 5 and may have a width W2. It should be noted that the width W2 of the second portion 62 may be the maximum width of the second portion 62 and may be substantially equal to the width W2 of the second through-hole 53 of the second insulating layer 5. The second portion 62 may include a portion of the peripheral layer 65 and a portion of the central material 60. The ratio of the difference between width W1 and width W2 to width W1 may be less than 10%. That is, the ratio of (W1-W2) / W1 may be less than 10%, 9%, 8%, 7%, or 6%. Therefore, the gap (or tolerance) between the sidewall of the first portion 61 and the sidewall of the second portion 62 can be very small. The sidewalls of the first portion 61 and the sidewalls of the second portion 62 may be substantially aligned with each other.

[0083] The third portion 63 may be disposed in the recessed portion 25 of the substrate 2 and may have a width W3. It should be noted that the width W3 of the third portion 63 may be the maximum width of the third portion 63 and may be substantially equal to the width W3 of the recessed portion 25 of the substrate 2. The third portion 63 may include a portion of the peripheral layer 65 and a portion of the central material 60. The width W3 may be smaller than the widths W1 and W2. The low-resistance layer 26 may be substantially conformally conformal to the third portion 63 of the electrical contact 6.

[0084] The first portion 61, the second portion 62, and the third portion 63 of the electrical contact 6 can be integrally formed and simultaneously, making the electrical contact 6 a monolithic structure. The electrical contact 6 can be disposed between the first MOS transistor 3 and the second MOS transistor 3a. The electrical contact 6 can be electrically connected to an electrode of the first MOS transistor 3 and / or the second MOS transistor 3a. In some embodiments, a low-resistance layer 26 can be disposed between the electrical contact 6 and the drain 22 of the substrate 2, thereby reducing the resistance of the ohmic contact between the electrical contact 6 and the substrate 2.

[0085] The structure of electrical contact 6a can be the same as that of electrical contact 6.

[0086] like Figure 12 As shown, the distance D between the first gate structure 30 of the first MOS transistor 3 and the electrical contact 6 can decrease towards the first surface 21 of the substrate 2. For example, the distance D between the side surface 303 of the first gate structure 30 of the first MOS transistor 3 and the side surface 67 of the electrical contact 6 can gradually decrease towards the first surface 21 of the substrate 2. The distance D2 between the side surface 333 of the second gate conductor layer 33 and the side surface 67 of the electrical contact 6 can be greater than the distance D1 between the side surface 323 of the first gate conductor layer 32 and the side surface 67 of the electrical contact 6. Therefore, the width of the insulating material between the side surface 333 of the second gate conductor layer 33 and the side surface 67 of the electrical contact 6 is greater than the width of the insulating material between the side surface 323 of the first gate conductor layer 32 and the side surface 67 of the electrical contact 6. As a result, the parasitic capacitance between the first MOS transistor 3 and the electrical contact 6 can be reduced.

[0087] Figures 13 to 16 According to an embodiment of this disclosure, the various stages of a method for preparing an electrical structure 1a are shown. The initial stage of the method shown is related to... Figure 2 The stages shown are the same or similar. Figure 13 show Figure 2 The subsequent stage of the steps.

[0088] Reference Figure 13 It can be removed simultaneously, for example, by etching. Figure 2 A portion of the second gate conductor layer 33 and a portion of the first gate conductor layer 32, such that Figure 2 The second gate conductor layer 33 in the middle can become Figure 13 In the second gate conductor layer 33b, and Figure 2 The first gate conductor layer 32 can be a first gate conductor layer 32b. The first gate conductor layer 32b can have a substantially constant third width W5, and the second gate conductor layer 33b can have a substantially constant fourth width W4'. The fourth width W4' of the second gate conductor layer 33b can be substantially equal to the third width W5 of the first gate conductor layer 32b.

[0089] Furthermore, the width of the gate oxide layer 31b and the width of the upper layer 34b can be substantially equal to the third width W5 of the first gate conductor layer 32b. Therefore, the first gate structure 30b can present a single rectangular shape. Figure 13 The fourth width W4' of the second gate conductor layer 33b can be less than Figure 2 The second width is W12. Figure 13 The third width W5 of the first gate conductor layer 32b can be less than Figure 2 The first width is W11.

[0090] Reference Figure 14 A portion of the upper layer 34b and the second gate conductor layer 33b can be further removed, for example, by etching, such that the fourth width W4 of the second gate conductor layer 33b is smaller than the third width W5 of the first gate conductor layer 32b. The fourth width W4 of the second gate conductor layer 33b can be substantially constant and can be smaller than... Figure 13 The fourth width W4'. Therefore, a first gate structure 30b can be formed. The first gate structure 30b may include a stepped structure.

[0091] Similarly, the outline of the second gate structure 30c can be the same as the outline of the first gate structure 30b. The second gate structure 30c may include a gate oxide layer 31c, a first gate conductor layer 32c, a second gate conductor layer 33c, and an upper layer 34c, which may be the same as the gate oxide layer 31b, the first gate conductor layer 32b, the second gate conductor layer 33b, and the upper layer 33b of the first gate structure 30b, respectively.

[0092] Reference Figure 15 A first layer 36b may be conformally formed or disposed on the side surface 303 of the first gate structure 30b. A first layer 36c may be conformally formed or disposed on the side surface of the second gate structure 30c. The materials of the first layers 36b and 36c may include nitride materials. Then, a second layer 37b may be formed or disposed on the side surface of the first layer 36b and on a portion of the first surface 21 of the substrate 2. A second layer 37c may be formed or disposed on the side surface of the first layer 36c and on a portion of the first surface 21 of the substrate 2. The second layers 37b and 37c may taper upwards and may include oxide materials. For example, the side surface 353 of the first spacer 35b may include a recessed portion 354 corresponding to the stepped structure of the first gate structure 30b.

[0093] Then, a protective layer 380 can be formed, for example, by deposition, on the first layers 36b, 36c and the second layers 37b, 37c. The protective layer 380 may include a nitride material. The protective layer 380 may include a third layer 38b located on the second layer 37b of the first spacer 35b, and a third layer 38c located on the second layer 37c of the second spacer 35c. Therefore, the first spacer 35b may include the first layer 36b, the second layer 37b, and the third layer 38b. The second spacer 35c may include the first layer 36c, the second layer 37c, and the third layer 38c. Simultaneously, a first MOS transistor 3b and a second MOS transistor 3c may be formed, and they may be separable from each other. The first MOS transistor 3b may include a first gate structure 30b and a first spacer 35b disposed on the side surface 303 of the first gate structure 30b. The second MOS transistor 3c may include a second gate structure 30c and a second spacer 35c disposed on the side surface of the second gate structure 30c.

[0094] The initial stage of the method shown is Figures 5 to 12 The stages shown are the same or similar, thus forming Figure 16 Electrical structure 1a.

[0095] Figure 16 A cross-sectional schematic diagram of electrical structure 1a is shown according to an embodiment of the present disclosure. Figure 16 The electrical structure 1a can be with Figure 12 The electrical structure is similar to that of 1, and the differences are described below.

[0096] In electrical structure 1a, the first gate conductor layer 32b may have a substantially constant width W5. The second gate conductor layer 33b may have a substantially constant width W4. The substantially constant width W5 of the first gate conductor layer 32b may be greater than the substantially constant width W4 of the second gate conductor layer 33b. The side surface 333 of the second gate conductor layer 33b may be recessed from the side surface 323 of the first gate conductor layer 32b. Alternatively, the side surface 303 of the first gate structure 30b may have a higher portion (e.g., the side surface 333 of the second gate conductor layer 33b) and a lower portion (e.g., the side surface 323 of the first gate conductor layer 32b), both substantially perpendicular to the first surface 21 of the substrate 2. The higher portion of the side surface 303 (e.g., the side surface 333 of the second gate conductor layer 33b) may be recessed from the lower portion of the side surface 303 (e.g., the side surface 323 of the first gate conductor layer 32b).

[0097] Figure 17 A cross-sectional schematic diagram of electrical structure 1b is shown according to an embodiment of the present disclosure. Figure 17 The electrical structure 1b can be with Figure 12The electrical structure is similar to that of the first MOS transistor 3d, except that the side surface 303 of the first gate structure 30d of the first MOS transistor 3d can be a concave surface or a curved surface. Furthermore, the structure of the second MOS transistor 3e can be the same as that of the first MOS transistor 3d.

[0098] Figure 18 A cross-sectional schematic diagram of electrical structure 1c is shown according to an embodiment of the present disclosure. Figure 18 The electrical structure 1c can be with Figure 16 The electrical structure is similar to that of the first MOS transistor 3f, except that the second gate conductor layer 33b and the upper layer 34b of the first MOS transistor 3f can gradually taper from the first gate conductor layer 32b of the first gate structure 30f of the first MOS transistor 3f. Furthermore, the structure of the second MOS transistor 3g can be the same as that of the first MOS transistor 3f.

[0099] One aspect of this disclosure provides an electrical structure including a substrate and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is disposed on a first surface of the substrate and includes a gate structure. The gate structure has a top surface and a bottom surface opposite to the top surface. The width of the top surface is smaller than the width of the bottom surface.

[0100] Another aspect of this disclosure provides an electrical structure including a substrate, a metal-oxide-semiconductor (MOS) transistor, and an electrical contact. The MOS transistor is disposed on a first surface of the substrate and includes a gate structure. The electrical contact is disposed adjacent to the MOS transistor and electrically connected to the first surface of the substrate. The distance between the gate structure of the MOS transistor and the electrical contact decreases toward the first surface of the substrate.

[0101] Another aspect of this disclosure provides a method for fabricating an electrical structure. The method includes forming a gate structure on a first surface of a substrate. The method also includes removing a portion of the gate structure such that the width of a top surface of the gate structure is smaller than the width of a bottom surface of the gate structure. The method further includes forming a spacer on one side surface of the gate structure.

[0102] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0103] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. An electrical structure, comprising: One substrate; as well as A metal-oxide-semiconductor transistor is disposed on a first surface of the substrate and includes a gate structure having a top surface and a bottom surface opposite to the top surface, wherein a width of the top surface is smaller than a width of the bottom surface.

2. The electrical structure of claim 1, wherein the gate structure tapers gradually from the first surface of the substrate.

3. The electrical structure of claim 1, wherein the ratio of the width of the top surface to the width of the bottom surface is 1 / 4 to 1 / 2.

4. The electrical structure of claim 1, wherein the gate structure has a side surface extending between the top surface and the bottom surface, and the entire side surface is a flat, inclined surface.

5. The electrical structure of claim 4, wherein the gate structure is trapezoidal.

6. The electrical structure of claim 1, wherein the gate structure further has a side surface extending between the top surface and the bottom surface, and the side surface is a concave surface.

7. The electrical structure of claim 1, wherein the gate structure further has a side surface extending between the top surface and the bottom surface, wherein the side surface has a higher portion and a lower portion substantially perpendicular to the first surface of the substrate, and the higher portion of the side surface is recessed from the lower portion of the side surface.

8. The electrical structure of claim 1, wherein the gate structure includes a first gate conductive layer and a second gate conductive layer disposed on the first gate conductive layer, and the width of a top surface of the second gate conductive layer is smaller than the width of a bottom surface of the first gate conductive layer.

9. The electrical structure of claim 8, wherein both the first gate conductive layer and the second gate conductive layer taper gradually from the first surface of the substrate, and one side surface of the first gate conductive layer is aligned with one side surface of the second gate conductive layer.

10. The electrical structure of claim 8, wherein the first gate conductive layer has a substantially constant width, the second gate conductive layer has a substantially constant width, and the substantially constant width of the first gate conductive layer is greater than the substantially constant width of the second gate conductive layer.

11. The electrical structure of claim 10, wherein one side surface of the second gate conductive layer is recessed from one side surface of the first gate conductive layer.

12. The electrical structure of claim 8, wherein the gate structure further includes a gate oxide layer disposed below the first gate conductive layer and an upper layer disposed on the second gate conductive layer.

13. The electrical structure of claim 12, wherein both the gate oxide layer and the upper layer taper gradually from the first surface of the substrate.

14. The electrical structure of claim 12, wherein a bottom surface of the gate oxide layer is the bottom surface of the gate structure, and a top surface of the upper layer is the top surface of the gate structure.

15. The electrical structure of claim 1, wherein the metal-oxide-semiconductor transistor further comprises a spacer disposed on the gate structure.

16. The electrical structure of claim 15, wherein the spacer comprises a first layer, a second layer, and a third layer, wherein the first layer covers the gate structure and comprises a nitride material, wherein the second layer is disposed on the first layer and comprises an oxide material, and wherein the third layer covers the second layer and comprises a nitride material.

17. The electrical structure of claim 15, wherein one side surface of the spacer includes a recessed portion.

18. The electrical structure of claim 1, wherein the substrate comprises silicon, the gate structure comprises a first gate conductive layer and a second gate conductive layer, the first gate conductive layer comprises a polysilicon material, the second gate conductive layer is disposed on the first gate conductive layer and comprises a tungsten material.

19. The electrical structure as claimed in claim 1, further comprising: A first insulating layer is disposed on the first surface of the substrate; A second insulating layer is disposed on the first insulating layer; as well as An electrical contact extends through the first insulating layer and the second insulating layer to electrically connect the first surface of the substrate.

20. The electrical structure of claim 19, wherein the electrical contact comprises a first portion disposed in the first insulating layer and a second portion disposed in the second insulating layer, wherein the first portion and the second portion of the electrical contact are integrally formed and simultaneously formed.

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