Ligbt device and method of fabricating the same

Abstract

This invention provides a LIGBT device and its fabrication method. The LIGBT device includes: a semiconductor structure, an emitter region, a collector region, an anode contact region, a clamping structure, a gate structure, first and second electrodes, and a gate. The semiconductor structure includes a drift region, a base region, and a buffer region. The base region and the buffer region are located on the upper surface of the drift region. The emitter region is located on the upper surface of the base region. The collector region and the anode contact region are located on the upper surface of the buffer region. The clamping structure is located in the buffer region and includes an isolation structure, a clamping diode, and a floating electrode. The clamping diode includes a cathode region and an anode region. The floating electrode is electrically connected to the anode contact region and the clamping diode. The gate structure is located on the upper surface of the base region between the emitter region and the drift region. The first electrode and the gate are electrically connected to their respective regions. The second electrode is electrically connected to the collector region and the clamping structure. This invention avoids the negative resistance effect during device conduction by setting a clamping structure in the buffer region, thus improving device reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a LIGBT device and its fabrication method. Background Technology

[0002] With the acceleration of global industrialization, short-circuit anode LIGBT devices are widely used due to their advantages such as high input impedance, good conduction performance, and strong saturation current capability, such as... Figure 1 The diagram shows a cross-sectional view of an anode-short-circuited LIGBT device, including a substrate 01, buried oxide layer 011, drift region 012, base region 013, N-type emitter region 014, P-type contact region 015, N-type buffer region 016, P-type collector region 017, N-type contact region 018, emitter 02, collector 03, polysilicon gate 04, and gate oxide layer 041. In an anode-short-circuited LIGBT device, due to the heavily doped N-type contact region electrically connected to the collector in the N-type buffer region at the anode, the device initially enters unipolar mode during conduction. Then, as the voltage between the emitter and collector increases, the parasitic transistor turns on, and the device enters bipolar mode, resulting in a negative resistance effect that affects the device's switching speed, switching losses, and reliability. Currently, the potential of the N-type buffer zone below the P-type collector is usually reduced by increasing the length of the drift region between the P-type collector region and the N-type contact region, in order to suppress the device from entering unipolar mode, improve the device performance, and enhance the device reliability. However, this will lead to an increase in chip area and cost. Moreover, increasing the drift region resistance can only suppress the negative resistance effect of the device, but cannot eliminate the negative resistance effect of the device.

[0003] Therefore, there is an urgent need to find a LIGBT device that can reduce chip area, suppress the negative resistance effect of the device, and improve device performance. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a LIGBT device and its fabrication method, which solves the problems of negative resistance effect affecting device performance and large chip area in the short-circuit anode LIGBT device during the conduction process in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a LIGBT device, comprising:

[0006] A semiconductor structure includes a first conductivity type drift region, a second conductivity type base region, and a first conductivity type buffer region, wherein the base region and the buffer region are disposed at an interval on the upper surface layer of the drift region;

[0007] The first conductivity type emission region is located on the upper surface of the base region and is spaced at a predetermined distance from the side wall of the base region near the buffer zone;

[0008] The second conductivity type current collector area and the first conductivity type anode contact area are both located on the upper surface of the buffer zone;

[0009] A clamping structure is located in the buffer zone and includes an isolation structure, a clamping diode, and a floating electrode. The clamping diode includes a cathode region of a first conductivity type and an anode region of a second conductivity type. The floating electrode is electrically connected to the anode contact region and one electrode of the clamping diode.

[0010] A gate structure is located on the upper surface of the base region between the emission region and the drift region;

[0011] The first electrode is electrically connected to the emission region;

[0012] The second electrode is electrically connected to the collector region and the other electrode of the clamping diode, respectively.

[0013] The gate is electrically connected to the gate structure.

[0014] Optionally, the semiconductor structure further includes a substrate and a buried oxide layer stacked sequentially, with the drift region located on the upper surface of the buried oxide layer.

[0015] Optionally, the upper surface of the base region is further provided with a second conductivity type cathode contact region electrically connected to the first electrode, and the cathode contact region is adjacent to the sidewall of the emission region away from the buffer zone.

[0016] Optionally, the isolation structure is located at a predetermined distance from the base region on the side of the collector region and penetrates the buffer zone and the drift region. The anode contact region is located on the upper surface of the buffer zone on the side of the isolation structure close to the collector region. The cathode region is located on the upper surface of the buffer zone on the side of the isolation structure away from the collector region. The floating electrode is electrically connected to the anode contact region and the cathode region. The anode region is located on the upper surface of the buffer zone and is adjacent to the sidewall of the cathode region on the side away from the isolation structure. The second electrode is electrically connected to the anode region.

[0017] Optionally, the clamping structure further includes a doped region of a second conductivity type. The isolation structure is embedded in the buffer at a predetermined distance away from the base region on the side of the collector region. The anode contact region is located on the upper surface of the buffer on the side of the isolation structure close to the collector region. The doped region is located on the upper surface of the buffer on the side of the isolation structure away from the collector region. The anode region is located on the upper surface of the buffer and is adjacent to the sidewall of the doped region close to the isolation structure. The floating electrode is electrically connected to the anode contact region and the anode region. The cathode region is located on the upper surface of the doped region and is electrically connected to the second electrode.

[0018] Optionally, the doping concentration of the doped region is not greater than the doping concentration of the anode region.

[0019] Optionally, the bottom surface of the isolation structure is higher than the bottom surface of the drift region but not higher than the bottom surfaces of the current collector region, the anode contact region, and the doped region.

[0020] This invention also provides a method for fabricating a LIGBT device, comprising the following steps:

[0021] A semiconductor structure is provided, comprising a first conductivity type drift region, a second conductivity type base region, and a first conductivity type buffer region, wherein the base region and the buffer region are disposed at an interval on the upper surface layer of the drift region;

[0022] A first conductivity type emitter region is formed on the upper surface of the base region, a second conductivity type collector region and a first conductivity type anode contact region are formed on the upper surface of the buffer zone, and a clamping structure is formed in the buffer zone. The emitter region is spaced at a predetermined distance from the sidewall of the base region near the buffer zone. The clamping structure includes an isolation structure, a clamping diode and a floating electrode. The clamping diode includes a first conductivity type cathode region and a second conductivity type anode region. The floating electrode is electrically connected to the anode contact region and one electrode of the clamping diode.

[0023] A gate structure is formed on the upper surface of the base region located between the emission region and the drift region;

[0024] A first electrode electrically connected to the emitter region, a second electrode electrically connected to the collector region and the other electrode of the clamping diode, and a gate electrically connected to the gate structure are formed.

[0025] Optionally, before forming the emission region, an isolation structure embedded in the buffer is formed, and the anode contact region and the cathode region are formed simultaneously with the formation of the emission region. The anode contact region is located on the upper surface of the buffer on the side of the isolation structure closer to the base region, and the cathode region is located on the upper surface of the buffer on the side of the isolation structure away from the base region. The anode region is formed simultaneously with the formation of the current collector region. The anode region is located on the upper surface of the buffer and adjacent to the sidewall of the cathode region on the side away from the isolation structure. The floating electrode is formed simultaneously with the formation of the first electrode and the second electrode. The floating electrode is electrically connected to the cathode region and the anode contact region, and the second electrode is electrically connected to the anode region.

[0026] Optionally, the clamping structure further includes a second conductivity type doped region. Before forming the emitter region, the doped region located on the upper surface of the buffer and the isolation structure located at a predetermined distance from the base region and embedded in the buffer are formed. The emitter region is formed simultaneously with the anode contact region and the cathode region located on the upper surface of the doped region. The current collector region is formed simultaneously with the anode region located between the doped region and the isolation structure and adjacent to the sidewall of the doped region near the isolation structure. The first electrode and the second electrode are formed simultaneously with the floating electrode electrically connecting the anode region and the anode contact region. The second electrode is electrically connected to the cathode region.

[0027] As described above, the LIGBT device and its fabrication method of the present invention, by setting a clamping structure in the buffer, wherein one terminal of the clamping diode in the clamping structure is electrically connected to the anode contact area and the other terminal of the clamping diode is electrically connected to the second electrode, the potential of the buffer and the anode contact area is lower than the potential of the collector area by the clamping diode, which facilitates the turn-on of the parasitic transistor in the device and does not affect the extraction of carriers during the device turn-off process, eliminates the negative resistance effect during the device conduction process, eliminates the need to increase the length of the drift region, reduces the chip area, and improves the high-frequency characteristics and reliability of the device, thus having high industrial application value. Attached Figure Description

[0028] Figure 1 The diagram shows a cross-sectional structure of a LIGBT device with an anode short circuit.

[0029] Figure 2 The diagram shown is a cross-sectional view of the LIGBT device of the present invention.

[0030] Figure 3 The diagram shown is a schematic cross-sectional view of another LIGBT device according to the present invention.

[0031] Figure 4 Displayed as Figure 2 Equivalent circuit diagram of the device.

[0032] Figure 5 Displayed as Figure 1 Chinese components and Figure 2 The curve showing the change of current density with voltage Vce during the forward conduction process of the device.

[0033] Figure 6 Displayed as Figure 1 Chinese components and Figure 2 The turn-off curve of the device.

[0034] Figure 7 The diagram shown is a process flow chart of the fabrication method of the LIGBT device of the present invention.

[0035] Figure 8 The diagram shown is a cross-sectional view of the semiconductor structure used in the fabrication method of the LIGBT device of the present invention.

[0036] Figure 9 The diagram shown is a cross-sectional view of the LIGBT device fabrication method of the present invention after the isolation structure is formed.

[0037] Figure 10 The diagram shows a cross-sectional view of the LIGBT device fabrication method of the present invention after forming the intercalation structure, emitter region, collector region, and anode contact.

[0038] Figure 11 The diagram shown is a cross-sectional view of the LIGBT device fabrication method of the present invention after the gate structure is formed.

[0039] Explanation of icon numbers

[0040] 01 Substrate

[0041] 011 Buried Oxygen Layer

[0042] 012 Drift Zone

[0043] 013 Base Area

[0044] 014 N-type launch area

[0045] 015 P-type contact area

[0046] 016 N-type buffer

[0047] 017 P-type collector area

[0048] 018 N-type contact area

[0049] 02 Emitter

[0050] 03 Collector

[0051] 04 Polysilicon gate

[0052] 041 Gate oxide layer

[0053] 1. Semiconductor Structure

[0054] 11 Substrate

[0055] 12. Buried Oxygen Layer

[0056] 13 Drift Zone

[0057] 14 base regions

[0058] Launch Area 15

[0059] 16 Cathode contact area

[0060] 17 Buffer

[0061] 18 power collection areas

[0062] 19 Anode contact area

[0063] 2 Clamping Diodes

[0064] 21. Isolation Structure

[0065] 22 Cathode region

[0066] 23 Anode Zone

[0067] 24 Floating Electrode

[0068] 25 Doped Regions

[0069] 3. Grid structure

[0070] 31 Gate conductive layer

[0071] 32 Gate dielectric layer

[0072] 4 First electrode

[0073] 5 Second electrode Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] Please see Figures 2 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] Example 1

[0077] This embodiment provides a LIGBT device, such as Figure 2 and Figure 3The figures shown are schematic diagrams of two cross-sectional structures of the LIGBT device, including a semiconductor structure 1, a first conductivity type emitter region 15, a second conductivity type collector region 18, a first conductivity type anode contact region 19, a clamping structure, a gate structure 3, a first electrode 4, a second electrode 5, and a gate. The semiconductor structure 1 includes a first conductivity type drift region 13, a second conductivity type base region 14, and a first conductivity type buffer region 17. The base region 14 and the buffer region 17 are disposed on the upper surface of the drift region 13 at a distance from each other. The emitter region 15 is located on the upper surface of the base region 14 and is spaced at a predetermined distance from the sidewall of the base region 14 near the buffer region 17. The collector region 18 and the anode contact region 19 are both located on the upper surface of the buffer zone 17; the clamping structure is located in the buffer zone 17 and includes an isolation structure 21, a clamping diode 2, and a floating electrode 24. The clamping diode 2 includes a cathode region 22 of a first conductivity type and an anode region 23 of a second conductivity type. The floating electrode 24 is electrically connected to the anode contact region 19 and one electrode of the clamping diode 2; the gate structure 3 is located on the upper surface of the base region 14 between the emitter region 15 and the drift region 13; the first electrode 4 is electrically connected to the emitter region 15; the second electrode 5 is electrically connected to the collector region 18 and the other electrode of the clamping diode 2 respectively; the gate is electrically connected to the gate structure 3.

[0078] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0079] As an example, the semiconductor structure 1 also includes a substrate 11 and a buried oxide layer 12 stacked sequentially, with the drift region 13 located on the upper surface of the buried oxide layer 12.

[0080] Specifically, while ensuring device performance, the thickness, size, and shape of the substrate 11 can be selected according to the actual situation; the thickness of the buried oxide layer 12 can be selected according to the actual situation; and the thickness and doping concentration of the drift region 13 can be selected according to the actual situation.

[0081] Specifically, while ensuring device performance, the length of the drift region 13 between the base region 14 and the buffer zone 17 can be selected according to actual conditions; the doping concentration, size, shape, and thickness of the base region 14 can also be selected according to actual conditions. Here, the thickness refers to the distance between the bottom surface of the base region 14 and the top surface of the base region 14 (i.e., the top surface of the drift region 13).

[0082] As an example, the doping concentration of buffer 17 is greater than that of drift region 13.

[0083] Specifically, while ensuring device performance, the doping concentration, size, shape, and thickness of buffer 17 can be selected according to actual conditions. Here, thickness refers to the distance between the bottom surface of buffer 17 and the top surface of buffer 17 (i.e., the top surface of drift region 13).

[0084] Specifically, emitter region 15 is typically a heavily doped region. While ensuring device performance, the size, shape, thickness, and doping concentration of emitter region 15 can be selected according to actual conditions. Here, thickness refers to the distance between the bottom surface of emitter region 15 and its top surface (i.e., the top surface of base region 14).

[0085] As an example, the upper surface of the base region 14 is also provided with a second conductivity type cathode contact region 16 electrically connected to the first electrode 4, and the cathode contact region 16 is adjacent to the sidewall of the emitter region 15 on the side away from the buffer zone 17.

[0086] Specifically, the cathode contact region 16 is usually a heavily doped region. While ensuring device performance, the doping concentration, thickness, size and shape of the cathode contact region 16 can be selected according to the actual situation.

[0087] Specifically, the collector region 18 and the anode contact region 19 are typically heavily doped regions. While ensuring device performance, the doping concentration, thickness, size, and shape of the collector region 18 can be selected according to actual conditions; the doping concentration, thickness, size, and shape of the anode contact region 19 can also be selected according to actual conditions; the distance between the collector region 18 and the anode contact region 19 can be selected according to actual conditions. Preferably, the anode contact region 19 is adjacent to the sidewall of the collector region 18 on the side facing away from the base region 14, in order to reduce the chip area.

[0088] As an example, the isolation structure 21 is located at a predetermined distance from the base region 14 on the side of the collector region 18 and penetrates the buffer zone 17 and the drift region 13. The anode contact region 19 is located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 closest to the collector region 18. The cathode region 22 is located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 away from the collector region 18. The floating electrode 24 is electrically connected to the anode contact region 19 and the cathode region 22. The anode region 23 is located on the upper surface of the buffer zone 17 and is adjacent to the sidewall of the cathode region 22 on the side away from the isolation structure 21. The second electrode 5 is electrically connected to the anode region 23. Figure 2 As shown.

[0089] It should be noted that when the floating electrode 24 is electrically connected to the anode contact area 19 and the cathode area 22, and the second electrode 5 is electrically connected to the anode area 23, the anode contact area 19 may or may not be adjacent to the collector area 18, provided that the device performance is guaranteed; the isolation structure 21 may or may not be adjacent to the side wall of the anode contact area 19 away from the collector area 18; the cathode area 22 may or may not be adjacent to the side wall of the isolation structure 21 away from the anode contact area 19; and the anode area 23 may or may not be adjacent to the cathode area 22. Preferably, when the floating electrode 24 is electrically connected to the cathode region 22 and the anode contact region 19, and the second electrode 5 is electrically connected to the anode region 23, the two side walls of the anode contact region 19 are respectively adjacent to the current collecting region 18 and the isolation structure 21. The cathode region 22 is located on the side of the isolation structure 21 away from the current collecting region 18, and the two side walls of the cathode region 22 are respectively adjacent to the isolation structure 21 and the anode region 23.

[0090] Specifically, when the floating electrode 24 is electrically connected to the anode contact region 19 and the cathode region 22, and the second electrode 5 is electrically connected to the anode region 23, the cathode region 22 and the anode region 23 on the side of the isolation structure 21 away from the collector region 18 constitute a clamping diode 2. The second electrode 5 (i.e., the collector of the device) is electrically connected to the anode region 23. The anode contact region 19 is connected to the cathode region 22 through the floating electrode 24. By controlling the turn-on voltage of the clamping diode 2, making it greater than the turn-on voltage of the PN junction between the collector region 18 and the buffer zone 17, the turn-on voltage of the clamping diode 2 restrains the buffer zone 17. During the forward conduction of the device, the potential of the buffer zone 17 is lower than the potential required for the PN junction between the buffer zone 17 and the collector region 18 to turn on. The parasitic transistor in the device can conduct under low current conditions, causing the parasitic transistor in the device to turn on before the clamping diode 2. The device skips the unipolar mode and directly enters the bipolar mode, avoiding the conduction of the parasitic MOS structure composed of emitter region 15, base region 14, gate structure 3, drift region 13, buffer region 17 and anode contact region 19. This avoids the negative resistance effect during the device's conduction process. Furthermore, during the device's forward conduction, the parasitic transistor in the device can normally provide holes. During the device's turn-off, the anode contact region 19 is not affected in its extraction of carriers from the drift region 13, improving the device's performance and reliability. At the same time, it is not necessary to increase the length of the drift region 13 to reduce the potential of the buffer region 17, which greatly reduces the chip area.

[0091] As an example, the clamping structure also includes a second conductivity type doped region 25, an isolation structure 21 embedded in a buffer zone 17 at a predetermined distance from the base region 14 on the side of the collector region 18, an anode contact region 19 located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 near the collector region 18, a doped region 25 located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 away from the collector region 18, an anode region 23 located on the upper surface of the buffer zone 17 and adjacent to the sidewall of the doped region 25 near the isolation structure 21, a floating electrode 24 electrically connecting the anode contact region 19 and the anode region 23, and a cathode region 22 located on the upper surface of the doped region 25 and electrically connected to the second electrode 5. Figure 3 As shown.

[0092] It should be noted that the clamping structure includes a doped region 25, and the floating electrode 24 is electrically connected to the anode contact region 19 and the anode region 23. When the second electrode 5 is electrically connected to the cathode region 22, the anode contact region 19 may or may not be adjacent to the collector region 18, provided that the device performance is guaranteed. The isolation structure 21 may or may not be adjacent to the sidewall of the anode contact region 19 on the side away from the collector region 18. The anode region 23 may or may not be adjacent to the sidewall of the isolation structure 21 on the side away from the anode contact region 19. Preferably, when the floating electrode 24 is electrically connected to the anode region 23 and the anode contact region 19, and the second electrode 5 is electrically connected to the cathode region 22, the two side walls of the anode contact region 19 are respectively adjacent to the current collector region 18 and the isolation structure 21. The anode region 23 is located on the side of the isolation structure 21 away from the current collector region 18 and is adjacent to the isolation structure 21. The anode region 23 is adjacent to the side wall of the doped region 25 on the side closer to the current collector region 18.

[0093] Specifically, the drift region 13 is located on the upper surface of the buried oxide layer 12. When the isolation structure 21 penetrates the drift region 13 and completely isolates the drift region 13 and the buffer zone 17 from the region near the collector region 18, the cathode region 22 in the clamping structure is located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 away from the collector region 18 and is adjacent to the anode region 23. At the same time, the cathode region 22 is electrically connected to the second electrode 5.

[0094] As an example, the bottom surface of the isolation structure 21 is higher than the bottom surface of the drift region 13 but not higher than the bottom surfaces of the collector region 18, the anode contact region 19, and the doped region 25. Preferably, the isolation structure 21 extends through the buffer zone 17 and its bottom surface is flush with the bottom surface of the buffer zone 17.

[0095] Specifically, the clamping structure includes a doped region 25, and the floating electrode 24 is electrically connected to the anode region 23 and the anode contact region 19. When the second electrode 5 is electrically connected to the cathode region 22, the anode region 23 on the side of the isolation structure 21 away from the collector region 18, the doped region 25 adjacent to the anode region 23, and the cathode region 22 located on the upper surface of the doped region 25 together constitute the clamping diode 2. The second electrode 5 (i.e., the collector of the device) is electrically connected to the cathode region 22. The anode contact region 19 is connected to the anode region 23 through the floating electrode 24. During the forward conduction of the device, the clamping diode 2 is in the reverse cutoff stage. The reverse biased PN junction clamps the buffer 17, so that the parasitic MOS structure composed of the emitter region 15, the base region 14, the gate structure 3, the drift region 13, the buffer 17, and the anode contact region 19 in the device cannot conduct, thereby avoiding the voltage foldback phenomenon during the conduction process of the device. At the same time, during the reverse conduction of the device, the clamping diode 2 conducts forward, improving the reverse conduction capability of the device.

[0096] Specifically, the isolation structure 21 includes an isolation trench and an isolation filling layer that fills the isolation trench. While ensuring device performance, the opening size and opening shape of the isolation trench can be selected according to the actual situation.

[0097] Specifically, the material of the isolation filling layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0098] As an example, the doping concentration of the doped region 25 is not greater than that of the anode region 23. That is, when the floating electrode 24 is electrically connected to the anode region 23 and the anode contact region 19, and the second electrode 5 is electrically connected to the cathode region 22, the doping concentration of the doped region 25 is relatively low.

[0099] It should be noted that when the floating electrode 24 is electrically connected to the cathode region 22 and the anode contact region 19, and the second electrode 5 is electrically connected to the anode region 23, the cathode region 22 and the anode region 23 in the clamping structure are usually heavily doped regions to ensure good ohmic contact between the floating electrode 24 and the anode contact region 19, the cathode region 22, and the second electrode 5 and the anode region 23. The doping concentration, size, shape, and thickness of each region in the clamping structure can be selected according to actual conditions. When the floating electrode 24 is electrically connected to the anode region 23 and the anode contact region 19, and the second electrode 5 is electrically connected to the cathode region 22, the anode region 23 and the cathode region 22 are usually heavily doped regions to ensure good ohmic contact between the floating electrode 24 and the anode contact region 19, the anode region 23, and the second electrode 5 and the cathode region 22. Meanwhile, the doped region 25 is a lightly doped region, and the doping concentration, size, shape, and thickness of each region in the clamping structure can be selected according to actual conditions.

[0100] Specifically, in the arrangement direction of the base region 14 and the buffer zone 17, the two sidewalls of the gate structure 3 are respectively located directly above the emitter region 15 and the drift region 13. The gate structure 3 includes a gate dielectric layer 32 and a gate conductive layer 31 stacked sequentially. The gate dielectric layer 32 is located on the upper surface of the base region 14 between the emitter region 15 and the drift region 13. The size of the gate dielectric layer 32 is not smaller than the size of the gate conductive layer 31. Here, the size is the size of the plane perpendicular to the stacking direction of the substrate 11, the buried oxide layer 12, and the drift region 13.

[0101] Specifically, the thickness of the gate dielectric layer 32 can be selected according to the actual situation, while ensuring device performance.

[0102] Specifically, the gate dielectric layer 32 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the gate conductive layer 31 is made of polysilicon or other suitable conductive materials.

[0103] Specifically, the device also includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor structure 1, the emitter region 15, the collector region 18, and the clamping structure. The first contact hole penetrates the interlayer dielectric layer directly above the emitter region 15 and exposes the emitter region 15 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer directly above the collector region 18 and exposes the collector region 18 on its bottom surface. The third contact hole penetrates the interlayer dielectric layer directly above the gate conductive layer 31 and exposes the gate conductive layer 31 on its bottom surface.

[0104] It should be noted that when the upper surface of the base region 14 is provided with a cathode contact region 16, the first contact hole also penetrates the interlayer dielectric layer directly above the cathode contact region 16 and exposes the cathode contact region 16 on the bottom surface.

[0105] Specifically, the cathode region 22 in the clamping structure is electrically connected to the second electrode 5. The second contact hole also penetrates the interlayer dielectric layer directly above the cathode region 22 and exposes the cathode region 22 on the bottom surface. The first electrode 4 fills the first contact hole so as to achieve an ohmic contact between the second electrode 5 and the cathode region 22.

[0106] Specifically, the anode region 23 in the clamping structure is electrically connected to the second electrode 5. The second contact hole also penetrates the interlayer dielectric layer directly above the anode region 23 and exposes the anode region 23 on its bottom surface. The second electrode 5 fills the second contact hole to facilitate the formation of an ohmic contact between the second electrode 5 and the anode region 23.

[0107] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer can be selected according to the actual situation; the opening size and shape of the first contact hole can be selected according to the actual situation; the opening size and shape of the second contact hole can be selected according to the actual situation; and the opening size and shape of the third contact hole can be selected according to the actual situation.

[0108] It should be noted that when the anode contact area 19 is adjacent to the cathode area 22 or the anode area 23 and the isolation structure 21, the floating electrode 24 can be directly disposed to cover the isolation structure 21, the upper surface of the anode contact area 19 electrically connected to the floating electrode 24 and the upper surface of the cathode area 22 or the anode area 23 electrically connected to the floating electrode 24, while the interlayer dielectric layer covers the exposed surface of the floating electrode 24. Alternatively, a fourth contact hole can be disposed in the interlayer dielectric layer. The fourth contact hole penetrates the interlayer dielectric layer directly above the anode contact area 19 electrically connected to the floating electrode 24 and the cathode area 22 or the anode area 23 electrically connected to the floating electrode 24, respectively. The bottom surface of the fourth contact hole exposes the anode contact area 19 and the cathode area 22 or the anode area 23 electrically connected to the floating electrode 24.

[0109] Specifically, the material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0110] Specifically, the materials of the first electrode 4 (emitter), the second electrode 5, the gate, and the floating electrode 24 are commonly used electrode materials for semiconductor devices, which will not be elaborated here.

[0111] Specifically, such as Figure 4 As shown, Figure 2 The equivalent circuit diagram of the device is shown in the figure. The IGBT device is equivalent to a transistor controlled by an NMOS device. The clamping structure is equivalent to the clamping diode 2 which is forward biased when the device is forward-biased. As can be seen from the figure, during the forward conduction of the device, the clamping diode 21 clamps the potential of the base (buffer zone 17) of the parasitic transistor.

[0112] Specifically, such as Figure 5 and Figure 6 As shown, they are respectively Figure 2 Chinese components and Figure 1 The curve showing the change in current density as a function of voltage Vce (the voltage between the emitter and collector of the device) during the forward conduction process of the device. Figure 2 Chinese components and Figure 1 The turn-off curve of the device, where, Figure 1 Chinese components and Figure 2 The drift region 13 of both devices is 13 μm in length, and the location, doping concentration, and size of the same region are identical in both devices. Figure 2The size and doping concentration of the anode region 23 in the device are the same as those of the collector region 18, and the size and doping concentration of the cathode region 22 are the same as those of the emitter region 15. Figure 5 It can be seen from this that Figure 2 The device does not exhibit a negative resistance effect during forward conduction, and at lower voltages, it performs better than... Figure 1 The medium-sized device has a higher current density and is easier to drive than the medium-sized device. Figure 1 Middle components; from Figure 6 It can be seen from this that Figure 2 The turn-off performance of the device is significantly better than that of the other device. Figure 1 The turn-off performance of the device is improved by setting a clamping structure, which eliminates the negative resistance effect during the device's conduction process and enhances the device's high-frequency characteristics.

[0113] Specifically, by setting a clamping structure including an isolation structure 21, an anode region 23, and a cathode region 22 in the buffer 17 of the device, the anode region 23 and the cathode region 22 constitute a clamping diode 2 electrically connected to the second electrode 5 and the anode contact region 19. The anode contact region 19 located on the side of the isolation structure 21 near the collector region 18 is electrically connected to the anode region 23 or the cathode region 22 of the clamping diode 2 through a floating electrode 24. This makes the potential of the anode contact region 19 and the buffer 17 on the side of the clamping structure near the collector region 18 lower than the potential of the collector region 18, which facilitates the turn-on of the parasitic transistor in the device, eliminates the negative resistance effect during the device conduction process, and improves the performance and reliability of the device.

[0114] The LIGBT device fabrication method of this embodiment improves the device structure by setting a clamping structure including an isolation structure 21, a clamping diode 2, and a floating electrode 24 in the buffer 17. The floating electrode 24 is electrically connected to the anode contact area 19 located on the side of the isolation structure 21 near the collector area 18 and one pole of the clamping diode 2. The second electrode 5 is electrically connected to the other pole of the clamping diode 2, so that the potential of the buffer 17 and the anode contact area 19 is lower than the potential of the collector area 18. This facilitates the turn-on of parasitic transistors in the device and does not affect the extraction of charge carriers during the device turn-off process. It eliminates the negative resistance effect during the device conduction process, reduces the chip area, and improves the high-frequency characteristics and reliability of the device.

[0115] Example 2

[0116] This embodiment also provides a method for fabricating a LIGBT device, such as... Figure 7 The diagram shown is a process flow chart of the fabrication method of the LIGBT device, including the following steps:

[0117] S1: A semiconductor structure is provided including a first conductivity type drift region, a second conductivity type base region, and a first conductivity type buffer region, wherein the base region and the buffer region are disposed at intervals on the upper surface layer of the drift region;

[0118] S2: Form a first conductivity type emitter region located on the upper surface of the base region, a second conductivity type collector region located on the upper surface of the buffer zone, a first conductivity type anode contact region, and a clamping structure located in the buffer zone. The emitter region is spaced apart from the sidewall of the base region near the buffer zone by a predetermined distance. The clamping structure includes an isolation structure, a clamping diode, and a floating electrode. The clamping diode includes a first conductivity type cathode region and a second conductivity type anode region. The floating electrode is electrically connected to the anode contact region and one electrode of the clamping diode.

[0119] S3: Form a gate structure on the upper surface of the base region located between the emission region and the drift region;

[0120] S4: Form a first electrode electrically connected to the emitter region, a second electrode electrically connected to the collector region and the other electrode of the clamping structure respectively, and a gate electrically connected to the gate structure.

[0121] Please see Figures 8 to 10 Steps S1 and S2 are executed as follows: A semiconductor structure 1 is provided, including a first conductivity type drift region 13, a second conductivity type base region 14, and a first conductivity type buffer region 17. The base region 14 and the buffer region 17 are disposed on the upper surface of the drift region 13 at intervals. A first conductivity type emitter region 15 is formed on the upper surface of the base region 14, a second conductivity type collector region 18 is formed on the upper surface of the buffer region 17, and a clamping structure is formed in the buffer region 17. The emitter region 15 and the sidewall of the base region 14 near the buffer region 17 are separated by a predetermined distance. The clamping structure includes an isolation structure 21, a clamping diode 2, and a floating electrode 24. The clamping diode 2 includes a first conductivity type cathode region 22 and a second conductivity type anode region 23. The floating electrode 24 is electrically connected to the anode contact region 19 and one electrode of the clamping diode 2.

[0122] Specifically, such as Figure 8 The diagram shows a cross-sectional view of semiconductor structure 1. Semiconductor structure 1 also includes a substrate 11 and a buried oxide layer 12 stacked sequentially. The substrate 11 is made of silicon, silicon germanium, silicon carbide, gallium nitride, or other suitable materials; the buried oxide layer 12 is made of silicon oxide or other suitable materials.

[0123] It should be noted that the drift region 13 is used to ensure the withstand voltage performance of the device. Typically, the drift region 13 is a lightly doped region with a low doping concentration. The base region 14 is typically used to form a lightly doped region for the conductive channel in the device. The buffer region 17 is typically used to reduce the on-state voltage drop of the device. The doping concentration of the buffer region 17 is generally greater than that of the drift region 13.

[0124] Specifically, the method for forming the emitter region 15 includes ion implantation or other suitable methods; the method for forming the collector region 18 includes ion implantation or other suitable methods; and the method for forming the anode contact region 19 includes ion implantation or other suitable methods.

[0125] Specifically, such as Figure 9 The diagram shows a cross-sectional view of the isolation structure 21 after its formation. The isolation structure 21 includes an isolation trench and an isolation filling layer that fills the isolation trench. The formation of the isolation structure 21 includes the following steps: forming a patterned masking layer covering the upper surface of the semiconductor structure 1; forming an isolation trench embedded in a buffer layer based on the patterned masking layer; forming an isolation filling material layer that fills the isolation trench and covers the upper surface of the semiconductor structure 1; and removing the isolation filling material layer that covers the upper surface of the semiconductor structure 1, leaving only the isolation filling material layer that fills the isolation trench as the isolation filling layer.

[0126] Specifically, the method for forming a patterned masking layer is the commonly used process of coating, drying, exposing, and developing photoresist layers, which will not be elaborated here.

[0127] Specifically, the methods for forming isolation trenches include dry etching, wet etching, or other suitable methods; the methods for forming isolation filling material layers include chemical vapor deposition, physical vapor deposition, or other suitable methods; and the methods for removing the isolation filling material layer covering the upper surface of the semiconductor structure 1 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods.

[0128] It should be noted that after the isolation trench is formed but before the filling isolation layer is formed, there is also a step of removing the masking layer. The method for removing the masking layer is the commonly used method for removing photoresist and hard mask layers, which will not be described in detail here.

[0129] As an example, such as Figure 10 The diagram shows a cross-sectional view of the clamping structure after it is formed. Before the emission region 15 is formed, an isolation structure 21 is formed embedded in the buffer zone 17. At the same time as the emission region 15 is formed, an anode contact region 19 and a cathode region 22 are formed. The anode contact region 19 is located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 that is close to the base region 14. The cathode region 22 is located on the upper surface of the buffer zone 17 on the side of the isolation structure 21 that is away from the base region 14. At the same time as the collector region 18 is formed, an anode region 23 is formed. The anode region 23 is located on the upper surface of the buffer zone 17 and is adjacent to the sidewall of the cathode region 22 that is away from the isolation structure 21. At the same time as the first electrode 4 and the second electrode 5 are formed, a floating electrode 24 is formed. The floating electrode 24 is electrically connected to the cathode region 22 and the anode contact region 19. The second electrode 5 is electrically connected to the anode region 23.

[0130] It should be noted that when the second electrode is formed subsequently, it is electrically connected to the anode region 23 to form an ohmic contact. When the anode contact region 19 and the cathode region 22 form an ohmic contact with the floating electrode 24, the anode contact region 19, the cathode region 22 and the emitting region 15 can be formed simultaneously or in stages. The anode region 23 and the collector region 18 can be formed in stages or simultaneously.

[0131] Specifically, when the second electrode formed subsequently is electrically connected to the anode region 23 and forms an ohmic contact, the isolation structure 21 penetrates the buffer zone 17 and the drift region 13 below the buffer zone 17. The anode region 23 and the cathode region 22 are located on the side of the isolation structure 21 away from the base region 14, and the buffer zone 17 and the drift region 13 are on the side of the isolation structure 21 close to the base region 14 and the side away from the base region 14.

[0132] As an example, the clamping structure also includes a second conductivity type doped region 25. Before forming the emitter region 15, a doped region 25 is formed on the upper surface of the buffer zone 17 and an isolation structure 21 is formed at a predetermined distance from the base region 14 on the side of the doped region 25 and embedded in the buffer zone 17. At the same time as forming the emitter region 15, an anode contact region 19 and a cathode region 22 are formed on the upper surface of the doped region 25. At the same time as forming the collector region 18, an anode region 23 is formed between the doped region 25 and the isolation structure 21 and adjacent to the sidewall of the doped region 25 near the isolation structure 21. At the same time as forming the first electrode 4 and the second electrode 5, a floating electrode 24 is formed that electrically connects the anode region 23 and the anode contact region 19. The second electrode 5 is electrically connected to the cathode region 22.

[0133] It should be noted that the clamping structure includes a doped region 25, a floating electrode 24, an isolation structure 21, an anode region 23, and a cathode region 22. When the subsequently formed second electrode is electrically connected to the cathode region 22 to form an ohmic contact, the floating electrode 24 forms ohmic contacts with the anode contact region 19 and the anode region 23, respectively. The doping concentration of the doped region 25 is not greater than the doping concentration of the anode region 23. Preferably, the doping concentration of the doped region 25 is less than the doping concentration of the anode region 23, and the doped region 25 is a lightly doped region to facilitate the control of the clamping voltage of the clamping structure. In this embodiment, the doping concentration range of the doped region 25 is 5 × 10⁻⁶. 16 ~1×10 17 .

[0134] Specifically, the methods for forming the cathode region 22 include ion implantation or other suitable methods; the methods for forming the anode region 23 include ion implantation or other suitable methods.

[0135] Specifically, the upper surface of the base region 14 also forms a second conductive type cathode contact region 16 that is electrically connected to the first electrode 4. The cathode contact region 16 is adjacent to the sidewall of the emitter region 15 on the side away from the buffer zone 17.

[0136] Specifically, the methods for forming the cathode contact region 16 include ion implantation or other suitable methods.

[0137] It should be noted that the contact type between the cathode contact area 16 and the subsequently formed first electrode is an ohmic contact. The contact area can be formed simultaneously with the current collector area 18, or it can be formed stepwise with the current collector area 18.

[0138] Please see Figure 11 Steps S3 and S4 are executed: a gate structure 3 is formed on the upper surface of the base region 14 located between the emitter region 15 and the drift region 13; a first electrode 4 electrically connected to the emitter region 15, a second electrode 5 electrically connected to the collector region 18 and the other electrode of the clamping diode 2 respectively, and a gate electrically connected to the gate structure 3 are formed.

[0139] Specifically, such as Figure 11 The diagram shows a cross-sectional view of the gate structure 3 after its formation. The gate structure 3 includes a gate dielectric layer 32 and a gate conductive layer 31 stacked sequentially. The formation of the gate structure 3 includes the following steps: forming a gate dielectric material layer and a gate conductive material layer stacked sequentially on the upper surface of the semiconductor structure 1 after forming the clamping structure, emitter region 15 and collector region 18; forming a patterned masking layer on the upper surface of the gate conductive material layer; etching the gate conductive material layer based on the patterned masking layer; the remaining gate conductive material layer serves as the gate conductive layer 31; and the gate dielectric material layer directly below the gate conductive layer 31 serves as the gate dielectric layer 32.

[0140] Specifically, methods for forming the gate dielectric material layer include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; methods for forming the gate conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0141] Specifically, the thickness of the gate dielectric material layer can be selected according to the actual situation, while ensuring the performance of the devices subsequently manufactured.

[0142] Specifically, the method for forming patterned masking layers is the commonly used photolithography process, which will not be elaborated here.

[0143] It should be noted that the gate dielectric layer 32 typically covers the exposed upper surfaces of the emitter region 15, the semiconductor structure 1, and the collector region 18. The two sidewalls of the gate conductive layer 31 formed after etching the gate conductive material layer are located directly above the emitter region 15 and the drift region 13, respectively. While ensuring device performance, the gate dielectric material layer can be etched after etching the gate conductive material layer based on the masking layer. The remaining gate dielectric material layer after etching is the gate dielectric layer 32.

[0144] Specifically, after forming the gate structure 3 and before forming the electrodes of the device (first electrode 4, second electrode 5 and gate), there is a step of removing the masking layer. The method for removing the masking layer is the commonly used photoresist or hard mask removal method, which will not be described in detail here.

[0145] Specifically, after forming the gate structure 3 and before forming each electrode of the device, the process further includes forming an interlayer dielectric layer covering the exposed upper surface of the emitter region 15, the semiconductor structure 1, the collector region 18, the clamping structure, and the exposed surface of the gate structure 3.

[0146] Specifically, methods for forming the interlayer dielectric layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0147] Specifically, after forming the interlayer dielectric layer and before forming the electrodes of the device, the process includes forming a first contact hole, a second contact hole, and a third contact hole. The first contact hole penetrates the interlayer dielectric layer directly above the emitter region 15 and exposes the emitter region 15 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer directly above the collector region 18 and the anode contact region 19 in the clamping structure that is electrically connected to the second electrode 5, and exposes the collector region 18 and the anode contact region 19 in the clamping structure that is electrically connected to the second electrode 5 on its bottom surface. The third contact hole penetrates the interlayer dielectric layer directly above the gate conductive layer 31 and exposes the gate conductive layer 31 on its bottom surface.

[0148] It should be noted that when the device is equipped with a floating electrode 24, a fourth contact hole is also formed in the interlayer dielectric layer. The fourth contact hole penetrates the interlayer dielectric layer directly above the area in the clamping structure that is electrically connected to the floating electrode 24, and the bottom surface exposes the area in the clamping structure that is electrically connected to the floating electrode 24.

[0149] Specifically, the first electrode 4 fills the first contact hole and is electrically connected to the emitter region 15 through the first contact hole; the second electrode 5 fills the second contact hole and is electrically connected to the collector region 18 at the bottom of the second contact hole; the gate fills the third contact hole and is electrically connected to the gate conductive layer 31 at the bottom of the third contact hole; the floating electrode 24 fills the fourth contact hole and is electrically connected to the anode contact region 19 and the area of ​​the clamping diode 2 exposed at the bottom of the fourth contact hole.

[0150] It should be noted that when the cathode contact area 16 is formed on the upper surface of the base region 14, the bottom surface of the first contact hole also exposes the cathode contact area 16, so as to facilitate the electrical connection between the first electrode 4 and the cathode contact area 16.

[0151] Specifically, the method for forming the first electrode 4, the second electrode 5, the gate electrode, and the floating electrode 24 is a commonly used electrode fabrication method, which will not be elaborated here.

[0152] Specifically, by forming a clamping structure in the buffer 17, one pole of the clamping diode 2 in the clamping structure is electrically connected to the anode contact area 19, and the other pole of the clamping diode 2 in the clamping structure is electrically connected to the second electrode 5, the high-frequency characteristics and reliability of the device are improved, and the negative resistance effect during the device conduction process is eliminated.

[0153] The LIGBT device fabrication method of this embodiment forms a clamping structure in the buffer 17. One pole of the clamping diode 2 in the clamping structure is electrically connected to the anode contact area 19 through the floating electrode 24, and the other pole of the clamping diode in the clamping structure is electrically connected to the second electrode 5. This eliminates the negative resistance effect during the device conduction process and improves the high-frequency characteristics and reliability of the device.

[0154] In summary, the LIGBT device and its fabrication method of the present invention, by setting a clamping structure in the buffer zone, wherein one terminal of the clamping diode in the clamping structure is electrically connected to the anode contact area through a floating electrode, and the other terminal of the clamping diode is electrically connected to the second electrode, the potential of the buffer zone and the anode contact area is restrained and kept lower than the potential of the collector region. This facilitates the turn-on of the parasitic transistor in the device without affecting the extraction of charge carriers during the device turn-off process, eliminates the negative resistance effect during the device conduction process, reduces the chip area, and improves the high-frequency characteristics and reliability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0155] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A LIGBT device, characterized in that, include: A semiconductor structure includes a first conductivity type drift region, a second conductivity type base region, and a first conductivity type buffer region, wherein the base region and the buffer region are disposed at an interval on the upper surface layer of the drift region; The first conductivity type emission region is located on the upper surface of the base region and is spaced at a predetermined distance from the side wall of the base region near the buffer zone; The second conductivity type current collector area and the first conductivity type anode contact area are both located on the upper surface of the buffer zone; A clamping structure is located in the buffer zone and includes an isolation structure, a clamping diode, and a floating electrode. The clamping diode includes a cathode region of a first conductivity type and an anode region of a second conductivity type. The floating electrode is electrically connected to the anode contact region and one electrode of the clamping diode. A gate structure is located on the upper surface of the base region between the emission region and the drift region; The first electrode is electrically connected to the emission region; The second electrode is electrically connected to the collector region and the other electrode of the clamping diode, respectively. The gate is electrically connected to the gate structure.

2. The LIGBT device according to claim 1, characterized in that: The semiconductor structure further includes a substrate and a buried oxide layer stacked sequentially, and the drift region is located on the upper surface of the buried oxide layer.

3. The LIGBT device according to claim 1, characterized in that: The upper surface of the base region is further provided with a second conductive type cathode contact region electrically connected to the first electrode, and the cathode contact region is adjacent to the side wall of the emission region away from the buffer zone.

4. The LIGBT device according to claim 1, characterized in that: The isolation structure is located at a predetermined distance from the base region of the collector region and penetrates the buffer zone and the drift region. The anode contact region is located on the upper surface of the buffer zone on the side of the isolation structure close to the collector region. The cathode region is located on the upper surface of the buffer zone on the side of the isolation structure away from the collector region. The floating electrode is electrically connected to the anode contact region and the cathode region. The anode region is located on the upper surface of the buffer zone and is adjacent to the sidewall of the cathode region on the side away from the isolation structure. The second electrode is electrically connected to the anode region.

5. The LIGBT device according to claim 1, characterized in that: The clamping structure further includes a second conductivity type doped region. The isolation structure is embedded in the buffer at a predetermined distance away from the base region on the side of the collector region. The anode contact region is located on the upper surface of the buffer on the side of the isolation structure close to the collector region. The doped region is located on the upper surface of the buffer on the side of the isolation structure away from the collector region. The anode region is located on the upper surface of the buffer and is adjacent to the sidewall of the doped region close to the isolation structure. The floating electrode is electrically connected to the anode contact region and the anode region. The cathode region is located on the upper surface of the doped region and is electrically connected to the second electrode.

6. The LIGBT device according to claim 5, characterized in that: The doping concentration in the doped region is not greater than the doping concentration in the anode region.

7. The LIGBT device according to claim 5, characterized in that: The bottom surface of the isolation structure is higher than the bottom surface of the drift region but not higher than the bottom surfaces of the current collecting region, the anode contact region, and the doped region.

8. A method for fabricating a LIGBT device, characterized in that, Includes the following steps: A semiconductor structure is provided, comprising a first conductivity type drift region, a second conductivity type base region, and a first conductivity type buffer region, wherein the base region and the buffer region are disposed at an interval on the upper surface layer of the drift region; A first conductivity type emitter region is formed on the upper surface of the base region, a second conductivity type collector region and a first conductivity type anode contact region are formed on the upper surface of the buffer zone, and a clamping structure is formed in the buffer zone. The emitter region is spaced at a predetermined distance from the sidewall of the base region near the buffer zone. The clamping structure includes an isolation structure, a clamping diode and a floating electrode. The clamping diode includes a first conductivity type cathode region and a second conductivity type anode region. The floating electrode is electrically connected to the anode contact region and one electrode of the clamping diode. A gate structure is formed on the upper surface of the base region located between the emission region and the drift region; A first electrode electrically connected to the emitter region, a second electrode electrically connected to the collector region and the other electrode of the clamping diode, and a gate electrically connected to the gate structure are formed.

9. The method for fabricating a LIGBT device according to claim 8, characterized in that: Before forming the emission region, an isolation structure embedded in the buffer is formed, and the anode contact region and the cathode region are formed simultaneously with the formation of the emission region. The anode contact region is located on the upper surface of the buffer on the side of the isolation structure closer to the base region, and the cathode region is located on the upper surface of the buffer on the side of the isolation structure away from the base region. The anode region is formed simultaneously with the formation of the current collector region. The anode region is located on the upper surface of the buffer and adjacent to the sidewall of the cathode region on the side away from the isolation structure. The floating electrode is formed simultaneously with the formation of the first electrode and the second electrode. The floating electrode is electrically connected to the cathode region and the anode contact region, and the second electrode is electrically connected to the anode region.

10. The method for fabricating a LIGBT device according to claim 8, characterized in that: The clamping structure further includes a second conductivity type doped region. Before forming the emitter region, the doped region is formed on the upper surface of the buffer and the isolation structure is formed at a predetermined distance from the base region and embedded in the buffer. The emitter region is formed simultaneously with the anode contact region and the cathode region on the upper surface of the doped region. The current collector region is formed simultaneously with the anode region located between the doped region and the isolation structure and adjacent to the sidewall of the doped region near the isolation structure. The first electrode and the second electrode are formed simultaneously with the floating electrode electrically connecting the anode region and the anode contact region. The second electrode is electrically connected to the cathode region.

Images