Semiconductor manufacturing method and semiconductor device

Abstract

A semiconductor manufacturing method and a semiconductor device, the method comprising: forming a stack of alternating nanostructure channels and sacrificial layers over a substrate; forming a source / drain opening extending through the stack; forming respective first dielectric layers on the nanostructure channels by flowing a first gas in the source / drain opening; forming a second dielectric layer on the sacrificial layer by flowing a first gas mixture including the first gas and a second gas in the source / drain opening; removing the second dielectric layer from the sacrificial layer by flowing a second gas mixture including the first gas and a third gas in the source / drain opening; forming an inner spacer opening by recessing the sacrificial layer after removing the second dielectric layer; and forming an inner spacer in the inner spacer opening.

Description

Technical Field

[0001] The present invention relates to a method and related apparatus for forming a field-effect transistor. Background Technology

[0002] Semiconductor devices are formed on, in, and / or from semiconductor wafers and are used in a wide range of electronic devices, such as mobile phones, laptops, desktop computers, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronic devices. One or more semiconductor manufacturing processes are performed to form semiconductor devices on, in, and / or from semiconductor wafers. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method is provided, comprising: forming a stack of alternating nanostructured channels and sacrificial layers over a substrate; forming a source / drain opening extending through the stack; forming respective first dielectric layers on the nanostructured channels by flowing a first gas in the source / drain opening; forming a second dielectric layer on the sacrificial layer by flowing a first gas mixture including the first gas and a second gas in the source / drain opening; removing the second dielectric layer from the sacrificial layer by flowing a second gas mixture including the first gas and a third gas in the source / drain opening; forming an inner spacer opening by recessing the sacrificial layer after removing the second dielectric layer; and forming an inner spacer in the inner spacer opening.

[0004] According to some embodiments of this disclosure, a method is provided comprising: forming a stack of alternating nanostructured channels and sacrificial layers over a substrate; forming a source / drain opening extending through the stack; performing a pretreatment process comprising: flowing a first gas into the source / drain opening; and flowing a first gas mixture comprising the first gas, a second gas, and a third gas into the source / drain opening; after performing the pretreatment process, forming an inner spacer opening by recessing the sacrificial layer; and forming an inner spacer in the inner spacer opening.

[0005] According to some embodiments of this disclosure, a semiconductor device is provided, the device comprising: a stack of nanostructured channels over a substrate, the nanostructured channels including a first channel and a second channel offset from each other; a source / drain region abutting the nanostructured channels; an inner spacer positioned between the first channel and the second channel; and a gate structure extending through an opening adjacent to the first channel, the second channel and the inner spacer, the gate structure in the opening including: a linewidth roughness of not more than 3 nanometers (nm); a first corner region associated with a first angle in the range of about 60 degrees to about 90 degrees; and a second corner region associated with a second angle in the range of about 60 degrees to about 90 degrees, the difference between the first angle and the second angle in the range of 0 degrees to about 5 degrees. Attached Figure Description

[0006] The nature of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A side view of an apparatus according to some embodiments is shown.

[0008] Figure 2A and 2B A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0009] Figure 3A and 3B A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0010] Figure 4A , 4B And 4C illustrates a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0011] Figure 5A , 5B Figures 5C, 5D, 5E, and 5F illustrate a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0012] Figure 6A and 6B A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0013] Figure 7A and 7BA schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0014] Figure 8A and 8B A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0015] Figure 9A and 9B A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0016] Figure 10A and 10B A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0017] Figure 11 A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0018] Figure 12 A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0019] Figure 13 A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0020] Figure 14 A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0021] Figure 15 A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0022] Figure 16 A schematic diagram illustrating a method for forming an apparatus at an intermediate manufacturing stage according to some embodiments.

[0023] Figure 17 Here is a flowchart illustrating a method according to some embodiments.

[0024] Figure 18 Here is a flowchart illustrating a method according to some embodiments.

[0025] Figure 19 An example computer-readable medium according to some embodiments is illustrated, which may contain processor-executable instructions configured to embody one or more of the settings set forth herein. Detailed Implementation

[0026] The following disclosure provides several different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, a first feature formed on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, references to numbers or letters may be repeated throughout the disclosure in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0027] Additionally, for ease of explanation, this application may use spatial relative terms such as "under," "below," "below," "above," "on top," and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations illustrated in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used in this application may be interpreted accordingly.

[0028] The terms "overlying" and / or similar terms can be used to describe an element or feature that is perpendicularly overlapped with another element or feature and is at a higher height than the other element or feature. For example, if a first element is at a higher height than a second element, then the first element overlies the second element, and at least a portion of the first element is perpendicularly overlapped with at least a portion of the second element.

[0029] The term "underlying" and / or similar terms can be used to describe an element or feature that is perpendicularly aligned with another element or feature and is at a lower height than the other element or feature. For example, if a first element is at a lower height than a second element, then the first element is underlying the second element, and at least a portion of the first element is perpendicularly aligned with at least a portion of the second element.

[0030] The term "over" can be used to describe an element or feature that is at a higher height than another element or feature. For example, if a first element is at a higher height than a second element, then the first element is above the second element.

[0031] The term "under" can be used to describe an element or feature that is at a lower height than another element or feature. For example, if a first element is at a lower height than a second element, then the first element is under the second element.

[0032] Gate-all-around (GAA) silicon nanosheet structures are a type of nanostructured device that offers improved power performance and area scaling benefits compared to other nanoscale technologies such as fin field-effect transistors (FETs). For example, GAA structures may have increased drive current due to their wide effective channel width while maintaining short-channel control. In semiconductor nanostructures such as silicon nanosheet (NS) GAA structures, uniform loading of silicon-germanium sacrificial nanosheets benefits both device electrical performance and manufacturing yield. "Loading" can refer to the dimensional uniformity of the top, middle, and bottom nanosheets of the sacrificial nanosheet. A lateral sacrificial nanosheet etching process prepares for subsequent formation of an inner spacer that isolates an alternative gate from adjacent source / drain electrodes. This etching process reduces the size (e.g., width) of the sacrificial nanosheet. The resulting top-to-bottom dimensional loading uniformity can be reduced due to surface impurities, autodoping, and geometric effects, resulting in different etch rates for the top, middle, and bottom (or "TMB") sacrificial nanosheets.

[0033] In one embodiment, a pretreatment process is performed prior to a SiGe recess etching process, which can result in improved loading uniformity that benefits device and yield performance. The embodiments generally relate to methods for controlling the uniformity of sacrificial nanosheet dimensions, and more specifically to methods for controlling the uniformity of alternative gate dimensions to improve device performance. The pretreatment process may include allowing an oxygen-containing gas to flow, which is beneficial for improving TMB loading uniformity, dimensional variation, surface roughness, fillet radius and uniformity, and the like.

[0034] Figure 1 This illustration shows a portion of an integrated circuit (IC) device 10 manufactured according to an embodiment of the present disclosure, wherein the IC device 10 includes a nanostructure device 20. For simplicity of illustration, certain features may be described from... Figure 1 Intentionally removed from that view. (See reference) Figure 1 Detailed description of IC device 10 is provided for reference in understanding. Figure 2A-16 The scenario described in the embodiments.

[0035] Figure 1This diagram shows a portion of an IC device 10 including a nanostructure device 20. In some embodiments, the nanostructure device 20 may include an N-type FET (NFET), a P-type FET (PFET), or both. The IC device 10 may include transistors having different threshold voltages based on their function in the IC device. For example, input / output (IO) transistors may have the highest threshold voltage, core logic transistors may have the lowest threshold voltage, and a third threshold voltage between the threshold voltage of the IO transistors and the threshold voltage of the core logic transistors may also be used for other functional transistors, such as static random access memory (SRAM) transistors. Some circuit blocks within the IC device 10 may include two or more NFETs and / or PFETs having two or more different threshold voltages.

[0036] Reference Figure 1 The nanostructure device 20 is formed above and / or therein on a substrate 110 and typically includes a gate structure 200 that bridges and / or surrounds semiconductor channels 22A, 22B, 22C, also referred to as "nanostructures", which are located in self-isolation regions 36 (e.g., shallow trench isolation or "STI" structures). Figure 3A and 3B (As shown in the diagram) Above the semiconductor fin 32, which protrudes and is separated by the isolation region. Channels 22A-22C are abutted by corresponding source / drain regions 82. The source / drain regions may be referred to individually or collectively as source or drain, depending on the context. The respective gate structures 200 are operable to increase and / or decrease current flow through the source / drain regions 82 of channels 22A-22C. Channels 22A-22C are optionally located above the fin 32. In some embodiments, the fin 32 and substrate 110 are absent, for example, when the fin 32 and substrate 110 are removed during the process of forming a back-side interconnect structure (e.g., including a back-side power rail, a back-side signal line, or both).

[0037] The substrate 110 is or includes at least one of the following: silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonyide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. The substrate 110 may include at least one of the following: single-crystal silicon, having… <100> Crystalline silicon with oriented crystallization, <110> Crystalline silicon with oriented crystallization, <111> Crystalline silicon or other suitable materials with oriented crystal structure. Other structures and / or configurations of the substrate 110 are within the scope of this disclosure.

[0038] Channels 22A-22C comprise semiconductor materials, such as silicon or silicon compounds, such as silicon germanium or the like. In some embodiments, fin structure 32 comprises silicon. Channels 22A-22C are nanostructures (e.g., having a size in the range of a few nanometers) and may each have an elongated shape and extend in the X direction. In some embodiments, channels 22A-22C each have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A-22C may be rectangular, circular, square, elliptical, hexagonal, or a combination thereof.

[0039] In some embodiments, the lengths of channels 22A-22C (e.g., measured in the X-axis direction) may differ from each other, for example, due to tapering during a fin etching process. In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. The length difference of channels 22A-22C may be referred to as "loading," and "loading uniformity" may refer to the degree to which the respective lengths are similar to each other.

[0040] Channels 22A-22C may not each have a uniform thickness, for example, due to channel trimming processes used to extend the spacing between channels 22A-22C (e.g., measured in the Z direction) to increase the gate structure fabrication process window. For instance, a middle portion of each of channels 22A-22C may be thinner than the ends of each of channels 22A-22C. This shape can be collectively referred to as a "dog-bone" shape.

[0041] In some embodiments, the spacing between adjacent pairs of channels 22A-22C along the Z-axis (e.g., between the middle channel 22B and the bottom channel 22A or the top channel 22C) is in the range of about 8 nanometers (nm) to about 12 nm. Other spacings smaller than about 8 nm are also contemplated as embodiments of the present invention. For example, in some embodiments, the spacing does not exceed about 3 nm. In some embodiments, the thickness of each of channels 22A-22C (e.g., measured in the Z-direction) is in the range of about 5 nm to about 8 nm. Other thicknesses smaller than about 5 nm are also contemplated as embodiments of the present invention. For example, in some embodiments, the thickness of each of channels 22A-22C does not exceed about 3 nm. In some embodiments, the thickness of each of channels 22A-22C (e.g., measured in the Y-axis direction, not shown in the figure) is... Figure 1In the case of a channel 22A-22C (orthogonal to the XZ plane), the width is at least about 8 nm. Other widths less than about 8 nm are also contemplated as embodiments of this invention. It should be understood that due to the size reduction of each successive semiconductor manufacturing node (e.g., 4 nm, 3 nm, etc.), the spacing, thickness, and width of channels 22A-22C can be smaller than those just described.

[0042] Gate structures 200 are respectively disposed above and between channels 22A-22C. In some embodiments, the gate structure 200 includes at least: (1) an interface layer (IL) 210, (2) one or more gate dielectric layers 600, and (3) a metal layer 290, which are referenced to Figure 14 Show and provide more detailed explanation.

[0043] The source / drain region 82 may include SiB, SiGe, SiGeB, or the like, and may include dopants such as Ge, Sb, B, or the like. In some embodiments, the source / drain region 82 includes silicon-phosphorus (SiP; Si:P), silicon-arsenic (SiAs, Si:As), or the like. In some embodiments, the source / drain region 82 has a width ranging from about 0.5 nm to about 100 nm (e.g., in the Y-axis direction). In some embodiments, the source / drain region 82 has a height ranging from about 0.1 nm to about 100 nm (e.g., in the Z-axis direction). The height of the source / drain region 82 can be measured from the interface between the respective source / drain region 82 and the dielectric layer 800 (or "flexible bottom isolation (FBI) layer 800" or "bottom isolation structure 800") disposed thereon to the top of the source / drain region 82. In some embodiments, the source / drain region 82 includes a first epitaxial region 82A, a second epitaxial region 82B on the first epitaxial region 82A, and a third epitaxial region 82C on the second epitaxial region 82B.

[0044] The nanostructure device 20 may include a gate or "sidewall" spacer 41 and an inner spacer 74 disposed on the sidewalls of the gate dielectric layer 600 and IL 210. The inner spacer 74 is disposed along the Z-axis between channels 22A-22C. The sidewall spacer 41 and the inner spacer 74 may include a dielectric material, such as a low-k material, such as SiOCN, SION, SiN, SiCN, or SiOC. In some embodiments, the sidewall spacer 41 may include one or more spacer layers. For example, such as Figure 1As shown, the sidewall spacer 41 includes a spacer layer. In some embodiments, the thickness of the inner spacer 74 (e.g., in the X-axis direction) is in the range of about 3 nm to about 10 nm. In some embodiments, the thickness of the sidewall spacer 41 (e.g., in the X-axis direction) is in the range of about 3 nm to about 10 nm. It should be understood that due to the size reduction of the various successive semiconductor manufacturing nodes (e.g., 4 nm, 3 nm, etc.), the thickness of the sidewall spacer 41, the inner spacer 74, or both may be smaller than those just described.

[0045] The nanostructure device 20 includes a bottom isolation structure 800 below the source / drain region 82. The bottom isolation structure 800 is formed at the bottom of the cavity of the source / drain region 82 and helps to reduce the volume of the source / drain region 82, thereby reducing the effective capacitance. The bottom isolation structure 800 also helps to constrain the growth of the source / drain region 82 from the edges of channels 22A-22C, and substantially prevents it from growing from the substrate 110. This can increase the strain of channels 22A-22C.

[0046] The bottom isolation structure 800 is or includes SiN, SiCN, SiCON, SiOC, SiC, SiO, or similar materials. The shape of the bottom isolation structure 800 can be a horizontal I-shape, a bowl shape, a disk shape, a U-shape, a V-shape, or similar, and can be selected by an etching process for forming the source / drain regions 82. The bottom isolation structure 800 can have a thickness in the range of about 1 nm to about 5 nm. The bottom isolation structure 800 can be formed by one or more conformal film deposition processes (e.g., a plasma-enhanced atomic layer deposition or "PEALD") followed by a film treatment (e.g., etching back), and can be a conformal film inheriting the shape of the underlying structure on which the bottom isolation structure is formed. Film deposition can be performed by a cyclic PEALD process using a reactive gas such as dichlorosilane (DCS) and an NH3 / Ar plasma. Film treatment (e.g., etching) can be performed using an Ar / N2 plasma.

[0047] exist Figure 1 In this configuration, a liner or "L0" layer 84 may be optionally disposed between the bottom isolation structure 800 and the substrate 110, fins 32, or both. In some embodiments, the liner layer 84 may be a silicon layer. In some embodiments, the liner layer 84 is absent. In embodiments where the liner layer 84 is present, the bottom isolation structure 800 may be a substantially horizontal thin layer; however, the bottom isolation structure 800 may be modified to have a U-shaped or V-shaped profile, such as... Figure 1 As shown in the image.

[0048] The source / drain region 82 may include one or more epitaxial regions, such as a first epitaxial region 82A, a second epitaxial region 82B, and a third epitaxial region 82C. The first epitaxial region 82A may be referred to as a first epitaxial layer or “L1” layer 82A. The second epitaxial region 82B may also be referred to as a second epitaxial layer or “L2” layer 82B, and is in contact with at least one of the following: (1) the first epitaxial layer 82A, (2) the inner spacer 74, (3) the bottom isolation structure 800, (4) an etch stop layer 131, (5) a silicide layer 118, and the like. The third epitaxial region 82C is in contact with the second epitaxial region 82B, the bottom isolation structure 800, and the silicide layer 118.

[0049] The nanostructure device 20 may include a source / drain contact 120 above one or more of the source / drain regions 82. The source / drain contact 120 may include one or more liner layers and a core conductive layer (in...). Figure 1 (Not shown separately). A silicide layer 118 may also be formed between the source / drain region 82 and the source / drain contact 120 to reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes one or more of the following: nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. For example, the silicide layer 118 may be TiSi, TiNiSi, NiSi, WSi, CoSi, MoSi, RuSi, or similar. In some embodiments, the thickness of the silicide layer 118 (in the Z-axis direction) is in the range of about 0.5 nm to about 10 nm, such as in the range of about 3 nm to about 10 nm. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 100 nm, such as in the range of about 10 nm to about 100 nm.

[0050] Although Figure 1 Not shown separately in the view, but the nanostructure device 20 may include an inter-dielectric layer (ILD) 130 on the etch-stop layer 131 (see, for example, see...). Figure 12 ILD 130 provides electrical isolation between the various components of the nanostructure device 20 discussed above, such as between and between the source / drain contacts 120 of the gate structures 200. An etch-stop layer 131 may be formed prior to the formation of ILD 130 and may be laterally positioned between ILD 130 and the sidewall spacer 41 and vertically positioned between ILD 130 and the source / drain region 82. In some embodiments, the etch-stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO2. x HfAlO x HfSiO xAl2O3 or other suitable materials. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1 nm to about 5 nm.

[0051] Figure 17 and 18 Flowcharts illustrating one or more embodiments of methods 1700 and 1800 for forming an IC device or a portion thereof from a workpiece, according to this disclosure, are provided. Methods 1700 and 1800 are merely exemplary and are not intended to limit this disclosure to those explicitly illustrated in methods 1700 and 1800. Additional actions may be provided before, during, and after methods 1700 and 1800, and some of the described actions may be substituted, eliminated, or moved for additional embodiments of the methods. For simplicity, not all actions are described in detail herein. For example, the formation of source / drain contacts 120, a front-side interconnect structure, a back-side interconnect structure, and the like may follow methods 1700 and 1800. The following description, in conjunction with embodiments according to methods 1700 and 1800, Figure 2A-16 Methods 1700 and 1800 are illustrated by partial perspective and / or cross-sectional views of a workpiece at different manufacturing stages. For the avoidance of ambiguity, throughout the figures, the X-axis is perpendicular to the Y-axis, and the Z-axis is perpendicular to both the X-axis and Y-axis. Note that because this workpiece can be manufactured into a semiconductor device, for the benefit of context, it may be referred to as a semiconductor device or simply as a "device". Methods 1700 and 1800 can be used to form... Figure 1 The device 10 illustrated in .

[0052] Figures 2A to 16 These are perspective and cross-sectional views of an intermediate stage in the fabrication of a nanostructure device, such as a gate all-around field-effect transistor (GAAFET), according to some embodiments. Figure 2A , 3A 4A, 5A, 6A, 7A and 12 are illustrative stereoscopic diagrams. Figure 2B , 3B Examples 4B and 14 are shown Figure 2A , 3A and the reference section B-B' (gate cut-off) illustrated in 4A. Figure 4C , 5B Examples of -5F, 8A, 9A, 10A, 11, 13 and 15 Figure 4A The reference section C-C' (vertical channel / fin cut) is illustrated in the figure. Figure 6B , 7B Examples 8B, 9B, 10B, and 16 are shown. Figure 6A The reference section B-B' (horizontal channel cut) is illustrated in the figure.

[0053] exist Figure 2A and 2BThe embodiment provides a substrate 110. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as monolayer, multilayer, or gradient substrates, may be used.

[0054] Subsequently, a multilayer stack 25 or "lattice" is formed over a substrate 110 consisting of alternating layers of first semiconductor layers 21A, 21B, and 21C (collectively referred to as first semiconductor layer 21) and a second semiconductor layer 23. In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for an n-type nanostructure device, such as silicon, silicon carbide, or the like, and the second semiconductor layer 23 may be formed of a second semiconductor material suitable as a sacrificial layer, such as silicon germanium, or the like, which can be etched with high selectivity relative to the material adjacent to the first semiconductor layer 21. Each of the layers in the multilayer stack 25 may be grown using programmed epitaxial growth methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.

[0055] The three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown in the figure. Figure 2A and 2B In some embodiments, the multilayer stack 25 may include one or two, four, five or more of each of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is illustrated to include a second semiconductor layer 23 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be a first semiconductor layer 21.

[0056] Because the second semiconductor material can be etched with high selectivity relative to the first semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form channel regions of nanostructure devices such as nanostructure devices 20.

[0057] exist Figure 3A and 3B In the middle, fins 32 are formed in the substrate 110 and nanostructures 22 and 24 are formed in the multilayer stack 25, corresponding to Figure 17 Action 1702 and Figure 18Action 1802. In some embodiments, nanostructures 22, 24 and fins 32 can be formed by etching trenches in the multilayer stack 25 and the substrate 110. The etching can be any acceptable etching procedure, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The first nanostructures 22A-22C (also referred to below as "channels") are formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The distance between adjacent fins 32 and nanostructures 22, 24 in the Y-axis direction can range from about 18 nm to about 100 nm. In some embodiments, this distance is less than 18 nm. For illustrative simplicity, a portion of the device 10 is illustrated in Figure 3A and 3B It includes two fins 32. (See reference...) Figure 2A-16 The methods 1700 and 1800 described herein can be extended to any number of fins, and are not limited to them. Figure 3A-16 The two fins 32 shown.

[0058] Figure 3A and 3B Example: A fin 32 with tapered sidewalls is shown such that the width of the fin 32 and each of the optionally chosen nanostructures 22, 24 increases continuously in the direction toward the substrate 110 along the Y-axis. In such embodiments, each of the nanostructures 22, 24 may have different widths and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fin 32 and the nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0059] exist Figure 3A and 3B In this configuration, an isolation region 36, which may be a shallow trench isolation (STI) region, is formed adjacent to the fins 32. The isolation region 36 can be formed by depositing an insulating material over the substrate 110, the fins 32, and the nanostructures 22, 24, and between the adjacent fins 32 and the nanostructures 22, 24. The insulating material can be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, a liner (not shown separately) can be first formed along the surfaces of the substrate 110, the fins 32, and the nanostructures 22, 24. Subsequently, a filler material, such as those discussed above, can be formed over the liner.

[0060] The insulating material undergoes a removal process, such as a chemical mechanical polishing (CMP), an etching process, a combination thereof, or the like, to remove excess insulating material above the nanostructures 22, 24. After the removal process is complete, the top surfaces of the nanostructures 22, 24 are exposed and flush with the insulating material. In some embodiments, one or more hard mask layers are present above the nanostructures 22, 24 to protect the nanostructures 22, 24 during the removal process to remove excess insulating material above the nanostructures 22, 24. After the removal process is complete, the hard mask layers are exposed and flush with the insulating material.

[0061] The insulating material is then recessed to form the isolation region 36. After recessing, the upper portions of the nanostructures 22, 24 and the fins 32 may protrude from between adjacent isolation regions 36. The isolation region 36 may have a flat, convex, concave, or a combination thereof top surface, as illustrated. In some embodiments, the isolation region 36 is recessed by a suitable etching process, such as removal using an oxide, for example, diluted hydrofluoric acid (dHF), which is selective for the insulating material and leaves the fins 32 and nanostructures 22, 24 substantially unchanged.

[0062] Figures 2A to 3B An embodiment of forming fins 32 and nanostructures 22, 24 is illustrated (e.g., post-etching). In some embodiments, fins 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in a dielectric layer (e.g., pre-etching). The epitaxial structure may comprise alternating semiconductor materials as discussed above, such as a first semiconductor material and a second semiconductor material.

[0063] In some embodiments, suitable pores (not shown separately) may be formed in fins 32, nanostructures 22, 24, and / or isolation region 36. Using a mask, n-type impurity implantation may be performed in the p-type region of substrate 110, while p-type impurity implantation may be performed in the n-type region of substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, or the like. Exemplary p-type impurities may include boron, boron fluoride, indium, or the like. An annealing process may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during the epitaxial growth of fins 32 and nanostructures 22, 24 may omit separate implantation, although in-situ and implantation doping may be used together.

[0064] The fins 32 and nanostructures 22, 24 can be patterned using any suitable method. For example, one or more photolithography processes, including dual patterning or multi-patterning processes, can be used to form the fins 32 and nanostructures 22, 24. Typically, dual or multi-patterning processes combine photolithography and self-alignment processes, allowing for smaller pitches than achievable using a single direct photolithography process in other ways. As an example of a multi-patterning process, a sacrificial layer can be formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can subsequently be used to pattern the fins 32.

[0065] exist Figure 4A , 4B In 4C, a dummy (or "sacrificial") gate structure 40 is formed over fins 32 and / or nanostructures 22, 24. A dummy or sacrificial gate layer 45 is formed over fins 32 and / or nanostructures 22, 24. The dummy gate layer 45 may be formed of a material with high etch selectivity relative to isolation region 36. The dummy gate layer 45 may be a conductive, semiconductive, or nonconductive material and may be or include one or more of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques suitable for depositing the selected material. A mask layer 47 is formed over the dummy gate layer 45 and may include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, a gate dielectric layer 43 is formed prior to a dummy gate layer 45 and positioned between the dummy gate layer 45 and the fins 32 and / or nanostructures 22, 24.

[0066] A spacer layer or sidewall spacer 41 is formed above the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the sidewall spacer 41 is or includes an insulating material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbide oxynitride, or the like, and may have a single-layer structure or a multilayer structure including multiple dielectric layers. Figure 4B The spacer layer illustrated includes a first spacer layer 41A and a second spacer layer 41B on the first spacer layer 41A. The sidewall spacers 41 can be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, portions of the spacer material layer between the dummy gate structures 40 are removed using an anisotropic etching process. In some embodiments, the sidewall spacers 41 cover the mask layer 47, such as... Figure 4B and Figure 4C As illustrated in the figure. In some embodiments, the mask layer 47 protrudes upward from between the sidewall spacers 41, as shown in the figure. Figure 4A As illustrated in the figure. In some embodiments, the mask layer 47 includes a first mask layer 47A and a second mask layer 47B on the first mask layer 47A.

[0067] Figures 4A-4C An example of a procedure for forming a sidewall spacer 41 is illustrated. In some embodiments, the sidewall spacer 41 is formed alternatively or additionally after the removal of the dummy gate layer 45. In such embodiments, the dummy gate layer 45 is removed, leaving an opening, and the sidewall spacer 41 can be formed by conformally coating the sidewall of the sidewall spacer 41 with a material along the sidewall of the opening. The conformally coated material can then be removed from the bottom of the opening corresponding to the top surface of the topmost channel, such as channel 22C, before forming an active gate, such as any of the gate structures 200.

[0068] exist Figure 5A and 5B In, corresponding to Figure 17 In action 1704, the source / drain trench 57 (or "source / drain opening 57") is formed by performing an etching process that recesses portions of the protruding fins 32 and / or nanostructures 22, 24 not covered by the dummy gate structure 40, resulting in the structure shown. This recess can be anisotropic, protecting portions of the fins 32 directly underlying the dummy gate structure 40 and sidewall spacers 41 from etching. In some embodiments, the etching process forming the source / drain trench 57 includes CH4, which can cause carbon to be embedded in the nanostructures 24. The carbon in the nanostructures 24 can cause a reduction in the width uniformity across the nanostructures 24 along the X-axis direction. In embodiments, carbon and other oxide particles are effectively removed by allowing oxygen, hydrogen, or both to flow into the source / drain trench 57, as described above. Figure 5C-5F illustrate.

[0069] According to some embodiments, the top surface of the recessed fin 32 may be substantially coplanar with the top surface of the isolation region 36, as shown. According to some other embodiments, the top surface of the recessed fin 32 may be lower than the top surface of the isolation region 36. Figure 5B Examples along Figure 5A A view of line C-C', for simplicity, illustrates three vertical stacks of nanostructures 22, 24 after the etching process. Generally, the etching process can be used to form any number of vertical stacks of nanostructures 22, 24 above the fin 32.

[0070] Figure 5C , 5D Examples of 5E and 5F are shown along Figure 5A A view of line C-C', which illustrates the pretreatment process performed on the second nanostructure 24 before the formation of the inner spacer 74. Figure 6A , 6B Views 7A and 7B illustrate the formation of nitride and oxide layers for removing particles 24P from nanostructure 24. In some embodiments, particles 24P may include silicon oxide (e.g., SiO2). x (SiO2), germanium oxide (e.g., GeO) x (e.g., GeO2) and the like, where "x" is in the range of about 1 to about 3. The pretreatment includes allowing oxygen, hydrogen, or both to flow into the source / drain trench 57, which is beneficial to improving the loading uniformity of the nanostructure 24 before its indentation and to improving the loading uniformity of the nanostructure 24 after its indentation.

[0071] exist Figure 5C In, corresponding to Figure 17 Action 1706 and Figure 18 Action 1806 causes a first gas to flow into the source / drain trench 57. In some embodiments, the first gas is nitrogen (N2). See reference... Figure 6A This first gas flow facilitates the formation of a thin nitride layer 22N (or "first dielectric layer 22N") on channels 22A-22C, which protects channels 22A-22C during the removal of particles 24P from nanostructure 24.

[0072] exist Figure 5D In, corresponding to Figure 17 Action 1708 causes a mixture of the first gas and a second gas to flow into the source / drain trench 57. In some embodiments, the second gas is oxygen (O2). Flowing this second gas facilitates the removal of carbon and / or other impurities (e.g., oxide particles) from the surface of the nanostructure 24. (See reference...) Figure 6A and 6BThe flow of the second gas oxidizes the surface of the nanostructure 24. By flowing the first gas and the second gas, the surfaces of channels 22A-22C are protected by the first gas (e.g., through a thin nitride layer 22N), while oxidation of the nanostructure 24 occurs via the second gas, which forms a dielectric layer 24O on the surface of the nanostructure 24. In some embodiments, the dielectric layer 24O is a thin layer of oxynitride. Therefore, the second gas can flow for a longer period, which is beneficial for increasing the uniformity of oxide thickness on the surfaces of the nanostructures 24. For example, a top nanostructure 24 between channels 22C and 22B may first be oxidized over an intermediate nanostructure 24 and a bottom nanostructure 24. Subsequently, the intermediate nanostructure 24 between channels 22B and 22A may be oxidized. Subsequently, the bottom nanostructure 24 between channel 22A and fin 32 may be oxidized. Therefore, the thickness of the dielectric layer 24O formed at each location in the nanostructure 24 can be substantially the same, which is beneficial to improving the loading uniformity of the nanostructure 24 before and after recessing. In some embodiments, after the first gas mixture is circulated, a first purging may be performed, such as by circulating N2 or another inert gas to clean the residual gas.

[0073] exist Figure 5E In, corresponding to Figure 17 In action 1710, after the first gas mixture is flowed and optionally purged, a second gas mixture comprising the first gas and a third gas is flowed into the source / drain trench 57. In some embodiments, the third gas is hydrogen (H2). This third gas is beneficial for removing carbon impurities from particles 24P of the nanostructure 24. By flowing the first gas with the third gas, the surfaces of channels 22A-22C are protected by a thin nitride layer 22N maintained by the first gas, while carbon removal occurs via the third gas. For example, if the thin nitride layer 22N were not present, H2 gas could attach to the silicon of channels 22A-22C, leading to the removal of material from channels 22A-22C. However, because the thin nitride layer 22N is formed and maintained on the surfaces of channels 22A-22C by the first gas, the reaction of H2 gas with channels 22A-22C is greatly reduced. In some embodiments, the third gas is beneficial for removing the dielectric layer 24O. In some embodiments, after the second gas mixture is circulated, a second purging may be performed, such as by circulating N2 or another inert gas to clean the residual gas.

[0074] exist Figure 5F In, corresponding to Figure 17 Action 1712 and Figure 18Action 1810 involves flowing a fourth gas into the source / drain trench 57. In some embodiments, the fourth gas is HF. This fourth gas can be beneficial in cleaning the source / drain trench 57 by removing a thin oxide layer 24O from the surface of the nanostructure 24 prior to recessing. In some embodiments, after the fourth gas is flowed, a third purging may be performed, such as by flowing N2 or another inert gas, to remove residual gas. (See reference...) Figure 7A and Figure 7B After the fourth gas is allowed to flow, a second thin layer 24O' can be formed on the nanostructure 24. For example... Figure 7B As shown, the pretreatment process can result in a smooth surface of the nanostructure 24 adjacent to the second thin layer 24O'. A measure of the smoothness or roughness of the surface of the nanostructure 24 is the linewidth roughness (LWR). Figure 7B In the process, the LWR of the surface of nanostructure 24 can be low due to the removal of particles 24P.

[0075] In reference Figure 5C-5F In the description, the pretreatment process includes flowing a first gas, then flowing a first gas mixture comprising the first and second gases, then flowing a second gas mixture comprising the first and third gases, and then flowing a fourth gas. In some embodiments, corresponding to Figure 18 Action 1808 does not involve first flowing the first gas mixture and then flowing the second gas mixture; rather, the first gas mixture may include a first gas, a second gas, and a third gas, and the second gas mixture may be omitted. For example, the first gas mixture may include nitrogen, oxygen, and hydrogen. The inventors have discovered that simultaneously flowing nitrogen, oxygen, and hydrogen has the benefits of improved loading uniformity and impurity removal, which can result in improved surface roughness or width uniformity at each of the nanostructures 24.

[0076] In some embodiments, refer to Figure 5C-5F The described preprocessing actions can be performed sequentially within the same processing chamber without automatically removing the wafer between processing chambers.

[0077] Figure 8A , 8B Examples 9A, 9B, 10A and 10B illustrate the formation of the inner spacer 74.

[0078] exist Figure 8A and Figure 8B In, corresponding to Figure 17 Action 1714 and Figure 18In action 1812, a selective etching process is performed to recess the end portions of the nanostructure 24 exposed through the openings in the sidewall spacers 41 without substantially attacking the nanostructure 22. In some embodiments, the selective etching process is performed using an etchant different from the one / other etchant used during the pretreatment process. For example, NF3 or another suitable etchant can be used to perform the selective etching process. After the selective etching process, a recess is formed at the location where the end portions of the nanostructure 24 have been removed. The resulting structure is shown in Figure 8A and 8B middle.

[0079] exist Figure 9A and 9B In the process, following a selective etching process that recesses the nanostructure 24, an inner spacer layer 74L is formed to fill the recesses in the nanostructure 24 formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material formed by a suitable deposition method, such as PVD, CVD, ALD, or the like, such as silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), or the like. For example, an ALD may be performed to deposit a SiN layer.

[0080] exist Figure 10A and 10B In the process, after depositing the inner spacer layer 74L, an etching process, such as an anisotropic etching process, is performed to remove a portion of the inner spacer layer 74L disposed outside the recess in the nanostructure 24. Corresponding to Figure 17 Action 1716 and Figure 18 In action 1814, the remaining portion of the inner spacer layer 74L (e.g., the portion disposed within the recess in the nanostructure 24) forms the inner spacer 74. The resulting structure is shown in... Figure 10A and 10B In the middle. The inner spacers 74 may have the same or different widths in the X-axis direction. For example, such as Figure 10A and 10B As shown, all the inner spacers 74 have substantially the same width.

[0081] Figure 11 An example of forming a source / drain region 82 is shown. In the illustrated embodiment, the source / drain region 82 is epitaxially grown from an epitaxial material. In some embodiments, the source / drain region 82 applies stress in the respective channels 22A-22C, thereby improving performance. The source / drain region 82 is formed such that each dummy gate structure 40 is disposed between a corresponding adjacent pair of source / drain regions 82. In some embodiments, sidewall spacers 41 separate the source / drain region 82 from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gate of the resulting device.

[0082] The source / drain region 82 may comprise any suitable material, such as that appropriate for an n-type or p-type device. For an n-type device, in some embodiments, the source / drain region 82 may comprise a material that applies a tensile strain in channels 22A-22C, such as silicon, SiC, SiCP, SiP, or the like. When forming a p-type device, according to some embodiments, the source / drain region 82 may comprise a material that applies a compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, or the like. The source / drain region 82 may have a surface raised from the respective surface of the fins 32 and may have facets, which are illustrated in... Figure 12 In some embodiments, adjacent source / drain regions 82 may be merged to form a single source / drain region 82 adjacent to two adjacent fins 32.

[0083] The source / drain region 82 can be implanted with dopants, followed by annealing. The source / drain region can have a density between approximately 10... 19 cm -3 With about 10 21 cm -3 The concentration of an impurity between these two values ​​could serve as a reference. Figure 1 Any of the dopant concentrations described. The n-type and / or p-type impurities used for the source / drain region 82 may be any of the impurities discussed with reference to the foregoing figures. In some embodiments, the source / drain region 82 is doped in situ during growth.

[0084] In some embodiments, forming the source / drain region 82 includes forming a liner layer 84, a bottom isolation structure 800, a first epitaxial region 82A, a second epitaxial region 82B, and a third epitaxial region 82C.

[0085] In some embodiments, the liner layer 84 is a silicon layer formed by a suitable growth operation. After the liner layer 84 is grown, it may have an upper surface that is substantially coplanar with the upper surface of the fin 32. In some embodiments, the upper surface of the liner layer 84 has a concave profile, such as... Figure 11 As illustrated. In some embodiments, the upper surface of the liner 84 is slightly higher than the bottom surface of the bottom inner spacer 74. In some embodiments, the liner 84 is not formed.

[0086] Subsequently, a bottom isolation structure 800 is formed in the source / drain trench 57. In some embodiments, the bottom isolation structure 800 is formed by a suitable process such as plasma-enhanced ALD and is or includes a dielectric material such as SiN. The bottom isolation structure 800 may include SiN, SiCN, SiCON, SiOC, SiC, SiO or the like, and may be deposited to a thickness of about 1-5 nm or slightly thick. After a conformal film deposition process (e.g., PEALD), a film treatment (e.g., etch-back) may be performed. The film deposition process may include a cyclic PEALD process with reactive gases of DCS and NH3 / Ar plasma, and the film treatment (e.g., etching) may be performed with Ar / N2 plasma. After the film treatment, the bottom isolation structure 800 may have a thickness in the range of about 1 nm to about 5 nm and be a horizontal I-shape, a bowl shape, a disk shape, a U-shape, a V-shape or other suitable shape that conforms to the reference as shown. Figure 5A and 5B The S / D trench 57 and the shape of the optional liner layer 84 are selected in the S / D trench etching process described.

[0087] Subsequently, source / drain regions 82 are epitaxially grown in the S / D trench 57. In some embodiments, a first epitaxial region 82A is formed in the S / D trench 57. Subsequently, a second epitaxial region 82B is formed on the first epitaxial region 82A in the S / D trench 57.

[0088] In some embodiments, a liner layer 84 may be disposed between the bottom isolation structure 800 and the substrate 110, fin 32, or both. In some embodiments, the liner layer 84 is not present. Each of the first epitaxial regions 82A may be formed in the S / D trench 57. Sequentially compressed SiGe:P or SiGe:As deposition allows for an epitaxial growth mechanism of sidewall (SW) growth, rather than bottom-to-top growth (e.g., growth starting from fin 32 or substrate 110). The bottom isolation structure 800 is disposed at the bottom of the S / D trench, so the SiGe:P or SiGe:As film formed at the bottom of the S / D trench may become amorphous and be removed during the selective epitaxial growth etching process. The sidewall SiGe:P or SiGe:As becomes crystalline and remains on the sidewalls, such as channels 22A-22B and optionally the internal spacers 74. The first epitaxial region 82A can be formed through multiple selective epitaxial growth processes (or so-called "cyclic deposition and etching processes"), which may include alternating or simultaneous deposition and etching operations. In some embodiments, the first epitaxial region 82A is not coupled and is offset from each other in the X-axis and Z-axis directions, such as... Figure 11 drawn.

[0089] After the formation of the first epitaxial region 82A, the second epitaxial region 82B can be formed by performing a second epitaxial growth process. In some embodiments, the first and second epitaxial growth processes are different, similar, or the same. In some embodiments, the first and second epitaxial growth processes are different stages of a single continuous growth process. In some embodiments, a visible interface exists between the first epitaxial region 82A and the second epitaxial region 82B. In some embodiments, the first epitaxial region 82A and the second epitaxial region 82B have the same or substantially the same Ge%, dopant atomic ratio, and dopant concentration. In some embodiments, one or more of the Ge%, dopant atomic ratio, and dopant concentration are different between the first epitaxial region 82A and the second epitaxial region 82B. A bottom isolation structure 800 is disposed at the bottom of the S / D trench, so that the SiGe:P or SiGe:As film formed at the bottom of the S / D trench can become amorphous and is removed during the selective epitaxial growth etching process. Figure 11 As shown, for example, after the first epitaxial region 82A is formed, the upper surface of each of the bottom isolation structures 800 may substantially lack the first epitaxial region 82A.

[0090] Subsequently, after forming the first epitaxial region 82A and the second epitaxial region 82B, a third epitaxial region 82C is formed. A third epitaxial growth process can be performed to form the third epitaxial region 82C. In some embodiments, a seam is formed during the formation of the third epitaxial region 82C. This seam may be formed due to the merging of the third epitaxial region 82C at its upper portion before its middle portion can be merged. In some embodiments, there is no seam, as illustrated in... Figure 11 The third epitaxial growth process can be similar to the first and second epitaxial growth processes in many respects, but different ratios of reactive gases and dopants can be used to make the third epitaxial region 82C different from the first epitaxial region 82A and the second epitaxial region.

[0091] exist Figure 12 In the process, after the source / drain region 82 is formed, an etch stop layer 131 and an interlayer dielectric (ILD) 130 are formed, which can cover the dummy gate structure 40 and the source / drain region 82.

[0092] exist Figure 13 In this process, channels 22A-22C are released by removing nanostructure 24, mask layer 47, and dummy gate layer 45. Subsequently, according to some embodiments, gate structure 200 is formed. A planarization process, such as chemical mechanical planarization (CMP), is performed to flush the top surfaces of the dummy gate layer 45 and sidewall spacers 41. The planarization process may also remove the mask layer 47 on the dummy gate layer 45 and portions of the sidewall spacers 41 along the sidewalls of the mask layer 47. Accordingly, the top surface of the dummy gate layer 45 is exposed.

[0093] Next, the dummy gate layer 45 is removed in an etching process, forming a recess. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the sidewall spacers 41. While the dummy gate layer 45 is being etched, the dummy gate dielectric 43 (if present) may serve as an etch stop layer. The dummy gate dielectric 43 may then be removed after the dummy gate layer 45 has been removed.

[0094] Nanostructure 24 is removed to release nanostructure 22. After removal of nanostructure 24, nanostructure 22 forms a plurality of nanosheets 22A, 22B, 22C extending horizontally (e.g., parallel to the main upper surface of substrate 110). Nanosheets 22A-22C can be collectively referred to as channels 22 of the formed nanostructure device 20.

[0095] In some embodiments, the nanostructure 24 is removed by using an etchant selectively selective to the material of the nanostructure 24, such that the nanostructure 24 is removed without substantially damaging the nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas comprises F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, or the like.

[0096] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by an additional etching process to improve the gate fill window. Reshaping can be performed by a selective isotropic etching process on the nanosheet 22. After reshaping, the nanosheet 22 may exhibit a dog-bone shape, wherein the central portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X-axis.

[0097] Subsequently, an alternative gate structure 200 is formed. The gate structure 200 generally includes an interface layer (IL or "first IL") 210, at least one gate dielectric layer 600, and a metal layer 290. (See reference...) Figure 14 The detailed structure and formation of the gate structure 200 are explained.

[0098] After the gate structure 200 is formed, a source / drain contact 120 may be formed on the source / drain region 82. In some embodiments, a silicide layer 118 is formed during the process of forming the source / drain contact 120.

[0099] Because the gate structure 200 essentially inherits the shape of the nanostructure 24, the loading uniformity of the gate structure 200 adjacent to the channels 22A-22C is improved, which improves the performance of the nanostructure device 20.

[0100] Figure 14 This is a detailed cross-sectional side view of a gate structure 200 according to various embodiments. In some embodiments, the gate structure 200 includes one or more of the following: (1) an interface layer 210, (2) a gate dielectric layer 600, (3) a second interface layer 240, (4) a work function barrier layer 700, (5) a work function metal layer 900, (6) a metal layer 290, or (7) an additional layer.

[0101] An interface layer 210 (which may be an oxide of the material of channels 22A-22C) is formed on the exposed areas of channels 22A-22C and on the top surface of fin 32 (when present). Interface layer 210 facilitates adhesion of the gate dielectric layer 600 to channels 22A-22C. In some embodiments, interface layer 210 has a thickness of about 5 angstroms (Å) to about 50 angstroms (Å). In some embodiments, interface layer 210 has a thickness of about 10 Å. Interface layer 210 that is too thin may exhibit voids or insufficient adhesion properties. Interface layer 210 that is too thick will consume the gate fill window, which is related to threshold voltage tuning and resistance as described above. In some embodiments, interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage tuning.

[0102] A gate dielectric layer 600 is positioned on the interface layer 210. In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant (k≈3.9) greater than that of silicon oxide. Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 Å to about 100 Å. In some embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, wherein at least one includes a dopant such as lanthanum, magnesium, yttrium, or the like, which can be driven by an annealing process to modify the threshold voltage of the nanostructure device 20.

[0103] In some embodiments, the gate dielectric layer 600 may include dopants of a concentration beneficial to achieving threshold voltage tuning, such as metal ions driven into the high-k gate dielectric from La2O3, MgO, Y2O3, TiO2, Al2O3, Nb2O5, or the like, or boron ions driven by B2O3. As an example, for N-type transistor devices, a higher concentration of lanthanum ions lowers the threshold voltage compared to a layer with a lower concentration or lack thereof, and the same is true for P-type devices. In some embodiments, the gate dielectric layer 600 of certain transistor devices (e.g., I / O transistors) lacks the dopants present in certain other transistor devices (e.g., N-type core logic transistors or P-type I / O transistors). In N-type I / O transistors, for example, a relatively high threshold voltage is desirable, such that the high-k dielectric layer of the I / O transistor is preferably free of lanthanum ions, which would otherwise lower the threshold voltage.

[0104] A second IL 240 is formed on the gate dielectric layer 600, and a work function barrier layer 700 is formed on the second IL 240. The second IL 240 is beneficial for improving metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 further improves the thermal stability of the gate structure 200 and reduces the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, forming the second IL 240 includes depositing a high-k capping layer (not illustrated for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer comprises one or more of the following: HfSiON, HfTaO, HfTiO, HfTaO, HfAION, HfZrO, or other suitable materials. In some embodiments, the high-k capping layer is or includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited via an ALD at a temperature of about 40 to about 450 degrees Celsius using about 40 to about 100 cycles. Subsequently, in some embodiments, a thermal annealing is performed to form a second IL 240, which may be or contain TiSiNO. After forming the second IL 240 via thermal annealing, atomic layer etching (ALE) with artificial intelligence (AI) control can be cycled to remove the high-k capping layer without substantially removing the second IL 240. Each cycle may include a first pulse of WCl5 followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further tuning of multiple threshold voltages by metal gate patterning.

[0105] According to some embodiments, a work function barrier layer 700 is optionally included in the gate structure 200. The work function barrier layer 700 is or contains a metal nitride, such as TiN, WN, MON, TaN, or the like. In a particular embodiment, the work function barrier layer 700 is TiN. The work function barrier layer 700 may have a thickness ranging from about 5 Å to about 20 Å. The inclusion of the work function barrier layer 700 provides additional threshold voltage tuning flexibility. Generally, the work function barrier layer 700 is advantageous for increasing the threshold voltage of an NFET transistor device and decreasing the threshold voltage (magnitude) of a PFET transistor device.

[0106] In some embodiments, a work function metal layer 900 is formed on the work function barrier layer 700. This work function metal layer may include one or more of an N-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. The N-type work function metal layer is or comprises an N-type metallic material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and / or other suitable methods, and has a thickness between about 10 Å and 20 Å. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or comprises TiN, TiSiN, TaN, or another suitable material, and has a thickness between about 10 Å and 20 Å. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type work function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that prevents oxygen from penetrating to the N-type work function metal layer and protects the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using an ALD and has a thickness of about 10 Å to about 20 Å.

[0107] Metal layer 290 is positioned on work function metal layer 900. In some embodiments, an adhesive layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and metal layer 290. The adhesive layer may promote and / or enhance adhesion between metal layer 290 and work function metal layer 900. In some embodiments, the adhesive layer may be formed using an ALD from a metal nitride such as TiN, TaN, MON, WN, or another suitable material. In some embodiments, the thickness of the adhesive layer is between about 10 Å and about 25 Å. Metal layer 290 may be formed on the adhesive layer and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, metal layer 290 may be deposited using methods such as CVD, PVD, plating, and / or other suitable procedures. Between channels 22A-22C, metal layer 290 is circumferentially surrounded (in cross-sectional views) by one or more work function metal layers 900, which are subsequently circumferentially surrounded by gate dielectric layer 600.

[0108] In some embodiments, a seam 510 for an air gap may be formed vertically between channels 22A, 22B in the metal layer 290. In some embodiments, the metal layer 290 is conformally deposited on the work function metal layer 900. The seam 510 may be formed due to the merging of sidewall deposited films during conformal deposition. In some embodiments, the seam 510 is not present between adjacent channels 22A, 22B or adjacent channels 22B, 22C.

[0109] Figure 15 and Figure 16 According to some embodiments, in reference to Figure 5C-7B A view of the nanostructure 24 after the described preprocessing procedure. The nanostructure 24 may include a bottom nanostructure 24B below channel 22A, an intermediate nanostructure 24M between channels 22A and 22B, and a top nanostructure 24T between channels 22B and 22C. (Refer to...) Figure 15 and 16 The description of nanostructure 24 can be applied to gate structure 200, which inherits the shape of nanostructure 24 after it is removed. Therefore, in the following description, the dimensions associated with nanostructure 24 are associated with gate structure 200 extending into the opening remaining after the removal of nanostructure 24.

[0110] exist Figure 15In the design, the top nanostructure 24T has a first width W1. The middle nanostructure 24M has a second width W2. The bottom nanostructure 24B has a third width W3. In some embodiments, the first width W1, the second width W2, and the third width W3 are respectively the minimum width, the maximum width, and the average width of the top nanostructure 24T, the middle nanostructure 24M, and the bottom nanostructure 24B at substantially the same level (e.g., the middle) or similar. A first difference (e.g., W2-W1) between the first width W1 and the second width W2 can range from about 0.5 nm to about 1.1 nm. A second difference (e.g., W3-W2) between the second width W2 and the third width W3 can range from 0 nm to about 1.5 nm. A third difference (e.g., W3-W1) between the first width W1 and the third width W3 can range from about 0.7 nm to about 1.1 nm.

[0111] Channel 22A has a first thickness T1. Channel 22B has a second thickness T2. Channel 22C has a third thickness T3. Each of the first thickness T1, second thickness T2, and third thickness T3 may vary along the width of the respective channel 22A, 22B, 22C in the X-axis direction. In some embodiments, the variation of the first thickness T1 is no more than about 3 nm. In some embodiments, the variation of the second thickness T2 is no more than about 3 nm. In some embodiments, the variation of the third thickness T3 is no more than about 3 nm. This may be attributed to a pretreatment including the flow of oxygen and hydrogen, which reduces the removal of material at the end portions of channels 22A-22C.

[0112] exist Figure 16 In this nanostructure 24, each of the nanostructures has a fourth width W4. Linewidth roughness (LWR) can be associated with the fourth width W4. For example, the linewidth roughness (LWR) can be characterized by a 3σ minimum dimension or "critical dimension" (CD) variation along a line segment. More simply, LWR can be a measure of the width of a printed line deviating from its ideal smooth shape, and can be represented by a standard deviation (σ). In some embodiments, a 3σ value is used because it represents approximately 99.7% of the measurement of the fourth width W4 falling within the normal distribution range. The variation of the fourth width W4 along the Y-axis can be measured from a first level of nanostructure 24 to a second level of nanostructure 24. The first level can be biased from a first end of nanostructure 24 by a first dimension D1. The second level can be biased from a second end of nanostructure 24 by a second dimension D2. In some embodiments, the first dimension D1 and the second dimension D2 are each approximately 3 nm. In some embodiments, the fourth width W4 varies along the Y-axis direction by no more than about 3 nm, such as in the range of about 0.5 nm to about 3 nm.

[0113] Each of the nanostructures 24 includes a first corner region 241, a second corner region 242, a third corner region 243, and a fourth corner region 244. The first corner region 241 is associated with a first angle A1. The second corner region 242 is associated with a second angle A2. The third corner region 243 is associated with a third angle A3. The fourth corner region 244 is associated with a fourth angle A4. In some embodiments, each of the first angle A1, second angle A2, third angle A3, and fourth angle A4 (or collectively, "angles A1-A4") may be an angle intercepted along the sidewall of the nanostructure 24 at a selected distance, such as 1 nm, 2 nm, 3 nm, or similar, offset from the adjacent end of the nanostructure 24. The offset may be the same for each of the angles A1-A4. That is, each of the angles A1-A4 may be measured at the same offset as the adjacent end of the nanostructure 24. In some embodiments, the angles A1-A4 of each of the nanostructures 24 (e.g., the top, middle, and bottom nanostructures 24T, 24M, 24B) can be in the range of about 60 degrees to about 90 degrees.

[0114] A first angular variation or difference among the nanostructures 24 (e.g., the top, middle, and bottom nanostructures 24T, 24M, 24B) may be the difference between a first angle A1 and a third angle A3, and between a second angle A2 and a fourth angle A4. In some embodiments, the first angular variation is in the range of about 0 degrees to about 5 degrees. A second angular variation or difference among the nanostructures 24 (e.g., the top, middle, and bottom nanostructures 24T, 24M, 24B) may be the difference between a first angle A1 and a second angle A2, and between a third angle A3 and a fourth angle A4. In some embodiments, the second angular variation is in the range of about 0 degrees to about 5 degrees.

[0115] One or more embodiments relate to a computer-readable medium containing processor-executable instructions configured to perform one or more of the technologies presented herein. An exemplary computer-readable medium is illustrated in... Figure 19In one embodiment, 90 includes a computer-readable medium 908 (e.g., a CD-R, DVD-R, flash drive, a disk of a hard disk drive, etc.) encoded with computer-readable data 906. This computer-readable data 906 then includes a set of processor-executable computer instructions 904 configured to perform one or more of the principles set forth herein when executed by a processor. In some embodiments of 90, the processor-executable computer instructions 904 are configured to perform a method 902, such as at least some of the foregoing methods, when executed by a processor. In some embodiments, the processor-executable computer instructions 904 are configured to perform a system, such as at least some of the foregoing systems, when executed by a processor. Those skilled in the art can design many such computer-readable media configured to operate according to the techniques presented herein.

[0116] In some embodiments, a method is provided. The method includes: forming a stack of alternating nanostructured channels and sacrificial layers over a substrate; forming a source / drain opening extending through the stack; forming respective first dielectric layers on the nanostructured channels by flowing a first gas in the source / drain opening; forming a second dielectric layer on the sacrificial layer by flowing a first gas mixture including the first gas and a second gas in the source / drain opening; removing the second dielectric layer from the sacrificial layer by flowing a second gas mixture including the first gas and a third gas in the source / drain opening; forming an inner spacer opening by recessing the sacrificial layer after removing the second dielectric layer; and forming an inner spacer in the inner spacer opening.

[0117] In some embodiments, causing the first gas to flow includes causing nitrogen to flow.

[0118] In some embodiments, flowing the first gas mixture includes flowing oxygen.

[0119] In some embodiments, flowing the second gas mixture includes flowing hydrogen.

[0120] In some embodiments, recessing the sacrificial layer includes allowing NF3 gas to flow in the source / drain opening.

[0121] In some embodiments, the method includes flowing a fourth gas into the source / drain opening after the second gas mixture has been circulated and before the inner spacer opening has been formed.

[0122] In some embodiments, the method includes forming a source / drain region in the source / drain opening; forming an opening by removing the sacrificial layer; and forming a gate structure in the opening.

[0123] In some embodiments, a method is provided. The method includes: forming a stack of alternating nanostructured channels and sacrificial layers over a substrate; forming a source / drain opening extending through the stack; performing a pretreatment process including: flowing a first gas into the source / drain opening; and flowing a mixture of the first gas, a second gas, and a third gas into the source / drain opening. The method further includes: after performing the pretreatment process, forming an inner spacer opening by recessing the sacrificial layer; and forming an inner spacer within the inner spacer opening.

[0124] In some embodiments, flowing the first gas mixture includes flowing nitrogen, oxygen, and hydrogen through the source / drain opening.

[0125] In some embodiments, the method includes, after allowing the first gas mixture to flow, allowing hydrofluoric acid to flow in the source / drain opening.

[0126] In some embodiments, the method includes purging the first gas mixture by flowing the first gas before flowing the hydrofluoric acid.

[0127] In some embodiments, forming the source / drain opening includes allowing CH4 to flow.

[0128] In some embodiments, the method includes removing carbon impurities from the sacrificial layer by circulating the third gas, while the surface of the nanostructured channel exposed by the source / drain opening is covered by a dielectric layer formed by the first gas.

[0129] In some embodiments, flowing the first gas mixture includes forming a layer of nitrogen oxides containing the carbon impurities on the surface of the sacrificial layer exposed by the source / drain opening.

[0130] In some embodiments, the method includes removing silicon oxide and germanium oxide from the sacrificial layer by circulating the third gas.

[0131] In some embodiments, an apparatus is provided. The apparatus includes: a stack of nanostructured channels above a substrate, the nanostructured channels including a first channel and a second channel offset from each other; a source / drain region abutting the nanostructured channels; an inner spacer located between the first channel and the second channel; and a gate structure extending through an opening adjacent to the first channel, the second channel and the inner spacer, the gate structure in the opening including: a linewidth roughness of not more than 3 nanometers (nm); a first corner region associated with a first angle in the range of about 60 degrees to about 90 degrees; and a second corner region associated with a second angle in the range of about 60 degrees to about 90 degrees, the difference between the first angle and the second angle in the range of 0 degrees to about 5 degrees.

[0132] In some embodiments, the first channel has a width along a first direction and a thickness along a second direction, the thickness having a variation of no more than about 3 nm along the first direction.

[0133] In some embodiments, the nanostructure channel includes a third channel, and a second opening is adjacent to the second channel and the third channel.

[0134] In some embodiments, the first channel has a first width; the second channel has a second width; the third channel has a third width; a first difference between the second width and the first width is in the range of about 0.5 nm to about 1.1 nm; a second difference between the third width and the second width is in the range of 0 nm to about 1.5 nm; and a third difference between the third width and the first width is in the range of about 0.7 nm to about 1.1 nm.

[0135] In some embodiments, the linewidth roughness is associated with a portion of the gate structure in the opening, the portion being biased by about 3 nm from a first end of the opening and about 3 nm from a second end of the opening.

[0136] Although the subject matter of this case has been described using terms specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not necessarily limited to the aforementioned specific features or actions. Rather, the aforementioned specific features and actions are disclosed as exemplary forms of implementing at least some of the claims.

[0137] This document provides various operations in the embodiments. The order of some or all of the operations described should not be construed as implying that such operations must rely on a specific order. Alternative orders will be understood to have the benefits of this description. Furthermore, it will be understood that not all operations must exist in the various embodiments provided in this document. Moreover, it will be appreciated that not all operations are necessary in some embodiments.

[0138] It will be understood that in some embodiments, the layers, features, elements, etc., illustrated herein are illustrated with specific dimensions relative to each other, such as structural dimensions or orientations, for example for the purpose of simplification and ease of understanding, and the actual dimensions are substantially different from those illustrated herein. Furthermore, various techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.

[0139] Furthermore, "exemplary" and / or similar terms in this application mean applicable to an example, instance, illustration, etc., and are not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or." Furthermore, "a" and "an" as used in this application and the appended claims are generally interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context as referring to a singular form. Moreover, "at least one of A and B" and / or similar terms generally mean A or B or both A and B. Furthermore, with regard to the use of "comprising," "having," "containing," "possessing," or variations thereof, these terms are intended to be inclusive, in a manner similar to the term "including." Furthermore, unless otherwise specified, "first," "second," or similar terms are not intended to imply a temporal aspect, a spatial aspect, a sequence, etc. Rather, these terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element typically correspond to element A and element B, or two different or two identical elements, or identical elements.

[0140] Furthermore, although this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure encompasses all such modifications and changes and is limited only by the scope of the claims. In particular, regarding the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component performing the specific function of said component (e.g., functionally equivalent), even if structurally not equivalent to the disclosed structure. Moreover, although a particular feature of this disclosure has been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of other embodiments, as it may be desirable and advantageous for any given or particular application.

Claims

1. A semiconductor manufacturing method, characterized in that, The semiconductor manufacturing method includes: An alternating stack of nanostructured channels and sacrificial layers is formed on a substrate; Form a source / drain opening that extends through the stack; A first dielectric layer is formed on the nanostructure channel by allowing a first gas to flow in the source / drain opening; A second dielectric layer is formed on the sacrificial layer by allowing a mixture of the first gas and a second gas to flow in the source / drain opening; The second dielectric layer is removed from the sacrificial layer by allowing a second gas mixture, including the first gas and a third gas, to flow in the source / drain opening; After removing the second dielectric layer, an inner spacer opening is formed by recessing the sacrificial layer; as well as An inner spacer is formed in the opening of the inner spacer.

2. The semiconductor manufacturing method according to claim 1, characterized in that, The flow of the first gas includes the flow of nitrogen.

3. The semiconductor manufacturing method according to claim 1, characterized in that, The semiconductor manufacturing method also includes: After the second gas mixture is circulated and before the inner spacer opening is formed, a fourth gas is circulated in the source / drain opening.

4. A semiconductor manufacturing method, characterized in that, The semiconductor manufacturing method includes: An alternating stack of nanostructured channels and sacrificial layers is formed on a substrate; Form a source / drain opening that extends through the stack; Perform a preprocessing procedure, which includes: A first gas flows through the source / drain opening; and A mixture of the first gas, a second gas, and a third gas is allowed to flow in the source / drain opening; After performing this preprocessing procedure, an inner spacer opening is formed by recessing the sacrificial layer; and An inner spacer is formed in the opening of the inner spacer.

5. The semiconductor manufacturing method according to claim 4, characterized in that, The flow of the first gas mixture includes: Nitrogen, oxygen, and hydrogen are allowed to flow through the source / drain opening.

6. The semiconductor manufacturing method according to claim 5, characterized in that, The semiconductor manufacturing method also includes: After the first gas mixture is allowed to flow, hydrofluoric acid is allowed to flow in the source / drain opening.

7. The semiconductor manufacturing method according to claim 4, characterized in that, Forming the source / drain opening involves allowing CH4 to flow.

8. A semiconductor device, characterized in that, The semiconductor device includes: A stack of nanostructured channels above a substrate, the nanostructured channels including a first channel and a second channel offset from each other; A source / drain region abuts the nanostructure channel; An inner spacer is positioned between the first channel and the second channel; as well as A gate structure extending through an opening adjacent to the first channel, the second channel, and the inner spacer, the gate structure in the opening comprising: Roughness with a linewidth not exceeding 3 nm; A first corner region associated with a first angle, the first angle being in the range of about 60 degrees to about 90 degrees; and A second corner region associated with a second angle, the second angle being in the range of about 60 degrees to about 90 degrees, and the difference between the first angle and the second angle being in the range of about 0 degrees to about 5 degrees.

9. The semiconductor device according to claim 8, characterized in that, in: The first channel has a width along a first direction and a thickness along a second direction, the thickness having a variation of no more than about 3 nm along the first direction.

10. The semiconductor device according to claim 8, characterized in that, The nanostructured channel includes a third channel, and a second opening is adjacent to the second channel and the third channel.

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