Semiconductor structure and method of forming a semiconductor device

Abstract

This invention provides a semiconductor structure and a method for forming the same, the structure having multiple channels disposed on a substrate and source / drain electrodes connected to the multiple channels. The source / drain electrodes include a first layer and a second layer located above the first layer. The structure also includes a CESL located above the source / drain electrodes and an ILD layer located above the CESL. The method further includes flipping the structure so that the back side of the substrate faces upward, and depositing a dielectric layer above the back side of the substrate. The method further includes performing an etching process using an etchant gas to form trenches extending through the dielectric layer and the substrate to expose the source / drain electrodes. The etchant gas may include a sulfur-containing gas. During the etching process, the etchant gas reacts with the material exposed by the trenches to form a passivation layer within the trenches, the passivation layer inhibiting etching of the source / drain electrodes.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming semiconductor devices. Background Technology

[0002] The electronics industry has a growing demand for smaller and faster electronic devices capable of supporting increasingly complex and sophisticated functions. Consequently, the semiconductor industry has a sustained trend towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down the size of semiconductor ICs (e.g., minimizing component size), thereby improving production efficiency and reducing associated costs.

[0003] However, this scaling also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar progress in semiconductor manufacturing processes and technologies. For example, as device scaling continues, the density of contact components and the high resistance of these contacts remain challenging. While existing structures and methods are generally sufficient for their intended purposes, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] One embodiment of this application provides a method for forming a semiconductor device, comprising:

[0005] A semiconductor structure is provided, the semiconductor structure comprising: a plurality of channels disposed above a substrate; a source / drain structure connected to the plurality of channels, wherein the source / drain structure includes a first layer located on the sidewalls of the plurality of channels and a second layer located above the first layer; a contact etch stop layer (CESL) located above the source / drain structure; and an interlayer dielectric (ILD) layer located above the contact etch stop layer;

[0006] Flip the semiconductor structure so that the back side of the substrate faces upward;

[0007] A dielectric layer is deposited over the back side of the substrate;

[0008] An etching process is performed using an etchant gas to form trenches that extend through the dielectric layer and the substrate to expose the source / drain structure.

[0009] The etchant gas includes a sulfur-containing gas; and

[0010] During the etching process, the etchant gas reacts with the material exposed by the trench to form a passivation layer within the trench, which inhibits the etching of the source / drain structure.

[0011] One embodiment of this application provides a method for forming a semiconductor device, comprising:

[0012] A semiconductor structure is provided, the semiconductor structure including an active region and a gate structure, the active region extending in a first direction in a top view, the active region including a channel region and a source / drain region adjacent to the channel region, wherein the source / drain region includes a first layer located on the sidewall of the channel region and a second layer located above the first layer; the gate structure is disposed above the channel region, wherein the gate structure extending in a second direction in the top view, the second direction being different from the first direction.

[0013] A dielectric layer is deposited on the back side of the semiconductor structure;

[0014] Patterning the dielectric layer to form trenches in the dielectric layer, the trenches exposing a semiconductor substrate that overlaps with the source / drain regions; and

[0015] An etching process is performed to extend the trench through the semiconductor substrate to expose the source / drain regions;

[0016] The etching process simultaneously forms a passivation layer within the trench, the passivation layer having a lower etching rate than the source / drain regions; and

[0017] The passivation layer provides at least one of sulfur passivation and CHF polymer passivation.

[0018] One aspect of this application provides a semiconductor structure, comprising: a first plurality of channels disposed above a substrate in a first device type region; a first source / drain component connected to the first plurality of channels, the first source / drain component including an etch stop layer located at the bottom of the first source / drain component; a second plurality of channels disposed above the substrate in a second device type region; a second source / drain component connected to the second plurality of channels, the second source / drain component not having the etch stop layer at its bottom; a contact etch stop layer (CESL) located above the first source / drain component; and an interlayer dielectric (I0). An LD layer is located above the contact etch stop layer; a contact member extends through the interlayer dielectric layer in at least one of the first device type region and the second device type region to be electrically coupled to a corresponding one of the first source / drain member and the second source / drain member; a dielectric layer is disposed on the back side of the substrate; a first back-side contact member extends through the dielectric layer, the substrate and the etch stop layer in the first device type region to be electrically coupled to the first source / drain member; and a second back-side contact member extends through the dielectric layer and the substrate in the second device type region to be electrically coupled to the second source / drain member. Attached Figure Description

[0019] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0020] Figure 1 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments is shown;

[0021] Figure 2 The following are illustrations based on some embodiments. Figure 1 Simplified top views of the semiconductor structure at different manufacturing stages of embodiments of the method; and

[0022] Figure 3A , Figure 3B , Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15A , Figure 15B , Figure 16 , Figure 17A , Figure 17B and Figure 18 The following are illustrations based on some embodiments. Figure 1 Cross-sectional views of the semiconductor structure at different manufacturing stages. Detailed Implementation

[0023] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact.

[0024] Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, the formation of components located on, connected to, and / or coupled to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components may be formed between the components so that the components are not in direct contact. Furthermore, for the convenience of describing the relationship between one component and another, spatially relative terms are used, such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.). Spatially relative terms are intended to include different orientations of devices (including components).

[0025] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account the inherent variations that occur during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with the value, the value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer with a thickness of "about 5 nm" could encompass dimensions ranging from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Other ranges are possible as known to those skilled in the art and can be process-dependent.

[0026] It should also be noted that embodiments are presented in the form of multi-gate transistors, which in some cases may be equivalently referred to as non-planar transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include P-type or N-type devices. Due to their finned structure, specific examples may be presented and referred to herein as FinFETs. FinFET devices may include fins (or nanostructures extending from a substrate) wherein the fins are composed of substantially uniform components. Embodiments of a type of multi-gate transistor referred to herein as a gate-all-around (GAA) transistor are also described. A GAA transistor includes any device whose gate structure or a portion thereof is formed on all four sides of a channel region (e.g., around a portion of the channel region). Devices presented herein also include embodiments having channel regions configured as various nanostructures, such as nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Embodiments of devices that may have one or more nanostructured channel regions (e.g., nanosheets / nanowires) associated with a single continuous gate structure are described herein. A GAA device may include multiple stacked channel layers (e.g., multiple stacked nanosheets) forming the channels of a GAA transistor. Those skilled in the art will recognize that the teachings disclosed herein can be applied to a single channel (e.g., a single nanosheet / nanowire) or any number of channels. Other examples of semiconductor devices that can benefit from the aspects of this disclosure will be recognized by those skilled in the art. For example, in some cases, the aspects of this disclosure can be equally applied to planar transistor devices, forked devices, complementary FET (CFET) devices, etc. A CFET device includes a first transistor of a first conductivity type (e.g., N-type or P-type) stacked vertically above a second transistor having an opposite conductivity type. In some examples, a GAA transistor can be used to implement a CFET device. Other embodiments of semiconductor devices that can benefit from the aspects of this disclosure will be recognized by those skilled in the art.

[0027] The continuous scaling of IC devices increases the complexity of semiconductor manufacturing processes. As an example, continuous device scaling increases the challenges associated with device density (and therefore contact density), as well as the challenge of reducing the resistance of these contact components. To address these issues, back-side power delivery networks (PDNs) have been introduced in some existing implementations. The advantage of back-side PDNs is that they provide power rails and contacts / vias formed on the back side of the substrate (rather than the front side). Therefore, fewer contacts and interconnects are crowded on the front side of the substrate, more space is available along the front side for routing signal interconnects, and devices with higher performance and lower power consumption can be achieved, at least in part because back-side PDNs provide more direct, lower-resistance power delivery to transistors.

[0028] However, even with these advantages, the continued scaling of IC dimensions still presents challenges in reducing the resistance of back-side routing components. For example, epitaxial source / drain components can include various material layers, such as SiP, SiGe, etc., which can be connected to back-side vias (VB) formed to contact the bottom region of such epitaxial source / drain components (e.g., as part of a back-side power transmission network). In the case of N-type devices, an interposer or stop layer (e.g., a nitride layer) can be formed at the bottom of the epitaxial source / drain components, allowing for the avoidance of excessively deep recesses during VB formation. However, in the case of P-type devices, an interposer may not be used. Therefore, forming VB in a P-type device allows for direct connection of the material layers to the epitaxial source / drain components (such as SiGe), which has a higher etch rate than silicon (Si). Consequently, the formation of VB can create excessively deep recesses in P-type devices, potentially leading to high resistance and current congestion. Therefore, while existing structures and methods are generally sufficient for their intended purposes, they are not entirely satisfactory in every respect.

[0029] The embodiments disclosed herein offer advantages over the prior art; however, it should be understood that other embodiments may offer different advantages, and not all advantages are necessarily discussed herein, nor is any particular advantage required for all embodiments. For example, the embodiments discussed herein include methods and structures for improving Si / SiGe etching selectivity to achieve suitable back-side via etching processes for N-type and P-type devices, thereby addressing challenges associated with prior art implementations. In some embodiments, the method of etching back-side vias (VBs) includes using an etchant gas comprising a sulfur-containing gas. In some embodiments, the sulfur-containing gas may include sulfur dioxide (SO2), carbonyl sulfide (COS), and / or sulfur hexafluoride (SF6). In some examples, the etchant gas may also include C x H y F zThe etchant gas is a gas, where x, y, and z are integers. In a particular example, the etchant gas may include CHF3. In various embodiments, the disclosed etchant gas may react with Ge and / or Si during etching of the back-side via (VB) to form a passivation layer. As a result, excessively deep trenches can be avoided. In some cases, the passivation layer may include S passivation. For example, by adding SO2 / COS / SF6, GeS... x C y F z The formation of (x, y, and z are integers) will passivate and suppress SiGe etching. In other cases, the passivation layer may include CHF polymer passivation. For example, GeCHF and / or SiCHF may be formed as the passivation layer. In some embodiments, GeCHF can passivate more effectively due to its low volatility. In other examples, N2 / O2 passivation may be used to form the passivation layer. In various embodiments, regardless of the type of passivation layer used, the passivation layer can be removed before the subsequent formation of a conductive layer (metal layer) within the trench formed by the back-side via etching. Furthermore, while the disclosed embodiments may be particularly advantageous in fabricating P-type devices, it will be understood that the disclosed back-side via fabrication process can be equally applied to N-type and P-type devices. In addition, other types of contact components (e.g., front-side source / drain contacts) and / or other processes (e.g., processes that are intended to protect or suppress etching of the germanium film) may benefit from aspects of this disclosure. Other embodiments and advantages will become apparent to those skilled in the art upon reading this disclosure.

[0030] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 A flowchart is provided illustrating a method 100 for forming a semiconductor structure according to embodiments of the present disclosure, with reference to... Figures 2 to 18 It has been described. Figure 2 It shows according to Figure 1 A simplified top view of the structure 200 at different manufacturing stages of an embodiment of method 100. Figure 3A , Figure 3B , Figure 5A , Figure 5B , Figure 7A , Figure 7B , Figure 9A , Figure 9B , Figure 11A , Figure 11B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 17A and Figure 17B It shows according to Figure 1 Along at different manufacturing stages of embodiments of method 100 Figure 2A cross-sectional view of structure 200 along line A-A'. Furthermore, Figure 3A , Figure 5A , Figure 7A , Figure 9A , Figure 11A , Figure 13A , Figure 15A and Figure 17A Corresponding to the N-type device region, and Figure 3B , Figure 5B , Figure 7B , Figure 9B , Figure 11B , Figure 13B , Figure 15B and Figure 17B This corresponds to the P-type device region. Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 It shows according to Figure 1 Along at different manufacturing stages of embodiments of method 100 Figure 2 A cross-sectional view of structure 200 along line B-B'. It should be noted that method 100 is merely exemplary and is not intended to limit this disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or rearranged for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. Because structure 200 will be fabricated as a semiconductor structure, it may be referred to herein as semiconductor structure 200 or semiconductor device 200, depending on the context. To avoid ambiguity, Figures 2 to 18 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. In this disclosure, unless otherwise stated, the same reference numerals denote the same parts. That is, the material properties of the various numbered elements described in association with a method or drawing, and their comparisons, should be applied to the same numbered elements described in association with different methods or drawings.

[0031] refer to Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 4 Method 200 begins at box 102, where structure 200 is formed or provided. For example... Figure 2As shown, in some embodiments, structure 200 may include a multi-gate device (or a non-planar device), such as a GAA device. Structure 200 may include a plurality of fins 212 extending from a substrate, gate structures 240 disposed above and around the fins 212, and source / drain structures 214, wherein the source / drain structures 214 are formed in, on, and / or around the fins 212. The channel region of structure 200 may include a plurality of nanostructured semiconductor channel layers (e.g., nanosheets / nanowires) extending along the […]. Figure 2 A plane substantially parallel to the plane defined by the cross section A-A' is disposed within the fin 212 below the gate structure 240. In some cases, the fin 212 may be equivalently referred to as the active region 212. The active region of the transistor includes the region of the transistor forming the source region, drain region, and channel region below the gate structure. In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structure 240. As shown, in Figure 2 In a top view, fin 212 can be described as extending in a first direction (Y), while Figure 2 In the top view, the gate structure 240 (and the sidewall spacers formed on the sidewalls of the gate structure 240) can be described as extending in a second direction (X). In some cases, the first direction (Y) may be perpendicular to the second direction (X). Various other components of the structure 200 are discussed in more detail below.

[0032] refer to Figure 3A , Figure 3B and Figure 4 Structure 200 includes a substrate 202. In some embodiments, substrate 202 is a bulk silicon substrate (i.e., including bulk single-crystal silicon). In some embodiments, substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In alternative embodiments, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, substrate 202 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. In some examples, various doped regions may be formed in or on substrate 202. Depending on design requirements, the doped regions may be doped with N-type dopants (such as phosphorus or arsenic) and / or P-type dopants (such as boron). The doped region can be formed directly on the substrate 202 in the form of a P-well structure, an N-well structure, a double-well structure, or using a bump structure. The doped region can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0033] In some embodiments, the semiconductor structure 200 includes an active region 212 above a substrate 202. As shown, the active region 212 (or fin 212) includes a semiconductor substrate 204 (or mesa 204) protruding from the substrate 202 and a stack of nanostructures 208 (also referred to as semiconductor channel layer 208 or epitaxial layer 208) vertically stacked above the semiconductor substrate 204. The semiconductor substrate 204 (or mesa 204) may have the same composition as the substrate 202. In some embodiments, the semiconductor substrate 204 includes silicon, silicon germanium, germanium, or other suitable semiconductors and may be doped with N-type or P-type dopants. The active region 212 can be patterned by any suitable method. For example, the active region 212 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used as masking elements for patterning the active region 212. For example, the masking elements can be used to etch grooves in a semiconductor layer over or within the substrate 202, leaving the active region 212 on the substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process can utilize oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasmas and / or combinations thereof. For example, a wet etching process may include etching in solutions such as dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method for forming the active region 212 (or fin 212) may be suitable.

[0034] As shown, nanostructure 208 (or semiconductor channel layer 208) connects to source / drain structure 214 and serves as the channel layer for the GAA transistor. In some embodiments, nanostructure 208 may include a semiconductor material suitable for the transistor channel, such as silicon, silicon germanium, or other semiconductor materials. In various embodiments, nanostructure 208 may be in the shape of a rod, strip, sheet, or other shape. In embodiments, nanostructure 208 is initially part of a stack of semiconductor layers comprising alternating layers of nanostructure 208 and other sacrificial semiconductor layers. The sacrificial semiconductor layers and nanostructure 208 comprise different material compositions (such as different semiconductor materials, different atomic percentages of components, and / or different weight percentages of components) to achieve etch selectivity. During the gate replacement process that forms gate stack 240, the sacrificial semiconductor layers are selectively removed, leaving nanostructure 208 above semiconductor substrate 204. It should be noted that while three (3) nanostructures 208 are vertically stacked in the illustrated embodiment, this is for illustrative purposes only and is not intended to limit the specific references in the claims. It will be understood that any number of nanostructures may be formed depending on device performance requirements. In some embodiments, the number of vertically stacked nanostructures 208 can be between 2 and 10.

[0035] In various embodiments, the semiconductor structure 200 further includes isolation components 218 formed around each active region 212. Figure 4 ), to isolate adjacent active regions 212. Isolation component 218 may also be referred to as shallow trench isolation (STI) component and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof and / or other suitable materials.

[0036] In some embodiments, the semiconductor structure 200 includes a fin-cut structure 220 above the substrate 202. Figure 3A / Figure 3BIn various embodiments, the fin-cut structure 220 is used to separate a first active region 212 from a second active region 212, the second active region 212 being aligned with the first active region 212 along the X direction. In the depicted embodiments, the fin-cut structure 220 contacts the semiconductor channel layer 208 (or nanostructure 208). The fin-cut structure 220 can be formed using various processes. As an example, fin-cut trenches are formed along the Y direction to segment one or more active regions 212 (or fins 212), followed by processes such as depositing dielectric material and performing chemical mechanical polishing (CMP). In some embodiments, the fin-cut structure 220 may include multiple dielectric layers. For example, the fin-cut structure 220 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride or silicon carbide, oxides formed from TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, degel, aerogel, amorphous fluorinated carbon, parylene, BCB, polyimide, other low-k dielectric materials, or combinations thereof.

[0037] In some embodiments, the semiconductor structure 200 includes source / drain structures 214 formed in and / or above the source / drain region of the active region 212 (or fin 212), each source / drain structure 214 being disposed adjacent to the gate stack 240. Depending on the context, the source / drain structure 214 may individually or collectively refer to a source or a drain. In the N-type device region, such as Figure 3A As shown, the source / drain structure 214 includes an N-type source / drain structure 214N. In the P-type device region, such as Figure 3B As shown, the source / drain structure 214 includes a P-type source / drain structure 214P. For the purposes of this disclosure, when referring to N-type and P-type device regions, the N-type source / drain structure 214N and the P-type source / drain structure 214P can be collectively referred to as source / drain structure 214. The source / drain structure 214 can be formed by any suitable technique, such as an etching process and subsequent one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of the active region 212 (or fin 212), thereby forming a source / drain trench (not shown) in the source / drain region 212SD. Before epitaxially growing the source / drain structure 214 inside and outside the source / drain trench, a cleaning process can be performed to clean the source / drain trench with a hydrofluoric acid (HF) solution or other suitable solution.

[0038] In some embodiments, the N-type source / drain structure 214N includes an interposer layer (e.g., 214-1 and / or 214-2) located at the bottom of the source / drain recess, and source / drain components (also referred to as epitaxial source / drain components) located above the interposer layer and connected to the adjacent semiconductor channel layer 208. The interposer layer may include a separator layer 214-1, a bottom layer 214-2, or both. The formation of the interposer layer is optional, and the interposer layer may not be present in the final structure. The separator layer 214-1 may include the same or different semiconductor material as the substrate 202 and may be formed by an epitaxial growth process. In some embodiments, the separator layer 214-1 is dopant-free, for example, no intentional doping is performed during the epitaxial growth process. The separator layer 214-1 may have a thickness of about 1 nm to about 30 nm (e.g., along the Z direction). The bottom layer 214-2 may be formed above the separator layer 214-1 or above the semiconductor substrate 204 (when the separator layer 214-1 is not formed). The bottom layer 214-2 may have a thickness of about 4 nm to about 8 nm (e.g., along the Z direction). In some embodiments, the bottom layer 214-2 is formed of an oxygen-free dielectric material, such as a nitride (e.g., silicon nitride). The bottom layer 214-2 can be formed by any suitable method, such as depositing a silicon nitride-containing chlorine layer in the source / drain region 212SD, and etching back (e.g., by a dry etching process) excess portions of the silicon nitride-containing chlorine layer. In some other embodiments, the bottom layer 214-2 comprises a semiconductor layer (e.g., Si) doped with a dopant (e.g., boron). In such embodiments, the bottom layer 214-2 can be formed by an epitaxial growth process.

[0039] In some embodiments, the P-type source / drain structure 214P may include only a separation layer 214-1 located at the bottom of the source / drain recess, wherein the source / drain components (epitaxy source / drain components) are disposed above the separation layer 214-1 and connected to the adjacent semiconductor channel layer 208. Optionally, in some cases, the P-type source / drain structure 214P may not include any interposer layer (e.g., 214-1 and / or 214-2) at the bottom of the source / drain recess. In some prior embodiments, as previously described, and at least due to the lack of an underlying layer 214-2 (e.g., silicon nitride) in the P-type source / drain structure 214P, forming a back-side via in a P-type device may result in an excessively deep recess in the P-type device. As discussed in more detail below, embodiments of this disclosure provide improved Si / SiGe etch selectivity to achieve suitable back-side via etching processes for both N-type and P-type devices, thereby avoiding such excessively deep recesses during back-side via formation.

[0040] For the N-type source / drain structure 214N, the epitaxial source / drain component above the interposer layer may include multiple epitaxial layers, such as a first layer 214N-3 on the sidewall of the channel layer 208 and a second layer 214N-4 located above the first layer 214N-3 and spaced apart from the sidewall of the channel layer 308. For the P-type source / drain structure 214P, the epitaxial source / drain component above the separator layer 214-1 may also include multiple epitaxial layers, such as a first layer 214P-3 on the sidewall of the channel layer 208 and a second layer 214P-4 located above the first layer 214P-3 and spaced apart from the sidewall of the channel layer 308. In some cases, for the P-type source / drain structure 214P, the first layer 214P-3 may also be formed above the separator layer 214-1, as shown in the figure. One or more epitaxial growth processes are performed to grow epitaxial layers (e.g., 214N-3, 214N-4, 214P-3, 214P-4). The N-type source / drain structure 214N of an N-type transistor may include one or more epitaxial layers of silicon (epiSi) or silicon-carbon (epiSiC) doped with N-type dopants (such as arsenic, phosphorus, and / or other N-type dopants) (e.g., 214N-3 and 214N-4). The P-type source / drain structure 214P of a P-type transistor may include one or more epitaxial layers of silicon-germanium (epiSiGe) doped with P-type dopants (such as boron, germanium, indium, and / or other P-type dopants) (e.g., 214P-3 and 214P-4). The dopant concentrations in the one or more epitaxial layers may be different. For example, in the N-type source / drain structure 214N, the dopant concentration in the second layer 214N-4 is higher than the dopant concentration in the first layer 214N-3. Similarly, in the P-type source / drain structure 214P, the dopant concentration in the second layer 214P-4 is higher than that in the first layer 214P-3.

[0041] In some embodiments, the semiconductor structure 200 further includes an internal spacer 216 disposed between the source / drain structure 214 and adjacent gate stacks 240. In some embodiments, the internal spacer 216 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the internal spacer 216 comprises a low-k dielectric material, such as those described herein. The internal spacer 216 can be formed by deposition and etching processes. For example, after etching the source / drain trenches and before forming the source / drain structure 214, an etching process can be used to partially recess the sacrificial semiconductor layer between adjacent semiconductor channel layers 208 to form a gap perpendicularly located between adjacent semiconductor channel layers 208. One or more dielectric materials (e.g., using CVD or ALD) are then deposited to fill the gap. Another etching process is performed to remove the dielectric material outside the gap, thereby forming the internal spacer 216.

[0042] In some embodiments, the semiconductor structure 200 includes a gate stack 240 located between two source / drain structures 214, the gate stack 240 being disposed over and enclosing each semiconductor channel layer 208. (Reference) Figure 3A / Figure 3B The gate stack 240 may include an interface layer 222 formed on the surface of the semiconductor channel layer 208 adjacent to the gate stack 240, a high-k dielectric layer 224 formed above the interface layer 222, and a gate electrode layer formed above the high-k dielectric layer 224. The interface layer 222 may include silicon dioxide, silicon oxynitride, or other suitable materials. The interface layer 222 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer 224 may include high-k dielectric materials such as HfO2, HfSiO, HfSiO4, HfSiNO, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. x ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, such as those greater than that of silicon oxide (K≈3.9). The high-k dielectric layer 224 can be formed by ALD, CVD, metal-organic CVD (MOCVD), PVD, and / or other suitable methods.

[0043] In some embodiments, the gate electrode layer includes a work function layer 226 as an N-type or P-type work function layer and a metal filler layer 228 located above the work function layer 226. For example, the N-type work function layer may include Ta, titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), TiAlN, or combinations thereof. As another example, the P-type work function layer may include TiN, TaN, WN, or combinations thereof. In some embodiments, the work function layer 226 may include a multilayer structure, such as a first work function layer and a second work function layer (not shown). In some examples, the first work function layer may include a metal such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof, and the second work function layer may include a metal such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. In some embodiments, the metal filler layer 228 includes aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the metal filler layer 228 disposed above the P-type work function layer is a P-type metal filler layer. In some embodiments, the metal filler layer 228 disposed above the N-type function layer is an N-type metal filler layer. In some embodiments, the P-type metal filler layer and the N-type metal filler layer may be the same material or different materials. The gate electrode layer may be formed by CVD, PVD, plating and / or other suitable processes. Because the gate stack 240 includes a high-k dielectric layer and a metal layer, it is also referred to as a high-k / metal gate structure. It should be noted that in some cases, for N-type devices in the N-type device region ( Figure 3A ) and P-type devices in the P-type device region ( Figure 3B The gate stack 240 (or at least the gate electrode layer) can be formed separately. In some cases, at least some layers of the gate stack 240 can be formed simultaneously in each of the N-type and P-type device regions.

[0044] In some embodiments, the gate stack 240 is formed after fabricating other components of the semiconductor structure 200, such as the source / drain structure 214. In some embodiments, the formation of the gate stack 240 may include a gate replacement process or a gate-first process. For example, the gate replacement process may include forming a dummy gate structure (not shown) as a placeholder for the gate stack 240, forming the source / drain structure 214, forming a first-level contact etch stop layer (CESL) and a first-level interlayer dielectric (ILD) layer over the source / drain structure 214, planarizing the semiconductor structure 200 (e.g., such as by using a CMP process) to expose the top surface of the dummy gate structure, removing the dummy gate structure to form a trench exposing the channel region 212C of the active region 212 (or fin 212), removing the sacrificial semiconductor layer (as part of a channel release process), and forming the gate stack 240 in the trench and around the semiconductor channel layer 208 to complete the gate replacement process. In some embodiments, the gate stack 240 may be partially recessed, and a dielectric capping layer may be formed on the recessed gate stack 240.

[0045] In some embodiments, the semiconductor structure 200 further includes a gate spacer 232 disposed on the sidewall of the gate stack 240. The gate spacer 232 may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon carbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon carbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicon, zirconium silicide, etc.), other suitable materials, or combinations thereof. The gate spacer 232 may include a single-layer or multi-layer structure, as shown in the figure. Notably, the composition of the gate spacer 232 differs from the composition of the surrounding dielectric components (e.g., CESL and ILD layers), allowing for etch selectivity between the gate spacer 232 and the surrounding dielectric components during subsequent etching processes. In an embodiment, the gate spacer 232 comprises SiN. The gate spacer 232 can be formed by first depositing a blanket layer of one or more spacer materials over the semiconductor structure 200, and then performing an anisotropic etching process to remove portions of the one or more spacer materials to form the gate spacer 232. For example... Figure 4 As shown, after the source / drain recess is formed, a portion of the gate spacer 232 can remain in the source / drain region 212SD.

[0046] In some embodiments, the semiconductor structure 200 includes a first-level CESL 234 disposed above the source / drain structure 214 and a first-level ILD layer 236 disposed above the first-level CESL 234. The first-level CESL 234 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen or carbon elements, other suitable materials, or combinations thereof, and may be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof. The first-level ILD layer 236 may include dielectric materials such as tetraethyl orthosilicate (TEOS), silicon oxide, low-k dielectric materials, doped silicon oxide (such as borosilicate glass (BPSG), phosphosilicate glass, FSG, boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. The first-level ILD layer 236 may include a monolayer structure or a multilayer structure having multiple dielectric materials, and may be formed by deposition processes such as, for example, CVD, flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof. The first ILD layer 236 can be deposited after the deposition of the first CESL 234.

[0047] In some embodiments, the semiconductor structure 200 further includes a second-level CESL 238 disposed above the first-level ILD layer 236, the fin-cut structure 220, the gate stack 240, and the gate spacer 232. In some embodiments, the semiconductor structure 200 further includes a second-level ILD layer 242 formed above the second-level CESL 238. The second-level CESL 238 may include components similar to the first-level CESL 234 and can be formed using a method similar to the first-level CESL 234. The second-level ILD layer 242 may include components similar to the first-level ILD layer 236 and can be formed using a method similar to the first-level ILD 236.

[0048] In some embodiments, the semiconductor structure 200 further includes a front source / drain contact 244 located above and electrically connected to the source / drain structure 214. The front source / drain contact 244 may extend through the first CESL 234, the first ILD layer 236, the second CESL 238, and the second ILD layer 242. In some embodiments, the semiconductor structure 200 further includes a silicide component 246 located between the front source / drain contact 244 and the corresponding source / drain structure 214. The silicide component 246 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In an embodiment, the front-side source / drain contact 244 includes a conductive barrier layer and a metal filler layer above the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filler layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the front source / drain contact 244. The front source / drain contact 244 may connect multiple source / drain structures 214 and may be referred to as a long contact in some cases. As shown, the semiconductor structure 200 may also include a dielectric liner 252 located on the sidewall of the front source / drain contact 244 and a dielectric component 254 located below the front source / drain contact 244.

[0049] In some embodiments, the semiconductor structure 200 further includes a dielectric structure 250. The dielectric structure 250 may be disposed above the second-level ILD layer 242, the front-side source / drain contact 244, and the dielectric liner 252. In some embodiments, the dielectric structure 250 includes multiple dielectric layers (e.g., 264-0, 264-1, 263-2, 264-2) and multiple CESLs (e.g., 262-0, 262-1, 262-2). CESLs may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials; and may be formed by CVD, PVD, ALD, or other suitable methods. The dielectric layer may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (such as borosilicate glass (BPSG), fluoride-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric layer can be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods.

[0050] In some embodiments, the semiconductor structure 200 further includes a source / drain via 260. The source / drain via 260 may be embedded in the dielectric structure 250 and connect the front source / drain contact 244 to a metal line disposed thereon. The source / drain via 260 may comprise a material similar to the front source / drain contact 244 and may be formed in a similar manner to the front source / drain contact 244.

[0051] In some embodiments, the semiconductor structure 200 further includes conductive components embedded in the dielectric structure 250. The conductive components and the dielectric structure 250 may be collectively referred to as a multilayer interconnect (MLI). The conductive components may include metal lines, metal vias, etc. The conductive components may include conductive materials, such as metals or metal alloys. The conductive components electrically connect various devices and / or components of the semiconductor structure 200 (e.g., source / drain structure 214, gate stack 240) such that the various devices and / or components can operate according to the design requirements of the semiconductor structure 200. The MLI may include one or more interconnect layers. In the illustrated embodiment, the MLI includes a metal zero interconnect layer (M0 level) (e.g., a layer including metal line 266) and a metal one interconnect layer (M1 level) (e.g., a layer including metal line 268). In some embodiments, the M0 metal line is electrically connected to the M1 metal line. Although not shown, the MLI may also include additional metal interconnect layers. Each of the M0 level, M1 level, ... and Mx level may be referred to as a metal level, where x is an integer. A metal line formed at the M0 level can be referred to as an M0 metal line. Similarly, vias or metal lines formed at the M1 and Mx levels can be referred to as M1 metal lines and Mx metal lines, respectively. This disclosure contemplates an MLI with more or fewer interconnect layers and / or levels, for example, the total number N of the N interconnect layers (levels) of the MLI is an integer from 1 to 10. Each level of the MLI includes conductive components (e.g., metal lines, metal vias) disposed in one or more dielectric layers and CESL, as described above. In some embodiments, conductive components are simultaneously formed at the same level of the MLI (such as the M0 level). In some embodiments, conductive components located at the same level of the MLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially planar to each other.

[0052] refer to Figure 1 , 15A 15B and 16, method 100 proceeds to block 104, wherein the semiconductor structure 200 is flipped. A carrier substrate (not shown) may be bonded and / or attached to the front side FS of the semiconductor structure 200 and flipped together with the semiconductor structure 200 such that the back side BS of the semiconductor structure 200 is oriented upwards and the front side FS of the structure 200 is oriented downwards.

[0053] Still referencing Figure 1 , Figure 5A , Figure 5B and Figure 6Method 100 proceeds to block 106, wherein the semiconductor structure 200 is thinned from the back side BS. Specifically, a thinning process can be performed to reduce the thickness of the substrate 202 (e.g., along the Z direction) to a range between about 10 nm and about 50 nm. The thinning process is applied to the back side BS of the semiconductor structure 200. In some embodiments, after the thinning process, a portion of the substrate 202, including the semiconductor substrate 204 (or mesa 204), is retained. The thinning process can include a polishing process, a planarization process (e.g., CMP), an etching process, other suitable processes, or combinations thereof. In some embodiments, the thinning process stops upon reaching the isolation member 218. In some embodiments, the thinning process can reduce the thickness of the isolation member 218 (e.g., along the Z direction). The thickness of the isolation member 218 can be in the range between about 5 nm and about 50 nm.

[0054] Still referencing Figure 1 , Figure 5A , Figure 5B and Figure 6 Method 100 proceeds to block 108, wherein a first dielectric layer 270 is deposited over the back side BS of the thinned semiconductor structure 200, and a second dielectric layer 272 is deposited over the first dielectric layer 270.

[0055] The first dielectric layer 270 may include a low-k dielectric material. In some embodiments, the first dielectric layer 270 may include SiN, SiCN, SiC, or combinations thereof. In some embodiments, the first dielectric layer 270 and the fin-cut structure 220 have different compositions. In some other embodiments, the first dielectric layer 270 includes the same composition as the fin-cut structure 220 and may be incorporated with the fin-cut structure 220. Forming the first dielectric layer 270 may include deposition processes such as, for example, chemical vapor deposition (CVD), flowable CVD (FCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coated glass (SOG), other suitable methods, or combinations thereof. The first dielectric layer 270 may have a thickness in the range of about 1 nm to about 30 nm along the Z-direction, or optionally may have a thickness in the range of about 1 nm to about 15 nm. In at least some cases, the first dielectric layer 270 has a thickness in the range of about 10.5 nm to 12.5 nm.

[0056] In some embodiments, the second dielectric layer 272 may comprise oxides, nitrides, carbides, or combinations thereof. For example, in some cases, the second dielectric layer 272 may comprise silicon oxide, SiCO, SiN, SiCN, aluminum oxide (e.g., Al2O3), or combinations thereof. In at least some embodiments, the second dielectric layer 272 comprises SiO2. In some cases, the second dielectric layer 272 and the first dielectric layer 270 may have different compositions. In some embodiments, the second dielectric layer 272 may have a greater thickness along the Z-direction than the first dielectric layer 270. In some examples, the second dielectric layer 272 may have a thickness of about 10 nm to about 100 nm along the Z-direction. In at least some cases, the second dielectric layer 272 has a thickness in the range of about 23 nm and 26 nm. The second dielectric layer 272 may be formed using suitable deposition processes, such as those described above for forming the first dielectric layer 270.

[0057] Still referencing Figure 1 , Figure 5A , Figure 5B and Figure 6 Method 100 proceeds to block 110, wherein a hard mask 275 is formed over the second dielectric layer 272. In some embodiments, the hard mask 275 may include hard mask layers 274 and 276. Hard mask layer 274 is disposed on the second dielectric layer 272, and hard mask layer 276 is disposed on hard mask layer 274. The thickness of hard mask layer 276 may be less than the thickness of hard mask layer 274. Hard mask layers 274 and 276 may be formed by CVD, ALD, other suitable processes, or combinations thereof. Hard mask layers 274 and 276 may be formed by the same type of deposition process or different types of deposition processes. The composition of hard mask layer 274 may be different from the composition of hard mask layer 276. In some embodiments, each of hard mask layers 274 and 276 includes silicon, oxygen, nitrogen, carbon, or combinations thereof. For example, hard mask layer 274 may be a silicon oxide layer, and hard mask layer 276 may be a silicon nitride layer.

[0058] refer to Figure 1 , Figure 7A , Figure 7B and Figure 8Method 100 proceeds to block 112, where a hard mask 275, a second dielectric layer 272, and a first dielectric layer 270 are patterned to form a trench 280. As shown, the trench 280 exposes a semiconductor substrate 204 (or mesa 204) overlapping with corresponding source / drain structures 214 (such as N-type source / drain structure 214N and P-type source / drain structure 214P) in a top view. In some embodiments, the process performed at block 112 may include forming a patterned photoresist layer 278 over the hard mask 275, and using the patterned photoresist layer 278 as an etching mask to etch the hard mask 75, the second dielectric layer 272, and the first dielectric layer 270. In some cases, an implantation process may be performed before using the patterned photoresist layer 278 as an etching mask to increase the width of the openings of the patterned photoresist layer 278 along the X direction, thereby increasing the width of the trench 280 formed by the etching process.

[0059] The patterning process of frame 112 may include photolithography and etching processes. In an example process, a photoresist layer may initially be deposited over semiconductor structure 200, including over hard mask 275. The photoresist layer is then exposed to radiation passing through or reflected from the mask, baked in a post-bake process, and developed in a developer to form a patterned photoresist layer 278, such as... Figure 7A , Figure 7B and Figure 8 As shown. In the illustrated embodiment, the patterned photoresist layer 278 has an opening directly located on the source / drain structure 214. In some embodiments, an etching process is then performed to etch the hard mask 275, the second dielectric layer 272, and the first dielectric layer 270 when the patterned photoresist layer 278 is used as an etching mask. In some examples, the etching process may include an isotropic etching process and / or anisotropic etching process. In some embodiments, the etching process is anisotropic etching process. In various embodiments, the etching process may include a dry etching process. A dry etching process may include using argon (Ar), oxygen (O2), nitrogen (N2), hydrogen (H2), C m H n F p Plasma of (m being about 1 to about 6, n being about 1 to about 5, and p being about 1 to about 8) or combinations thereof. In some embodiments, the patterned photoresist layer 278 and hard mask 275 may be selectively removed during or after the etching process. After frame 112 is completed, semiconductor substrate 204 (or mesa 204) may be exposed by trench 280.

[0060] Still referencing Figure 1 , Figure 7A , Figure 7B and Figure 8Method 100 proceeds to block 114, wherein a cleaning process is performed to clean the surface of the semiconductor structure 200, including the surface within the trench 280. In some embodiments, the cleaning process includes wet cleaning. In some examples, wet cleaning includes using a mixture of deionized water, ammonium hydroxide and hydrogen peroxide, a mixture of deionized water, hydrochloric acid and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. In some examples, wet cleaning is performed at a temperature above room temperature (e.g., above 100°C in one example).

[0061] refer to Figure 1 , Figure 9A , Figure 9B and Figure 10 Method 100 proceeds to block 116, where an etching process 281 is performed on the semiconductor substrate 204 (or mesa 204) to extend trench 280 and expose the epitaxial layer of the source / drain structure 214. Specifically, trench 280 exposes a second layer 214N-4 of the N-type source / drain structure 214N and a second layer 214P-4 of the P-type source / drain structure 214P. In various embodiments, trench 280 for both N-type and P-type devices can be formed simultaneously. In other cases, devices for N-type and P-type devices can be formed separately, as further described below.

[0062] refer to Figure 9A , Figure 9B and Figure 10 In some embodiments, for the N-type source / drain structure 214N, after etching process 281, trench 280 extends through semiconductor substrate 204 (or mesa 204) and interposer (including separator layer 214-1 and bottom layer 214-2), and exposes the epitaxial layer of N-type source / drain structure 214N. In some embodiments, for the P-type source / drain structure 214P, after etching process 281, trench 280 extends through semiconductor substrate 204 (or mesa 204) and separator layer 214-1 (because, as discussed above, P-type source / drain structure 214P does not include bottom layer 214-2), and exposes the epitaxial layer of P-type source / drain structure 214P.

[0063] Etching process 281 may use the second dielectric layer 272 as an etching mask. Etching process 281 may include, for example, transferring a pattern in the second dielectric layer 272 to a component (e.g., semiconductor substrate 204 or mesa 204) beneath the trench 280 by removing portions of the semiconductor substrate 204 (or mesa 204) exposed by the trench 280. Etching process 281 may also include removing an interposer layer or portions thereof (if present) exposed by the trench 280 after removing portions of the semiconductor substrate 204 (or mesa 204). In various examples, etching process 281 may include isotropic and / or anisotropic etching processes. In at least some embodiments, etching process 281 includes anisotropic etching processes. In some embodiments, etching process 281 may also form a tapered profile for the trench 280, as shown.

[0064] In some examples, a sulfur-containing gas can be used to perform the etching process 281. In some embodiments, the sulfur-containing gas may include sulfur dioxide (SO2), carbonyl sulfide (COS), sulfur hexafluoride (SF6), or a combination thereof. In some examples, the etchant gas may also include C x H y F z The etchant gas is a gas, where x, y, and z are integers. In a particular example, the etchant gas may include CHF3. In other embodiments, the etchant gas may also include N2 gas, O2 gas, or combinations thereof. In various embodiments, during the etching of the back-side via (VB) at frame 116, the disclosed etchant gas used during etching process 281 may react with Ge and / or Si (or more generally with the material exposed by trench 280) to form passivation layer 273. Thus, in some cases, etching process 281 may include simultaneous etching and passivation processes. In various embodiments, passivation layer 273 is used to suppress SiGe etching and thus improve Si / SiGe etch selectivity. In other words, in various embodiments, passivation layer 273 may have a lower etch rate than SiGe. As a result, excessively deep trenches can be avoided, particularly for P-type devices that do not include the portion of the bottom layer 214-2 as the P-type source / drain structure 214P and include the portion of SiGe as the epitaxial layer of the P-type source / drain structure 214P. In other words, for N-type and P-type devices, the trench 280 formed by etching process 281 extends to a depth insufficient to be directly laterally adjacent to the corresponding semiconductor channel layer 208 closest to the semiconductor substrate 204 (or mesa 204). In some cases, passivation layer 273 may provide sulfur (S) passivation. In some embodiments, passivation layer 273 may provide oxygen (O) passivation, carbon (C) passivation, or oxygen / carbon passivation. For example, by using SO2, COS, SF6, or a combination thereof as the etchant gas, passivation layer 273 may include GeS... x Cy F z (x, y, and z are integers), GeS x C y F z Used to suppress SiGe etching and provide high Si / SiGe etch selectivity. In some embodiments, passivation layer 273 can provide CHF polymer passivation. For example, by using C x H y F z The passivation layer 273 may include GeCHF and / or SiCHF, which also serve to suppress SiGe etching and provide high Si / SiGe etch selectivity. In some embodiments, GeCHF can passivate more effectively than SiCHF due to its lower volatility. In some examples, the passivation layer 273 may provide N2 / O2 passivation. For example, by using N2 gas, O2 gas, or a combination thereof (and optionally a fluorinated gas, such as CHF3) as the etchant gas, O2 gas can oxidize the surface of Ge after Si is consumed by F, and the combination with N2 gas can form NO, which weakens SiO bonds and forms GeO. x N y The non-volatile layer serves as passivation layer 273, which also suppresses SiGe etching and provides high Si / SiGe etching selectivity. It will be understood that in various embodiments, the various etchant gases can be used alone or in combination with other gases in the etchant gas family. Therefore, in some cases, passivation layer 273 may comprise a single-layer structure or a multilayer structure comprising one or more of the material layer components described above. It should also be noted that etching process 281 may also use other gases, such as H2, Ar, other fluorine-containing gases (such as C4F6), or other suitable gases.

[0065] As an example, an exemplary process formulation of an embodiment of etching process 281 including sulfur (S) passivation and CHF polymer passivation is now described. In this example, the etchant gas used for etching process 281 may include C4F6 (provided at a flow rate of about 5 sccm (standard cubic centimeters per minute) to 35 sccm), COS (provided at a flow rate of about 10 sccm to 50 sccm), CHF3 (provided at a flow rate of about 10 sccm to 50 sccm), H2 (provided at a flow rate of about 100 sccm to 400 sccm), Ar (provided at a flow rate of about 0 sccm to 900 sccm), and N2 (provided at a flow rate of about 0 sccm to 900 sccm). Continuing with this example, etching process 281 can be performed at a pressure of about 5 mT to about 70 mT and a temperature between about 30 degrees Celsius and about 60 degrees Celsius. Furthermore, the plasma of the etching process 281, which uses one or more of the gases, can be provided using a duty cycle between about 0 and 90% and a pulse frequency between about 10 Hz and about 10,000 Hz.

[0066] In various embodiments, etching process 281 may form trench 280 using a single etching process or a multi-step etching process. Regarding multi-step processes, in some embodiments, for the N-type source / drain structure 214N, multiple steps may be used to remove portions of the semiconductor substrate 204 and the interposer (including separator layer 214-1 and bottom layer 214-2), such as a first etching process selectively removing portions of the semiconductor substrate 104 without etching (or ignoring) the interposer; a second etching process selectively removing portions of the separator layer 214-1 without etching (or ignoring) the bottom layer 214-2; and a third etching process selectively removing portions of the bottom layer 214-2. In some embodiments, different etchants and / or etching parameters may be used in different etching processes within the multi-step process for the N-type source / drain structure 214N. Still regarding multi-step processes, in some examples, for the P-type source / drain structure 214P, a multi-step process can be used to remove portions of the semiconductor substrate 204 and the separator layer 214-1 (as discussed above, since the P-type source / drain structure 214P does not include the underlying layer 214-2), such as a first etching process that selectively removes portions of the semiconductor substrate 204 without etching (or negligibly removes) the separator layer 214-1; and a second etching process that selectively removes portions of the separator layer 214-1. In some embodiments, different etchants and / or etching parameters can be used in different etching processes of the multi-step process for the P-type source / drain structure 214P.

[0067] In some embodiments, as previously described, the presence of the bottom layer 214-2 in the N-type source / drain structure 214N can serve as an etch stop layer to prevent excessive recessing during the formation of the back-side via. It should be noted that although the passivation layer 273 is shown as being formed in both the N-type and P-type device regions, the bottom layer 214-2 can primarily serve to prevent excessive recessing in the N-type device region. Certainly, in some examples, the presence of the passivation layer 273 can further contribute to preventing excessive recessing in the N-type device region. In contrast, since the P-type device source / drain structure 214P does not include (or has no) an etch stop layer (bottom layer 214-2), the passivation layer 273 can primarily serve to prevent excessive recessing in the P-type device region. In at least some examples, trenches 280 for the back-side via can be formed individually for each of the N-type and P-type device regions. In such examples, the etching process for the N-type device region can use one or more optional etchant gases that do not form the passivation layer 273 in the N-type device region.

[0068] refer to Figure 1 , Figure 11A , Figure 11B and Figure 12 Method 100 proceeds to block 118, wherein after etching process 281, an ashing process and a cleaning process may be performed to remove the passivation layer 273 and etching residues (e.g., such as N2, H2, etc.) formed by etching process 281, and to clean the exposed surfaces in trench 280. In some embodiments, the ashing process may use oxygen or hydrogen ashing, and the cleaning process may be similar to that described above at block 114. In some cases, after the ashing process, at least some C (if used as part of etching process 281) may remain disposed along the bottom surface of trench 280. In some embodiments, the cleaning process may apply a hot SPM solution (a mixture of sulfuric acid and hydrogen peroxide) at a temperature, for example, above 100°C. Figure 11A and Figure 11B As shown, since the P-type device source / drain structure 214P does not include an etch stop layer (bottom layer 214-2), the recess depth R1 of the trench 280 in the N-type device region can be smaller than the recess depth R2 of the trench in the P-type device region. As shown, the recess depths R1 and R2 can be measured from the corresponding surface of the semiconductor substrate 204 (or mesa 204) to the bottom surface of the trench 280. In some embodiments, the recess depth R1 in the N-type device region can be in the range of approximately 8.2 nm to approximately 8.6 nm, and the recess depth R2 in the P-type device region can be in the range of approximately 9.7 nm to approximately 10.3 nm. Typically, the difference between the recess depth R1 and the recess depth R2 can be between approximately 1 nm and 2 nm.

[0069] refer to Figure 1 , Figure 13A , Figure 13B and Figure 14 Method 100 proceeds to block 120, wherein a back-side contact 285 is formed in trench 280. In some embodiments, the back-side contact 285 may have substantially the same recess depths R1, R2 as discussed above with respect to trench 280. Forming the back-side contact 285 may include depositing a dielectric liner 284 in trench 280, etching through a bottom portion of the dielectric liner 284, forming a silicide component 286 (e.g., including an N-type source / drain structure 214N and a P-type source / drain structure 214P) on an epitaxial layer of the source / drain structure 214, and forming a metal filler 288 in trench 280 and over the dielectric liner 284 and the silicide component 286. In some embodiments, the back-side contact 285 may be formed simultaneously for each of the N-type source / drain structure 214N and the P-type source / drain structure 214P. Optionally, in some examples, for each of the N-type source / drain structure 214N and the P-type source / drain structure 214P, the back-side contact component 285 can be formed individually (e.g., sequentially).

[0070] The dielectric liner 284 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the dielectric liner 284 includes silicon nitride. The dielectric liner 284 may have a thickness of about 1 nm to about 10 nm. For example, the dielectric liner 284 may be formed by conformally blanket-depositing a dielectric material layer over the back side of the semiconductor structure 200 using a process such as CVD, SACVD, ALD, PVD, or other suitable processes. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back process (e.g., an anisotropic etch-back process) to remove the dielectric material layer from the horizontal surface of the semiconductor structure 200 outside the trench 280. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof. In some embodiments, the etch-back process includes a directional etching process. In an embodiment, after the etch-back process, the surfaces of the epitaxial layers (e.g., second layer 214N-4 and second layer 214P-4) of the N-type source / drain structure 214N and the P-type source / drain structure 214P are exposed. A dielectric material layer may be retained as a dielectric liner 284 on the sidewalls of the semiconductor substrate 204 (or mesa 204), the interposer (if present), the first dielectric layer 270, and the second dielectric layer 272. The dielectric liner 284 provides electrical isolation between the metal filler 288 and surrounding components (e.g., the semiconductor substrate 204). In some embodiments, the deposited dielectric material layer used to form the dielectric liner 284 is first treated to alter its composition. In this case, the treated portion of the dielectric material layer is retained after the etch-back process to form the dielectric liner 284, and the untreated portion is removed by the etch-back process. In a further disclosed embodiment, the dielectric liner 284 may comprise silicon oxide, and the processing may include an ion implantation process using suitable ions (such as nitrogen ions) to introduce nitrogen into the bottom portion of the dielectric material layer. Thereafter, the processed portion of the dielectric material layer may be selectively removed by an etch-back process using a suitable etchant (e.g., phosphoric acid). In embodiments where the bottom layer 214-2 is substantially unetched during etching process 281 (for N-type device regions, since the P-type device regions do not include the bottom layer 214-2), the bottom layer 214-1 may be removed in the etch-back process to expose the epitaxial layer of the N-type source / drain structure 214N.

[0071] After forming the dielectric liner 284, a silicide component 286 may be formed. Forming the silicide component 286 may include depositing one or more metals into the trench 280 using CVD, PVD, ALD, or other suitable methods; performing an annealing process on the semiconductor structure 200 to cause the one or more metals to react with the exposed epitaxial layers of the N-type source / drain structure 214N and the P-type source / drain structure 214P to produce the silicide component 286; and removing unreacted portions of the one or more metals, leaving the silicide component 286 in the trench 280. In such an embodiment, the silicide component 286 is formed on the exposed surfaces of the epitaxial layers of the N-type source / drain structure 214N and the P-type source / drain structure 214P, but not on the exposed sidewall surfaces of the dielectric liner 284. In the illustrated embodiment, the silicide component 286 is formed in the bottom of the trench 280. In various embodiments, the silicide component 286 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. In some embodiments, the silicide component 286 comprises TiSi. The silicide component 286 is formed between the epitaxial layer of the source / drain structure 214 (N-type source / drain structure 214N and P-type source / drain structure 214P) and the metal filler 288 to further reduce contact resistance.

[0072] Metal filler 288 may be disposed above dielectric liner 284 and silicide component 286, and may be laterally surrounded by dielectric liner 284. In various embodiments, metal filler 288 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, metal filler 288 includes W. After forming metal filler 288, a planarization process (e.g., a CMP process) may be performed. Figure 13A , Figure 13B and Figure 14 The semiconductor structure 200 after planarization is shown. Silicide components 286, dielectric liner 284, and metal filler 288 together form a back contact component 285. The back contact component 285 is electrically connected to the corresponding epitaxial layers of the source / drain structures 214 (N-type source / drain structure 214N and P-type source / drain structure 214P).

[0073] refer to Figure 1 , Figure 15A , Figure 15B and Figure 16 Method 100 proceeds to block 122, where a planarization process is performed to remove portions of the back-side contact members 285 in the second dielectric layer 272 and the second dielectric layer 272. In some embodiments, the planarization process also removes a top portion of the first dielectric layer 270 and a portion therein of the back-side contact members 285. The remaining portion of the back-side contact members 285 may be referred to as the back-side source / drain contact 285'. The remaining portion of the first dielectric layer 270 may be referred to as the first dielectric layer 270'. The planarization process may be performed up to, or shortly thereafter, the first dielectric layer 270, resulting in the removal of the top portion of the first dielectric layer 270 (and a portion therein of the back-side contact members 285). After the planarization process is completed, the back-side surfaces of the back-side source / drain contact members 285' and the first dielectric layer 270' form substantially flat surfaces.

[0074] refer to Figure 1 , Figure 17A , Figure 17B and Figure 18 Method 100 proceeds to block 122, wherein a back-side metal line 294 electrically connected to the back-side source / drain contact 285' is formed above the back-side source / drain contact 285'. In various embodiments, a first back-side metal line 294 may be formed above and electrically connected to the back-side source / drain contact 285' of the N-type source / drain structure 214N, and a second back-side metal line 294 may be formed above and electrically connected to the back-side source / drain contact 285' of the P-type source / drain structure 214. In other embodiments, the back-side metal line 294 may be formed above and electrically connected to one of the back-side source / drain contacts 285' of the N-type source / drain structure 214N or the back-side source / drain contacts 285' of the P-type source / drain structure 214P.

[0075] Before forming the back-side metal line 294, a CESL 290 and an ILD layer 292 may be formed over the back-side source / drain contacts 285' and the first dielectric layer 270'. The CESL 290 and ILD layer 292 may be formed using materials and methods similar to those used for the CESL (e.g., 262-0, 262-1, 262-2) and dielectric layers (e.g., 264-0, 264-1, 263-2, 264-2) in the dielectric structure 250. The back-side metal line 294 may be formed by patterning the CESL 290 and ILD layer 292 to form openings to expose the back-side source / drain contacts 285', filling the openings with a conductive material, and performing a planarization process to remove excess material. The conductive material may include metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. The backside metalline 294 may include a barrier layer and a metal filler layer deposited above the barrier layer. The backside metalline 294 may be powered and is referred to as a backside power rail. The CESL 290, ILD layer 292, and backside metalline 294 may be located in the BM0 level of a backside multilayer interconnect (BMLI) structure. The BMLI may include additional metal levels (e.g., BM1, BM2) that include the CESL, ILD layers, and metal lines and / or metal vias embedded in the CESL and ILD layers.

[0076] Semiconductor device 200 may undergo further processing to form various components and regions known in the art. For example, subsequent processing may form additional back-side dielectric layers and contacts / vias / lines over the back side of substrate 202, configured to connect various components to form functional circuitry, which may include one or more devices, including semiconductor structure 200. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures. Furthermore, additional process steps may be performed before, during, and after method 100, and some of the above-described process steps may be modified, replaced, or eliminated according to various embodiments of method 100.

[0077] The description provided herein discloses methods and structures for improving Si / SiGe etching selectivity to achieve suitable back-side via (VB) etching processes for N-type and P-type devices. In some embodiments, the method of etching VBs includes using an etchant gas comprising a sulfur-containing gas. In some embodiments, the sulfur-containing gas may include sulfur dioxide (SO2), carbonyl sulfide (COS), and / or sulfur hexafluoride (SF6). In some examples, the etchant gas may also include C x H y F zThe etchant gas is a gas, where x, y, and z are integers. In a particular example, the etchant gas may include CHF3. In various embodiments, the disclosed etchant gas may react with Ge and / or Si during etching of the back-side via (VB) to form a passivation layer. As a result, excessively deep trenches can be avoided. In some cases, the passivation layer may include S passivation. For example, by adding SO2 / COS / SF6, GeS... x C y F z The formation of (x, y, and z are integers) will passivate and suppress SiGe etching. In other cases, the passivation layer may include CHF polymer passivation. For example, GeCHF and / or SiCHF can be formed as a passivation layer. In other examples, N2 / O2 passivation can be used to form the passivation layer. In various embodiments, regardless of the type of passivation layer used, the passivation layer can be removed before the subsequent formation of a conductive layer (metal layer) within the trench formed by back-side via etching. Embodiments of this disclosure provide improved yield and wafer acceptance testing (WAT) for Super Power Rail (SPR) development. Furthermore, in some embodiments, the chemical reaction principles shown and described regarding the passivation layer and various etchant gases can also be used in other applications (e.g., beyond SPR development) to provide protection for the Ge layer and / or suppress the etching process of the Ge layer.

[0078] Therefore, one embodiment of this disclosure describes a method including providing a semiconductor structure. The semiconductor structure includes a plurality of channels disposed over a substrate; a source / drain structure connected to the plurality of channels, wherein the source / drain structure includes a first layer on the sidewalls of the plurality of channels and a second layer above the first layer; a contact etch stop layer (CESL) above the source / drain structure; and an interlayer dielectric (ILD) layer above the CESL. In some embodiments, the method further includes flipping the semiconductor structure so that the back side of the substrate faces upward, depositing a dielectric layer over the back side of the substrate, and performing an etching process using an etchant gas to form trenches extending through the dielectric layer and the substrate to expose the source / drain structure. In some embodiments, the etchant gas includes a sulfur-containing gas. In some embodiments, during the etching process, the etchant gas reacts with the material exposed by the trench to form a passivation layer within the trench, the passivation layer inhibiting etching of the source / drain structure.

[0079] In some embodiments, the sulfur-containing gas includes at least one of sulfur dioxide (SO2), carbonyl sulfide (COS), and sulfur hexafluoride (SF6).

[0080] In some embodiments, the etchant gas further includes C x H y F z A gas, where x, y, and z are integers.

[0081] In some embodiments, the etchant gas further includes CHF3.

[0082] In some embodiments, the sulfur-containing gas includes at least one of sulfur dioxide (SO2), carbonyl sulfide (COS), and sulfur hexafluoride (SF6), wherein the passivation layer includes GeS. x C y F z , where x, y, and z are integers.

[0083] In some embodiments, the etchant gas further includes C x H y F z The gas, wherein x, y, and z are integers, wherein the passivation layer comprises at least one of GeCHF and SiCHF.

[0084] In some embodiments, the etchant gas further includes N2 gas and O2 gas, and wherein the passivation layer comprises GeO. x N y .

[0085] In some embodiments, the method further includes performing an ashing process and a cleaning process after performing the etching process to remove the passivation layer and etching residue from the trench.

[0086] In some embodiments, the method further includes forming contact components in the trench after performing the etching process.

[0087] In some embodiments, forming the contact component includes: depositing a dielectric liner on the sidewalls of the trench; forming a silicide layer on the exposed surface of the source / drain structure in the trench; and depositing a metal filler over the silicide layer and the dielectric liner.

[0088] In another embodiment, a method of providing a semiconductor structure is discussed. The semiconductor structure includes an active region extending in a first direction in a top view, the active region including a channel region and a source / drain region adjacent to the channel region, wherein the source / drain region includes a first layer on a sidewall of the channel region and a second layer above the first layer. The semiconductor structure also includes a gate structure disposed above the channel region, wherein the gate structure extends in a second direction in a top view, the second direction being different from the first direction. In some embodiments, the method further includes depositing a dielectric layer on a back side of the semiconductor structure, patterning the dielectric layer to form a trench in the dielectric layer exposing a semiconductor substrate overlapping the source / drain region, and performing an etching process to extend the trench through the semiconductor substrate to expose the source / drain region. In some embodiments, the etching process simultaneously forms a passivation layer within the trench, the passivation layer having a lower etch rate than the source / drain region. In some embodiments, the passivation layer provides at least one of sulfur passivation and CHF polymer passivation.

[0089] In some embodiments, the source / drain regions do not have an etch stop layer.

[0090] In some embodiments, the etching process is performed using a sulfur-containing gas, the sulfur-containing gas including at least one of sulfur dioxide (SO2), carbonyl sulfide (COS), and sulfur hexafluoride (SF6).

[0091] In some embodiments, the etching process is performed using CxHyFz gas, where x, y, and z are integers.

[0092] In some embodiments, the passivation layer includes GeSxCyFz, where x, y, and z are integers.

[0093] In some embodiments, the passivation layer includes at least one of GeCHF and SiCHF.

[0094] In some embodiments, the method further includes: removing the passivation layer after performing the etching process; and forming contact components in the trench after removing the passivation layer.

[0095] In yet another embodiment, a semiconductor structure is discussed, comprising: a first plurality of channels disposed over a substrate in a first device type region; and a first source / drain component connected to the first plurality of channels, the first source / drain component including an etch stop layer at its bottom. In some embodiments, the semiconductor structure further comprises a second plurality of channels disposed over a substrate in a second device type region; and a second source / drain component connected to the second plurality of channels, the second source / drain component not having an etch stop layer at its bottom. In some embodiments, the semiconductor structure further comprises a contact etch stop layer (CESL) above the first source / drain component, an interlayer dielectric (ILD) layer above the CESL, and contact components extending through at least one of the ILD layers in the first and second device type regions to be electrically coupled to a corresponding one of the first and second source / drain components. In some embodiments, the semiconductor structure further comprises a dielectric layer disposed on a back side of the substrate, a first back-side contact component extending through the dielectric layer in the first device type region, the substrate, and the etch stop layer to be electrically coupled to the first source / drain component. In some embodiments, the semiconductor structure further includes a second back-side contact extending through the dielectric layer and substrate in the second device type region to be electrically coupled to a second source / drain component.

[0096] In some embodiments, the first back-side contact member has a first recessed depth, and wherein the second back-side contact member has a second recessed depth different from the first recessed depth, and wherein the difference between the first recessed depth and the second recessed depth is between about 1 nm and 2 nm.

[0097] In some embodiments, the first device type region includes an N-type device type region, and the second device type region includes a P-type device type region.

[0098] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A semiconductor structure is provided, the semiconductor structure comprising: a plurality of channels disposed above a substrate; a source / drain structure connected to the plurality of channels, wherein the source / drain structure includes a first layer located on the sidewalls of the plurality of channels and a second layer located above the first layer; a contact etch stop layer located above the source / drain structure; and an interlayer dielectric layer located above the contact etch stop layer; Flip the semiconductor structure so that the back side of the substrate faces upward; A dielectric layer is deposited over the back side of the substrate; An etching process is performed using an etchant gas to form trenches that extend through the dielectric layer and the substrate to expose the source / drain structure. The etchant gas includes a sulfur-containing gas; and During the etching process, the etchant gas reacts with the material exposed by the trench to form a passivation layer within the trench, which inhibits the etching of the source / drain structure.

2. The method according to claim 1, wherein, The sulfur-containing gas includes at least one of sulfur dioxide (SO2), carbonyl sulfide (COS), and sulfur hexafluoride (SF6).

3. The method according to claim 1, wherein, The etchant gas also includes C x H y F z A gas, where x, y, and z are integers.

4. The method according to claim 1, wherein, The etchant gas also includes CHF3.

5. The method according to claim 2, wherein, The passivation layer includes GeS. x C y F z , where x, y, and z are integers.

6. The method according to claim 3, wherein, The passivation layer includes at least one of GeCHF and SiCHF.

7. The method according to claim 1, wherein, The etchant gas also includes N2 gas and O2 gas, and the passivation layer includes GeO. x N y .

8. The method according to claim 1, further comprising: After the etching process is performed, an ashing and cleaning process is performed to remove the passivation layer and etching residue from the trench.

9. A method for forming a semiconductor device, comprising: A semiconductor structure is provided, the semiconductor structure comprising: an active region extending in a first direction in a top view, the active region including a channel region and a source / drain region adjacent to the channel region, wherein the source / drain region includes a first layer located on a sidewall of the channel region and a second layer located above the first layer; and a gate structure disposed above the channel region, wherein the gate structure extending in a second direction in the top view, the second direction being different from the first direction; A dielectric layer is deposited on the back side of the semiconductor structure; Patterning the dielectric layer to form trenches in the dielectric layer, the trenches exposing a semiconductor substrate that overlaps with the source / drain regions; and An etching process is performed to extend the trench through the semiconductor substrate to expose the source / drain regions; The etching process simultaneously forms a passivation layer within the trench, the passivation layer having a lower etching rate than the source / drain regions; and The passivation layer provides at least one of sulfur passivation and CHF polymer passivation.

10. A semiconductor structure, comprising: The first plurality of channels are disposed above the substrate in the first device type region; A first source / drain component is connected to the first plurality of channels, and the first source / drain component includes an etch stop layer located at the bottom of the first source / drain component; A second plurality of channels are disposed above the substrate in the second device type region; A second source / drain component is connected to the second plurality of channels, and the second source / drain component does not have the etch stop layer at the bottom of the second source / drain component; A contact etch stop layer is located above the first source / drain component; An interlayer dielectric layer is located above the contact etch stop layer; A contact component extends through the interlayer dielectric layer in at least one of the first device type region and the second device type region to be electrically coupled to a corresponding one of the first source / drain component and the second source / drain component; A dielectric layer is disposed on the back side of the substrate; A first back-side contact component extends through the dielectric layer, the substrate, and the etch stop layer in the first device type region to be electrically coupled to the first source / drain component; as well as The second back-side contact component extends through the dielectric layer and the substrate in the second device type region to be electrically coupled to the second source / drain component.

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