Method of forming a semiconductor device

Abstract

The method includes receiving a substrate having a front side and a back side; forming a source / drain and a gate structure on the front side of the substrate, the gate structure including a gate dielectric layer, a gate electrode, and a gate spacer disposed on a sidewall of the gate electrode, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; forming a capping layer over the back side of the substrate; patterning the capping layer to form a capping layer opening therein, the capping layer opening exposing a portion of the substrate overlapping with the source / drain; forming a back-side source / drain via opening in the substrate exposing the source / drain by patterning the exposed portion of the substrate with the capping layer; performing a back-side ion implantation process on the source / drain from the back side of the substrate by introducing two different materials; and forming a back-side source / drain via in the back-side source / drain via opening. Embodiments of this disclosure also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of this disclosure relate to methods for forming semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of handling and manufacturing ICs, and similar advancements in IC handling and manufacturing are needed to achieve these progresses. For example, to further reduce the density of advanced IC technology nodes, front-side and back-side interconnect structures may be required to facilitate electrical connections and / or operation with IC devices. While existing interconnect structures used to facilitate electrical connections are generally sufficient for their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] One embodiment of this application provides a method for forming a semiconductor device, comprising: receiving a substrate having a front side and a back side; forming a source / drain electrode on the front side of the substrate, and forming a gate structure on the front side of the substrate, the gate structure being adjacent to the source / drain electrode, wherein the gate structure includes a gate dielectric layer, a gate electrode located above the gate dielectric layer, and a gate spacer disposed on the sidewall of the gate electrode and the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; A capping layer is formed on the back side of the substrate; the capping layer is patterned to form a capping opening in the capping layer, the capping opening exposing a portion of the substrate overlapping the source / drain; a back-side source / drain via opening is formed in the substrate exposing the source / drain by patterning the exposed portion of the substrate using the capping layer; a back-side ion implantation process is performed on the source / drain from the back side of the substrate by introducing two different materials; and a back-side source / drain via is formed in the back-side source / drain via opening.

[0005] Another aspect of this application provides a method for forming a semiconductor device, comprising: forming a plurality of channels on a front side of a substrate; forming source / drain electrodes connected to the plurality of channels; and forming a gate structure surrounding the plurality of channels; forming a capping layer over a back side of the substrate; patterning the capping layer to form a capping layer opening in the capping layer, the capping layer opening exposing a portion of the substrate overlapping the source / drain electrodes; forming a back-side source / drain via opening in the substrate exposing the source / drain electrodes by patterning the exposed portion of the substrate using the capping layer; and forming dielectric via spacers on the sidewalls of the back-side source / drain via openings, wherein the gate structure surrounds the source / drain electrodes. The device includes a gate dielectric layer of a first dielectric material having a first dielectric constant and a dielectric via spacer of a second dielectric material having a second dielectric constant less than the first dielectric constant; performing a back-side ion implantation process on the source / drain from the back side of the substrate, wherein the back-side ion implantation process includes performing a first ion implantation process to pre-amorphize the source / drain by introducing a first material into the source / drain, performing a second ion implantation process by introducing a second material into the source / drain, the second material being different from the first material, and performing an annealing process on the source / drain; and forming a back-side source / drain via in the opening of the back-side source / drain via.

[0006] This application provides, in another aspect, a method for forming a semiconductor device, comprising: receiving a substrate having a front side and a back side; forming a source / drain electrode on the front side of the substrate, and forming a gate structure on the front side of the substrate, the gate structure being adjacent to the source / drain electrode, wherein the gate structure includes a gate dielectric layer, a gate electrode located above the gate dielectric layer, and a gate spacer disposed on the sidewalls of the gate electrode and the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; forming a capping layer above the back side of the substrate; patterning the capping layer to form a capping layer opening in the capping layer, the capping layer opening exposing a portion of the substrate overlapping the source / drain electrode; and using the capping layer to pattern the exposed portion of the substrate, in the... The process involves forming a back-side source / drain via opening in the substrate to expose the source / drain; performing a first ion implantation process by introducing a first material into the source / drain to pre-amorphize the source / drain; performing a second ion implantation process on the source / drain by introducing a second material into the source / drain, the second material being different from the first material; subsequently, performing an annealing process on the source / drain; and forming a back-side source / drain via opening in the back-side source / drain via opening, wherein the first ion implantation process includes a first implantation step having a first tilt angle and a second implantation step having a second tilt angle greater than the first tilt angle, and the second ion implantation process includes a third implantation step having a third tilt angle and a fourth implantation step having a fourth tilt angle greater than the third tilt angle. Attached Figure Description

[0007] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 , Figure 14 , Figure 18 and Figure 22 This is a flowchart of part or all of a method for manufacturing a two-sided interconnect structure for a device according to various aspects of this disclosure.

[0009] Figure 2 , Figure 3 , Figure 4 and Figure 5 Based on all aspects of this disclosure and Figure 1 The method relates to partial or complete cross-sectional views of the device at various manufacturing stages.

[0010] Figures 6A to 13A Based on all aspects of this disclosure and Figure 1 The method relates to partial or complete cross-sectional views of the device at various manufacturing stages.

[0011] Figures 6B to 13B Based on all aspects of this disclosure and Figure 1 The method relates to partial or complete cross-sectional views of the device at various manufacturing stages.

[0012] Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 19 , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 23 , Figure 24A , Figure 24B , Figure 25A and Figure 25B Based on all aspects of this disclosure and Figure 1 The method relates to partial or complete cross-sectional views of the device at various manufacturing stages.

[0013] Figure 26 Based on all aspects of this disclosure and Figure 1 The method is associated with partial or complete schematic views of the device at various manufacturing stages. Detailed Implementation

[0014] This disclosure generally relates to two-sided interconnects for devices (such as multi-gate devices and / or stacked devices) and methods of manufacturing the same.

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, for the convenience of describing the relationship between one component and another component in this disclosure, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used. Spatially relative terms are intended to include different orientations of devices (including components). Reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having characteristics associated with that value, the value or range encompasses a reasonable range including the described value, such as within + / -10% of the described value. For instance, a material layer with a thickness of "about 5 nm" can encompass dimensions ranging from 4.5 nm to 5.5 nm, where a manufacturing tolerance of + / -10% is known to one of ordinary skill in the art to be associated with the deposited material layer. Furthermore, taking into account variations inherent in any manufacturing process, when a device component is described as having "basic" characteristics and / or features, the term is intended to capture characteristics and / or features within the tolerances of the manufacturing process. For example, a "basically vertical" or "basically horizontal" component is intended to capture a component that is approximately vertical and horizontal—but not mathematically or perfectly vertical and horizontal—within a given tolerance of the manufacturing process used to manufacture such a component.

[0017] Figure 1 This is a flowchart of part or all of a method 10 for manufacturing a dual-side device hierarchy interconnect structure according to various aspects of this disclosure. Figures 2 to 15 It is based on the various aspects of this disclosure in relation to Figure 1Method 10 describes partial or complete cross-sectional views of the IC structure (or simply device) 100 at various manufacturing stages associated with it. Device 100 may be included in a microprocessor, memory, other integrated circuit (IC) device, or a combination thereof. In some embodiments, device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, and includes various passive and / or active electronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Various transistors may be planar or non-planar transistors, such as FinFETs or gate-all-around (GAA) transistors. For ease of description and understanding, this document also discusses… Figure 1 and Figures 2 to 15 For clarity, the following has been simplified. Figure 1 and Figures 2 to 15 To better understand the inventive concept of this disclosure. Additional steps may be provided before, during, and after method 10, and for additional embodiments of method 10, some described steps may be moved, replaced, or eliminated. Figures 2 to 15 Add additional components to device 100, and Figures 2 to 15 In other embodiments of device 100, some of the components described below may be replaced, modified, or eliminated.

[0018] refer to Figure 1 and Figure 2 Method 10 at block 15 includes receiving a workpiece (e.g., a device or IC structure 100) that has undergone FEOL processing, which may include forming electrical functional devices (e.g., transistors 104A, 104B, 104C, and 104D) on a substrate (e.g., a silicon substrate) 102. Device 100 and / or the electrical functional devices include various components / assemblies such as mesa 102' (e.g., an extension of substrate 102), substrate isolation structure (or simply isolation structure) 106, semiconductor layer 110, gate structures 112 (each having a corresponding gate stack 114 and a corresponding gate spacer 116), internal spacers 118, source / drain 120, and a first-level dielectric layer (e.g., ILD0, which may include a contact etch stop layer (CESL) 122 and an interlayer dielectric (ILD) layer 124). The various components / assemblies and their corresponding configurations are merely exemplary. This disclosure contemplates that device 100 may have any combination of parts / components and / or devices, and any configuration of such parts / components and / or devices that can be manufactured by FEOL processing.

[0019] In the depicted embodiments, transistors 104A-104D are GAA transistors. For example, each of transistors 104A-104D has three channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by semiconductor layer 110, which are suspended over substrate 102 and extend between respective source / drain terminals (e.g., source / drain 120). In some embodiments, transistors 104A-104D include more or fewer channels (and therefore more or fewer semiconductor layers 110). Each of transistors 104A-104D also has a respective gate stack 114 located over its semiconductor layer 110, bonding its semiconductor layer 110, and located between its source / drain terminals 120 (e.g., epitaxial source / drain). Along the gate width direction (e.g., in the XZ cross-sectional view), the gate stack 114 is located above the top semiconductor layer 110, between the semiconductor layers 110, and between the bottom semiconductor layer 110 and the substrate 102 (e.g., its mesa 102'). Along the gate longitudinal direction (e.g., in the YZ cross-sectional view), the gate stack 114 wraps around and / or surrounds the respective semiconductor layer 110. During operation of the GAA transistor, current can flow through the semiconductor layers 110 and between the source and drain 120.

[0020] Substrate 102 and semiconductor layer 110 include: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiments, substrate 102 and semiconductor layer 110 include silicon. In some embodiments, substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. Substrate 102 (including mesa 102' extending therefrom) may include various doped regions, such as p-wells and n-wells. n-wells are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-wells are doped with p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, semiconductor layer 110 includes p-type dopants, n-type dopants, or combinations thereof.

[0021] Substrate isolation structure 106 electrically isolates active device regions and / or passive device regions. For example, substrate isolation structure 106 separates and electrically isolates active regions (such as transistors 104A-104D) from other device regions and / or devices. Substrate isolation structure 106 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof), or combinations thereof. Substrate isolation structure 106 may have a multilayer structure. For example, substrate isolation structure 106 includes a bulk dielectric (e.g., an oxide layer) over a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof). In another example, substrate isolation structure 106 includes a bulk dielectric over a doped liner (such as a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner). The dimensions and / or characteristics of the substrate isolation structure 106 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a localized oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof.

[0022] Gate stacks 114 are configured to achieve desired functionality according to the design requirements of device 100, and the gate stacks 114 of transistors 104A-104D may include the same or different layers and / or materials. Each gate stack includes a corresponding gate dielectric 126 and a corresponding gate electrode 128. The gate dielectric 126 includes at least one dielectric gate layer, and the gate electrode 128 includes at least one conductive gate layer. For example, the gate dielectric 126 may include an interface layer 130 and a high-k dielectric layer 132, and the gate electrode 128 may include a work function layer 134, a body (fill) layer 136, and an intermediate gate electrode layer 138. The interface layer 130 includes a dielectric material such as SiO2 or SiGeO. x High-k dielectric layer 132 includes high-k dielectric materials, which typically refer to dielectric materials with a dielectric constant greater than that of silicon dioxide (k≈3.9), such as HfO2, HfSiO, HfSiO4, HfSSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. The work function layer 134 is a conductive layer tuned to have a desired work function (such as an n-type or p-type work function). The function layer 134 comprises a function metal and / or an alloy thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. The body layer 136 comprises Al, W, Co, Cu, polycrystalline silicon, other suitable conductive materials, alloys thereof, or combinations thereof. The intermediate gate electrode layer 138 may include a cap (e.g., a metal nitride cap and / or a silicon cap above the function layer 134) and / or a barrier layer (e.g., a cap and / or a metal nitride barrier above the function layer 134). The intermediate gate electrode layer 138 may include materials that prevent or eliminate diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers, such as between the function layer 134 and the body layer 136. In some embodiments, the intermediate gate electrode layer 138 includes metals and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, silicon titanium nitride, silicon tantalum nitride, other suitable metal nitrides, or combinations thereof. In some embodiments, the gate stack 114 also includes a hard mask located above the gate electrode 128 and between the gate spacer 116. The hard mask includes a material different from the first-level dielectric layer to achieve etch selectivity during subsequent processing. In some embodiments, the hard mask includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbs, or combinations thereof. In some embodiments, the hard mask comprises a metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, aluminum zirconium oxide, other metal oxides, other metal nitrides, or combinations thereof. In some embodiments, the interface layer 130, the high-k dielectric layer 132, the work function layer 134, the body layer 136, the intermediate gate electrode layer 138, other gate stack layers, or combinations thereof have a multilayer structure. In various embodiments, the dielectric constant of the gate dielectric 126 is greater than the dielectric constant of other dielectric materials, such as the substrate isolation structure 106, the back-side source / drain via spacer 210 (described later), the ILD layer 124 (described later), and / or the gate spacer 116.

[0023] Gate spacer 116 is disposed along the sidewall of the top portion of gate stack 114, fin / mesa spacers may be disposed along the sidewall of mesa 102', and inner spacer 118 is disposed below gate spacer 116 along the sidewall of gate stack 114. The inner spacer 118 is located between semiconductor layers 110, between semiconductor layers 110 and mesa 102', and between gate stack 114 and source / drain 120. Gate spacer 116, fin / mesa spacers, and inner spacer 118 comprise a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof). Gate spacer 116, fin / mesa spacers, and inner spacer 118 may comprise different materials and / or different configurations (e.g., different numbers of layers). In some embodiments, the gate spacer 116, the fin / mesa spacer, the internal spacer 118, or combinations thereof have a multilayer structure. In some embodiments, the gate spacer 116 and / or the fin / mesa spacer includes more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. Each set of spacers may have different compositions.

[0024] The source / drain 120 comprises a semiconductor material, which may be doped with n-type and / or p-type dopants. The source / drain 120 comprises multiple semiconductor layers and / or semiconductor materials, and each semiconductor layer / material may comprise the same or different materials and / or the same or different dopant concentrations. In some embodiments, the semiconductor material is epitaxially grown from mesa 102' and / or semiconductor layer 110, and the source / drain 120 may be referred to as an epitaxial source / drain. In some embodiments, the source / drain 120 comprises silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., Si:C source / drain, Si:P source / drain, or Si:C:P source / drain). In some embodiments, the source / drain 120 comprises silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof (e.g., Si:Ge:B source / drain). The source / drain 120 may have the same or different compositions and / or materials, depending on the configuration of their respective transistors. For example, the source / drain 120 of an n-type transistor may include silicon doped with phosphorus and / or carbon, and the drain / source 120 of a p-type transistor may include silicon germanium doped with boron. In some embodiments, the source / drain 120 includes materials and / or dopants that achieve desired tensile and / or compressive stresses in adjacent channel regions (e.g., semiconductor layer 110). As used herein, source / drain regions, source / drain, source / drain components, etc., may refer to the source of a device (e.g., the source of one of transistors 104A-104D), the drain of a device (e.g., the drain of one of transistors 104A-104D), or the sources and / or drains of multiple devices.

[0025] In the disclosed embodiments, during the formation of the source / drain 120, the source / drain 120 is epitaxially grown through multiple steps, each step having a corresponding precursor, the precursor including a semiconductor-containing gas and a dopant-containing gas. The semiconductor-containing gas includes silicon-containing gases (such as silane SiH4) and / or germanium-containing gases (such as GeH4). The dopant-containing gas includes phosphorus (P) or arsenic (As)-containing gases for the n-type source / drain 120 of an nFET, or boron-containing gases for the p-type source / drain 120 of a pFET. Thus, the source / drain 120 is in-situ doped. However, the formation of the source / drain 120 also includes performing an ion implantation process from the front-side FS to additionally introduce dopant into the source / drain 120, thereby increasing the dopant concentration, increasing the conductivity of the source / drain 120, and reducing the resistance from the front-side power line (such as from the front-side contact, described later) to the source / drain 120. The ion implantation process performed from the front-side FS is also called the front-side ion implantation process, in contrast to the back-side ion implantation process 52 described later (such as...). Figure 14 The front-side ion implantation process differs from the back-side ion implantation process (such as...). Figure 14(as described in method 52), but implemented from the front FS.

[0026] In some embodiments, the source / drain 120 includes multiple semiconductor layers and / or semiconductor materials, and each semiconductor layer / material may include the same or different materials and / or the same or different dopant concentrations. For example, the source / drain 120 may include semiconductor layer 144, semiconductor layer 146, and semiconductor layer 148. Semiconductor layer 146 is disposed above semiconductor layer 110 (e.g., along the sidewall of semiconductor layer 110), and semiconductor layer 148 is disposed on semiconductor layer 146, and semiconductor layer 144 is semiconductor layer 146. In some embodiments, semiconductor layers 144, 146, and 148 have different compositions. For example, semiconductor layers 144, 146, and 148 may include the same semiconductor material but with different dopant concentrations. In a further example, semiconductor layer 144 includes silicon and has a higher dopant concentration than semiconductor layer 148; and semiconductor layer 148 includes silicon and has a higher dopant concentration than semiconductor layer 146. In some embodiments, semiconductor layers 144, 146, and 148 have different dopants and different doping concentrations. For example, semiconductor layer 146 comprises arsenic-doped silicon (SiAs), semiconductor layer 148 comprises phosphorus-doped silicon (SiP), and semiconductor layer 144 comprises phosphorus-doped silicon (SiP). The dopant concentration increases from semiconductor layer 146 to semiconductor layer 148 and further to semiconductor layer 144.

[0027] In some embodiments, the IC structure 100 further includes an interposer layer (such as a first interposer layer 142 and a second interposer layer 150) formed on the bottom of the source / drain to provide isolation between the source / drain 120 and the substrate 102. The first interposer layer 142 is a semiconductor layer. For example, the first interposer layer 142 is an undoped silicon layer, and the second interposer layer 150 comprises one or more dielectric materials, which may be referred to as flexible bottom isolation (FBI). The composition of the second interposer layer 150 differs from that of the first interposer layer 142 to facilitate selective etching during processing, as further described below. For example, the second interposer layer 150 comprises silicon and oxygen, nitrogen, carbon, or combinations thereof. In the depicted embodiments, the second interposer layer 150 is a nitride layer, such as a silicon nitride layer (e.g., SiN). x (layer). In some embodiments, the thickness of the second interposer 150 (e.g., along the z-direction) is about 1 nm to about 10 nm.

[0028] ILD layer 124 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), BSG, PSG, borosilicate glass (BPSG), fluorosilicate glass (FSG), degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutenyl (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 124 includes a dielectric material with a dielectric constant less than that of silicon dioxide. CESL 122 includes a material different from that of ILD layer 124. For example, if ILD layer 124 includes a low-k dielectric material (e.g., porous silicon oxide), CESL 122 may include silicon and nitrogen and / or carbon, such as silicon nitride, silicon carbonitride, or silicon carbonitride. In some embodiments, CESL 122 may include a metal and oxygen, nitrogen, carbon, or combinations thereof. In some embodiments, ILD layer 124 and / or CESL 122 have a multilayer structure. In the following description, for better discussion of the structure of workpiece 100, reference is made to the front side (FS) and back side (BS) of workpiece 100.

[0029] refer to Figure 1 and Figure 3 Method 10 includes forming a front-side rear-end structure 169 at block 20, such as a front-side interconnect structure above various devices, a passivation structure above the front-side interconnect structure, and / or other structures. The front-side interconnect structure includes various conductors (such as metal wires) distributed in one or more metal layers, and also includes contacts and vias to provide vertical connections between devices and metal wires and between metal wires in adjacent metal layers.

[0030] As Figure 3The example shown includes a front-side interconnect structure comprising front-side source / drain contacts formed on the source / drain of a transistor, and method 10 includes forming front-side source / drain contacts 160 on the drain / source of a transistor, such as front-side source / drain contacts 120 on the source / drain of transistors 104A-104D. The front-side source / drain contacts 160 comprise conductive materials such as tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, the front-side source / drain contacts 160 are unobstructed / unlined metal plugs, such as tungsten plugs, cobalt plugs, or ruthenium plugs. For example, each of the front source / drain contacts 160 may include a metal body layer (i.e., a metal plug), such as a tungsten plug, that physically contacts the surrounding dielectric material, such as contact spacer 166, and / or a second-level dielectric layer (e.g., CESL 162 and / or ILD layer 164). In some embodiments, the front source / drain contact 160 includes a metal body layer and one or more barrier / liner layers. The barrier / liner layers are located between the metal body layer and the surrounding dielectric material.

[0031] Forming the front source / drain contact 160 may include depositing a second-level dielectric layer (e.g., ILD1, which may include CESL 162 and ILD layer 164) over a first-level dielectric layer (e.g., ILD0, which may include CESL 122 and ILD layer 124), patterning the second-level dielectric layer and the first-level dielectric layer to form a front source / drain contact opening extending therethrough, the front source / drain contact opening exposing the source / drain 120 (e.g., its semiconductor layer 144), depositing a conductive material over the second-level dielectric layer (filling the front source / drain contact opening), and performing a planarization process (e.g., chemical mechanical polishing (CMP)) to remove portions of the conductive material disposed over the second-level dielectric layer. CESL 162 and ILD layer 164 are similar to CESL 122 and ILD layer 124 described above. A planarization process can be performed until the second-level dielectric layer is reached and exposed, and the remaining portion of the conductive material forms one or more layers of the front source / drain contact 160. In some embodiments, one or more insulating layers can be formed in the front source / drain contact openings before depositing the conductive material, and the insulating layers are patterned to form contact spacers 166. Contact spacers 166 are disposed along the sidewalls of the front source / drain contact 160 and are located between the front source / drain contact 160 and the surrounding dielectric material (e.g., the second-level dielectric layer and the first-level dielectric layer). Contact spacers 166 include dielectric layers and air gaps.

[0032] Prior to depositing the conductive material, a silicide process may be performed to form a front silicide layer 168 on top of and above the source / drain 120, such that the front silicide layer 168 is located between the top of the source / drain 120 (e.g., formed by its semiconductor layers 144 and 148) and the front source / drain contact 160. In embodiments where the front source / drain contact 160 includes a barrier / liner layer, the barrier / liner layer may be located between the metal body layer and the front silicide layer 168. The silicide process may include depositing a metal layer over the source / drain 120 (e.g., its semiconductor layers 144 and 148) using a suitable deposition process, and heating the device 100 (e.g., by subjecting it to an annealing process) to react the components of the source / drain 120 with the metal components in the metal layer. In some embodiments, the silicide process consumes a portion of the source / drain 120 and transforms that portion of the source / drain 120 into a front silicide layer 168. The metal layer includes a metallic component suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The front silicide layer 168 may therefore include the metallic component and the components of the source / drain 120 (e.g., silicon and / or germanium). In some embodiments, the metal layer is a titanium-containing layer, and the front silicide layer 168 includes titanium and silicon and / or germanium. In some embodiments, the metal layer is a cobalt-containing layer, and the front silicide layer 168 includes cobalt and silicon and / or germanium. In some embodiments, the metal layer is a nickel-containing layer, and the front silicide layer 168 includes nickel and silicon and / or germanium. Any unreacted metal is selectively removed by a suitable etching process.

[0033] In some embodiments, prior to depositing the conductive material, an etching process is performed to extend the front source / drain contact opening to below the top surface of the source / drain 120 and the top semiconductor layer 110. This process may be referred to as source / drain etch-back and / or source / drain recess. After recess, the front source / drain contact opening extends a distance below the top surface of the first dielectric layer and / or the top semiconductor layer 110. This distance is between the bottom of the front source / drain contact opening and the top of the top semiconductor layer 110 (and / or the bottom of the first dielectric layer). Additionally, after recess, the source / drain 120 may have a dished, concave top surface that forms the bottom of the front source / drain contact opening. In the depicted embodiment, the dish-shaped, concave top surface is formed by semiconductor layers 144 and 148, and a front silicide layer 168 is formed on and conformally to the dish-shaped, concave top surface, such that the front silicide layer 168 has a curved, concave profile. The source / drain grooves increase the contact area between the top and front of the source / drain 120 and the front source / drain contact 160, which can reduce contact resistance (such as the contact resistance generated between the source / drain (epi) and the front source / drain contact (MD) (e.g., the contact resistance from epi to MD)) and thereby improve the performance of device 100.

[0034] In some embodiments used for illustration, the front interconnect structure includes a via 242 formed on a front source / drain contact 160, and a metal line 245 falling on the via 242 and connected to the respective source / drain 120.

[0035] refer to Figure 1 and Figures 4 to 5 Method 10 at block 25 may include bonding a carrier substrate 170 to the front side of workpiece 100, and thinning the workpiece (e.g., device 100) from the back side. Figure 4As shown, a carrier substrate 170 is bonded and / or attached to the front side FS of device 100 to provide mechanical support during the following back-side processes. Bonding may include forming a bonding layer 174 (e.g., a first dielectric layer) over the front side FS of device 100, forming a bonding layer 176 (e.g., a second dielectric layer) over the carrier substrate 170, placing the carrier substrate 170 over the front side FS of device 100, and performing an annealing process and / or other suitable processes to bond the bonding layers 174 and 176. In such embodiments, a bonding layer 178 may be formed between the carrier substrate 170 and the front side FS of device 100, a bonding layer 178 and / or a portion thereof, a bonding layer 176 and / or a portion thereof, a bonding portion of the bonding layers 174 and 176, or a combination thereof. In some embodiments, bonding is a dielectric-to-dielectric bonding. In such embodiments, bonding layers 178, 176, and 174 are dielectric layers, and the dielectric layers may include silicon, oxygen, nitrogen, carbon, other suitable dielectric components, or combinations thereof. For example, bonding layers 176 and 174 may be nitride layers, such as silicon nitride layers. In another example, bonding layers 176 and 174 may be oxide layers. In some embodiments, the carrier substrate 170 includes silicon, soda-lime glass, fused silica, fused silica, calcium fluoride, other suitable carrier substrate materials, or combinations thereof. In yet another embodiment, bonding layer 178 may be part of a passivation structure. The passivation structure may include multiple material layers, such as phosphosilicate glass (PSG), silicon nitride (SiN), other suitable dielectric materials, or combinations thereof.

[0036] refer to Figure 5 The thinning process may include thinning the workpiece 100 from the back side to reduce the thickness of the substrate 102 (e.g., along the z-direction). The thinning process is applied to the back side BS of the device 100, and in the depicted embodiment, the thinning process reduces the thickness of the substrate 102 above the source / drain 120. In some embodiments, an extension of the substrate 102 (i.e., mesa 102') is retained after the thinning process. The thinning process may be a polishing process, a planarization process (e.g., CMP), an etching process, other suitable processes, or a combination thereof. In some embodiments, the thinning process stops upon reaching the substrate isolation structure 106. In some embodiments, the thinning process may reduce the thickness of the substrate isolation structure 106 (e.g., along the z-direction), such as exposing the interposers 142, 150 or exposing the source / drain 120.

[0037] refer to Figure 1 and Figures 6A to 13A and Figures 6B to 13BMethod 10 includes forming a back-side source / drain via at block 30 on the source / drain of a transistor, such as the bottom of the source / drain 120 of transistors 104A-104D, and a back-side source / drain via 230 on the back side. Figure 14 ). Figures 6A to 13A and Figures 6B to 13B This is a cross-sectional view of portions of workpiece 100 at various manufacturing stages, constructed according to some embodiments. For example, substrate isolation structure 106 is not shown. In another example, for better observation and simplification, front-side rear-end structure 169 including front-side interconnect structures is not shown. Further note, Figures 6A to 13A and Figures 6B to 13B The structure of workpiece 100 can be related to Figures 2 to 5 The structure of the workpiece 200 varies. For example, according to various embodiments, the source / drain 120 may include different numbers of semiconductor layers. In some embodiments, the IC structure 100 may also include a hard mask layer disposed on the substrate isolation structure 106, such as... Figure 6B Hard mask layers 182 and 184 are shown. In various embodiments, hard mask layers 182 and 184 comprise dielectric materials with different compositions. For example, hard mask layer 182 comprises silicon oxide, and hard mask layer 184 comprises silicon nitride. Processes related to forming back-side source / drain vias 230 are performed on the back side BS of device 100.

[0038] refer to Figure 1 and Figure 6A and Figure 6B Method 10 includes forming a capping layer 180 at frame 35 over the back side of the workpiece. This capping layer is formed from a substrate 102 (e.g., its mesa 102') and a substrate isolation structure 106. The capping layer 180 can serve as a hard mask to define areas to be patterned for back-side source / drain vias. The capping layer 180 includes one or more dielectric materials, such as silicon nitride, silicon oxide, other dielectric materials, or combinations thereof. In some embodiments, the capping layer 180 includes a silicon nitride film. In some embodiments, the capping layer 180 includes a thickness in the range of 20 nm to 150 nm.

[0039] In some embodiments, the capping layer 180 includes a silicon nitride film and a silicon oxide film situated on the silicon nitride film. In a further embodiment, the thickness of the silicon nitride film is less than the thickness of the silicon oxide film. In some embodiments, the thickness of the silicon nitride film is about 5 nm to about 30 nm. In some embodiments, the thickness of the silicon oxide film is about 10 nm to about 100 nm. The silicon nitride film and the silicon oxide film are formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. The capping layer 180, with its two dielectric materials having different compositions, enables selective removal / etching / polishing (e.g., the silicon oxide film can be removed without removing (or can be ignored) the silicon nitride film). Additionally, because (1) the double capping layer 180 will serve as a mask for patterning (e.g., etching) the substrate 102, and (2) the silicon nitride film electrically isolates the back side of the substrate 102 from the subsequently formed back side routing layer.

[0040] refer to Figure 1 and Figure 7A and Figure 7B Method 10 includes a patterned capping layer 180 at frame 40 to form an opening therein that exposes a portion of the substrate overlapping the source / drain 120. For example, the capping layer 180 is patterned to form an opening 190 therein that exposes a portion of the substrate 102 overlapping the source / drain 120. The capping layer 180 may be referred to as a hard mask layer, and frame 40 of method 10 may be referred to as a hard mask patterning step and / or a hard mask (HM) etching step.

[0041] The capping layer 180 can be patterned using photolithography and etching processes. The photolithography process may include forming a patterned photoresist layer. The patterned photoresist layer is formed by a photolithography process that includes spin-coating the photoresist layer, exposing the photoresist layer through a photomask, and developing the exposed photoresist layer. The photolithography process may also include various baking processes at different stages, such as soft baking after spin-coating, post-exposure baking after exposure, and hard baking after development. More specifically, according to some embodiments, the photoresist process may also include processing steps of photoresist coating, soft baking, mask alignment, pattern exposure, post-exposure baking, photoresist development, and hard baking. Photolithographic patterning can also be implemented or replaced by other suitable methods, such as maskless lithography, electron beam writing, ion beam writing, or molecular imprinting.

[0042] The etching process may include dry etching, wet etching, other suitable etching methods, or combinations thereof. In some embodiments, if the capping layer 180 is a silicon nitride layer, the etching process may include a wet etching process using an etchant having thermal phosphoric acid. In some embodiments, if the capping layer 180 comprises multiple dielectric material layers, the etching process may include multiple etching steps. In a further embodiment, if the capping layer 180 comprises a silicon nitride layer and a silicon oxide layer above the silicon nitride layer, the etching process includes a first wet etching process using a first etchant having thermal phosphoric acid and a second wet etching process using a second etchant having hydrofluoric acid. In some embodiments, the etching process includes a dry etching process using an etching gas comprising CF4, SF6, NF3, CH2F2, or combinations thereof. In some embodiments, after the etching process, the patterned photoresist layer may be removed from the capping layer 180, for example, by a photoresist stripping process, plasma ashing, and / or etching process.

[0043] Still referencing Figure 1 and Figure 7A and Figure 7B Method 10 includes, at block 45, patterning an exposed portion of substrate 102 to form a back-side source / drain via opening to expose the source / drain. The patterning process includes etching substrate 102 through openings 190 of the patterned capping layer 180 using a patterned capping layer 180 as a hard mask. For example, the exposed portion of substrate 102 is patterned to form a back-side source / drain via opening 200 therein, which exposes the back side of a corresponding source / drain 120. After patterning substrate 102, the back-side source / drain via opening 200 extends through substrate 102 to expose the source / drain 120. In the depicted embodiment, method 10 also includes, at block 45, extending the back-side source / drain via opening 200 by removing portions of the first interposer 142 and the second interposer 150. Therefore, the etching process can include multiple etching steps utilizing different etchants to efficiently etch the corresponding material layers.

[0044] As described above, the first interposer 142 comprises undoped silicon, and the second interposer 150 comprises silicon nitride. The substrate 102 comprises silicon. In some embodiments, the etching process includes a first wet etching process using a first etchant containing a KOH solution to etch the silicon of the substrate 102 and the first interposer 142; and a second wet etching process using a second etchant containing hydrofluoric acid to etch the silicon nitride of the second interposer 150. In some embodiments, the etching process includes a dry etching process using an etching gas comprising CF4, SF6, NF3, CH2F2, or a combination thereof.

[0045] After etching the substrate 102, the first interposer 142, and the second interposer 150 through the opening 190 of the capping layer 180, an opening 200 is formed, exposing the source / drain 120 within the opening 200. The opening 200 is also referred to as the back-side source / drain via opening 200. Figure 7B As shown, a portion of the substrate isolation structure 106 above the bottom of the gate stack 114 and / or the top of the mesa 102' is also removed. Block 45 of method 10 may be referred to as a substrate patterning and / or etching step and / or a source / drain via (VB) patterning and / or etching step.

[0046] refer to Figure 1 , Figure 8A and Figure 8B Method 10 includes forming a via spacer in the back-side source / drain via opening at block 50. For example, via spacer 210 is formed in the back-side source / drain via opening 200. Via spacer 210 can electrically isolate the subsequently formed back-side source / drain via from the substrate 102 and / or gate stack 114, which suppresses and / or prevents the subsequently formed back-side source / drain via from electrically coupling to each other and / or to the gate stack 114. Reference Figure 8A and Figure 8B Forming the via spacer 210 may include forming a via spacer layer on the sidewalls of the back-side source / drain via opening 200. The via spacer layer liner and partially fills the back-side source / drain via opening 200 in the substrate 102. The via spacer layer also liner and partially fills the opening 190 in the capping layer 180. In the depicted embodiment, the via spacer layer is directly disposed on the sidewalls of the back-side source / drain via opening 200 (e.g., formed by the substrate 102), the sidewalls of the opening 190 (e.g., formed by the capping layer 180), and the bottom of the back-side source / drain via opening 200 (e.g., formed by the source / drain 120). The via spacer layer is formed by CVD, ALD, other suitable processes, or combinations thereof. In some embodiments, the via spacer layer is a furnace-deposited layer. In some embodiments, the via spacer layer is conformally deposited such that the via spacer layer has a substantially uniform thickness above the respective surfaces of the device 100. In some embodiments, the thickness of the via spacer layer is from about 1 nm to about 10 nm.

[0047] In some embodiments, the via spacer layer has a different composition than the top film of the capping layer 180 to achieve selective etching / removal, and the via spacer layer includes an electrically insulating material. The dielectric material of the via spacer layer includes silicon and oxygen, nitrogen, carbon, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, other suitable dielectric materials, or combinations thereof). In some embodiments, as shown, the via spacer layer includes the same material as the second interposer 150. For example, the via spacer layer includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. In such embodiments, the via spacer layer may be referred to as a nitride layer, and the process for forming the via spacer 210 may be referred to as a back-side self-protected nitride redeposition (BSNR) deposition (DP) and etching (ET) step. In some embodiments, the via spacer layer 210, the second interposer 150, and the substrate isolation structure 106 include different materials and / or different compositions.

[0048] Subsequently, an anisotropic etching process is applied to remove a portion of the via spacer layer deposited on the bottom surface of the back-side source / drain via opening 200, thereby exposing the source / drain 120 within the back-side source / drain via opening 200.

[0049] The etching process can selectively remove the via spacer layer and the second interposer layer 150 relative to other materials, such as semiconductor layer 144. For example, the etching process etches the via spacer layer and the second interposer layer 150 without etching (or negligibly etches) the semiconductor layer 144. The etchant in the etching process can etch the dielectric material having the first component (e.g., via spacer layer 210 and the second interposer layer 150) at a higher rate than the dielectric material having the second component (e.g., silicon oxide if present in the top portion of capping layer 180) and the semiconductor material (e.g., semiconductor layer 144). The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is reactive ion etching (RIE). In some embodiments, where the via spacer layer and the second interposer layer 150 are nitride layers (e.g., silicon nitride layers) and the top portion of capping layer 180 is an oxide layer (e.g., silicon oxide layer), the etchant can selectively etch the nitride without etching (or negligibly etch) the oxide. In such an embodiment, the etching process can remove portions of the via spacer layer above capping layer 180 and portions of the via spacer layer above substrate isolation structure 106, thereby exposing substrate isolation structure 106. The etching process continues to remove the exposed substrate isolation structure 106 until the semiconductor layer 144 is reached and / or exposed. In some embodiments, the etching process can further extend the back-side source / drain via opening 200 by removing and / or recessing semiconductor layer 144. In some embodiments, the etchant used to recess semiconductor layer 144 is different from the etchant used to etch via spacer layer and second interposer layer 150. In some embodiments, the etchant used to recess semiconductor layer 144 is the same as the etchant used to etch via spacer layer and second interposer layer 150. For example, the etchant can selectively etch nitrides (e.g., via spacer layer and second interposer layer 150) and silicon (or silicon-germanium) (e.g., semiconductor layer 144) without (or at least) etching oxides (e.g., top portion of capping layer 180). In such embodiments, the etchant can exhibit etch selectivity between nitride and silicon (or silicon-germanium), achieving the desired removal of semiconductor layer 144. Additionally, in such embodiments, parameters of the etching process (e.g., etching duration, etching temperature, etc.) can be adjusted to achieve the desired recess of semiconductor layer 144 and the desired removal of via spacer layer and second interposer layer 150. In some embodiments, the anisotropic etching process includes a dry etching process utilizing a suitable etchant (such as an etching gas containing CF4, SF6, NF3, CH2F2, or combinations thereof).

[0050] In some embodiments, the first interposer 142 and the second interposer 150 may not be etched at frame 45, but rather at frame 50 using the same anisotropic process, or alternatively etched using another etching process employing one or more etchants to remove the first interposer 142 and the second interposer 150 after the anisotropic etching process. In some embodiments, the first interposer 142 and the substrate 102 are etched at frame 45, but the second interposer 150 and the via spacer layer are etched at frame 50 using the same anisotropic process.

[0051] As described above, the back-side source / drain via opening 200 extends through the first interposer 142 and the second interposer 150 to expose the semiconductor layer 144 of the source / drain 120, thereby forming a back-side source / drain via 230, which directly contacts the semiconductor layer 144 with reduced contact resistance.

[0052] Additionally, the semiconductor layer 144 of the exposed source / drain 120 at the bottom of the extended back-side source / drain via opening 200 can have a dished, concave surface, which provides a dished, convex bottom surface for the source / drain 120 when the device 100 is vertically oriented (i.e., its back side BS is oriented downwards and its front side FS is oriented upwards). Making the back side of the source / drain 120 concave increases the contact area between the bottom, back side, and subsequently formed back-side source / drain via of the source / drain 120, which can reduce contact resistances (such as the contact resistance generated between the source / drain (epi) and the back-side source / drain via (VB) – e.g., the contact resistance from epi to VB) and thus improve the performance of the device 100.

[0053] refer to Figure 1 and Figure 9A and Figure 9BMethod 10 includes performing an ion implantation process on the source / drain 120 at block 52 to introduce a dopant into the source / drain 120, thereby increasing the conductivity of the source / drain 120 and reducing the contact resistance between the source / drain 120 and the back-side source / drain via 230. The dopant type is related to the type of the source / drain 120. When the source / drain 120 is an n-type source / drain of an n-type FET, the dopant is an n-type dopant, such as phosphorus (P) or arsenic (As). When the source / drain 120 is a p-type source / drain of a p-type FET, the dopant is a p-type dopant, such as boron (B). Therefore, when the back-side source / drain via 230 is formed on the bottom surface of the n-type and p-type source / drain 120, the n-type and p-type back-side source / drain vias 230 are formed separately, and the ion implantation process is performed separately with the corresponding type of dopant. In the following description, a p-type source / drain 120 and a p-type ion implantation process for a pFET are shown. However, it should be understood that a similar process is formed for an n-type drain / source 120 for an nFET, but using an n-type dopant.

[0054] In some embodiments, the ion implantation process 84 includes, for example, Figure 14 The steps are shown. Figure 14 This is a flowchart of method 52 constructed according to some embodiments. Method 52 includes block 86, performing a pre-amorphous implantation (PAI) process on source / drain 120. The PAI process is applied to source / drain 120 by implanting atoms into substrate 102 to form an amorphous region and disrupt the crystal structure of substrate 102. The PAI process reduces channeling effects, and method 52 performs two ion implantations immediately one after the other without an annealing step in between. The first implantation is a PAI process used to disrupt the crystal structure of substrate 102. The second implantation introduces desired dopant atoms, which will be described later. The implanted ion material used in the PAI process is non-electrolyte. In some embodiments, the ion material used in the PAI process includes silicon, germanium, or combinations thereof. In some embodiments, the ion material used in the PAI process includes silicon, germanium, xenon, argon, nitrogen, or combinations thereof. In some embodiments, the PAI process includes a tilted ion implantation process with various parameters designed to optimize the results. In some embodiments, the PAI process includes an ion implantation process having the aforementioned material; a tilt angle of less than 60 degrees, such as in the range of 5 degrees to 60 degrees; and a 5x10... 13 / cm 3 and 1x10 16 / cm 3The dosage is within the range of 0.5 keV to 10 keV; the ion energy is within the range of -100°C to 500°C; and the temperature is below 500°C. In some embodiments, the PAI process includes multiple implantation steps with different tilt angles to reach different portions of the source / drain 120 and form different profiles of the source / drain 120. For example, the PAI process includes a first PAI step with a tilt angle of zero and a second PAI step with a tilt angle of X°. According to some embodiments, X° is in the range of 5° to 35°.

[0055] Method 52 includes block 88, performing a second ion implantation process to introduce a dopant into source / drain 120. In the illustrated example, source / drain 120 is a p-type source / drain, and the dopant is boron. Source / drain 120 comprises silicon, germanium, or silicon-germanium. In some embodiments, source / drain 120 comprises Si1Ge 1-x B, boron concentration at 1x10 20 ~1x10 21 Within the range of X=0.5~1), in some embodiments, the second ion implantation process includes a tilted ion implantation process having various parameters designed to optimize the results. In some embodiments, the second ion implantation process includes an ion implantation process having the aforementioned material (such as boron); a tilt angle of less than 60 degrees, such as in the range between 5 degrees and 60 degrees; and a range of 5x10... 13 / cm 3 and 1x10 16 / cm 3 Dosage range between 0.5 keV and 10 keV; ion energy range between 0.5 keV and 10 keV; temperature below 500 °C, such as within the range of -100 °C to 500 °C. After the second ion implantation process, the dopant concentration in the source / drain 120 is greater than 1 x 10⁻⁶. 19 Such as in 1x10 19 / cm 3 and 1x10 22 / cm 3 Within the range between [specific values]. In some embodiments, the second implantation process includes multiple implantation steps with different tilt angles to reach different portions of the source / drain 120 and form different profiles of the source / drain 120. For example, the second implantation process includes a first implantation step with a tilt angle of zero and a second implantation step with a tilt angle of X°. According to some embodiments, X° is in the range between 5 degrees and 35 degrees.

[0056] Method 52 includes block 90, performing an annealing process to activate source / drain 120. The annealing process is performed at a temperature higher than that of the ion implantation process described above. In some embodiments, the annealing process includes a temperature greater than 900°C, such as in the range between 900°C and 1050°C; and an annealing duration greater than 1 second, such as in the range between 1 second and 10 seconds.

[0057] refer to Figure 1 and Figure 10A and Figure 10B Method 10 includes forming a silicide layer on the exposed source / drain 120 at block 55. For example, a silicide process can be performed to form a back-side silicide layer 220 on the bottom and back side of the exposed source / drain 120, the back-side silicide layer 220 being formed from the semiconductor layer 144 of the source / drain 120. In the depicted embodiment, the back-side silicide layer 220 is formed on and conformally to the dished, convex surface of the exposed source / drain 120, such that when the device 100 is vertically oriented (i.e., its back side BS is oriented downwards and its front side FS is oriented upwards), the back-side silicide layer 220 has a curved, convex profile. Therefore, some of the sources / drains 120 are sandwiched between the back-side silicide layer 220 and the front-side silicide layer 168. Because the back-side source / drain via openings 200 extend over the top of the gate stack 114 and / or mesas 102', the back-side silicide layer 220 is disposed over the substrate isolation structure residue 106 and the via spacer 210 when the device 100 is vertically oriented. In the depicted embodiments, each back-side silicide layer 220 is disposed on a corresponding semiconductor layer 144, between corresponding semiconductor layers 148, and between corresponding substrate isolation structure residues 106. In some embodiments, the thickness of the back-side silicide layer 220 (e.g., along the z-direction) is from about 2 nm to about 20 nm. In some embodiments, the thickness of the back-side silicide layer 220 is substantially uniform.

[0058] The silicide process may include depositing a metal layer over a capping layer 180, via spacers 210, and exposed source / drain 120 (e.g., its semiconductor layer 144) using a suitable deposition process, and heating device 100 (e.g., by subjecting it to an annealing process) to react the components of the source / drain 120 with the metal components in the metal layer. The metal layer at least partially fills the back-side source / drain via opening 200. In some embodiments, the deposition process is CVD, physical vapor deposition (PVD), other suitable methods, or combinations thereof. In some embodiments, the metal layer is a sputtered deposition layer. In some embodiments, the silicide process consumes a portion of the source / drain 120 (e.g., its semiconductor layer 144) and transforms that portion of the source / drain 120 into a back-side silicide layer 220. The metal layer includes metal components suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. Therefore, the back-side silicide layer 220 may include a metal composition and the composition of the source / drain 120 (e.g., silicon and / or germanium). In some embodiments, the metal layer is a titanium-containing layer, and the back-side silicide layer 220 includes titanium and silicon and / or germanium. In some embodiments, the metal layer is a cobalt-containing layer, and the back-side silicide layer 220 includes cobalt and silicon and / or germanium. In some embodiments, the metal layer is a nickel-containing layer, and the back-side silicide layer 220 includes nickel and silicon and / or germanium. In some embodiments, the metal layer is a tungsten-containing layer, and the back-side silicide layer 220 includes tungsten and silicon and / or germanium.

[0059] Any unreacted metal is selectively removed using a suitable process. In some embodiments, the etching process selectively removes unreacted metal relative to the capping layer 180, via spacer 210, and source / drain 120. For example, the etching process etches the metal layer without etching (or negligibly) the capping layer 180, via spacer 210, source / drain 120, and backside silicide layer 220. The etchant in the etching process can etch the metal material (e.g., the metal layer) at a higher rate than the dielectric material (e.g., capping layer 180 and via spacer 210) and the metal and semiconductor materials (e.g., backside silicide layer 220). The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, as shown, the etching process can be tuned to selectively etch the metal layer, but can partially and / or negligibly etch the capping layer 180, via spacer 210, substrate isolation structure 106, or combinations thereof. In such embodiments, the thickness of the via spacer 210 (e.g., along the x and / or y directions) and / or the thickness of the capping layer 180 (e.g., along the z direction) can be reduced by an etching process. Therefore, the thickness of the via spacer 210 after the formation of the back silicide layer 220 can be less than the thickness of the via spacer 210 before the formation of the back silicide layer 220, and / or the thickness of the capping layer 180 after the formation of the back silicide layer 220 can be greater than the thickness of the capping layer 180 before the formation of the back silicide layer 220. Additionally, the length of the via spacer 210 (e.g., along the z direction) can be reduced when the back silicide layer 220 is formed. In some embodiments, as shown, a portion of the via spacer 210 is removed along the sidewall of the capping layer 180 forming the opening 190. In some embodiments, the width and / or length (e.g., along the x and / or y directions) of the substrate isolation structure residue 106 can also be reduced by an etching process. Therefore, the width / length of the substrate isolation structure residue 106 after the formation of the back silicide layer 220 can be smaller than the width / length of the substrate isolation structure residue 106 before the formation of the back silicide layer 220.

[0060] refer to Figure 1 , Figure 11A and Figure 11B as well as Figure 12A and Figure 12BMethod 10 includes forming a back-side source / drain via 230 at frames 60 and 65. The back-side source / drain via 230 is formed in back-side source / drain region via openings 200 and 190, such that the back-side source / drain via 230 extends through capping layer 180, through substrate 102 (e.g., its mesa 102'), and to the bottom, back side (e.g., formed by its semiconductor layer 144) of source / drain 120. In the depicted embodiment, a back-side silicide layer 220 is located between the back-side source / drain via 230 and the bottom of source / drain 120. The back-side source / drain via 230 includes tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In the depicted embodiments, the back-side source / drain via 230 is a non-blocking metal plug. For example, the back-side source / drain via 230 includes a metal body layer, such as a tungsten plug or a cobalt plug, which physically contacts the surrounding dielectric material, such as via spacer 210, second interposer residue 150, substrate isolation structure 106, capping layer 180, or combinations thereof. In some embodiments, one or more back-side source / drain vias 230 include a metal body layer and a metal liner, wherein the metal liner is located between the metal body layer and the surrounding dielectric material. In such embodiments, the metal liner may be located between the metal body layer and the back-side silicide layer 220. In some embodiments, the thickness of the back-side source / drain via 230 (e.g., along the z-direction) is from about 100 nm to about 500 nm.

[0061] refer to Figure 1 and Figure 11A and Figure 11BMethod 10 includes depositing a conductive material (e.g., source / drain via material 230') in a back-side source / drain via opening (e.g., back-side source / drain via opening 200) above a via spacer (e.g., via spacer 210) and a silicide layer (e.g., back-side silicide layer 220) at frame 60. The source / drain via material 230' is formed over a capping layer 180, filling the back-side source / drain via opening 200 and filling opening 190 in the capping layer 180. The source / drain via material 230' includes tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. The source / drain via material 230' is formed by PVD, CVD, ALD, sputtering deposition, electroplating, electroless plating, other suitable deposition processes, or combinations thereof. In the depicted embodiments, the source / drain via material 230' (e.g., tungsten or cobalt) is formed by a blanket deposition process (e.g., blanket CVD or blanket PVD), which may include flowing a metal-containing precursor (e.g., a tungsten-containing precursor such as WF6 and / or WCl5, or a cobalt-containing precursor) and a reactant precursor (e.g., H2, other suitable reactive gases, or combinations thereof) into the process chamber. A carrier gas may be used to deliver the metal-containing precursor gas and / or the reactive gas into the process chamber. The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, a bottom-up deposition process is implemented to fill the back-side source / drain via opening 200 with the source / drain via material 230' (e.g., tungsten or cobalt) from bottom to top. Bottom-up deposition processes (e.g., selective CVD) may include flowing a metal precursor (e.g., a tungsten precursor, such as WF6 and / or WCl5, or a cobalt precursor), a reactant precursor (e.g., H2, other suitable reactive gases, or combinations thereof), and a carrier gas into a process chamber, and adjusting deposition parameters to selectively grow source / drain via material 230' from the back-side silicide layer 220 and / or the metal seed layer, while restricting the growth of source / drain via material 230' from the dielectric material (e.g., via spacer 210). Deposition parameters may include deposition precursors (e.g., metal precursors and / or reactant precursors), precursor flow rates, deposition temperature, deposition time, deposition pressure, source power, bias voltage, bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, the bottom-up deposition process includes multiple deposition / etch cycles.

[0062] refer to Figure 1 and Figure 12A and Figure 12BMethod 10 includes performing a planarization process (e.g., CMP) at block 65 to remove excess source / drain via material 230', such as material disposed above capping layer 180. The remaining portion of the source / drain via material 230' filling the back-side source / drain via openings 200 and 190 forms the back-side source / drain via 230. The planarization process also removes capping layer 180. In such an embodiment, the planarization process may be performed until the substrate 102 is reached and / or exposed, and the substrate 102 may serve as a planarization stop layer (e.g., a CMP stop layer). The bottom surface of the back-side source / drain via 230 may be planarized such that the bottom surface of the substrate 102 and the bottom surface of the back-side source / drain via 230 form a substantially flat surface.

[0063] The process associated with forming the front-side source / drain contacts 160 and the back-side source / drain vias 230 is generally referred to as a mid-stage (MOL) process. This typically refers to the fabrication of MOL interconnects that physically and / or electrically connect FEOL components (e.g., electrically active components of a device) to a first metallization layer (layer) formed during a back-end (BEOL) process. The process may also include a BEOL process to form front-side interconnect structures (as described above) and / or back-side interconnect structures (generally referred to as BEOL components) electrically connected to the front-side source / drain contacts 160 and the back-side source / drain vias 230. For example, refer to… Figure 1 and Figure 13A and Figure 13BMethod 10 includes forming a back-side interconnect structure 240 at block 80. The back-side interconnect structure 240 is similar in structure and formation to the front-side interconnect structure. For example, the back-side interconnect structure 240 includes metal lines distributed in one or more metal layers and vias between the metal layers, the vias being configured to couple the metal lines in different metal layers. In the illustrated embodiment, the back-side interconnect structure includes a back-side power rail 250 (e.g., a back-side power rail 250) connected to a back-side source / drain via (e.g., one or more back-side source / drain vias 230). The back-side power rail 250 is formed on a back-side interlayer dielectric (ILD) layer having one or more dielectric materials and may also include an etch stop layer having one or more dielectric materials with a composition different from the back-side ILD layer to provide etch selectivity. The back-side power rail 250 is electrically connected to the back-side source / drain via 230. Therefore, some of the source / drain 120 are electrically connected to the front interconnect structure (e.g., through the front source / drain contact 160 and the front source / drain via 242, and the front metal line or front power line 245) and the back power rail 250 (e.g., through the back source / drain via 230), so that power can be delivered to transistors 104A-104D through the front power rail 245 (via the front source / drain via 242 and the front source / drain contact 160) and / or the back power rail 250 (via the back source / drain via 230). Providing dual power rails for transistors 104A-104D reduces the resistance associated with power delivery, which can reduce IR drop and improve the performance of device 100. Additionally, providing dual power rails reduces the area consumed by device 100. In some embodiments, the front power rail 245 is electrically connected to the back power rail 250. In some embodiments, the source / drain 120 electrically connected to the front power rail 245 and the rear power rail 250 is the source of transistor 104A-104D. In such embodiments, other source / drain 120s of transistor 104A-104D can be their drains, which can be electrically connected to ground. Different embodiments may have different advantages, and no particular advantage is required in any embodiment.

[0064] In some embodiments, method 10 (such as block 45 of method 10) further includes deeply recessing the source / drain 120 to increase the silicide landing area and reduce contact resistance, such as Figure 15 As shown. Figure 15 Similar to Figure 7B However, the source / drain 120 is deeply recessed within the opening 200. For example, the source / drain 120 is recessed such that the bottom surface 120B of the source / drain 120 is perpendicularly located between two adjacent semiconductor layers 110, which are the channels of the respective FET devices. For example, Figure 15The FET device includes three semiconductor layers 110, and the bottom surface 120B of the source / drain 120 is vertically located between the first semiconductor layer 110 and the second semiconductor layer 110 (counting from the front side FS). Therefore, the subsequently formed back-side silicide layer 220 has deep recessed contacts encapsulating the silicide.

[0065] In some embodiments, each of blocks 86 and 88 of method 52 includes multiple implantation steps with different tilt angles to reach different portions of the source / drain 120 and form different profiles of the source / drain 120. In the disclosed embodiments, the PAI process at block 86 and the second ion implantation process at block 88 have the same number of tilt ion implantation steps, such that any regions of the source / drain 120 doped from the back side are also pre-amorphized. For example, each of the first and second ion implantation processes includes three steps: a first step where the first tilt angle X1° is zero, a second step where the second tilt angle X2° is greater than the first tilt angle, and a third step where the tilt angle X3° is greater than the second tilt angle. In some embodiments, X2° is in the range between 10° and 20°, and X3° is in the range between 30° and 50°.

[0066] In some embodiments, the PAI process includes multiple implantation steps with different tilt angles to reach different portions of the source / drain 120 and form different profiles of the source / drain 120. For example, the PAI process includes a first PAI step with a tilt angle of zero and a second PAI step with a tilt angle of X°. According to some embodiments, X° is in the range of 5° and 35°. In some embodiments, the second implantation process includes multiple implantation steps with different tilt angles to reach different portions of the source / drain 120 and form different profiles of the source / drain 120. For example, the second implantation process includes a first implantation step with a tilt angle of zero and a second implantation step with a tilt angle of X°. According to some embodiments, X° is in the range of 5° and 35°.

[0067] Figure 16A and Figure 16B This is a cross-sectional view of the IC structure 100 constructed according to various embodiments. For example... Figure 16AAs shown, the source / drain 120 is shallowly recessed (e.g., the bottom surface of the source / drain 120 is recessed to be at approximately the same level as the lowest semiconductor layer 110 from the front FS to the back BS, or the bottom surface of the drain / source 120 is recessed to be at the level between the lowest semiconductor layer 110 from the front FS to the back BS and the adjacent semiconductor layer 110), and each of the implantation processes at blocks 86 and 88 includes an implantation step with a zero tilt angle. For example, the implantation process at block 88 includes an implantation step with a zero tilt angle, and the dopant 120D1 is distributed on the surface portion of the source / drain 120 directly below the opening 200, but not in the portion of the source / drain 120 directly below the via spacer 210, because the implantation process has a zero tilt angle and cannot reach the portion of the drain / source 120 directly below the via spacer 210. Dopant 120D1 refers only to the dopant introduced into the source / drain 120 through an implantation process.

[0068] like Figure 16B As shown, the source / drain 120 is deeply recessed (such as...). Figure 15 The implantation process at frames 86 and 88 includes two or more implantation steps with different tilt angles. For example, the implantation process at frame 88 includes a first implantation step with a zero tilt angle, and dopant 120D1 is distributed on the surface portion of the source / drain 120 directly below the opening 200, but not in the portion of the source / drain 120 directly below the via spacer 210, because the implantation process has a zero tilt angle and cannot reach the portion of the drain / source 120 directly below the via spacer 210. The implantation process at frame 88 also includes a second implantation step with a tilt angle greater than zero (such as in the range of 5° and 35°), and dopant 120D2 is distributed on the surface portion of the source / drain 120 directly below the opening 200, and also in the portion of the source / drain 120 directly below the via spacer 210. In a further embodiment, the subsequently formed back silicide layer 220 is in direct contact with the front silicide layer 168. Dopant 120D1 and dopant 120D2 refer only to the dopant introduced into the source / drain 120 through the first and second steps of the implantation process.

[0069] Figure 17A and Figure 17B This is a cross-sectional view of the IC structure 100 constructed according to various embodiments. Figure 17A and Figure 17B They are similar to Figure 16A and Figure 16B However, it has additional components, such as the front-side dopant 120D3 (and 120D4) and the back-side source / drain via 230, as further shown. Figure 17AAs shown, the source / drain 120 is shallowly recessed (e.g., the bottom surface of the source / drain 120 is recessed to be at approximately the same level as the lowest semiconductor layer 110 from the front side FS to the back side BS, or the bottom surface of the drain / source 120 is recessed to be at the level between the lowest semiconductor layer 110 from the front side FS to the back side BS and the adjacent semiconductor layer 110), and each of the implantation processes at blocks 86 and 88 includes an implantation step with a zero tilt angle. For example, the implantation process at block 88 includes an implantation step with a zero tilt angle, and the dopant 120D1 is distributed on the surface portion of the source / drain 120 directly below the opening 200, but not in the portion of the source / drain 120 directly below the via spacer 210, because the implantation process has a zero tilt angle and cannot reach the portion of the drain / source 120 directly below the via spacer 210. The front side of the source / drain 120 also includes a similar structure. Specifically, the source / drain 120 is also shallowly recessed from the front FS, and additional dopant 120D3 is introduced into the source / drain 120 from the front FS via a front-side ion implantation process. The front-side ion implantation process includes an implantation step and is performed with a zero tilt angle. The dopant 120D3 introduced into the source / drain 120 from the front FS is also distributed within the portion of the source / drain 120 that is perpendicularly aligned with the front source / drain contact 160, and cannot reach the portion of the source / drain 120 beyond the front source / drain contact 160 because the dopant 120D3 is introduced via a front-side ion implantation process with a zero tilt angle.

[0070] like Figure 17B and Figure 14 As shown, the source / drain 120 is deeply recessed (such as...). Figure 15 (as described above), and each of the back-side injection processes at boxes 86 and 88 includes two or more injection steps with different tilt angles. For example, the injection process at box 88 includes a first injection step 88A with a tilt angle of zero (in... Figure 14 In the middle), the dopant 120D1 is distributed on the surface portion of the source / drain 120 directly below the opening 200, but not in the portion of the source / drain 120 directly below the via spacer 210, because the implantation process has a zero tilt angle and cannot reach the portion of the drain / source 120 directly below the via spacer 210. The back-side implantation process at frame 88 also includes a second implantation step 88B with a tilt angle greater than zero (such as in the range between 5° and 35°). Figure 14 (In the middle), and the dopant 120D2 is distributed in the surface portion of the source / drain 120 directly below the opening 200, and also in the portion of the source / drain 120 directly below the via spacer 210. Further reference Figure 14The PAI process at frame 86 also includes a first injection step 86A with a zero tilt angle (in Figure 14 The second injection step 86B (in the middle) and the tilt angle greater than zero (such as in the range between 5° and 35°) Figure 14 middle).

[0071] The front side of the source / drain 120 also includes a similar structure. Specifically, the source / drain 120 is also deeply recessed from the front side FS, and additional dopant is introduced into the source / drain 120 from the front side FS via a front-side ion implantation process. The front-side ion implantation process includes multiple steps, such as a first implantation step with a first tilt angle of zero, and dopant 120D3 is distributed within the portion of the source / drain 120 perpendicularly aligned with the front-side source / drain contact 160, and cannot reach the portion of the source / drain 120 perpendicularly extending beyond the front-side source / drain contact 160, because dopant 120D3 is introduced via a zero-tilt-angle front-side ion implantation process. The front-side implantation process also includes a second implantation step with a tilt angle greater than zero (such as in the range between 5° and 35°), and dopant 120D4 is distributed in the surface portion of the source / drain 120 perpendicularly extending beyond the front-side source / drain contact 160. In the disclosed embodiments, as Figure 17B As shown, dopant 120D1 from the back side BS and dopant 120D3 from the front side FS are in direct contact with each other.

[0072] The multiple operations of method 10 can have different orders and be implemented in different sequences. In, for example... Figure 1 In some embodiments shown, the via spacer 210 at frame 50 is formed first, followed by the ion implantation process at frame 52. In such... Figure 18 In some of the embodiments shown, the ion implantation process at block 52 is performed first, and then the via spacer 210 at block 50 is formed. Figure 18 This is a flowchart of method 10 constructed according to some embodiments. Figure 18 Method 10 is similar to Figure 1 The methods described in [the document] are implemented in blocks 50 and 52, but in a different order. Similar processes at each block are not repeated here. These different methods 10 lead to different results, including different structures such as different dopant profiles.

[0073] The following description focuses on Figure 1 and Figure 18 Boxes 50 and 52 in the middle, and from Figure 19 start. Figure 19 This is a cross-sectional view of an IC structure 100 constructed according to some embodiments. Figure 19 Similar to Figure 7A And this is the structure following the operation at box 45. See the following description for further reference. Figures 20A to 20C and Figures 21A to 21C To compare the differences. Figures 20A to 20C and Figures 21A to 21C This is a cross-sectional view of a portion of IC structure 100 (such as only) Figure 19 (The portion within the dashed box 211). Specifically, Figures 20A to 20C It is through each stage of manufacturing Figure 1 A cross-sectional view of the IC structure 100 formed by method 10; and Figures 21A to 21C It is through each stage of manufacturing Figure 18 A cross-sectional view of the IC structure 100 formed by method 10.

[0074] refer to Figure 1 and Figure 20A and Figure 20B Method 10 includes a frame 50 forming a through-hole spacer 210, as described above. Figure 1 As stated in [the text]. Figure 20A In the process, depositing through-hole spacer material, and in Figure 20B In this process, an anisotropic etching process is applied to the via spacer material to remove a portion of the via spacer material deposited on the bottom of the back-side source / drain via opening 200.

[0075] refer to Figure 1 and Figure 20C Method 10 includes block 52, performing a back-side ion implantation process. In some embodiments, the back-side ion implantation process includes, for example... Figure 14 The first step described in box 88A; and as Figure 14 The second step is described in block 88B. The first step of the back-side ion implantation process has a zero tilt angle and introduces dopant 120D1; and the second step of the back-side ion implantation process has a greater than zero tilt angle and introduces dopant 120D2. Specifically, dopant 120D1 is distributed on the top portion of the source / drain 120 not covered by the back-side source / drain via spacer 210, but not in the portion of the source / drain 120 directly below the back-side source / drain via spacer 210. Dopant 120D2 is distributed on the top portion of the source / drain 120 not covered by the back-side source / drain via spacer 210, and also in the portion of the source / drain 120 directly below the back-side source / drain via spacer 210.

[0076] refer to Figure 18 and Figure 21A Method 10 includes block 52, performing a back-side ion implantation process. In some embodiments, the back-side ion implantation process includes, for example... Figure 14 The first step described in box 88A; and as Figure 14The second step is described in block 88B. The first step of the back-side ion implantation process has a tilt angle of zero and introduces dopant 120D1; and the second step of the back-side ion implantation process has a tilt angle of greater than zero and introduces dopant 120D2.

[0077] refer to Figure 18 and Figure 21B and Figure 20C Method 10 includes a frame 50 forming a through-hole spacer 210, similar to the above described in Figure 1 As stated in [the text]. Figure 21B In the middle, the material for the through-hole spacer is deposited, and in Figure 21B In this process, an anisotropic etching process is applied to the via spacer material to remove a portion of the via spacer material deposited on the bottom of the back-side source / drain via opening 200.

[0078] Specifically, dopant 120D1 is distributed on the top portion of the source / drain 120 not covered by the back-side source / drain via spacer 210, and also in the portion of the source / drain 120 directly below the back-side source / drain via spacer 210. Dopant 120D2 is distributed on the top portion of the source / drain 120 not covered by the back-side source / drain via spacer 210, and also in the portion of the source / drain 120 directly below the back-side source / drain via spacer 210, and may extend beyond the portion of the source / drain beyond the back-side source / drain via spacer 210.

[0079] In such Figure 1 In some embodiments shown, the formation of the back-side silicide layer 220 at block 55 is performed after the ion implantation process at block 52. In such embodiments... Figure 22 In some of the embodiments shown, the formation of the back-side silicide layer 220 at block 55 is performed prior to the ion implantation process at block 52. Figure 22 This is a flowchart of method 10 constructed according to some embodiments. Figure 22 Method 10 is similar to Figure 1 The method described in [the document] is the same, but blocks 52 and 55 are implemented in a different order. Similar processes at each block are not repeated here. These different methods 10 lead to different results, including different structures such as different dopant profiles.

[0080] The following description focuses on Figure 1 and Figure 22 Boxes 52 and 55 in the middle, and from Figure 23 start. Figure 23 This is a cross-sectional view of an IC structure 100 constructed according to some embodiments. Figure 23 Similar to Figure 8AAnd this is the structure following the operation at box 50. See the following description for further reference. Figures 24A to 24B and Figures 25A to 25B To compare the differences. Figures 24A to 24B and Figures 25A to 25B This is a cross-sectional view of a portion of IC structure 100 (such as only) Figure 23 (The portion within the dashed box 211). In particular, Figures 24A to 24B It is through each stage of manufacturing Figure 1 A cross-sectional view of the IC structure 100 formed by method 10; and Figures 25A to 25B It is through each stage of manufacturing Figure 22 A cross-sectional view of the IC structure 100 formed by method 10.

[0081] refer to Figure 1 and Figure 24A Method 10 includes block 52, performing a back-side ion implantation process. In some embodiments, the back-side ion implantation process includes, for example... Figure 14 The first step described in box 88A; and as Figure 14 The second step is described in block 88B. The first step of the back-side ion implantation process has a zero tilt angle and introduces dopant 120D1; and the second step of the back-side ion implantation process has a greater than zero tilt angle and introduces dopant 120D2. Specifically, dopant 120D1 is distributed on the top portion of the source / drain 120 not covered by the back-side source / drain via spacer 210, but not in the portion of the source / drain 120 directly below the back-side source / drain via spacer 210. Dopant 120D2 is distributed on the top portion of the source / drain 120 not covered by the back-side source / drain via spacer 210, and also in the portion of the source / drain 120 directly below the back-side source / drain via spacer 210.

[0082] refer to Figure 1 and Figure 24B Method 10 proceeds to block 55, where a backside silicide layer 220 is formed on the source / drain 120, particularly on the portion of the source / drain 120 in which dopants 120D1 and 120D2 are introduced.

[0083] refer to Figure 22 and Figure 25A Method 10 includes block 55, forming a backside silicide layer 220 on the source / drain 120.

[0084] refer to Figure 22 and Figure 25B Method 10 proceeds to block 52, where a back-side ion implantation process is performed. In some embodiments, the back-side ion implantation process includes, for example... Figure 14 The first step described in box 88A; and as Figure 14 The second step described in block 88B. The first step of the back-side ion implantation process has a zero tilt angle and introduces dopant 120D1; and the second step of the back-side ion implantation process has a greater than zero tilt angle and introduces dopant 120D2. By implementing Figure 22 Method 10, with its enhanced silicide thickness and increased uniformity between the sidewall and bottom portions, while pre-amorphous implantation induces sufficient damage. The thickness of the back-side silicide layer ranges from 2 nm to 10 nm.

[0085] By implementing Figure 1 (or Figure 18 or Figure 22 Method 10, the source / drain 120 includes a unique dopant profile and doping concentration with a non-uniform distribution. According to some examples, this... Figure 26 This is further illustrated in the text. Figure 26 This is a graphical view of the dopant concentration in the source / drain 120, particularly along the bottom portion of the source / drain 120 (such as...) in a direction perpendicular to the back side BS towards the front side FS. Figure 9A (The part indicated by the dashed arrow 302 in the image). Figure 26 In the diagram, the horizontal axis represents the depth in the vertical direction from the back side (BS) to the front side (FS). The vertical axis represents the dopant concentration. In the disclosed embodiment, the back-side PAI process at block 86 introduces gallium (Ga) into the source / drain 120, and the second ion implantation process at block 88 introduces boron (B) into the source / drain 120. Figure 26 As shown, dashed line 304 represents the dopant contribution introduced by in-situ epitaxial growth, which has a substantially uniform distribution. Curve 306 represents the Ga concentration, and curve 308 represents the B concentration; both are non-uniform. More specifically, the Ga concentration peaks near the back surface of source / drain 120 and then gradually decreases towards the front FS. Similarly, the B concentration peaks near the back surface of source / drain 120 and then gradually decreases towards the front FS.

[0086] In some embodiments, the method further includes forming a back-side silicide layer over the exposed source / drain before forming the back-side source / drain via. Another exemplary method includes forming a front-side source / drain contact on the source / drain of the transistor, forming a back-side source / drain via on the drain / source of the transistor, forming a front-side power rail over the front-side source / drain contact, and forming a back-side power rail over the back-side source / drain via. The front-side power rail is electrically connected to the front-side source / drain contact, and the back-side power rail is physically and electrically connected to the back-side source / drain via.

[0087] Various dielectric layers comprise different compositions to achieve etch selectivity and / or self-alignment. In some embodiments, capping layer 180 comprises silicon oxide (SiO2), SiOC, SiOCN, silicon nitride (SiN), low-thermal oxide (LTOX), other suitable dielectric materials, or combinations thereof. In some embodiments, capping layer 180 comprises a silicon nitride layer and silicon oxide disposed on the silicon nitride layer. Back-side via spacer 210 comprises a silicon nitride layer or silicon oxynitride. In this case, when etching back-side via spacer 210, the top silicon oxide layer of capping layer 180 serves as an etch stop layer to achieve etch selectivity.

[0088] In some embodiments, the p-type source / drain 120 formed by in-situ epitaxial growth includes Si1Ge. 1-x :B, where x is in the range between 0.5 and 1, and the boron concentration is in the range of 1 x 10⁻⁶. 20 cm 3 and 1x10 21 cm 3 Within the range between. In some embodiments, the n-type source / drain 120 formed by in-situ epitaxial growth includes phosphorus-doped silicon (SiP), arsenic-doped silicon (SiAs), phosphorus and arsenic-doped silicon (SiP and SiAs), antimony-doped silicon (SiSb), phosphorus, arsenic and antimony-doped silicon (SiP, SiAs and SiSb) or combinations thereof.

[0089] This disclosure provides an integrated circuit structure and a method for manufacturing the same. The method includes performing an ion implantation process from the back side; forming a back-side source / drain via; and forming a back-side power rail connected to the back-side source / drain via. The IC structure has power rails to supply power to the FET from the back side, increasing the contact area and reducing resistance.

[0090] In one example aspect, this disclosure provides a semiconductor manufacturing method. The method includes receiving a substrate having a front side and a back side; forming a source / drain electrode on the front side of the substrate and forming a gate structure adjacent to the source / drain electrode on the front side of the substrate, wherein the gate structure includes a gate dielectric layer, a gate electrode located above the gate dielectric layer, and a gate spacer disposed on sidewalls of the gate dielectric layer and the gate electrode, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; forming a capping layer over the back side of the substrate; patterning the capping layer to form a capping layer opening therein, the capping layer opening exposing a portion of the substrate overlapping with the source / drain electrode; forming a back-side source / drain via opening in the substrate exposing the source / drain electrode by patterning the exposed portion of the substrate with the capping layer; performing a back-side ion implantation process on the source / drain electrode from the back side of the substrate by introducing two different materials; and forming a back-side source / drain via in the back-side source / drain via opening.

[0091] In some embodiments, the backside ion implantation process includes: performing a first ion implantation process by introducing a first material into the source / drain to pre-amorphize the source / drain; performing a second ion implantation process on the source / drain by introducing a second material into the source / drain, the second material being different from the first material; and subsequently performing an annealing process on the source / drain.

[0092] In some embodiments, the first material comprises gallium, and the second material comprises boron; and the second ion implantation process is performed after the first ion implantation process.

[0093] In some embodiments, the first ion implantation process includes a first implantation step having a first tilt angle and a second implantation step having a second tilt angle greater than the first tilt angle; and the second ion implantation process includes a third implantation step having a third tilt angle and a fourth implantation step having a fourth tilt angle greater than the third tilt angle.

[0094] In some embodiments, each of the first tilt angle and the third tilt angle is zero; and each of the second tilt angle and the fourth tilt angle is in the range between 5° and 35°.

[0095] In some embodiments, the execution of the first ion implantation process includes using a 5x10 13 / cm 3 Up to 1x10 16 / cm 3 The first ion implantation process is performed with a dose within the range of 0.5 keV and 10 keV, an ion energy within the range of 0.5 keV and 10 keV, and a temperature below 500°C.

[0096] In some embodiments, forming the back-side source / drain via opening in the substrate includes: etching the substrate; etching a first interposer layer of semiconductor material and a second interposer layer of dielectric material; and causing the source / drain to be recessed from the back side of the substrate.

[0097] In some embodiments, the source / drain includes a first semiconductor layer with a first dopant concentration and a second semiconductor layer with a second dopant concentration disposed on the first semiconductor layer, the second dopant concentration being greater than the first dopant concentration; and the recessing of the source / drain from the back side of the substrate includes: recessing the source / drain from the back side of the substrate such that the second semiconductor layer of the source / drain is exposed.

[0098] In some embodiments, recessing the source / drain from the back side of the substrate includes: recessing the source / drain from the back side of the substrate such that the source / drain has a concave surface.

[0099] In some embodiments, the method further includes: forming a dielectric via spacer on the sidewall of the back-side source / drain via opening in the substrate; and forming a back-side silicide layer on the source / drain from the back side of the substrate through the back-side source / drain via opening.

[0100] In some embodiments, forming the dielectric via spacer on the sidewall of the back-side source / drain via opening in the substrate includes: forming the dielectric via spacer on the sidewall of the back-side source / drain via opening in the substrate after performing the back-side ion implantation process on the source / drain from the back side of the substrate.

[0101] In some embodiments, forming the backside silicide layer on the source / drain from the back side of the substrate through the backside source / drain via opening comprises: forming the backside silicide layer on the source / drain from the back side of the substrate before performing the backside ion implantation process on the source / drain from the back side of the substrate.

[0102] In another example aspect, this disclosure provides a semiconductor manufacturing method. The method includes forming a plurality of channels on a front side of a substrate, forming source / drain electrodes connected to the plurality of channels, and forming a gate structure enclosing the plurality of channels; forming a capping layer over a back side of the substrate; patterning the capping layer to form capping layer openings therein, the capping layer openings exposing portions of the substrate overlapping with the source / drain electrodes; forming back-side source / drain via openings in the substrate exposing the source / drain electrodes by patterning the exposed portions of the substrate with the capping layer; forming dielectric via spacers on the sidewalls of the back-side source / drain via openings, wherein the gate structure includes a first dielectric having a first dielectric constant. The material includes a gate dielectric layer and a dielectric via spacer of a second dielectric material having a second dielectric constant less than a first dielectric constant; a back-side ion implantation process is performed on the source / drain from the back side of the substrate, wherein the back-side ion implantation process includes performing a first ion implantation process to pre-amorphize the source / drain by introducing a first material into the source / drain, performing a second ion implantation process by introducing a second material into the source / drain, the second material being different from the first material, and performing an annealing process on the source / drain; and forming a back-side source / drain via in the opening of the back-side source / drain via.

[0103] In some embodiments, the execution of the second ion implantation process is performed after the first ion implantation process; the execution of the annealing process is performed after the second ion implantation process; and the first material includes gallium, and the second material includes boron.

[0104] In some embodiments, the first ion implantation process includes a first implantation step having a first tilt angle and a second implantation step having a second tilt angle greater than the first tilt angle; and the second ion implantation process includes a third implantation step having a third tilt angle and a fourth implantation step having a fourth tilt angle greater than the third tilt angle.

[0105] In some embodiments, forming the back-side source / drain via opening in the substrate includes: etching the substrate; etching a first interposer layer of semiconductor material and a second interposer layer of dielectric material; and recessing the source / drain from the back side of the substrate such that the recessed surface of the source / drain is perpendicularly located between two adjacent channels of the plurality of channels.

[0106] In some embodiments, the source / drain includes a first semiconductor layer with a first dopant concentration and a second semiconductor layer with a second dopant concentration disposed on the first semiconductor layer, the second dopant concentration being greater than the first dopant concentration; and the source / drain being recessed from the back side of the substrate includes: recessing the source / drain from the back side of the substrate such that the second semiconductor layer of the source / drain is exposed and has a concave surface.

[0107] In some embodiments, the method further includes: forming a back-side silicide layer on the source / drain through the back-side source / drain via opening from the back side of the substrate, wherein forming the dielectric via spacer on the sidewall of the back-side source / drain via opening includes: forming the dielectric via spacer on the sidewall of the back-side source / drain via opening after performing the back-side ion implantation process on the source / drain from the back side of the substrate.

[0108] In yet another example aspect, this disclosure provides a semiconductor manufacturing method. The method includes receiving a substrate having a front side and a back side; forming a source / drain electrode on the front side of the substrate and forming a gate structure on the front side of the substrate, the gate structure being adjacent to the source / drain electrode, wherein the gate structure includes a gate dielectric layer, a gate electrode located above the gate dielectric layer, and gate spacers disposed on sidewalls of the gate dielectric layer and the gate electrode, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacers; forming a capping layer over the back side of the substrate; patterning the capping layer to form a capping layer opening therein, the capping layer opening exposing a portion of the substrate overlapping the source / drain electrode; and forming a back-side source / drain passage exposing the source / drain electrode in the substrate by using the capping layer to pattern the exposed portion of the substrate. The process includes: opening a via; performing a first ion implantation process by introducing a first material into the source / drain to pre-amorphize the source / drain; performing a second ion implantation process on the source / drain by introducing a second material into the source / drain, the second material being different from the first material; subsequently, performing an annealing process on the source / drain; and forming a back-side source / drain via in the opening of the back-side source / drain via, wherein the first ion implantation process includes a first implantation step having a first tilt angle and a second implantation step having a second tilt angle greater than the first tilt angle, and the second ion implantation process includes a third implantation step having a third tilt angle and a fourth implantation step having a fourth tilt angle greater than the third tilt angle.

[0109] In some embodiments, forming the back-side source / drain via opening in the substrate includes: etching the substrate, etching a first interposer layer of semiconductor material and a second interposer layer of dielectric material, and recessing the source / drain from the back side of the substrate; the source / drain includes a first semiconductor layer with a first dopant concentration and a second semiconductor layer with a second dopant concentration disposed on the first semiconductor layer, the second dopant concentration being greater than the first dopant concentration; and the recessing of the source / drain from the back side of the substrate includes: recessing the source / drain from the back side of the substrate such that the second semiconductor layer of the source / drain is exposed and has a concave surface.

[0110] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Receives a substrate having a front side and a back side; A source / drain electrode is formed on the front side of the substrate, and a gate structure is formed on the front side of the substrate, the gate structure being adjacent to the source / drain electrode, wherein the gate structure includes a gate dielectric layer, a gate electrode located above the gate dielectric layer, and a gate spacer disposed on the sidewall of the gate electrode and the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; A capping layer is formed on the back side of the substrate; The capping layer is patterned to form capping openings that expose portions of the substrate that overlap with the source / drain. By using the capping layer to pattern the exposed portion of the substrate, back-side source / drain via openings that expose the source / drain are formed in the substrate; A back-side ion implantation process is performed on the source / drain electrodes from the back side of the substrate by introducing two different materials; and A back-side source / drain via is formed in the opening of the back-side source / drain via.

2. The method according to claim 1, wherein, The back-side ion implantation process includes: A first ion implantation process is performed by introducing a first material into the source / drain to pre-amorphize the source / drain; A second ion implantation process is performed on the source / drain by introducing a second material, different from the first material, into the source / drain; and Subsequently, an annealing process is performed on the source / drain electrodes.

3. The method according to claim 2, wherein, The first substance includes gallium, and the second substance includes boron; and The second ion implantation process is performed after the first ion implantation process.

4. The method according to claim 2, wherein, The first ion implantation process includes a first implantation step with a first tilt angle and a second implantation step with a second tilt angle greater than the first tilt angle; and The second ion implantation process includes a third implantation step with a third tilt angle and a fourth implantation step with a fourth tilt angle greater than the third tilt angle.

5. The method according to claim 4, wherein, Each of the first tilt angle and the third tilt angle is zero; and Each of the second tilt angle and the fourth tilt angle is in the range of 5° and 35°.

6. The method according to claim 2, wherein, The execution of the first ion implantation process includes 5x10 13 / cm 3 Up to 1x10 16 / cm 3 The first ion implantation process is performed with a dose within the range of 0.5 keV and 10 keV, an ion energy within the range of 0.5 keV and 10 keV, and a temperature below 500°C.

7. The method according to claim 1, wherein, Forming the back-side source / drain via opening in the substrate includes: Etch the substrate; Etching the first interposer layer of the semiconductor material and the second interposer layer of the dielectric material; and The source / drain is recessed from the back side of the substrate.

8. The method according to claim 7, wherein, The source / drain includes a first semiconductor layer with a first dopant concentration and a second semiconductor layer with a second dopant concentration disposed on the first semiconductor layer, wherein the second dopant concentration is greater than the first dopant concentration; and The recessing of the source / drain from the back side of the substrate includes: recessing the source / drain from the back side of the substrate such that the second semiconductor layer of the source / drain is exposed.

9. A method for forming a semiconductor device, comprising: Multiple channels are formed on the front side of the substrate, source / drain electrodes are formed to connect to the multiple channels, and a gate structure is formed to surround the multiple channels. A capping layer is formed above the back side of the substrate; The capping layer is patterned to form capping openings in the capping layer that expose portions of the substrate that overlap with the source / drain. By using the capping layer to pattern the exposed portion of the substrate, back-side source / drain via openings that expose the source / drain are formed in the substrate; A dielectric via spacer is formed on the sidewall of the back-side source / drain via opening, wherein the gate structure includes a gate dielectric layer of a first dielectric material having a first dielectric constant and the dielectric via spacer of a second dielectric material having a second dielectric constant less than the first dielectric constant; Performing a back-side ion implantation process on the source / drain from the back side of the substrate, wherein the back-side ion implantation process includes performing a first ion implantation process to pre-amorphize the source / drain by introducing a first material into the source / drain, performing a second ion implantation process by introducing a second material into the source / drain, the second material being different from the first material, and performing an annealing process on the source / drain; and A back-side source / drain via is formed in the opening of the back-side source / drain via.

10. A method of forming a semiconductor device, comprising: Receives a substrate having a front side and a back side; A source / drain electrode is formed on the front side of the substrate, and a gate structure is formed on the front side of the substrate, the gate structure being adjacent to the source / drain electrode, wherein the gate structure includes a gate dielectric layer, a gate electrode located above the gate dielectric layer, and a gate spacer disposed on the sidewall of the gate electrode and the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; A capping layer is formed above the back side of the substrate; The capping layer is patterned to form capping openings in the capping layer that expose portions of the substrate that overlap with the source / drain. By using the capping layer to pattern the exposed portion of the substrate, back-side source / drain via openings that expose the source / drain are formed in the substrate; A first ion implantation process is performed by introducing a first material into the source / drain to pre-amorphize the source / drain; A second ion implantation process is performed on the source / drain by introducing a second substance into the source / drain, the second substance being different from the first substance; Subsequently, an annealing process is performed on the source / drain electrodes; and A back-side source / drain via is formed in the opening of the back-side source / drain via, wherein, The first ion implantation process includes a first implantation step with a first tilt angle and a second implantation step with a second tilt angle greater than the first tilt angle. The second ion implantation process includes a third implantation step with a third tilt angle and a fourth implantation step with a fourth tilt angle greater than the third tilt angle.

Images