Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a transistor, the transistor including: a plurality of nanostructures disposed above a substrate region; an isolation component disposed adjacent to the substrate region; a source / drain component coupled to the plurality of nanostructures; a gate structure including a first portion enclosing the plurality of nanostructures and a second portion located above the isolation structure; a first gate isolation structure and a second gate isolation structure configured to cut the gate structure into segments, each of the first gate isolation structure and the second gate isolation structure extending through the second portion of the gate structure and the isolation component; a conductive component coupled to the transistor and disposed between and spaced apart from the first gate isolation structure and the second gate isolation structure; and a conductive via extending through the isolation component and disposed below and coupled to the conductive component.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] As technology nodes shrink, signals can be routed from the back side of a semiconductor device and / or routed to the back side for power and chip space optimization. For example, feedthrough vias (FTVs) can be used to connect signals from the back side of a wafer to the front side. This allows for flexibility in forming semiconductor components on both the front and back sides of the wafer. While existing methods for forming feedthroughs are generally sufficient for their intended purposes, they are not entirely satisfactory in every respect. Summary of the Invention

[0004] One embodiment of this application provides a method for forming a semiconductor structure, comprising:

[0005] A receiving precursor structure, the precursor structure comprising: an active region and a gate structure, the active region being located above a substrate and extending longitudinally along a first direction, the active region including a channel region and a source / drain component adjacent to the channel region, the gate structure extending longitudinally along a second direction different from the first direction, the gate structure including a first portion located above the channel region and a second portion adjacent to the first portion;

[0006] A second gate isolation structure and a first gate isolation structure are formed that extend through the second portion of the gate structure;

[0007] A source / drain contact is formed above the source / drain component, and the source / drain contact is electrically coupled to the source / drain component, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain component;

[0008] A conductive component is formed between the first gate isolation structure and the second gate isolation structure, wherein the source / drain contact and the conductive component are formed simultaneously, and wherein the source / drain contact is spaced apart from the conductive component;

[0009] A metal line is formed above the source / drain contact and the conductive component, and the metal line is electrically coupled to the source / drain contact and the conductive component;

[0010] The substrate is flipped over, and the thickness of the substrate is reduced from its bottom surface;

[0011] A mask is deposited over the bottom surface of the substrate;

[0012] A trench is formed extending through the mask to expose the conductive component and the second portion of the gate structure;

[0013] A conductive material layer is deposited in the trench; and

[0014] The conductive material layer and the mask are planarized to form conductive vias in the trench.

[0015] Another embodiment of this application provides a method for forming a semiconductor structure, comprising: forming a first active region and a second active region over a substrate; depositing an isolation component along a direction over the substrate and between the first active region and the second active region; forming a gate structure over the first active region and the second active region, thereby forming a first transistor and a second transistor, respectively, wherein the first transistor includes a first portion of the gate structure located over the first active region, and the second transistor includes a second portion of the gate structure located over the second active region, wherein the gate structure further includes a third portion located over the isolation component and disposed between the first portion and the second portion, the gate structure including... The gate dielectric layer and at least one metal layer located above the gate dielectric layer; removing a portion of the third portion of the gate structure to form a first trench and a second trench; forming a first gate isolation structure and a second gate isolation structure in the first trench and the second trench, respectively, wherein the first gate isolation structure includes a first portion located above the isolation member and a second portion extending into the isolation member; after forming the first gate isolation structure and the second gate isolation structure, forming a conductive member disposed between the first gate isolation structure and the second gate isolation structure and located above the isolation member; interconnecting the conductive member to the first transistor; and forming a feedthrough via extending through the isolation member to couple to the bottom surface of the conductive member.

[0016] In another aspect, embodiments of this application provide a semiconductor structure, comprising:

[0017] A transistor comprising: a plurality of nanostructures disposed above a substrate region; an isolation component disposed adjacent to the substrate region; a source / drain component coupled to the plurality of nanostructures, wherein a portion of the source / drain component is suspended above the isolation component; and a gate structure comprising a first portion enclosing the plurality of nanostructures and a second portion located above the isolation structure;

[0018] A first gate isolation structure and a second gate isolation structure are configured to cut the gate structure into segments, each of the first gate isolation structure and the second gate isolation structure extending through the second portion of the gate structure and the isolation member;

[0019] A conductive component, coupled to the transistor, wherein, in a top view, the conductive component is disposed between and spaced apart from the first gate isolation structure and the second gate isolation structure; and

[0020] A conductive via extends through the isolation member, wherein the conductive via is disposed below the conductive member and coupled to the conductive member. Attached Figure Description

[0021] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0022] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure is shown.

[0023] Figure 2 Experiences based on various aspects of this disclosure are shown. Figure 1 A partial top view of the exemplary precursor structure for each stage of the operation in the method.

[0024] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 11A , Figure 13A , Figure 15A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 22A This illustrates one or more aspects of the present disclosure. Figure 1Along such as during each manufacturing stage in the method Figure 2 The diagram shows a partial cross-sectional view of the precursor structure taken by line A-A'.

[0025] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 11B , Figure 13B , Figure 15B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 22B The following are shown in accordance with various aspects of this disclosure. Figure 1 Along such as during each manufacturing stage in the method Figure 2 The diagram shows a partial cross-sectional view of the precursor structure taken by line B-B'.

[0026] Figure 3C , Figure 4C , Figure 5C , Figure 8C , Figure 9C , Figure 11C , Figure 13C , Figure 15C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 22C The following are shown in accordance with various aspects of this disclosure. Figure 1 Along such as during each manufacturing stage in the method Figure 2 The diagram shows a partial cross-sectional view of the precursor structure taken by line C-C'.

[0027] Figure 3D , Figure 4D , Figure 5D , Figure 8D , Figure 9D , Figure 11D , Figure 13D , Figure 15D , Figure 17D , Figure 18D , Figure 19D , Figure 20D , Figure 22D The following are shown in accordance with various aspects of this disclosure. Figure 1 Along such as during each manufacturing stage in the method Figure 2 The diagram shows a partial cross-sectional view of the precursor structure taken by line D-D'.

[0028] Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 21 The following are shown in accordance with various aspects of this disclosure. Figure 1 Partial top view of the precursor structure during each manufacturing stage of the method.

[0029] Figure 23A , Figure 23B , Figure 23C , Figure 23D The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial cross-sectional view of the first optional precursor structure during each manufacturing stage of the method.

[0030] Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial cross-sectional view of the second optional precursor structure during each manufacturing stage of the method.

[0031] Figure 26 and Figure 27 The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial cross-sectional view of the third optional precursor structure during each manufacturing stage of the method.

[0032] Figure 28 and Figure 29 The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial cross-sectional view of the fourth optional precursor structure during each manufacturing stage of the method.

[0033] Figure 30 and Figure 31 The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial cross-sectional view of the fifth optional precursor structure during each manufacturing stage of the method.

[0034] Figure 32 The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial top view of the sixth optional precursor structure during each manufacturing stage of the method.

[0035] Figure 33 The following are shown in accordance with various aspects of this disclosure. Figure 1 A partial top view of the seventh optional precursor structure during each manufacturing stage of the method.

[0036] Figure 34A , Figure 34B , Figure 34C , Figure 34D , Figure 34E The following are shown in accordance with various aspects of this disclosure. Figure 1 Along such as during each manufacturing stage in the method Figure 33 The partial cross-sectional view of the seventh optional precursor structure is shown, taken from lines A-A', B-B', C-C', D-D', and E-E'. Detailed Implementation

[0037] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or component to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0039] Additionally, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account the inherent variations that occur during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with the value, the value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer with a thickness of "about 5 nm" could encompass dimensions ranging from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%.

[0040] As described above, to improve design flexibility, feedthrough vias (FTVs) can be used to connect signals (e.g., electrical signals or power supplies) between the back side and the front side of a substrate. In some embodiments, the semiconductor structure may include transistor regions for forming transistors and one or more feedthrough circuit regions for forming feedthrough vias. The feedthrough via may be coupled to the source / drain components or gate structure of one or more transistors in the transistor region. Forming the feedthrough via involves forming a trench from the back side of the substrate to expose the front-side conductive components, and filling the trench with a conductive material. Large feedthrough vias are desirable to reduce parasitic resistances (e.g., contact resistance between the feedthrough and the front-side conductive components, and parasitic resistance associated with the feedthrough itself) and power consumption. In various embodiments, a gate isolation structure is used to define the region for forming the feedthrough via. Ideally, the feedthrough via is isolated from adjacent conductive components (e.g., segments of the gate structure in the transistor region) by a gate isolation structure. However, coverage issues during the formation of the front-side conductive components and the feedthrough via can lead to unwanted leakage between the segments of the gate structure and the feedthrough via, adversely affecting reliability. Increasing the size of the gate isolation structure is one way to address this problem. However, if the gate isolation structure is too large, the risk of damage to the channel region and source / drain components increases during the formation of the gate isolation structure.

[0041] This disclosure provides a semiconductor structure including two gate isolation structures configured to define regions for forming feedthrough vias. In an exemplary method, instead of forming a large gate isolation structure, two gate isolation structures are formed in the feedthrough region after forming gate structures extending in a transistor region and a feedthrough region. The dimensions of the two gate isolation structures are smaller than the dimensions of a single gate isolation structure. Front-side conductive components and feedthrough vias are then formed in the feedthrough region and isolated from adjacent conductive components by the two gate isolation structures. By forming two gate isolation structures in the feedthrough region, a large feedthrough via can be formed without increasing the risk of damage to the channel region and source / drain components. Therefore, parasitic resistance can be reduced, leakage between segments of the gate structure in the feedthrough region and transistor region can be reduced, and reliability can be improved.

[0042] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor device according to an embodiment of the present disclosure. The following is in conjunction with... Figures 2 to 34E Description method 100, Figures 2 to 34EThis is a partial top view or cross-sectional view of the precursor structure 200 at different manufacturing stages according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and after method 100, and some of the described steps may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Because the precursor structure 200 will be fabricated into a semiconductor structure after the manufacturing process, the precursor structure 200 may be referred to as semiconductor structure 200 as needed by the context. To avoid ambiguity, Figures 2 to 34E The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. Unless otherwise specified, the same reference numerals denote the same parts throughout this disclosure.

[0043] refer to Figure 1 , Figure 2 , Figures 3A to 3D Method 100 includes block 102, wherein a precursor structure 200 is received. Figure 2 A partial top view of the precursor structure 200 is depicted. Figure 3A , Figure 3B , Figure 3C and Figure 3D Depicting along Figure 2 The diagram shows partial cross-sectional views of the precursor structure 200 cut by lines A-A', B-B', C-C', and D-D'.

[0044] The precursor structure 200 includes components for forming transistors (e.g., Figure 10 The illustrated transistor 200T has regions (e.g., regions 200A and 200B). Regions 200A and 200B may be referred to as transistor regions 200A and 200B, respectively. The precursor structure 200 also includes a region adjacent to the transistor (e.g., region 200C). In this illustrated embodiment, one or more feedthrough vias (FTVs) will be formed in the region adjacent to the transistor (e.g., region 200C). Region 200C may be referred to as feedthrough circuit region 200C. In this embodiment, the feedthrough circuit region 200C is disposed between transistor region 200A and transistor region 200B.

[0045] The precursor structure 200 includes a substrate 202. In embodiments, the substrate 202 is a bulk silicon substrate (i.e., including bulk single-crystal silicon). In various embodiments, the substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some alternative embodiments, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate.

[0046] The precursor structure 200 also includes a plurality of fin structures (e.g., fin structures 204a and 204b) protruding from the substrate 202. Each of the fin structures 204a and 204b extends longitudinally along the X direction. Each fin structure is divided into a channel region 204C overlapping with the dummy gate stack 210 (described below) and a source / drain (S / D) region 204SD adjacent to the channel region 204C. Depending on the context, the source / drain (S / D) region may refer individually or collectively to a source region for forming a source or a drain region for forming a drain. In an embodiment, the fin structures 204a and 204b are formed from a portion 202t of the substrate 202 and a vertical stack 207 of alternating channel layers 208 and sacrificial layers 206 using a combination of photolithography and etching steps. The channel layer 208 may be formed of silicon (Si), and the sacrificial layer 206 may be formed of silicon germanium (SiGe). The channel layer 208 and sacrificial layer 206 can be epitaxially deposited on the substrate 202 using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), and / or other suitable epitaxial growth processes. In this embodiment, the fin structures 204a / 204b include three pairs of alternating sacrificial layers 206 and channel layers 208. In some embodiments, the fin structures 204a / 204b may include a total of four to ten pairs of alternating sacrificial layers 206 and channel layers 208; of course, other configurations may also be applicable depending on specific design requirements. As shown, the feedthrough circuit region 200C is disposed between the fin structure 204a in the transistor region 200A and the fin structure 204b in the transistor region 200B.

[0047] The precursor structure 200 also includes an isolation member 203 formed to isolate two adjacent fin structures. The isolation member 203 may also be referred to as a shallow trench isolation (STI) member and may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In embodiments, the isolation member 203 comprises an oxide-based material having a dielectric constant of about 3 to about 5. Although not shown, in various embodiments, the top surface of the isolation member 203 is non-planar.

[0048] Still referencing Figure 2 and Figures 3A to 3D The precursor structure 200 also includes a dummy gate stack 210 disposed above the channel region 204C of the fin structures 204a and 204b. The fin structures 204a and 204b extend longitudinally along a first direction (e.g., the X direction), and the dummy gate stack 210 extends longitudinally along a second direction (e.g., the Y direction) different from the first direction. The channel region 204C and the dummy gate stack 210 also define a source / drain (S / D) region 204SD that does not vertically overlap with the dummy gate stack 210. In this embodiment, a gate replacement process (or a post-gate process) is employed, wherein the dummy gate stack 210 serves as a gate structure 228 (e.g., Figure 10 Placeholders are shown (as indicated). Other processes and configurations are possible. The dummy gate stack 210 includes a dummy dielectric layer, a dummy gate electrode layer above the dummy dielectric layer, and a gate top hard mask layer above the dummy gate electrode layer. The dummy dielectric layer may include silicon oxide. The dummy gate electrode layer may include polysilicon. The gate top hard mask layer may be a multilayer structure, including a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer. Suitable deposition, photolithography, and etching processes can be used to form the dummy gate stack 210. As shown, each dummy gate stack 210 has a first portion above the fin structure 204a, a second portion above the fin structure 204b, and a third portion above the isolation member 203 and extending between the first and second portions.

[0049] refer to Figure 1 and Figures 4A to 4D Method 100 includes block 104, wherein a gate spacer layer 214 is deposited over a precursor structure 200. In some embodiments, forming the gate spacer layer 214 includes conformally depositing one or more dielectric layers over the precursor structure 200. In some embodiments, the gate spacer layer 214 may be deposited using chemical vapor deposition (CVD), subatmospheric pressure chemical vapor deposition (SACVD), or atomic layer deposition (ALD), and may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, combinations thereof, or other suitable materials. Although not shown, the gate spacer layer 214 may be a multilayer structure, including, for example, a first material layer and a second material layer located above the first material layer, the first material layer and the second material layer having different compositions.

[0050] refer to Figure 1 , Figures 5A to 5DMethod 100 includes block 106, wherein gate spacer layer 214 is etched back to form gate spacer 214a extending along the sidewall surface of dummy gate stack 210 and fin sidewall spacer 214b extending along the sidewall surface of fin structures 204a-204b. That is, gate spacer 214a and fin sidewall spacer 214b are formed simultaneously. Figures 5A to 5D As shown, the gate spacer layer 214 is etched back to remove portions of the gate spacer layer 214 from, for example, the top surface of the dummy gate stack 210, the top surface of the fin structures 204a-204b, and the top surface of the isolation member 203, to form the gate spacer 214a (as shown). Figure 5B (as shown) and fin sidewall spacer 214b (as shown) Figure 5A (As shown). In some embodiments, the etch-back of the gate spacer layer 214 may include performing an anisotropic etching process. In this embodiment, the fin sidewall spacer 214b is in direct contact with the top surface of the isolation member 203 and covers a portion of the sidewall surface of the fin structures 204a-204b. In this embodiment, the fin sidewall spacer 214b and the gate spacer 214a are formed simultaneously by etching the same gate spacer layer 214. In some embodiments, the precursor structure 200 does not include the fin sidewall spacer 214b.

[0051] Still referencing Figure 1 and Figures 5A to 5D Method 100 includes block 108, wherein the source / drain regions 204SD of the fin structures 204a and 204b are recessed to form source / drain openings 216. In some embodiments, the source / drain regions 204SD are anisotropically etched by dry etching or other suitable etching processes to form the source / drain openings 216. Exemplary dry etching processes may employ oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Figure 5A and Figure 5B In the illustrated embodiment, the source / drain opening 216 extends through the vertical stack 207 and partially extends into the substrate 202. Figure 5B As shown, the sidewalls of the channel layer 208 and the sacrificial layer 206 are exposed in the source / drain opening 216.

[0052] refer to Figure 1 and Figures 6A to 6BMethod 100 includes a frame 110 in which an internal spacer component 218 is formed. After forming source / drain openings 216, a sacrificial layer 206 is exposed in the source / drain openings 216, and then the sacrificial layer 206 is selectively and partially recessed to form internal spacer recesses, while the exposed channel layer 208 is substantially unetched. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 may include using a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 is controlled by the duration of the etching process. A dielectric layer can then be conformally deposited over the precursor structure 200 (including in the internal spacer recesses) by an ALD, CVD, or any other suitable deposition process. For ease of description of a layer having a substantially uniform thickness over the various regions of the precursor structure 200, the term "conformally" may be used herein. The dielectric layer can then be etched back to form the internal spacer component 218. The dielectric layer may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. It is worth noting that the formation of the internal spacer (including the corresponding manufacturing steps described above) may be optional. That is, in some embodiments, the formation of the internal spacer component 218 may be omitted, and the internal spacer component 218 may not be present in the final structure.

[0053] refer to Figure 1 and Figures 7A to 7B Method 100 includes block 112, wherein a source / drain component 220 is formed in a source / drain opening 216. Depending on the context, the source / drain component may refer individually or collectively to a source or a drain. In the illustrated example, the source / drain component 220 includes a lower portion 220a and an upper portion 220b located above the lower portion 220a. The dopant concentration in the upper portion 220b is greater than the dopant concentration in the lower portion 220a. The upper portion 220b may include one or more epitaxial layers. For example, the upper portion 220b may include a first layer and a second layer, the first layer being adjacent to the channel region 204C and the second layer being spaced apart from the channel region 204C by the first layer, the dopant concentration in the first layer being less than the dopant concentration in the second layer. The width of the source / drain component 220 is greater than the width of the channel region 204C. Figure 7AAs shown, the upper portion 220b of the source / drain component 220 is suspended above the isolation component 203. In some embodiments, the lower portion 220a may be an undoped epitaxial layer. In another alternative embodiment, the lower portion 220a may be a dielectric layer. In some other embodiments, the lower portion 220a may include an undoped epitaxial layer and a dielectric layer on top of the undoped epitaxial layer. In various embodiments, the top surface of the lower portion 220a may be lower than the bottom surface of the bottommost channel layer of the channel layer 208.

[0054] Depending on the conductivity type of the transistor to be formed, the source / drain component 220 can be an n-type source / drain component 220 or a p-type source / drain component 220. An exemplary n-type source / drain component 220 may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials (e.g., SiC, SiCP, SiCAs), and can be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus, arsenic, or antimony), or out-of-situ doped using a junction implantation process. An exemplary p-type source / drain component may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and can be in-situ doped during the epitaxial process by introducing a p-type dopant (such as boron or gallium), or out-of-situ doped using a junction implantation process.

[0055] refer to Figure 1 and Figures 8A to 8D , Figures 9A to 9D Method 100 includes block 114, wherein the dummy gate stack 210 and sacrificial layer 206 are replaced by gate structure 228. (See reference...) Figures 8A to 8D A contact etch stop layer (CESL) 224 and a first interlayer dielectric (ILD) 226 are deposited over the precursor structure 200. CESL 224 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. After depositing CESL 224, the first ILD layer 226 is deposited over the precursor structure 200 by a PECVD process or other suitable deposition technique. The first ILD layer 226 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. A planarization process (such as chemical mechanical polishing (CMP)) may be performed on the precursor structure 200 to remove excess material and expose the top surface of the dummy gate electrode layer in the dummy gate stack 210.

[0056] With the dummy gate electrode layer exposed, block 114 of method 100 proceeds to removal of the dummy gate stack 210. Removal of the dummy gate stack 210 may include performing one or more etching processes selectively applied to the material in the dummy gate stack 210 to form a gate trench. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 210. After removing the dummy gate stack 210, the sacrificial layer 206 is selectively removed to release the channel layer 208 as a channel member 208 in the channel region 204C. The selective removal of the sacrificial layer 206 may be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonia-hydrogen peroxide-water mixture). The selective removal of multiple sacrificial layers 206 forms a gate opening.

[0057] With the selective removal of the dummy gate stack 210 and the sacrificial layer 206, block 114 of method 100 proceeds to forming the gate structure 228. Figures 9A to 9D In the illustrated embodiment, a gate structure 228 is formed in a gate opening and a gate trench. That is, the gate structure 228 includes an inner portion enclosing the channel member 208 and an outer portion located above the channel member 208. Although not individually labeled, each gate structure 228 may include an interface layer, a gate dielectric layer above the interface layer, and a gate electrode above the gate dielectric layer. In some embodiments, the interface layer comprises silicon oxide. The gate dielectric layer may be a high-k dielectric layer. Here, a high-k dielectric layer refers to a dielectric material with a dielectric constant greater than that of silicon dioxide (approximately 3.9). The gate dielectric layer may be deposited above the interface layer using ALD, CVD, and / or other suitable methods. The gate dielectric layer may include hafnium oxide. Optionally, the gate dielectric layer may include other high-k dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)TiO3 (BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer 214a. Figure 9CAs shown, gate structure 228 also extends over isolation member 203. In some embodiments, the gate dielectric layer and isolation member 203 are mixed at the interface between the gate dielectric layer and the isolation member. The gate electrode can be deposited over the gate dielectric layer using ALD, physical vapor deposition (PVD), CVD, electron beam evaporation, or other suitable methods. The gate electrode can comprise a single-layer or optionally multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode can comprise titanium nitride, aluminum titanium nitride, aluminum titanium nitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, silicon tantalum nitride, copper, other refractory metals, or other suitable metallic materials or combinations thereof. Furthermore, when the semiconductor structure 200 includes n-type transistors and p-type transistors, different gate electrodes can be formed for the n-type transistors and p-type transistors respectively, and they can include different work function metal layers (e.g., to provide different n-type and p-type work function metal layers). In various embodiments, the gate electrode may include a titanium-containing metal layer. When forming the gate structure 228, a plurality of transistors 200T are formed in transistor regions 200A and 200B.

[0058] refer to Figure 1 , Figure 10 and Figures 11A to 11D Method 100 includes block 116, wherein a first gate isolation structure 230a and a second gate isolation structure 230b are formed. Figure 10 A partial top view of the precursor structure 200, including the first gate isolation structure 230a and the second gate isolation structure 230b, is depicted. Figure 11A , Figure 11B , Figure 11C and Figure 11D Depicting along Figure 10 The diagram shows a partial cross-sectional view of the precursor structure 200 taken along lines A-A', B-B', C-C', and D-D'. A first gate isolation structure 230a and a second gate isolation structure 230b are configured to cut one or more gate structures 228 into three physically separated segments 228a, 228b, and 228c. In this embodiment, the first gate isolation structure 230a and the second gate isolation structure 230b are formed in the feedthrough circuit region 200C to limit the area used to form the feedthrough via 276. In various embodiments, the feedthrough via 276 physically separates the segments 228a and 228b from the first gate isolation structure 230a and the second gate isolation structure 230b.

[0059] An exemplary process for forming the first gate isolation structure 230a and the second gate isolation structure 230b may include forming a mask film over the precursor structure 200. In some embodiments, the mask film may include a photoresist layer. The photoresist layer may be formed on the precursor structure 200, exposed to a radiation source through a patterned mask, and subsequently developed to form the patterned mask film. The patterned mask film includes a first opening and a second opening extending longitudinally along the X direction and disposed between transistor regions 200A and 200B and over the isolation member 203. When using the patterned mask film as an etching mask, an etching process is performed to remove portions of the precursor structure 200 (e.g., portions of the gate structure 228, CESL 224 and the first ILD layer 226, the isolation member 203, and the gate spacer 214a), thereby forming the first trench and the second trench (now filled by the first gate isolation structure 230a and the second gate isolation structure 230b, respectively). After the formation of the first trench and the second trench, the patterned mask film may be selectively removed. After forming the first and second trenches, a first dielectric layer 232 is conformally deposited over the precursor structure 200 (e.g., ...). Figure 11A As shown), to partially fill the first and second trenches. The first dielectric layer 232 can be deposited by any suitable method including CVD, ALD, and can include any suitable dielectric material. In an embodiment, the first dielectric layer 232 includes silicon oxide. A second dielectric layer 234 (e.g., as shown) is deposited over the first dielectric layer 232. Figure 11A As shown, the second dielectric layer 234 essentially fills the remaining portions of the first and second trenches. The second dielectric layer 234 can be deposited by CVD, ALD, other suitable methods, or combinations thereof, and can comprise any suitable dielectric material. Notably, the composition of the second dielectric layer 234 differs significantly from that of the first dielectric layer 232. In some embodiments, the dielectric constant of the second dielectric layer 234 is greater than that of the first dielectric layer 232. In one embodiment, the second dielectric layer 234 comprises silicon nitride. After depositing the first dielectric layer 232 and the second dielectric layer 234, a planarization process (e.g., one or more chemical mechanical polishing processes) can be performed to remove excess portions of the first dielectric layer 232 and the second dielectric layer 234 until the top surface of the gate structure 228 is exposed, thereby forming a first gate isolation structure 230a and a second gate isolation structure 230b in the first and second trenches, respectively. In the illustrated embodiment, each of the first gate isolation structure 230a and the second gate isolation structure 230b comprises two dielectric layers (e.g., the first dielectric layer 232 and the second dielectric layer 234). However, other configurations are possible. For example, the first gate isolation structure 230a and the second gate isolation structure 230b can be a single-layer structure formed of a dielectric material.

[0060] like Figure 11C As depicted, a first gate isolation structure 230a is disposed between segments 228a and 228c, and a second gate isolation structure 230b is disposed between segments 228b and 228c. That is, segment 228c is separated from segments 228a and 228c in transistor regions 200A and 228B by the first gate isolation structure 230a and the second gate isolation structure 230b. Figure 11A As shown, each of the first gate isolation structure 230a and the second gate isolation structure 230b also extends through the first ILD layer 226 and CESL 224 without exposing the source / drain components 220. When viewed from above, each of the first gate isolation structure 230a and the second gate isolation structure 230b extends longitudinally along the X direction. Figure 10 , Figure 11A and Figure 11C In the illustrated embodiment, the first gate isolation structure 230a and the second gate isolation structure 230b extend through the gate structure 228 and into the isolation member 203. Figure 23A In another alternative embodiment shown, the first gate isolation structure 230a and the second gate isolation structure 230b may extend through the gate structure 228 and the isolation member 203, and into the substrate 202. This alternative embodiment will be described in more detail later.

[0061] refer to Figure 1 , Figure 12 and Figures 13A to 13D Method 100 includes block 116, wherein a source / drain contact 236 is formed above the source / drain component 220, and a conductive component 238 is formed between the first gate isolation structure 230a and the second gate isolation structure 230b. Figure 12 A partial top view of the precursor structure 200, including source / drain contacts 236 and conductive components 238, is depicted. Figure 13A , Figure 13B , Figure 13C and Figure 13D Depicting along Figure 12 The diagram shows partial cross-sectional views of the precursor structure 200 cut by lines A-A', B-B', C-C', and D-D'.

[0062] In an exemplary process, an etch stop layer 240 and a second ILD layer 242 are formed over the gate structure 228 and the source / drain component 220. The formation and composition of the etch stop layer 240 and the second ILD layer 242 are similar to those of the contact etch stop layer 224 and the first ILD layer 226, and repeated descriptions are omitted for simplicity. A combination of photolithography and etching processes can then be performed to form a first opening (now filled by the silicide layer and the source / drain contact 236) and a second opening (now filled by the conductive component 238). The first opening is formed within transistor regions 200A and 200B. The first opening extends through the etch stop layers 224 and 240 and the first ILD layer 226 and the second ILD layer 242, and exposes the source / drain component 220. The second opening is formed within the feedthrough circuit region 200C. In this embodiment, the second opening extends through etch stop layers 224 and 240, as well as the first ILD layer 226 and the second ILD layer 242, and exposes the isolation member 203. In this embodiment, the etchant used in the etching process for forming the first and second openings can etch the first ILD layer 226 at a higher etch rate than that used for etching CESL 224. As a result, as... Figure 13A As shown, the depth of the second opening (now filled by the conductive component 238) is greater than the depth of the first opening (now filled by the source / drain contact 236).

[0063] After forming the first and second openings, an optional dielectric barrier layer 244 (e.g., silicon nitride) may be formed to extend along the sidewalls of the first and second openings. The formation of the dielectric barrier layer 244 may enhance the isolation between the gate structure (e.g., segment 228b of gate structure 228) and the source / drain contacts 236. The formation of the dielectric barrier layer 244 may include depositing a dielectric material layer over the substrate 202 (including in the first and second openings) and etching back the dielectric material layer to form the dielectric barrier layer 224 extending along the sidewalls of the first and second openings. A silicide layer 246 may then be formed in the first opening and in the transistor regions 200A and 200B. To form the silicide layer 246, a metal layer (via ALD, CVD, and / or other deposition processes) is deposited over the precursor structure 200 (including in the first and second openings), and then an annealing process is performed to induce a silicide reaction between the metal layer and the source / drain components 220. Excess portions of the metal layer where the silicide layer 246 is not formed can be removed. Suitable metal layers may include titanium, tantalum, nickel, cobalt, or tungsten. In embodiments where the metal layer includes nickel and the source / drain component 220 includes silicon-germanium, the silicide layer 246 includes nickel silicide, nickel germanide, and nickel-germanium silicon. In some other embodiments, the silicide layer 246 may include titanium silicide, tantalum silicide, cobalt silicide, or tungsten silicide. In embodiments, the conductivity of the silicide layer 246 is greater than the conductivity of the source / drain component 220.

[0064] After forming the silicide layer 246, a conductive layer may be deposited over the precursor structure 200 to fill the first and second openings. The conductive layer may include aluminum, rhodium, ruthenium, copper, iridium, or tungsten. A planarization process (such as CMP) may then be performed to remove excess portions of the conductive layer over the second ILD layer 242, thereby forming source / drain contacts 236 in transistor regions (e.g., transistor regions 200A and 200B) and conductive members 238 in the second opening in the feedthrough region 200C. In some alternative embodiments, the planarization process may be stopped until the top surface of the etch stop layer 240 is exposed or until the etch stop layer 240 is removed. The depth of the conductive member 238 is greater than the depth of the source / drain contact 236. The top surface of the source / drain contact 236 is coplanar with the top surface of the conductive member 238, and the bottom surface of the source / drain contact 236 is higher than the bottom surface of the conductive member 238. Source / drain contacts 236 are electrically coupled to source / drain components 220 via a silicide layer 246. Although conductive components 238 are not formed above source / drain components 220, they are formed together with source / drain contacts 236 through a common process, and therefore may also be referred to as source / drain contacts in some embodiments.

[0065] refer to Figure 1 , Figure 14 and Figures 15A to 15D Method 100 includes block 120, wherein a source / drain contact via 256 is formed over a source / drain contact 236, a conductive rail 258 is formed over a conductive member 238, and a gate via 259 is formed over a segment of the gate structure 228. Figure 14 A partial top view of the precursor structure 200, including source / drain contact vias 256, gate vias 259, and conductive rails 258, is depicted. Figure 15A , Figure 15B , Figure 15C and Figure 15D Depicting along Figure 14 The diagram shows partial cross-sectional views of the precursor structure 200 cut by lines A-A', B-B', C-C', and D-D'.

[0066] In an exemplary process, an etch stop layer 250 and a third ILD layer 252 are formed over the source / drain contacts 236 and conductive components 238. The formation and composition of the etch stop layer 250 and the third ILD layer 252 can be similar to the formation and composition of the contact etch stop layer 224 and the first ILD layer 226, and repeated descriptions are omitted for simplicity. A combination of photolithography and etching processes can then be performed to form a third opening (now filled by the source / drain contact via 256), a fourth opening (now filled by the conductive rails 258), and a fifth opening (now filled by the gate via 259). The third opening is formed within the transistor region 200A. The third opening extends through the etch stop layer 250 and the third ILD layer 252 and exposes the source / drain contacts 236. The fourth opening is formed within the feedthrough region 200C. In this embodiment, the fourth opening extends through the etch stop layer 250 and the third ILD layer 252 and exposes a plurality of conductive components 238.

[0067] After forming the third and fourth openings, source / drain contact vias 256 and conductive rails 258 are formed in the third and fourth openings, respectively. The formation and composition of the source / drain contact vias 256 and conductive rails 258 can be similar to the formation and composition of the source / drain contact 236, and repeated descriptions are omitted for simplicity. The source / drain contact via 256 is disposed on and electrically coupled to the source / drain contact 236. The conductive rails 258 are disposed on and electrically coupled to the conductive component 238. Figure 14 and Figure 15D As shown, the conductive rail 258 extends longitudinally along the X direction, extends above the segment 228c of the plurality of conductive components 238 and the gate structure 228, and is disposed between the first gate isolation structure 230a and the second gate isolation structure 230b. Figure 15CAs shown, the conductive rail 258 is physically separated from segment 228c of the gate structure 228. A gate via 259 is disposed on and electrically coupled to segment 228b of the gate structure 228. Although only one source / drain contact via and one gate via are depicted in the figure, it is understood that any suitable number of source / drain contact vias and any suitable number of gate vias can be formed in transistor regions 200A and 200B.

[0068] refer to Figure 1 , Figure 16 , Figures 17A to 17D Method 100 includes a block 122, wherein interconnect layers 266 and 268 are formed over source / drain contact vias 256 and conductive rails 258. Figure 16 A partial top view of the precursor structure 200, including metal lines 264 of interconnect layers 266 and 268, is depicted. Figure 17A , Figure 17B , Figure 17C and Figure 17D Depicting along Figure 16 The diagram shows a partial cross-sectional view of the precursor structure 200 taken along lines A-A', B-B', C-C', and D-D'. In the exemplary process for forming the interconnect layer 266, an etch stop layer 260 and an inter-metal dielectric (IMD) layer 262 are formed over the source / drain contact vias 256 and conductive rails 258. The formation and composition of the etch stop layer 260 and the IMD layer 262 can be similar to the formation and composition of the contact etch stop layer 224 and the first IMD layer 226, and repeated descriptions are omitted for simplicity. Metal lines 264 are then formed to extend through the etch stop layer 260 and the IMD layer 262 to couple to the source / drain contact vias 256 and conductive rails 258. Figure 16 In the top view depicted, metal line 264 extends longitudinally along the Y direction and extends above transistor region 200A and feedthrough circuit region 200C.

[0069] After forming interconnect layer 266, an additional interconnect layer 268 may be formed over the precursor structure 200. Similar to interconnect layer 266, the additional interconnect layer 268 may include multiple inter-metal dielectric (IMD) layers and multiple metal lines or contact vias located in each IMD layer. In some cases, the IMD layers and the first IMD layer 226 may have similar compositions. The metal lines 264 and the metal lines and contact vias located in each IMD layer may be formed of metals such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to reduce electromigration. Interconnect layers 266 and 268 are part of interconnect structure 269. Figure 17AAs depicted, the metal line 264 is located above and in direct contact with the source / drain contact via 256 and the conductive rail 258. That is, the source / drain contact via 256 is electrically coupled to the conductive rail 258 via the metal line 264. In some other embodiments, the source / drain contact via 256 is electrically coupled to the conductive rail 258 via a combination of vias and metal lines disposed in the interconnect structure 269.

[0070] refer to Figure 1 and Figures 18A to 22D Method 100 includes a frame 124, wherein a feedthrough 276 is formed below the conductive member 238 and disposed between a first gate isolation structure 230a and a second gate isolation structure 230b. (See reference) Figures 18A to 18D After the interconnect structure 269 is formed, a carrier substrate (not shown) may be bonded to the interconnect structure 269, for example, by fusion bonding, using an adhesive layer, or a combination thereof. In some cases, the carrier substrate may comprise a semiconductor material (such as silicon), sapphire, glass, a polymer material, or other suitable material. Once the carrier substrate is bonded to the interconnect structure 269, the precursor structure 200 is flipped over. For ease of description, the positional relationships between these components will be described with reference to the accompanying drawings. For example, after flipping, the substrate 202 is positioned above the isolation member 203, and the bottom surface of the substrate 202 is now facing upwards.

[0071] refer to Figures 19A to 19D Planarization (e.g., through a planarization process such as chemical mechanical polishing (CMP)) of the back side of the precursor structure 200 is performed to reduce the thickness of the substrate 202. In an embodiment, as... Figures 19A to 19D As shown, the planarization process can be stopped after the bottom surface of the isolation member 203 and a portion 202t of the substrate 202 are exposed. In some embodiments, the planarization process may also remove a portion of the isolation member 203.

[0072] Still referencing Figures 19A to 19D A dielectric structure 270 is formed above the bottom surface of the isolation member 203. In this embodiment, to provide an endpoint for a subsequent planarization process, the dielectric structure 270 includes a first layer 270a and a second layer 270b having a material composition different from that of the first layer 270b. In this embodiment, the first layer 270a includes a nitride layer (e.g., silicon nitride), and the second layer 270b includes an oxide layer (e.g., silicon oxide). The dielectric structure 270 is then patterned to form an opening 272. The opening 272 exposes the isolation member 203 and is disposed in the feedthrough circuit region 200C. In this embodiment, when viewed from above, the opening extends longitudinally along the X direction and overlaps perpendicularly with the conductive rail 258.

[0073] refer to Figures 20A to 20DWhen using the patterned dielectric structure 270 as an etching mask, an etching process is performed to etch through the isolation member 203, thereby forming the feedthrough trench 274. The etching process can be a selective wet etching process or a selective dry etching process. In some embodiments, the etching process can etch dielectric elements (e.g., isolation member 203, CESL 226, gate spacer 214a, interface layer of gate structure 228) and conductive elements (e.g., gate electrode of gate structure 228, conductive member 238) at different etching rates. Figure 20D As shown, after the etching process is completed, the feedthrough trench 274 exposes the bottom surface 238b of the conductive component 238 and the bottom surface 228cb of the segment 228c of the gate structure 228. In the embodiment, since different components are etched at different etching rates, the bottom surface of the precursor structure 200 exposed by the trench 274 is a non-flat bottom surface 200e. For example, the bottom surface 200de of the dielectric elements (e.g., gate spacer 214a, dielectric barrier layer 244, first ILD layer 226) is lower than the bottom surface 238b of the conductive component 238 and the bottom surface 228cb of the segment 228c of the gate structure 228. Furthermore, since at least part of the interface layer and gate dielectric layer of the segment 228c of the gate structure 228 are removed, such as Figure 20C As shown by the dashed lines, the bottom surface 228cb of segment 228c may be lower than the bottom surface 238b of conductive component 238, the bottom surface 228ab of segment 228a, and the bottom surface of segment 228b. In some embodiments, the bottom surface 228cb of segment 228c may also be curved.

[0074] refer to Figure 21 and Figures 22A to 22D Feedthrough holes 276 are formed in feedthrough grooves 274. Figure 21 A partial top view of the precursor structure 200, including the feed hole 276, is depicted. Figure 22A , Figure 22B , Figure 22C and Figure 22D Depicting along Figure 21The diagram shows partial cross-sectional views of the precursor structure 200 taken along lines A-A', B-B', C-C', and D-D'. After forming the feedthrough trench 274, a conductive material layer is deposited above the bottom surface 200e of the precursor structure 200 (including within the feedthrough trench 274). The conductive material layer may include titanium nitride (TiN), titanium (Ti), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), other suitable materials, or combinations thereof, and can be formed by any suitable deposition process (e.g., CVD). A planarization process (such as a chemical mechanical polishing (CMP) process) can then be performed to remove excess material above the bottom surface of the first layer 270a of the dielectric structure 270 to define the final structure of the feedthrough via 276. The feedthrough via 276 typically follows the shape of the feedthrough trench 274. That is, the profile of the top surface of the feedthrough via 276 is the same as the profile of the bottom surface 200e of the precursor structure 200. The bottom surface of the feedthrough hole 276 is coplanar with the bottom surface of the first layer 270a of the dielectric structure 270. For example... Figure 22D As shown, the feedthrough 276 has an uneven depth due to its uneven bottom surface. The feedthrough 276 is formed in the feedthrough circuit region 200C and extends on the bottom surface of segment 228c and conductive member 238. Figure 21 and Figure 22D As shown, the feedthrough 276 is electrically coupled to the source / drain contact 236 through the conductive component 238, the conductive rail 258, the metal wire 264, and the source / drain contact via 256. In this embodiment, the feedthrough 276 extends longitudinally along the X direction. Figure 21 As shown in the top view, the length of the feedthrough 276 is greater than the length of the conductive rail 258, and the width of the feedthrough 276 is greater than the width of the conductive rail 258. In this embodiment, the feedthrough 276 is disposed between the first gate isolation structure 230a and the second gate isolation structure 230b. By forming two isolation structures (e.g., the first gate isolation structure 230a and the second gate isolation structure 230b), the feedthrough 276 is limited by the first gate isolation structure 230a and the second gate isolation structure 230b or isolated from segments 228a and 228b through the first gate isolation structure 230a and the second gate isolation structure 230b.

[0075] refer to Figure 1Method 100 includes block 126, in which further processing is performed. This further processing may include forming a back-side via above the bottom surface of the source / drain component 220, and forming a back-side interconnect structure below the back-side via. In some embodiments, the back-side interconnect structure may include multiple inter-metal dielectric (IMD) layers and multiple metal lines or contact vias located in each IMD layer. The metal lines and contact vias in each IMD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to reduce electromigration.

[0076] Figures 23A to 23D A cross-sectional view of the precursor structure 200 according to a first alternative embodiment of the present disclosure is depicted. In the above embodiment, as Figure 11A and Figure 22A As shown, the first gate isolation structure 230a and the second gate isolation structure 230b extend into the isolation member 203. Figures 23A to 23D In the first alternative embodiment shown, the first gate isolation structure 230a and the second gate isolation structure 230b extend through the isolation member 203 and into the substrate 202. (See above reference) Figures 19A to 19D The described planarization process removes not only a portion of the substrate 202, but also the lower portions of the first gate isolation structure 230a and the second gate isolation structure 230b. For example, after the planarization process is completed, the second dielectric layer 234 of the first gate isolation structure 230a and the second gate isolation structure 230b is exposed. That is, the first dielectric layer 232 now extends on the sidewalls of the second dielectric layer 234, and a portion of the first dielectric layer 232 extending on the bottom surface of the second dielectric layer 234 is removed.

[0077] Figures 24A to 24D and Figures 25A to 25D A cross-sectional view of a semiconductor structure 200 according to a second alternative embodiment of the present disclosure is depicted. In the above embodiments, as Figure 13A and Figure 13D As shown, conductive component 238 extends through CESL 224 and the first ILD layer 226, and is disposed on insulating component 203. Figures 24A to 24D In the second alternative embodiment shown, the conductive member 238 may not extend through CESL 224 and the first ILD layer 226, and may be disposed above and spaced apart from the isolation member 203. That is, the bottom surface of segment 228c is lower than the bottom surface of the conductive member 238. The operations performed at blocks 120-126 are then performed to form a structure composed of... Figures 25A to 25D The semiconductor structure 200 is represented. Figures 25A to 25D The semiconductor structure 200 shown is similar to that made of Figures 23A to 23DThe semiconductor structure 200 is shown. Some differences between them include: the conductive component 238 in the second alternative embodiment has a reduced depth, and the feedthrough 276 in the second alternative embodiment has an increased depth. In the second alternative embodiment, the depth difference between the conductive component 238 and the segment 228c is greater than that between the conductive component 238 and the segment 228c. Figures 23A to 23D The depth difference between the conductive component 238 and segment 228c in the illustrated embodiment.

[0078] Figure 26 and Figure 27 A cross-sectional view of a semiconductor structure 200 according to a third alternative embodiment of the present disclosure is depicted. In the above embodiment, the feedthrough 276 is spaced apart from both the first gate isolation structure 230a and the second gate isolation structure 230b. In the third alternative embodiment, due to various reasons (e.g., coverage issues), the etching process used to form the feedthrough trench 274 may also etch a portion of one of the first gate isolation structure 230a and the second gate isolation structure 230b (e.g., the second gate isolation structure 230b). As a result, as Figure 26 and Figure 27 As shown, the feedthrough hole 276 formed in the feedthrough trench 274 can be disposed on one of the etched parts of the first gate isolation structure 230a and the second gate isolation structure 230b.

[0079] Figure 28 and Figure 29 A cross-sectional view of a semiconductor structure 200 according to a fourth alternative embodiment of the present disclosure is shown. Compared to the other embodiments described above, the feedthrough 276 in the fourth alternative embodiment may have an increased size. For example, Figures 28 to 29 The width of the bottom surface of the feedhole 276 in the middle is greater than Figures 23C to 23D The width of the bottom surface of the feedthrough 276 in the fourth alternative embodiment. The feedthrough 276 may extend along the sidewall of the first gate isolation structure 230a and / or the sidewall of the second gate isolation structure 230b.

[0080] Figure 30 and Figure 31 A cross-sectional view of a semiconductor structure 200 according to a fifth alternative embodiment of the present disclosure is depicted. (As described above) Figures 28 to 29 Compared to the fourth alternative embodiment shown, the feedthrough 276 in the fifth alternative embodiment may have an increased size and overlap with the first gate isolation structure 230a and the second gate isolation structure 230b.

[0081] Figure 32A partial top view of a semiconductor structure 200 according to a sixth alternative embodiment of the present disclosure is shown. In the above embodiment, a feedthrough 276 in the feedthrough circuit region 200C is electrically coupled to the source / drain component 220 of the transistor 200T. In this sixth alternative embodiment, the feedthrough 276 in the feedthrough circuit region 200C may be electrically coupled to the gate structure of another transistor (e.g., segment 228c of the gate structure 228). The differences and similarities between this sixth alternative embodiment and the above embodiments are explained by... Figure 21 and Figure 32 This indicates that, for the sake of simplicity, repeated descriptions have been omitted.

[0082] Figure 33 and Figures 34A to 34E This represents a seventh alternative embodiment of the present disclosure. Figure 33 A partial top view of the precursor structure 200 according to a seventh alternative embodiment of the present disclosure is depicted. Figure 34A , Figure 34B , Figure 34C , Figure 34D and Figure 34E Depicting along Figure 33 The diagram shows partial cross-sectional views of the precursor structure 200 taken along lines A-A', B-B', C-C', D-D', and E-E'. In this seventh alternative embodiment, transistor regions 200A and 200B may include source / drain contacts 236 formed above some source / drain components 220 and back-side vias (e.g., back-side vias 290) formed below other source / drain components 220. The total number of source / drain contacts 236 in this seventh embodiment is less than the total number of source / drain contacts 236 in the other embodiments described above. In this seventh embodiment, the total number of conductive components 238 is less than the total number of conductive components 238 in the other embodiments described above. The back-side vias 290 are laterally spaced from adjacent components by dielectric barrier layers 292. The dielectric barrier layers 292 may be similar to dielectric barrier layers 244. The back-side vias 290 are electrically coupled to the corresponding source / drain components 220 below them through a silicide layer 294. Silicide layer 294 can be similar to silicide layer 246. In this embodiment, as... Figure 33 As shown, to reduce parasitic capacitance, the source / drain contacts 236 and conductive components 238 are arranged in an interleaved pattern. That is, the source / drain contacts 236 are offset from the conductive components 238. In various embodiments, when viewed from above, the sidewall edges of the feedthrough via 276 may be aligned with the sidewall edges of the first gate isolation structure 230a and the second gate isolation structure 230b. In some alternative embodiments, the length of the feedthrough via 276 may be greater than, equal to, or less than the lengths of the first gate isolation structure 230a and the second gate isolation structure 230b. This disclosure includes multiple embodiments, and these embodiments may be combined in different ways, all of which are within the scope of this disclosure.

[0083] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor structures and their formation. This disclosure provides methods for forming feedthroughs and structures including feedthroughs. In embodiments, this disclosure provides a semiconductor structure including two gate isolation structures configured to define regions for forming feedthroughs. By forming two gate isolation structures in the feedthrough region, large feedthroughs can be formed without increasing the risk of damage to the channel region and source / drain components. Therefore, parasitic resistance can be reduced, leakage between segments of the gate structure in the feedthrough and transistor regions can be reduced, and reliability can be improved.

[0084] This disclosure provides numerous different embodiments. Semiconductor devices and methods of manufacturing the same are disclosed herein. In one exemplary aspect, this disclosure relates to a method. The method includes receiving a precursor structure comprising: an active region located above a substrate and extending longitudinally along a first direction, the active region including a channel region and a source / drain component adjacent to the channel region; and a gate structure extending longitudinally along a second direction different from the first direction, the gate structure including a first portion located above the channel region and a second portion adjacent to the first portion; forming a first gate isolation structure and a second gate isolation structure extending through the second portion of the gate structure; forming a source / drain contact above the source / drain component and electrically coupling the source / drain contact to the source / drain component, wherein the conductivity of the source / drain contact is greater than that of the source / drain component. The conductivity of the component forms a conductive component disposed between a first gate isolation structure and a second gate isolation structure, wherein source / drain contacts and conductive components are formed simultaneously, and wherein the source / drain contacts are spaced apart from the conductive components, a metal line is formed above the source / drain contacts and conductive components, and the metal line is electrically coupled to the source / drain contacts and conductive components, the substrate is flipped and the thickness of the substrate is reduced from the bottom surface of the substrate, a mask is deposited above the bottom surface of the substrate, a trench extending through the mask is formed to expose a second portion of the conductive components and gate structure, a conductive material layer is deposited in the trench, and the conductive material layer and the mask are planarized, thereby forming a conductive via in the trench.

[0085] In some embodiments, the bottom surface of the conductive component is lower than the bottom surface of the source / drain contact. In some embodiments, the top surface of the conductive component is coplanar with the top surface of the source / drain contact. In some embodiments, the method may further include forming a conductive line on the conductive component and forming a source / drain via on the source / drain contact, with the metal line extending above the conductive line and the source / drain via. In some embodiments, the conductive line and the conductive via extend longitudinally along a first direction, and the length of the conductive via is greater than the length of the conductive line. In some embodiments, the conductive component is a first conductive component, the source / drain contact is spaced apart from the first conductive component along a second direction, and the method may further include forming a second conductive component spaced apart from the first conductive component along the first direction, and the second conductive component being disposed between the first gate isolation structure and the second gate isolation structure. In some embodiments, the conductive line also extends above the second conductive component. In some embodiments, the conductive via is also disposed below the second conductive component and coupled to the second conductive component. In some embodiments, the conductive via is disposed between and spaced apart from the first gate isolation structure and the second gate isolation structure.

[0086] In another exemplary aspect, this disclosure relates to a method. The method includes forming a first active region and a second active region over a substrate, depositing an isolation component along a direction over the substrate and between the first active region and the second active region, and forming a gate structure over the first active region and the second active region, thereby forming a first transistor and a second transistor, respectively. The first transistor includes a first portion of the gate structure located over the first active region, and the second transistor includes a second portion of the gate structure located over the second active region. The gate structure further includes a third portion located over the isolation component and disposed between the first and second portions. The gate structure includes a gate dielectric layer and a gate dielectric layer. At least one metal layer above the layer, removing a portion of the third part of the gate structure to form a first trench and a second trench, forming a first gate isolation structure and a second gate isolation structure in the first trench and the second trench respectively, wherein the first gate isolation structure includes a first portion located above the isolation member and a second portion extending into the isolation member, after forming the first gate isolation structure and the second gate isolation structure, forming a conductive member disposed between the first gate isolation structure and the second gate isolation structure and located above the isolation member, interconnecting the conductive member to a first transistor, and forming a feedthrough via extending through the isolation member to couple to the bottom surface of the conductive member.

[0087] In some embodiments, the first active region may include a channel region disposed between the first source / drain component and the second source / drain component, the channel region including multiple nanostructures. In some embodiments, interconnecting the conductive component to the first transistor may include forming a source / drain contact over the first source / drain component, depositing a source / drain contact via on the source / drain contact, depositing a conductive line on the conductive component, and forming a metal line electrically coupled to the source / drain contact via and the conductive line. In some embodiments, the length and width of the via are greater than the length and width of the conductive line, respectively. In some embodiments, when viewed from top, the conductive line is disposed between the first gate isolation structure and the second gate isolation structure. In some embodiments, when viewed from top, the conductive line and the metal line extend longitudinally in different directions. In some embodiments, forming the first gate isolation structure and the second gate isolation structure may include depositing a dielectric liner in the first trench and the second trench, and depositing a dielectric fill layer on the dielectric liner to fill the first trench and the second trench.

[0088] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a transistor comprising: a plurality of nanostructures disposed above a substrate region; an isolation component disposed adjacent to the substrate region; a source / drain component coupled to the plurality of nanostructures, portions of the source / drain component suspended above the isolation component; and a gate structure including a first portion enclosing the plurality of nanostructures and a second portion located above the isolation structure. The semiconductor structure further includes: a first gate isolation structure and a second gate isolation structure configured to segment the gate structure, each of the first and second gate isolation structures extending through the second portion of the gate structure and the isolation component; a conductive component coupled to the transistor, which, in a top view, is disposed between and spaced apart from the first and second gate isolation structures; and a conductive via extending through the isolation component, wherein the conductive via is disposed below and coupled to the conductive component.

[0089] In some embodiments, the semiconductor structure may further include a source / drain contact located above and electrically coupled to the source / drain component, wherein the top surface of the conductive component is coplanar with the top surface of the source / drain contact, and the bottom surface of the conductive component is lower than the bottom surface of the source / drain contact. In some embodiments, the semiconductor structure may further include: a first via located on the source / drain contact; and a second via located on the conductive component, wherein the length of the second via is greater than the length of the first via and less than the length of the conductive via, and in a top view, the second via is disposed between and spaced apart from the first gate isolation structure and the second gate isolation structure. In some embodiments, the top surface of the conductive via is non-flat.

[0090] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A receiving precursor structure, the precursor structure comprising: an active region located above a substrate and extending longitudinally along a first direction, the active region including a channel region and source / drain components adjacent to the channel region; and a gate structure extending longitudinally along a second direction different from the first direction, the gate structure including a first portion located above the channel region and a second portion adjacent to the first portion; A second gate isolation structure and a first gate isolation structure are formed that extend through the second portion of the gate structure; A source / drain contact is formed above the source / drain component, and the source / drain contact is electrically coupled to the source / drain component, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain component; A conductive component is formed between the first gate isolation structure and the second gate isolation structure, wherein the source / drain contact and the conductive component are formed simultaneously, and wherein the source / drain contact is spaced apart from the conductive component; A metal line is formed above the source / drain contact and the conductive component, and the metal line is electrically coupled to the source / drain contact and the conductive component; The substrate is flipped over, and the thickness of the substrate is reduced from its bottom surface; A mask is deposited over the bottom surface of the substrate; A trench is formed extending through the mask to expose the conductive component and the second portion of the gate structure; A conductive material layer is deposited in the trench; and The conductive material layer and the mask are planarized to form conductive vias in the trench.

2. The method according to claim 1, wherein, The bottom surface of the conductive component is lower than the bottom surface of the source / drain contact.

3. The method according to claim 2, wherein, The top surface of the conductive component is coplanar with the top surface of the source / drain contact.

4. The method according to claim 1, further comprising: Conductive lines are formed on the conductive component; as well as Source / drain vias are formed on the source / drain contacts. The metal wire extends above the conductive wire and the source / drain via.

5. The method according to claim 4, wherein, The conductive wire and the conductive via extend longitudinally along the first direction, and the length of the conductive via is greater than the length of the conductive wire.

6. The method according to claim 4, wherein, The conductive component is a first conductive component, the source / drain contacts are spaced apart from the first conductive component along the second direction, and the method further includes: A second conductive component is formed that is spaced apart from the first conductive component along the first direction. The second conductive component is disposed between the first gate isolation structure and the second gate isolation structure.

7. The method according to claim 6, wherein, The conductive line also extends above the second conductive component.

8. The method according to claim 6, wherein, The conductive via is also disposed below the second conductive component and coupled to the second conductive component.

9. A method for forming a semiconductor structure, comprising: A first active region and a second active region are formed above the substrate; An isolation component is deposited along the direction above the substrate and between the first active region and the second active region; A gate structure is formed over the first active region and the second active region to form a first transistor and a second transistor, respectively. The first transistor includes a first portion of the gate structure located over the first active region, and the second transistor includes a second portion of the gate structure located over the second active region. The gate structure further includes a third portion located over the isolation member and disposed between the first portion and the second portion. The gate structure includes a gate dielectric layer and at least one metal layer located over the gate dielectric layer. A portion of the third part of the gate structure is removed to form a first trench and a second trench; A first gate isolation structure and a second gate isolation structure are formed in the first trench and the second trench, respectively, wherein the first gate isolation structure includes a first portion located above the isolation member and a second portion extending into the isolation member; After the first gate isolation structure and the second gate isolation structure are formed, a conductive component is formed between the first gate isolation structure and the second gate isolation structure and above the isolation component; Interconnecting the conductive component to the first transistor; and A feedthrough is formed, which extends through the isolation member to couple to the bottom surface of the conductive member.

10. A semiconductor structure, comprising: A transistor comprising: a plurality of nanostructures disposed above a substrate region; an isolation component disposed adjacent to the substrate region; a source / drain component coupled to the plurality of nanostructures, wherein a portion of the source / drain component is suspended above the isolation component; and a gate structure comprising a first portion enclosing the plurality of nanostructures and a second portion located above the isolation structure; A first gate isolation structure and a second gate isolation structure are configured to cut the gate structure into segments, each of the first gate isolation structure and the second gate isolation structure extending through the second portion of the gate structure and the isolation member; A conductive component, coupled to the transistor, wherein, in a top view, the conductive component is disposed between and spaced apart from the first gate isolation structure and the second gate isolation structure; and A conductive via extends through the isolation member, wherein the conductive via is disposed below the conductive member and coupled to the conductive member.

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