Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method for forming the semiconductor device are disclosed. The semiconductor device includes a first substrate portion having a first width, a second substrate portion having a second width, a first source / drain region and a second source / drain region respectively disposed on the first substrate portion and the second substrate portion, a first nanostructure channel region having a third width disposed on the first substrate portion, a second nanostructure channel region having a fourth width disposed on the second substrate portion, a first contact structure having a fifth width disposed on the back surface of the first source / drain region, and a second contact structure having a sixth width disposed on the back surface of the second source / drain region. The fourth width is smaller than the third width, and the sixth width is smaller than the fifth width.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry is constantly scaling down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (including planar MOSFETs), fin field-effect transistors (FinFETs), and gate-all-around field-effect transistors (GAAFETs). This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] One embodiment of this application provides a semiconductor device, comprising: a first substrate portion having a first width along a first direction; a second substrate portion having a second width along the first direction; a first source / drain region and a second source / drain region respectively disposed on the first substrate portion and the second substrate portion, wherein, along a cross-section, the thickness of the first source / drain region is different from the width of the first source / drain region; a first nanostructure channel region having a third width along the first direction and disposed on the first substrate portion; a second nanostructure channel region having a fourth width along the first direction and disposed on the second substrate portion, wherein the fourth width is smaller than the second width; a first contact structure disposed on the front surface of the first source / drain region, wherein the first contact structure includes a silicide layer having a curved profile; a second contact structure having a fifth width along the first direction and disposed on the back surface of the first source / drain region; and a third contact structure having a sixth width along the first direction and disposed on the back surface of the second source / drain region, wherein the sixth width is smaller than the fifth width.

[0004] Another aspect of this application provides a method for forming a semiconductor device, comprising: forming a superlattice structure on a substrate structure, the superlattice structure including a first nanostructure layer, a second nanostructure layer, and a sacrificial nanostructure layer, wherein the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer are arranged alternately; forming a polycrystalline silicon structure on the superlattice structure; forming source / drain regions on the substrate structure, wherein, along a cross-section, the thickness of the source / drain regions is different from the width of the source / drain regions; removing the polycrystalline silicon structure to expose the top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; performing a trimming process on the exposed top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; and replacing the polycrystalline silicon structure and the sacrificial nanostructure layer with a gate structure including a gate dielectric layer and a gate metal layer, wherein the gate metal layer comprises a titanium-based material.

[0005] Embodiments of this application further provide a method for forming a semiconductor device, comprising: forming a substrate structure having a first substrate portion and a second substrate portion on a substrate, the first substrate portion and the second substrate portion having widths along a first direction and different from each other; forming a superlattice structure including a nanostructure layer and a sacrificial nanostructure layer, wherein the nanostructure layer includes a first nanostructure layer portion having a first width along the first direction and a second nanostructure layer portion having a second width along the first direction, wherein the second width is smaller than the first width; forming an isolation region including a top surface having a curved profile and surrounding the superlattice structure; forming a first polysilicon structure and a second polysilicon structure on the first nanostructure layer portion and the second nanostructure layer portion, respectively; forming spacers along the sidewalls of the first polysilicon structure and the second polysilicon structure; depositing a mask layer on the first polysilicon structure; removing the second polysilicon structure to expose the second nanostructure layer portion; modifying the dimensions of the second nanostructure layer portion; and forming a gate structure surrounding the modified second nanostructure layer portion, wherein the thickness of the gate dielectric layer of the gate structure is smaller than the thickness of the spacer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description.

[0007] Figure 1A An isometric view of a semiconductor device according to some embodiments is shown.

[0008] Figures 1B to 1HDifferent cross-sectional views of semiconductor devices with active regions of different widths are shown according to some embodiments.

[0009] Figure 1I A top view of a semiconductor device with active regions of different widths is shown according to some embodiments.

[0010] Figure 1J and Figure 1K Different cross-sectional views of another semiconductor device with active regions of different widths according to some embodiments are shown.

[0011] Figures 1L to 1N Different cross-sectional views of another semiconductor device with active regions of different widths according to some embodiments are shown.

[0012] Figure 10 A top view of another semiconductor device with an active region of different widths according to some embodiments is shown.

[0013] Figure 1P A cross-sectional view of another semiconductor device with an active region of different widths according to some embodiments is shown.

[0014] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device with an active region of different widths, according to some embodiments.

[0015] Figure 3 , Figure 4 , Figures 5A to 17A , Figures 5B to 17B and Figures 5C to 17C Isometric views and cross-sectional views of semiconductor devices with active regions of varying widths at various stages of their manufacturing process are shown, according to some embodiments.

[0016] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0018] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or component to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in the specification indicate that the described embodiment may include specific components, structures, or features, but each embodiment may not necessarily include specific components, structures, or features. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific component, structure, or feature is described in connection with an embodiment, those skilled in the art will be able to implement such a component, structure, or feature in conjunction with other embodiments (whether explicitly described or not).

[0020] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, and therefore the terminology or terminology used herein should be interpreted by those skilled in the art based on the teachings herein.

[0021] In some embodiments, the terms "about" and "substantially" may refer to the value of a given quantity that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to the percentage of the value as interpreted by one of skill in the art based on the teachings herein.

[0022] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0023] This disclosure provides example semiconductor devices (e.g., GAAFETs) with active regions of different widths and example methods for manufacturing semiconductor devices, wherein there is a reliable connection between the back-side contact structure and the source / drain (S / D) regions in the active regions. Active regions of different widths can provide different device characteristics (e.g., drive current, power consumption, device speed) in different regions of the semiconductor device. In some embodiments, the semiconductor device may have a wide active region and a narrow active region separated by an isolation structure extending through a substrate structure having a first substrate portion and a second substrate portion. The wide active region may include a first S / D region and a first nanostructure channel region disposed on the first substrate portion. The narrow active region may include a second S / D region and a second nanostructure channel region disposed on the second substrate portion. The widths of the first substrate portion, the first S / D region, and the first nanostructure channel region may be wider than the widths of the second substrate portion, the second S / D region, and the second nanostructure channel region. In some embodiments, the first nanostructured channel region in the wide active region can achieve a higher drive current than the second nanostructured channel region in the narrow active region, while the second nanostructured channel region can achieve lower power consumption than the first nanostructured channel region.

[0024] In some embodiments, a second nanostructure channel region with a width less than or equal to about 20 nm (e.g., about 5 nm to about 20 nm) can be formed to achieve low power consumption. In some embodiments, a second nanostructure channel region with a width less than or equal to about 30 nm (e.g., about 5 nm to about 30 nm) can be formed to achieve low power consumption. In some embodiments, a second nanostructure channel region with a width less than or equal to about 35 nm (e.g., about 5 nm to about 35 nm) can be formed to achieve low power consumption. A second substrate portion located below the second nanostructure channel region and the second S / D region can be formed to have a width larger than the width of the second nanostructure channel region (e.g., about 10 nm to about 40 nm). By using a second substrate portion wider than the second nanostructure channel region, the second S / D region can be grown on the second substrate with sufficient width to provide sufficient contact area for forming a contact structure on the back surface of the second S / D region. As a result, the electrical connection between the contact structure and the second S / D region in the narrow active region can be more reliable compared to semiconductor devices with a second substrate portion and a second nanostructure channel region of equal width in a narrow active region.

[0025] Figure 1A An isometric view of a semiconductor device 100 (also referred to as "FET 100" or "GAA FET 100") according to some embodiments is shown. Figure 1B and Figure 1L The following is illustrated according to some embodiments. Figure 1A Different cross-sectional views of semiconductor device 100 with line AA. Figure 1C The following is illustrated according to some embodiments. Figure 1A A cross-sectional view of the semiconductor device 100 of line BB. Figure 1D The following is illustrated according to some embodiments. Figure 1A A cross-sectional view of the semiconductor device 100 with line CC. Figure 1E The following is illustrated according to some embodiments. Figure 1A A cross-sectional view of the semiconductor device 100 with line DD. Figure 1F The following is illustrated according to some embodiments. Figure 1A A cross-sectional view of the semiconductor device 100 of line EE. Figure 1G , Figure 1J and Figure 1M The following is illustrated according to some embodiments. Figure 1A Different cross-sectional views of the semiconductor device 100 with line FF. Figure 1H , Figure 1K and Figure 1N The following is illustrated according to some embodiments. Figure 1A Different cross-sectional views of the semiconductor device 100 of line GG. Figure 1IThe following is illustrated according to some embodiments. Figure 1B and Figure 1L A top view of the semiconductor device 100 with line HH. Figures 1B to 1N It shows that, for simplicity, it is not shown in Figure 1A The image shows a top view and cross-sectional view of the semiconductor device 100 with additional structures. Unless otherwise stated, Figures 1A to 1N Discussions of elements with the same annotations are applicable to each other.

[0026] refer to Figures 1A to 1I The semiconductor device 100 may include a wide active region 100w and a narrow active region 100n. In some embodiments, the wide active region 100w may include (i) a base portion 101w (also referred to as "fin base portion 101w"), (ii) S / D regions 102w1 and 102w2, (iii) an S / D spacer 103w, (iv) a first interposer structure 104w, (v) a second interposer structure 105w, (vi) a nanostructured channel region 106w, (vii) a nanostructured layer 107w, (viii) a gate structure 108w configured to surround the nanostructured channel region 106w, (ix) an external spacer 110w, (x) an internal spacer 112w, (xi) an etch stop layer (ESL) 114w, (xii) an interlayer dielectric (ILD) layer 116w, (xiii) a shallow trench isolation (STI) region 118w, (xiv) a front side (FS) contact structure 122Fw and (xv) a back side (BS) contact structure 122Bw.

[0027] In some embodiments, the narrow active region 100n may include (i) a base portion 101n (also referred to as "fin base portion 101n"), (ii) S / D regions 102n1 and 102n2, (iii) an S / D spacer 103n, (iv) a first interposer structure 104n, (v) a second interposer structure 105n, (vi) a nanostructured channel region 106n, (vii) a nanostructured layer 107n, (viii) a gate structure 108n configured to surround the nanostructured channel region 106n, (ix) an external spacer 110n, (x) an internal spacer 112n, (xi) an ESL 114n, (xii) an ILD layer 116n, (xiii) an STI region 118n, (xiv) an FS contact structure 122Fn and (xv) a BS contact structure 122Bn. In some embodiments, the semiconductor device may further include (i) a BS ESL 114B disposed on the BS surfaces of the substrate portions 101w and 101n, (ii) an ESL 114 disposed on the ESL 114w and 114n and on the ILD layers 116w and 116n, (iii) an ILD layer 116 disposed on the ESL 114, and (iv) an isolation structure 130 disposed on the BS ESL 114B.

[0028] In the following description, S / D regions 102w1 and 102w2 are collectively referred to as "S / D region 102w", and S / D regions 102n1 and 102n2 are collectively referred to as "S / D region 102n". Depending on the context, each of S / D regions 102w and 102n may individually or collectively refer to the source or drain. FS elements of semiconductor device 100 are disposed on FS surfaces 102f of S / D regions 102w and 102n, and BS elements of semiconductor device 100 are disposed on BS surfaces 102b of S / D regions 102w and 102n.

[0029] In some embodiments, substrate portions 101w and 101n may comprise semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, substrate portions 101w and 101n may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). Substrate portions 101w and 101n may have elongated sides extending along the X-axis. In some embodiments, substrate portion 101w may have a width W1w (e.g., about 50 nm to about 100 nm) along the Y-axis greater than the width W1n (e.g., about 10 nm to about 40 nm) of substrate portion 101n. Within these width ranges, the substrate portions 101w and 101n can provide a substrate with sufficient width for the formation of the S / D regions 102w and 102n, the nanostructured channel regions 106w and 106n, and / or the BS contact structures 122w and 122n, to achieve higher voltage and / or higher drive current in the wide active region 100w, and lower power consumption and / or faster switching speed in the narrow active region 100n.

[0030] In some embodiments, S / D regions 102w and / or 102n may be n-type and may include epitaxially grown semiconductor material (such as Si) and n-type dopants (such as phosphorus and other suitable n-type dopants). In some embodiments, S / D regions 102w and / or 102n may be p-type and may include epitaxially grown semiconductor material (such as Si and SiGe) and p-type dopants (such as boron and other suitable p-type dopants). In some embodiments, the thickness of S / D regions 102w and 102n along the Z-axis may be different from the width of S / D regions 102w and 102n along the Y-axis. Since S / D regions 102w and 102n are formed on substrate portions 101w and 101n, respectively, the relative width of S / D regions 102w and 102n may depend on the relative width of substrate portions 101w and 101n along the Y-axis. In some embodiments, the width W2w of the S / D region 102w along the Y-axis can be greater than the width W2n of the S / D region 102n along the Y-axis. In some embodiments, such as... Figure 1F and Figure 1I As shown, the width W2w of the S / D region 102w along the Y-axis can be greater than the width W1w of the base portion 101w along the Y-axis, and as... Figure 1F and Figure 1I As shown, the width W2n of the S / D region 102n along the Y-axis can be greater than the width W1n of the base portion 101n along the Y-axis.

[0031] In some embodiments, the epitaxial lateral growth of S / D regions 102w and 102n along the Y-axis can be controlled by S / D spacers 103w and 103n, respectively. Therefore, during the epitaxial growth of S / D regions 102w and 102n, S / D spacers 103w and 103n can prevent adjacent S / D regions 102w and 102n from merging with each other. In some embodiments, S / D spacers 103w and 103n may include dielectric materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiCON), and other suitable dielectric materials. In some embodiments, in addition to controlling the epitaxial lateral growth of S / D regions 102w and 102n, S / D spacers 103w and 103n can reduce or minimize the etching of STI regions 118w and 118n during the formation of S / D regions 102w and 102n.

[0032] In some embodiments, the first and second interposer structures 104w and 104n, and the second and third interposer structures 105w and 105n, may be disposed below the BS surface 102b of the S / D regions 102w and 102n (such as S / D regions 102w1 and 102n2 without BS contact structures 122Bw and 112Bn). The first and second interposer structures 104w and 104n, and the second and third interposer structures 105w and 105n, can prevent dopant from diffusing from the S / D regions 102w and 102n to the substrate structures 101w and 101n, thus preventing current leakage and short-channel effects between adjacent S / D regions in the semiconductor device 100. In some embodiments, the first and second interposer structures 104w and 104n, and the second and third interposer structures 105w and 105n, can electrically isolate the S / D regions 102w and 102n from the substrate structures 101w and 101n.

[0033] In some embodiments, the first intermediary structures 104w and 104n can be in direct contact with the BS surface 102b of the S / D regions 102w1 and 102n2. For example... Figure 1B As shown, the sidewalls of the first intermediate structures 104w and 104n extending along the Y-axis can contact the bottommost internal gate spacers 112w and 112n, respectively, and as... Figure 1A , Figure 1E and Figure 1F As shown, the sidewalls of the first intermediate structures 104w and 104n, extending along the X-axis, can contact the S / D spacers 103w and 103n, respectively. Figure 1E and Figure 1FAs shown, since the first intermediary structures 104w and 104n are formed in the base portions 101w and 101n respectively, the relative widths of the first intermediary structures 104w and 104n can depend on the relative widths of the base portions 101w and 101n along the Y-axis. In some embodiments, the width of the first intermediary structure 104w along the Y-axis can be greater than the width of the first intermediary structure 104n along the Y-axis.

[0034] In some embodiments, the first intermediate structures 104w and 104n may include dielectric nitride materials such as SiN, SiON, SiCON, and SiCN. In some embodiments, the first intermediate structures 104w and 104n may include silicon-rich dielectric materials. In some embodiments, the silicon-rich dielectric materials may include (i) silicon-rich nitrides (SiN, SiON, SiCON, and SiCN) with a silicon atom concentration higher than the nitrogen atom concentration. x N y (ii) Silicon-rich nitrides (Si) with a silicon atom concentration higher than that of oxygen and nitrogen atoms. x O y N z (iii) Silicon-rich carbon oxides (SiO2) with a silicon atom concentration higher than that of oxygen and carbon atoms. x O y C z (iv) Silicon-rich carbon nitrides (SiO2) with silicon atom concentrations higher than those of oxygen, carbon, and nitrogen atoms. w O x C y N z (v) Silicon-rich boron oxynitride (SiO2) with a silicon atom concentration higher than that of oxygen, boron, and nitrogen atoms. w B x O y N z (vi) Silicon-rich boron oxide (SiO2) with a silicon atom concentration higher than that of oxygen, boron, and carbon atoms. w B x O y C z(vii) other suitable silicon-rich silicon nitride or carbide-based dielectric materials. The silicon-rich dielectric material can provide the first interposer structures 104w and 104n with high resistance to etch chemicals used during the formation of the gate structures 108w and 108n and / or the BS contact structures 122Bw and 122Bn. In some embodiments, the first interposer structures 104w and 104n can have a thickness of about 2 nm to about 8 nm. Within this thickness range, the first interposer structures 104w and 104n can adequately protect the S / D regions 102w and 102n and / or adequately prevent current leakage between adjacent S / D regions during the formation of the gate structures 108w and 108n without compromising the device size and manufacturing cost of the semiconductor device 100.

[0035] In some embodiments, the second intermediary structures 105w and 105n may be disposed below the first intermediary structures 104w and 104n, and in portions of the base portions 101w and 101n below the S / D regions 102w and 102n (such as S / D regions 1024w1 and 102n2 without BS contact structures 122Bw and 122Bn). Figure 1E and Figure 1F As shown, since the second intermediary structures 105w and 105n are formed by replacing portions of the base portions 101w and 101n respectively, the relative widths of the second intermediary structures 105w and 105n can depend on the relative widths of the base portions 101w and 101n along the Y-axis. In some embodiments, the width of the second intermediary structure 105w along the Y-axis can be greater than the width of the second intermediary structure 105n along the Y-axis. The second intermediary structures 105w and 105n can directly contact the first intermediary structures 104w and 104n respectively. In some embodiments, such as Figure 1B As shown, the second intermediate structures 105w and 105n can extend vertically below the BS surface of the bottommost internal gate spacers 112w and 112n, respectively. Figure 1B As shown, the sidewalls of the second intermediate structures 105w and 105n extending along the Y-axis can contact the base portions 101w and 101n respectively, and the sidewalls of the second intermediate structures 105w and 105n extending along the X-axis can contact the STI regions 118w and 118n and / or the S / D spacers 103w and 103n (e.g.) Figure 1A , Figure 1E and Figure 1F (As shown).

[0036] In some embodiments, the second interposer structures 105w and 105n may be electrically inert and may include an undoped Si layer, an undoped SiGe layer, or other suitable undoped semiconductor material. In some embodiments, the second interposer structures 105w and 105n may include an undoped SiGe layer with a Ge concentration of about 40 atomic% to about 50 atomic%. In some embodiments, the second interposer structures 105w and 105n may include a Ge layer having boron or phosphorus dopants and no Si atoms. In some embodiments, the second interposer structures 105w and 105n may have a height H1 of about 10 nm to about 15 nm along the Z-axis. The height H1 may be the vertical dimension between the highest point on the top surface of the second interposer structures 105w and 105n and the lowest point on the bottom surface of the second interposer structures 105w and 105n. In some embodiments, if the height H1 is less than about 10 nm, the second interposer structures 105w and 105n may not adequately prevent dopant from diffusing from the S / D regions 102w and 102n to the substrate portions 101w and 101n, and may not adequately prevent current leakage between adjacent S / D regions. On the other hand, if the height H1 is greater than about 15 nm, the processing time (e.g., etching time, deposition time) for forming the second interposer structures 105w and 105n increases, and thus increases the manufacturing cost of the semiconductor device 100.

[0037] In some embodiments, the nanostructured channel regions 106w and 106n and the nanostructured layers 107w and 107n may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructure shapes. As used herein, the term "nanostructure" defines a structure, layer, and / or region having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the lengths of the nanostructured channel regions 106w and 106n along the X-axis may be greater than the lengths of the nanostructured layers 107w and 107n along the X-axis. In some embodiments, the nanostructured channel regions 106w and 106n may be electrically active, and the nanostructured layers 107w and 107n may be electrically inert. The nanostructured channel region 106w can be disposed between the S / D regions 102w1 and 102w2, and the nanostructured channel region 106n can be disposed between the S / D regions 102n1 and 102n2. In some embodiments, the nanostructured layer 107w can be disposed between the S / D region 102w2 and the isolation structure 130, and the nanostructured layer 107n can be disposed between the S / D region 102n1 and the isolation structure 30.

[0038] In some embodiments, the nanostructured channel regions 106w and 106n and the nanostructured layers 107w and 107n may comprise Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. The nanostructured channel regions 106w and 106n and the nanostructured layers 107w and 107n may comprise the same materials. Although a stack of three nanostructured channel regions 106w and 106n and a stack of three nanostructured layers 107w and 107n are shown, the semiconductor device 100 may have any number of nanostructured channel regions 106w and 106n and nanostructured layers 107w and 107n.

[0039] In some embodiments, the widths W3w and W4w of the nanostructured channel regions 106w along the Y-axis can be greater than the widths W3n and W4n of the nanostructured channel regions 106n along the Y-axis (e.g., ...). Figure 1G , Figure 1H and Figure 1I As shown), to achieve higher voltage and / or higher drive current in a wide active region 100W, and lower power consumption and / or faster switching speed in a narrow active region 100N. In some embodiments, such as Figure 1B As shown, the widths of the nanostructured channel regions 106w and 106n along the X-axis can be substantially equal to each other. In some embodiments, such as Figure 1I As shown, the nanostructured channel region 106w can have a rectangular cross-sectional profile along the XY plane, and the nanostructured channel region 106n can have an I-shaped cross-sectional profile along the XY plane. In some embodiments, such as Figure 1B , Figure 1G and Figure 1I As shown, the nanostructured channel region 106w may have a channel portion 106wa surrounded by the gate structure 108w and a channel portion 106wb surrounded by the gate spacer 110w. Along the Y-axis, the width W3w of the channel portion 106wb (e.g., about 50 nm to about 100 nm) and the width W4w of the channel portion 106wa (e.g., about 50 nm to about 100 nm) may be substantially equal to each other and substantially equal to the width W1w of the substrate portion 101w. In some embodiments, such as Figure 1B , Figure 1H and Figure 1IAs shown, the nanostructured channel region 106n may have a channel portion 106na surrounded by a gate structure 108n and a channel portion 106nb surrounded by a gate spacer 110n. The width W3n of the channel portion 106nb along the Y-axis (e.g., about 10 nm to about 40 nm) may be substantially equal to the width W1n of the substrate portion 101n along the Y-axis, while the width W4n of the channel portion 106na (e.g., about 4 nm to about 35 nm) may be smaller than the width W1n of the substrate portion 101n and the width W3n of the channel portion 106nb.

[0040] The channel portion 106na can be formed narrower than the base portion 101n to achieve low power consumption in the narrow active region 100n, and the base portion 101n can be formed wider to provide sufficient contact area for forming the BS contact structure 122Bn on the BS surface 102b of the S / D region 102n1. If the width W1n of the base portion 101n is equal to the width W4n of the channel portion 106na, the BS contact structure 122Bn may not be able to form a reliable electrical connection on the BS surface 102b of the S / D region 102n1. In some embodiments, such as Figure 1H As shown, the base portion 101n can extend along the Y-axis on both sides of the channel portion 106na by distances D1 and D2. In some embodiments, the distances D1 and D2 can be substantially equal to each other and can be from about 2 nm to about 10 nm. Within these ranges of width W4n and distances D1 and D2, sufficient low power consumption can be achieved in the narrow active region 101n without compromising the reliability of the electrical connection between the BS contact structure 122Bn and the S / D region 102n1, as well as the manufacturing cost of the semiconductor device 100. In some embodiments, the thickness of the topmost channel portion 106na along the Z-axis can be less than the thickness of the lower channel portion 106na because the topmost channel portion 106na can be etched along the Z-axis during modification of the channel portion 106na along the Y-axis, as referenced below. Figure 11A and Figure 11C Detailed description.

[0041] refer to Figure 1J and Figure 1K In some embodiments, such as Figure 1JAs shown, the width W3w of the channel portion 106wb along the Y-axis can be substantially equal to the width W1w of the base portion 101w along the Y-axis, while the width W4w of the channel portion 106wa can be approximately 1 nm to approximately 2 nm smaller than the widths W3w of the channel portion 106wb and W1w of the base portion 101w. The difference between the width W4w of the channel portion 106wa and the width W1w of the base portion 101w may be due to etching of the exposed surface of the channel portion 106wa during the formation of the STI region 118w and / or the formation of the gate structure 108w. The difference between the width W4w of the channel portion 106wa and the width W1w of the base portion 101w can be smaller than the difference between the width W4n of the channel portion 106na and the width W1n of the base portion 101n (e.g., the sum of distances D1 and D2).

[0042] refer to Figure 1L , Figure 1M and Figure 1N In some embodiments, the nanostructured channel region 106w may have (i) widths W3w and W4w along the Y-axis that are greater than the widths W3n and W4n along the Y-axis of the nanostructured channel region 106n, and (ii) a thickness T1w along the Z-axis that is greater than the thicknesses T1n and T2n along the Z-axis of the nanostructured channel region 106n, to achieve higher voltage and / or higher drive current in the wide active region 100w, and lower power consumption and / or lower drain-induced barrier reduction (DIBL) in the narrow active region 100n. In some embodiments, such as Figure 1L As shown, the thickness T1n of the channel portion 106na can be less than the thickness T2n of the channel portion 106nb. In some embodiments, as shown in FIG. L, the nanostructured channel region 106n can have an I-shaped cross-sectional profile along the XZ plane.

[0043] refer to Figure 10 In some embodiments, the semiconductor device 100 may have another narrow active region electrically isolated from the narrow active region 100n by another isolation structure 130. Instead of a wide active area of ​​100W. Figure 10 It shows a narrow active region A top view of a 100n semiconductor device 100. Figure 1P The following is illustrated according to some embodiments. Figure 10 A cross-sectional view of the semiconductor device 100 with JJ lines. Unless otherwise stated, the discussion of the narrow active region 100n applies to the narrow active region. Unless otherwise stated, Figures 1A to 1P The discussion of elements with the same annotations applies to each other. In some embodiments, narrow active regions The widths W3n of the channel portions 106na and 106nb can be equal to each other, equal to the width W3w of the channel portion 106na of the narrow active region 100n, and equal to the width W1n of the base portion 101n. Narrow active region The width W3w of the channel portions 106na and 106nb can be greater than the width W4w of the channel portion 106na of the narrow active region 100n. In some embodiments, in addition to the wide active region 100w and the narrow active region 100n, a narrow active region may exist in the semiconductor device 100. .

[0044] refer to Figures 1A to 1I In some embodiments, gate structures 108w and 108n can be multilayer structures and can surround nanostructure channel regions 106w and 106n, respectively. Therefore, gate structures 108w and 108n can be referred to as "GAA structures," and semiconductor device 100 can be referred to as "GAA FET 100." In some embodiments, each of gate structures 108w and 108n may include (i) an interface oxide (IL) layer 108A disposed on nanostructure channel region 106, (ii) a high-k gate dielectric layer 108B disposed on IL layer 108A, and (iii) a conductive layer 108C disposed on high-k gate dielectric layer 108B. In some embodiments, IL layer 108A may include an oxide of the material of nanostructure channel region 106, such as SiO2 or SiGeO. x or germanium oxide (GeO) x In some embodiments, the high-k gate dielectric layer 108B may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), aluminum zirconium oxide (ZrAlO), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3).

[0045] In some embodiments, the conductive layer 108C may be a multilayer structure. For simplicity, the different layers of the conductive layer 108C are not shown. In some embodiments, the conductive layer 108C may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 108B and a gate metal fill layer disposed on the WFM layer. In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (Taj1C), aluminum-doped Ti, aluminum-doped TiN, aluminum-doped Ta, aluminum-doped TaN, or other suitable Al-based materials. In some embodiments, the WFM layer may include a Ti-based or Ta-based nitride or alloy that is substantially Al-free (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the gate metal filling layer may include suitable conductive materials such as W, Ti, Ag, Ru, Mo, Cu, Co, Al, Ir, Ni, metal alloys, and combinations thereof.

[0046] In some embodiments, gate structures 108w and 108n are electrically isolated from adjacent FS contact structures 122Fw and 122Fn by external spacers 110w and 110n, and portions of gate structures 108w and 108n surrounding nanostructure channel regions 106w and 106n are electrically isolated from adjacent S / D regions 102w and 102n by internal spacers 112w and 112n. In some embodiments, external spacer 110w extends along the sidewall of gate structure 108w and may be directly disposed on the topmost channel portion 106wb, and external spacer 110n extends along the sidewall of gate structure 108n and may be directly disposed on the topmost channel portion 106nb. External spacers 110w and 110n and internal spacers 112w and 112n may comprise materials similar to or different from each other. In some embodiments, the outer spacers 110w and 110n and the inner spacers 112w and 112n may comprise insulating materials such as SiO2, SiN, SiON, SiCO, SiCN, SiCON, and other suitable insulating materials. In some embodiments, the dielectric constant of the HK gate dielectric layer 108B may be greater than the dielectric constant of the outer spacers 110w and 110n. In some embodiments, the thickness of the HK gate dielectric layer 108B may be less than the thickness of the outer spacers 110w and 110n. In some embodiments, the S / D spacers 103w and 103n and the outer spacers 110w and 110n are portions of the same spacer material layer.

[0047] In some embodiments, FS contact structures 122Fw and 112Fn can be directly disposed on the FS surface 102f of S / D regions 102w and 102n to electrically connect S / D regions 102w and 102n to other components of the semiconductor device 100 and / or other active and / or passive devices (not shown) in the integrated circuit. In some embodiments, such as Figure 1C , Figure 1D , Figure 1E and Figure 1F As shown, the relative widths of FS contact structures 122Fw and 112Fn can depend on the relative widths of S / D regions 102w and 102n along the Y-axis. In some embodiments, the width of FS contact structure 122Fw along the Y-axis can be greater than the width of FS contact structure 122Fn along the Y-axis. In some embodiments, each of the FS contact structures 122Fw and 122Fn may include (i) a silicide layer 124F directly disposed on the FS surface 102f, (ii) a conductive layer 126F directly disposed on the silicide layer 124F, and (iii) an interface layer 128F directly disposed on the sidewalls of the conductive layer 126F and surrounding the conductive layer 126F. In some embodiments, the silicide layer 124F may have a curved profile. In some embodiments, as Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F As shown, the FS contact structure 122Fw can be surrounded by the ILD layer 116w, and the FS contact structure 122Fn can be surrounded by the ILD layer 116n. Figure 1B As shown, the width of the conductive layer 126F along the X-axis can be smaller than the width of the S / D regions 102w and 102n along the X-axis.

[0048] In some embodiments, the silicide layer 124F may include titanium silicide (Ti) for the n-type S / D regions 102w and 102n. x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), Zirconium silicide (Zr) x Si y ), Hafnium silicide (Hf) x Si y Scandium silicide (Sc) x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Siy ), Erbium silicide (Er x Si y ), Ytterbium silicide (Yb x Si y Europium silicide (Eu) x Si y ), Thorium silicide (Th) x Si y Other suitable metal silicide materials or combinations thereof. In some embodiments, the silicide layer 124F may include nickel silicide (Ni) for the p-type S / D regions 102w and 102n. x Si y ), cobalt silicide (Co) x Si y ), manganese silicide (Mn) x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe) x Si y Rhodium silicide (Rh) x Si y ), palladium silicide (Pd) x Si y Ruthenium silicide (Ru) x Si y Platinum silicide (Pt) x Si y ), Iridium silicide (Ir) x Si y Os(siliconium) silicide (Os) x Si y Other suitable metal silicide materials or combinations thereof. In some embodiments, the conductive layer 126F may include conductive materials such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and combinations thereof. In some embodiments, the conductivity of the conductive layer 126F may be greater than the conductivity of the S / D regions 102w and 102n.

[0049] In some embodiments, the interface layer 128F can prevent oxidation of the conductive layer 126F by preventing oxygen atoms from diffusing from adjacent structures to the conductive layer 126F. In some embodiments, the interface layer 128F may include a dielectric material such as silicon oxide (SiO2), SiN, SiON, SiCN, SiOCN, aluminum oxide (Al2O3), aluminum oxynitride (AlON), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), aluminum zirconium oxide (ZrAlO), zinc oxide (ZnO2), and other suitable dielectric materials. In some embodiments, the interface layer 128F may have a thickness of about 1.5 nm to about 4 nm. Within this thickness range, the interface layer 128F can sufficiently prevent oxidation of the conductive layer 126F without compromising the size and manufacturing cost of the semiconductor device 100.

[0050] In some embodiments, ESL 114w and ILD layer 116w can provide electrical isolation between adjacent FS contact structures 122Fw and between FS contact structure 122Fw and gate structure 108w. In some embodiments, ESL 114n and ILD layer 116n can provide electrical isolation between adjacent FS contact structures 122Fn and between FS contact structure 122Fn and gate structure 108n. In some embodiments, ESL 114w can be directly disposed on S / D region 102w, S / D spacer 103w and STI region 118w, and ESL 114n can be directly disposed on S / D region 102n, S / D spacer 103n and STI region 118n. In some embodiments, the portions of ILD layers 116w and 116n extending below S / D spacers 103w and 103n, respectively, may have curved cross-sectional profiles, and the portions of ESL layers 114w and 114n extending below S / D spacers 103w and 103n may have curved cross-sectional profiles, such as... Figure 1A , Figure 1C , Figure 1D , Figure 1E and Figure 1FAs shown, they follow the curved cross-sectional profile of the top surfaces of STI regions 118w and 118n. In some embodiments, ESL 114 and ILD layer 116 may provide electrical isolation between adjacent FS contact structures 122Fw. In some embodiments, ESL 114w, 114n and 114, ILD layers 116w, 116n and 116, and STI regions 118w and 118n may include dielectric materials such as SiO2, SiN, SiON, SiOC, SiCN, SiCON, and other suitable dielectric materials. In some embodiments, ILD layers 116w, 116n and 116 may include oxide materials, and ESL 114w, 114n and 114 may include nitride materials different from ILD layers 116w, 116n, and 116.

[0051] In some embodiments, BS contact structures 122Bw and 122Bn can be directly disposed on the BS surface 102b of the S / D regions 102w2 and 102n1. BS contact structures 122Bw and 122Bn can electrically connect the S / D regions 102w2 and 102n1 to a BS power rail (not shown) disposed on the BS ESL 114B. The BS power rail may include a metal wire (not shown) of ruthenium (Ru), copper (Cu), or other suitable metal for supplying power to the S / D regions 102w2 and 102n1 through the BS contact structures 122Bw and 122Bn. As discussed below, BS contact structures 122Bw and 122Bn are formed by respectively replacing portions of the base portions 101w and 101n, the first intermediate structures 104w and 104n, and the second intermediate structures 105w and 105n. The relative widths of the BS contact structures 122Bw and 122Bn can depend on the relative widths of the base portions 101w and 101n, the first intermediate structures 104w and 104n, and the second intermediate structures 105w and 105n along the Y-axis, such as... Figure 1C and Figure 1D As shown. In some embodiments, portion 122Bw1 of the BS contact structure 122Bw may be wider than portion 122Bw2 of the BS contact structure 122Bw (e.g., ...). Figure 1B and Figure 1C As shown), because the BS contact structure 1220Bw is formed in the contact opening 1422w with a non-uniform width (as shown). Figure 14A As shown below (refer to the reference below). Figure 14A and Figure 14B The discussion continues. Similarly, in some embodiments, portion 122Bn1 of the BS contact structure 122Bn may be wider than portion 122Bn2 of the BS contact structure 122Bn (e.g., ...). Figure 1B and Figure 1DAs shown), because the BS contact structure 122Bn is formed in the contact opening 1422n with a non-uniform width (as shown). Figure 14A and Figure 14B As shown below (refer to the reference below). Figure 14A and Figure 14B The discussion is as follows. In some embodiments, the width of the BS contact structure 122Bw along the Y-axis may be greater than the width of the BS contact structure 1220Bn along the Y-axis. In some embodiments, each of the BS contact structures 122Bw and 122Bn may include (i) a silicide layer 124B directly disposed on the BS surface 102b of the S / D regions 102w2 and 102n1, (ii) a conductive layer 126B directly disposed on the silicide layer 124B, and (iii) an interface layer 128B directly disposed on the sidewalls of the conductive layer 126B and surrounding the conductive layer 126B. Unless otherwise stated, the discussion of the materials and dimensions of the silicide layer 124F, the conductive layer 126F, and the interface layer 128F applies to the silicide layer 124B, the conductive layer 126B, and the interface layer 128B. In some embodiments, the silicide layer 124B may have a curved profile. Figure 1B , Figure 1C and Figure 1D As shown, the width of the conductive layer 126B along the X and Y axes can be equal to or greater than the widths of the S / D regions 102w and 102n along the Y and X axes. Figure 1B As shown, the sidewalls of the BS contact structures 122Bw and 122Bn extending along the Y-axis can contact the base portions 101w and 101n respectively, and as... Figure 1C and Figure 1D As shown, the sidewalls of the BS contact structures 122Bw and 122Bn extending along the X-axis can contact the STI regions 118w and 118n and / or BSESL114B.

[0052] In some embodiments, such as Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F As shown, the BS ESL 114B can be directly disposed on the BS surfaces of the base portions 101A and 101B and the BS surfaces of the STI regions 118w and 118n. In some embodiments, the BS ESL 114B can surround portions of the BS contact structures 122Bw and 112Bn extending below the STI regions 118w and 118n of the base portions 101w and 101n. In some embodiments, the BS surface of the BS ESL 114B can be substantially coplanar with the BS surfaces of the BS contact structures 122Bw and 122Bn, such as... Figure 1B , Figure 1C and Figure 1DAs shown. Figure 1A , Figure 1E and Figure 1F As shown, BSESL 114B does not contact the second interposers 105w and 105n, and is separated from them by substrate portions 101w and 101n. Unless otherwise stated, the discussion of the materials of ESL 114 applies to BS ESL 114B. In some embodiments, BS power rails (not shown) may be directly disposed on BS ESL 114B and BS contact structures 122Bw and 122Bn. In some embodiments, BS ESL 114B may be absent in semiconductor device 100 because it is removed after the formation of BS contact structures 122Bw and 122Bn. In the absence of BS ESL 114B, the BS surfaces of BS contact structures 122Bw and 122Bn may be substantially coplanar with the substrate structures 101w and 101n, the isolation structure 130, and the BS surfaces of STI regions 118w and 118n (not shown).

[0053] refer to Figure 1A , Figure 1B and Figure 1I In some embodiments, isolation structure 130 may be disposed between a wide active region 100w and a narrow active region 100n, and may electrically isolate the wide active region 100w and the narrow active region 100n from each other. Isolation structure 130 may extend vertically between ESL 114 and BS ESL 114B. The top surface of isolation structure 130 may contact the BS surface of ESL 114, and the BS surface of isolation structure 130 may contact the top surface of BS ESL 114B. The top surface of isolation structure 130 may be substantially coplanar with the top surfaces of gate structures 108w and 118n, external spacers 110w and 110n, ESL 114w and 114n, and ILD layers 116w and 116n. Figure 1A As shown, the BS surface of the isolation structure 130 can be substantially coplanar with the BS surfaces of the STI regions 118w and 118n. The sidewalls of the isolation structure 130, extending along the Y-axis and located below the S / D regions 102w and 102n, can be coplanar with the STI regions 118w and 118n (e.g., ...). Figure 1A (As shown) and the base portions 101w and 101n (as shown in Table 1B) are in contact. Figure 1A , Figure 1B and Figure 1IAs shown, the sidewalls of the isolation structure 130, extending along the Y-axis and located above the S / D regions 102w and 102n, can contact the outer spacers 110w and 110n, the inner spacers 112w and 112n, and the nanostructure layers 107w and 107n. In some embodiments, the isolation structure 130 may include an oxide-filled layer (not shown) and a nitride liner (not shown) surrounding the oxide-filled layer. In some embodiments, the oxide-filled layer may include SiO2 or a SiO2-based material (e.g., silicon oxycarbide), and the nitride liner may include a SiN material.

[0054] Figure 2 This is a flowchart of an example method 200 for manufacturing a semiconductor device 100 according to some embodiments, the semiconductor device 100 having Figures 1B to 1I The top view and cross-sectional view are shown. For illustrative purposes, references will be made to, such as... Figure 3 , Figure 4 , Figures 5A to 17A , Figures 5B to 17B and Figures 5C to 17C The example manufacturing process for manufacturing semiconductor device 100 is described below. Figure 2 The operation shown. Figure 3 and Figure 4 This is an isometric view of a semiconductor device 100 at various stages of its manufacturing process, according to some embodiments. Figures 5A to 17A It is according to some embodiments along Figure 1A A cross-sectional view of the semiconductor device 100 at various stages of its manufacturing process. Figures 5B to 17B It is according to some embodiments along Figure 1A Cross-sectional views of the semiconductor device 100 of line CC at various stages of its manufacturing process. Figures 5C to 17C It is according to some embodiments along Figure 1A The diagram shows cross-sectional views of the semiconductor device 100 at various stages of its fabrication. Depending on the specific application, operations may be performed in different sequences or not at all. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only a few other processes may be briefly described herein. Unless otherwise stated, Figures 1A to 1I , Figure 3 , Figure 4 , Figures 5A to 17A , Figures 5B to 17B and Figures 5C to 17C Discussions of elements with the same annotations are applicable to each other.

[0055] refer to Figure 2In operation 205, a substrate structure having a first substrate portion and a second substrate portion is formed on a substrate, and superlattice structures having a first superlattice portion and a second superlattice portion are formed on the first substrate portion and the second substrate portion, respectively. For example, as referenced... Figure 3 and Figure 4 The substrate structure 101, having substrate portions 101w and 101n, is formed on the substrate 301, and a superlattice structure 307 (also referred to as a "nanosheet stack 307") having superlattice portions 307w and 307n is formed on the substrate portions 101w and 101n, respectively. The superlattice structure 307 may include nanostructure layers 106 and sacrificial nanostructure layers 306 arranged in an alternating configuration. The superlattice portion 307w may include the nanostructure layer portion of the nanostructure layer 106. and the sacrificial nanostructure layer portion of sacrificial nanostructure layer 306 The superlattice portion 307n may include the nanostructure layer portion of the nanostructure layer 106. and the sacrificial nanostructure layer portion of sacrificial nanostructure layer 306 During subsequent processing, the nanostructured layers partially... and Nanostructured channel regions of 106w and 106n can be formed.

[0056] In some embodiments, the formation of the substrate structure 101 and the superlattice structure 307 may include (i) epitaxially growing alternating semiconductor layers on the substrate 301. and Stacked components, such as Figure 3 As shown, (ii) a photolithography process is used to fabricate a semiconductor layer. and (iii) A patterned mask layer 336 is formed on the stacked components, and (iii) the semiconductor layer not covered by the mask layer 336 is etched. and The stacked components and substrate 301 are used to form Figure 4 The structure is described above. In some embodiments, substrate 301 may be a semiconductor material, such as Si, Ge, SiGe, silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, substrate 301 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). Since substrate structure 101 is an etched portion of substrate 301, substrate structure 101 includes the material of substrate 301. Substrate structure 101 may have an elongated side extending along the X-axis. In some embodiments, the semiconductor layer... It may include Si, and a semiconductor layer It can include SiGe. Since the nanostructure layer 106 is a semiconductor layer. The etched portion, therefore the nanostructure layer 106 includes a semiconductor layer. The material. Similarly, since the sacrificial nanostructure layer 306 is a semiconductor layer. The etched portion thus sacrifices the nanostructure layer 306, which includes the semiconductor layer. The material. In some embodiments, the substrate portion 101w may be formed having a width W1w, and the superlattice portion 307w may be formed having a width W3w, the widths W1w and W3w being substantially equal to each other. In some embodiments, the substrate portion 101n may be formed having a width W1n, and the superlattice portion 307n may be formed having a width W3n, the widths W1n and W3n being substantially equal to each other and smaller than the widths W1w and W3w. In some embodiments, an STI region 118w may be formed after the formation of the superlattice structure 307 (in Figures 5A to 5C (not visible in the cross-sectional view) and 118n (as shown in the cross-sectional view) Figure 5B and Figure 5C As shown, in Figure 5A (Not visible in the cross-sectional view).

[0057] refer to Figure 2 In operation 210, a first polycrystalline silicon structure and a second polycrystalline silicon structure are formed on the first superlattice portion and the second superlattice portion, respectively, and a third polycrystalline silicon structure is formed in the transition region between the first superlattice portion and the second superlattice portion. For example, as referenced... Figures 5A to 5C The polycrystalline silicon structure 508w is formed on the superlattice portion 307w, the polycrystalline silicon structure 508n is formed on the superlattice portion 307n, and the polycrystalline silicon structure 507 is formed on the transition region 101t between the superlattice portions 307w and 307n and between the substrate portions 101w and 101n. The polycrystalline silicon structures 508w, 508n, and 507 are... Figure 5B It is not visible in the cross-sectional view, and the polycrystalline silicon structures 508w and 507 are in Figure 5C Not visible in the cross-sectional view. During subsequent processing, (i) portions of the polysilicon structure 507 and the superlattice structure 307 below the polysilicon structure 507 can be replaced with the isolation structure 130, and (ii) portions of the polysilicon structures 508w and 508n and the sacrificial nanostructure layer 306 below the polysilicon structures 508w and 508n can be replaced with the gate structures 108w and 108n in a gate replacement process. In some embodiments, silicon oxide layers 509w, 509n, and 509 can be deposited on the superlattice structure 307 prior to the formation of the polysilicon structures 508w, 508n, and 507.

[0058] refer to Figure 2In operation 215, external spacers, S / D spacers, and internal spacers are formed on the first superlattice portion and the second superlattice portion. For example, as referenced... Figures 5A to 5C and Figures 6A to 6C As described, external spacers 110w and 110n, S / D spacers 103w and 103n, and internal spacers 112w and 112n are formed on the superlattice portions 307w and 307n. The external spacers 110w and 110n and the internal spacers 112w and 112n are... Figure 6B and Figure 6C Not visible in the cross-sectional view. S / D spacers 103w and 103n are in Figure 6A and Figure 6C Not visible in the cross-sectional view. In some embodiments, the external spacers 110w and 110n and the S / D spacers 103w and 103n can be formed from the same spacer material layer (not shown) at different stages of selective dry etching of the spacer material layer. The spacer material layer may include SiO2, SiN, SiON, SiCO, SiCN, SiCON and other suitable insulating materials. In some embodiments, the formation of the external spacers 110w and 110n and the S / D spacers 103w and 103n may begin by depositing a substantially conformal spacer material layer (not shown) directly on the polycrystalline silicon structures 508w, 508n and 507, the superlattice structure 307 and the STI regions 118w and 118n. After depositing the spacer material layer, the external spacers 110w and 110n may be subjected to a first etching process, such as... Figure 5A As shown, a first etching process is performed on the spacer portion 503 on the sidewall surface of the superlattice structure 307, as follows. Figure 5B As shown.

[0059] A second etching process can be performed after the first etching process to selectively etch (i) portions of the spacer portion 503 to form the S / D spacer 103w (in Figures 6A to 6C (not visible in the cross-sectional view) and 103n (as shown in the figure) Figure 6B (as shown), and (ii) portions of the superlattice structure 307 and the substrate portions 101w and 101n to form S / D openings 602w and 602n, which extend to a distance D3 in the substrate portions 101w and 101n, as shown. Figure 6A and Figure 6B As shown. S / D openings 602w and 602n are in Figure 6CNot visible in the cross-sectional view. The formation of S / D openings 602w and 602n results in the formation of the following structures: (i) a nanostructure layer 106w (also referred to as "nanostructure channel region 106w") and a sacrificial nanostructure layer 306w beneath the polysilicon structure 508w, (ii) a nanostructure layer 606n and a sacrificial nanostructure layer 306n beneath the polysilicon structure 508n, and (iii) sacrificial nanostructure layers 607 and 608 beneath the polysilicon structure 507, which are replaced by isolation structure 130 in subsequent processing. In some embodiments, the width of S / D opening 602w along the Y-axis is greater than the width of S / D opening 602n along the Y-axis.

[0060] In some embodiments, during the second etching process, the top surfaces of the polysilicon structures 508w, 508n, and 507, as well as the top surfaces of the external spacers 110w and 110n, can be protected with a mask layer (not shown) formed after the first etching process. In some embodiments, the etching gas used in the second etching process can be selective for the STI regions 118w and 118n, and therefore, portions of the STI regions 118w and 118n can be etched to form grooves in the STI regions 118w and 118n. In some embodiments, after the second etching process, internal spacers 112w and 112n can be formed on the sidewall surfaces of the sacrificial nanostructure layers 306w, 306n, and 608, such as... Figure 6A As shown. Internal spacers 112w and 112n are in Figure 6B and Figure 6C It is not visible in the cross-sectional view.

[0061] refer to Figure 2 In operation 220, a first intermediate structure and a second intermediate structure are formed in the first base portion and the second base portion, and an S / D region is formed on the first intermediate structure. For example, as referenced... Figures 7A to 7C and Figures 8A to 8C The second intermediate structures 105w and 105n and the first intermediate structures 104w and 104n are formed in the base portions 101w and 101n, and the S / D regions 102w and 102n are formed on the first intermediate structures 104w and 104n. The second intermediate structures 105w and 105n, the first intermediate structures 104w and 104n, and the S / D regions 102w and 102n are... Figure 8C Not visible in the cross-sectional view. In some embodiments, the formation of the second intermediate structures 105w and 105n may include the following sequential operations: (i) etching the base portions 101w and 101n to extend the S / D openings 602w and 602n to a distance D4 in the base portions 101w and 101n, such as Figure 7A and Figure 7B As shown (S / D openings 602w and 602n in) Figure 7C(not visible in the cross-sectional view), and (ii) the material of the second intermediate structure 105w and 105n epitaxially grown on the exposed surfaces of the base portions 101w and 101n in the S / D openings 602w and 602n, such as Figure 8A and Figure 8B As shown. In some embodiments, the second intermediate structures 105w and 105n may be formed having the same semiconductor material (e.g., Si) as the substrate portions 101w and 101n, or may be formed having a different semiconductor material (e.g., SiGe) than the substrate portions 101w and 101n.

[0062] In some embodiments, the formation of the first intermediate structures 104w and 104n may include the following sequential operations: (i) depositing material (not shown) of the first intermediate structures 104w and 104n on the structure formed after the growth of the second intermediate structures 105w and 105n using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable dielectric material deposition process; and (ii) performing an etching process on the deposited material to form the first intermediate structures 104w and 104n, such as... Figure 8A and Figure 8B As shown. After forming the first intermediate structures 104w and 104n, the S / D regions 102w and 102n can be formed. In some embodiments, the formation of the S / D regions 102w and 102n may include epitaxially growing semiconductor material on the exposed surfaces of the nanostructure layers 106w, 606n, and 607 facing the S / D openings 602w and 602n. In some embodiments, ESL 114w and 114n can be formed after the formation of the S / D regions 102w and 102n. Figure 8A and Figure 8B As shown, after the formation of ESL 114w and 114n, ILD layers 116w and 116n can be deposited on ESL 114w and 114n. ESL 114w and 114n, as well as ILD layers 116w and 116n, are... Figure 8C It is not visible in the cross-sectional view.

[0063] refer to Figure 2 In operation 225, an isolation structure is formed in the transition region. For example, as referenced... Figures 9A to 9C As described above, an isolation structure 130 is formed extending through the transition region 101t. The isolation structure 130 is in... Figure 9B and Figure 9CThe cross-sectional view is not visible. The formation of the isolation structure 130 may include the following sequential operations: (i) forming an isolation opening (not shown) by removing portions of the polysilicon structure 507 and oxide layer 509 and nanostructure layers 607 and 608, as well as the substrate portions 101w and 101n below the polysilicon structure 507; (ii) depositing a dielectric nitride liner (not shown) along the sidewalls of the isolation opening and the external spacers 110w and 110n, ESL 114w and 114n, IDL layer 116w and 116n and the top surface of the polysilicon structure 508w and 508n; (iii) depositing a dielectric oxide filling layer (not shown) on the dielectric nitride liner to fill the isolation opening; and (iv) performing a chemical mechanical polishing (CMP) process on the dielectric nitride liner and the dielectric oxide filling layer to make the top surface of the dielectric nitride liner and the dielectric oxide filling layer flush with the external spacers 110w and 110n, ESL 114w and 114n, and the substrate portions 101w and 101n below the polysilicon structure 507; (ii) depositing a dielectric nitride liner (not shown) along the sidewalls of the isolation opening and the external spacers 110w and 110n, ESL 114w and 114n, IDL layer 116w and 116n and the top surface of the polysilicon structure 508w and 508n; (iii) depositing a dielectric oxide filling layer (not shown) on the dielectric nitride liner to fill the isolation opening; and (iv) performing a chemical mechanical polishing (CMP) process on the dielectric nitride liner and the dielectric oxide filling layer so that the top surface of the dielectric nitride liner and the dielectric oxide filling layer is flush with the external spacers 110w and 110n The top surfaces of 114w and 114n, IDL layers 116w and 116n, and polysilicon structures 508w and 508n are essentially coplanar, as shown below. Figure 9A As shown.

[0064] refer to Figure 2 In operation 230, the nanostructure layer of the second superlattice portion is modified. For example, as referenced... Figures 10A to 10C and Figures 11A to 11C The nanostructure layer 606n of the superlattice portion 307n is modified (e.g., trimmed) to form the nanostructure channel region 106n. In some embodiments, the modification (e.g., trimming) of the nanostructure layer 606n may include (i) in Figure 9A and Figure 9B A patterned mask layer 1040 with openings 1041 is formed in the structure, such as Figure 10A and Figure 10B As shown, (ii) the polysilicon structure 508n and oxide layer 509n are removed to form opening 1042, as... Figure 10A and Figure 10C As shown, (iii) an isotropic wet etching process (also known as a “trimming process”) is performed on the portion of the nanostructure layer 606n not covered by the external spacer 110n and the sacrificial nanostructure layer 306n to laterally etch the portion of the nanostructure layer 606n and the sacrificial nanostructure layer 306n along the Y-axis by distances D1 and D2, as shown. Figure 11C As shown, and (iv) removing the mask layer 1040. Lateral etching modifies (e.g., reduces and trims) the width W3n of the nanostructure layer 606n not covered by the external spacer 110n to a width W4n, as... Figure 11C cross-sectional view and Figure 1I and Figure 10 The top view is shown. Figure 10CThe dashed arrows in the image indicate the etching directions of the nanostructure layer 606n and the sacrificial nanostructure layer 306n during the isotropic wet etching process. (See image for details.) Figure 10C As shown, during the isotropic wet etching process, in addition to lateral etching, the topmost nanostructure layer 606n can be etched vertically, while the other nanostructure layers 606 and the sacrificial nanostructure layer 306n are not vertically etched during the isotropic wet etching process. Therefore, the thickness of the channel portion 106na of the topmost nanostructure channel region 106n can be less than the thickness of the channel portions 106na of the other nanostructure channel regions 106n. When an etching process (also known as a "trimming process") is performed on a portion of the nanostructure layer 606n, the nanostructure channel region 106w in the wide active region 100w is not etched or trimmed because the wide active region 100w is protected by a patterned mask layer 1040 during the etching process, as shown in the image. Figure 10A As shown. In some embodiments, since the sidewalls of the substrate portion 101n are covered by the STI region 118n, the substrate portion 101n is not etched during the isotropic wet etching process.

[0065] refer to Figure 2 In operation 235, a gate structure is formed around a nanostructure layer surrounding the first superlattice portion and the second superlattice portion. For example, as referenced... Figures 12A to 12C and Figures 13A to 13C As described above, gate structures 108w and 108n are formed around the nanostructure channel regions 106w and 106n. The gate structures 108w and 108n are in... Figure 13B Not visible in the cross-sectional view. In some embodiments, the formation of gate structures 108w and 108n may include the following sequential operations: (i) from Figure 11A and Figure 11C The polysilicon structure 508w, oxide layer 509w, and sacrificial nanostructure layers 306w and 306n are removed to form gate opening 1244, as shown. Figure 12A and Figure 12C As shown; (ii) an IL layer 108A is formed in the gate opening 1244, as shown. Figure 13A and Figure 13C As shown, (iii) an HK dielectric layer 108B is deposited on dielectric layer 108A, as follows: Figure 13A and Figure 13C As shown, and (iv) depositing a conductive layer 108C on the HK dielectric layer 108B, as Figure 13A and Figure 13C As shown. Figures 13A to 13CAs shown, after forming the gate structures 108w and 108n, ESL 114 can be deposited on the gate structures 108w and 108n, the external spacers 110w and 110n, the ESL 114w and 114n, and the ILD layers 116w and 116n. Figures 13A to 13C As shown, ILD layer 116 can be deposited after ESL 114 deposition.

[0066] refer to Figure 2 In operation 240, an FS contact structure is formed on the S / D region. For example, as referenced... Figures 13A to 13C The FS contact structures 122Fw and 112Fn are formed on the FS surface 102f of the S / D regions 102w and 102n. The FS contact structures 122Fw and 122Fn are... Figure 13C Not visible in the cross-sectional view. In some embodiments, the formation of FS contact structures 122Fw and 122Fn may include the following sequential operations: (i) forming contact openings (not shown) by etching ILD layers 116, 116w and 116n and ESL 114, 114w and 114n from the FS surface 102f of the S / D regions 102w and 102n; (ii) forming an interface layer 128F along the sidewalls of the contact openings, as shown in the figure. Figure 13A and Figure 13B As shown, (iii) a silicide layer 124F is formed on the surfaces of the S / D regions 102w and 102n in the contact opening, as... Figure 13A and Figure 13B As shown; (iv) a conductive layer 126F is deposited on the silicide layer 124F to fill the contact opening, as shown. Figure 13A and Figure 13B As shown, and (v) performing a CMP process to make the top surfaces of conductive layer 126F and ILD layer 116 substantially coplanar, as Figure 13A and Figure 13B As shown. In some embodiments, after the formation of FS contact structures 122Fw and 122Fn, via structures (not shown) may be formed on the FS contact structures 122Fw and 122Fn, and interconnect structures (not shown) may be formed on the via structures. In some embodiments, a carrier substrate (not shown) may be bonded to the interconnect structures before performing operation 245.

[0067] refer to Figure 2 In operation 245, a BS contact structure is formed on the S / D region. For example, as referenced... Figures 14A to 14C and Figures 15A to 15C The BS contact structures 122Bw and 122Bn are formed on the BS surfaces of the S / D regions 102w2 and 102n1. The BS contact structures 122Bw and 122Bn are... Figure 15CNot visible in the cross-sectional view. In some embodiments, the formation of BS contact structures 122Bw and 122Bn may include the following sequential operations: (i) performing a CMP process on the BS surface of substrate 301 to remove substrate 301 and expose the substrate portions 101w and 101n, STI regions 118w and 118n, and the BS surface of the isolation structure 130; (ii) depositing BS ESL 114B on the BS surfaces of the substrate portions 101w and 101n, the isolation structure 130, and the STI regions 118w and 118n, as shown in the figure. Figures 14A to 14C and Figure 13B As shown, (iii) the first intermediate structures 104w and 104n, the second intermediate structures 105w and 105n, and portions of the BS ESL 114B and the substrate portions 101w and 101n located below the S / D regions 102w2 and 102n1 are etched to form contact openings 1422w and 1422n (as shown). Figure 14A and Figure 14B (iv) As shown by the dashed lines in the diagram, an interface layer 128B is deposited along the sidewalls of the contact openings 1422w and 1422n and on the BS surface of the S / D regions 102w2 and 102n1 with BS ESL 114B (not shown), and (v) the horizontal portion of the interface layer 128B is etched to form as shown in the diagram. Figure 15A and Figure 15B As shown, interface layer 128B, (vi) forms a silicide layer 124B on the exposed BS surfaces of S / D regions 102w2 and 102n1, as... Figure 15A and Figure 15B As shown, (vii) a conductive layer 126B is deposited to fill the contact opening, and (viii) a CMP process is performed to make the BS surfaces of BS ESL 114B, interface layer 128B, and conductive layer 126B substantially coplanar with each other, as... Figure 15A and Figure 15B As shown.

[0068] In some embodiments, since the openings 1422w1 and 1422n1 are formed by a first etching process different from the second etching process used to form the openings 1422w2 and 1422n2, the openings 1422w1 and 1422n1 of the contact openings 1422w and 1422n can be wider than the openings 1422w2 and 1422n2 of the contact openings 1422w and 1422n. The first etching process may use a first etchant that has higher etch selectivity for the BS ESL 114B and the substrate portions 101w and 101n than for the first intermediate structures 104w and 104n and the second intermediate structures 105w and 105n beneath the S / D regions 102w2 and 102n2. The second etching process may use a second etchant that exhibits higher etch selectivity for the first intermediate structures 104w and 104n and the second intermediate structures 105w and 105n than for the substrate portion 101w surrounding the second intermediate structure 105w and the substrate portion 101n surrounding the second intermediate structure 105n. As a result, during the second etching process, the substrate portions 101w and 101n surrounding the second intermediate structures 105w and 105n may not be etched, and the widths of the opening portions 1422w2 and 1422n2 depend on the widths of the second intermediate structures 105w and 105n. In some embodiments, while the substrate portions 101w and 101n and the second intermediate structures 105w and 105n may have Si or a Si substrate, the epitaxially grown Si or Si substrate of the second intermediate structures 105w and 105b may have a higher crystal structure than the Si or Si substrate of the substrate portions 101w and 101n. As a result, the etching selectivity of the substrate portions 101w and 101n differs from that of the second intermediate structures 105w and 105n for the first and second etchants. In some embodiments, the opening portions 1422w1 and 1422n1 may have tapered sidewalls because the etch selectivity of BS ESL 114B to the first etchant is higher than that of the substrate portions 101w and 101n to the first etchant, and because the etch selectivity of the substrate portions 101w and 101n to the first etchant is higher than that of the second intermediate structures 105w and 105n to the first etchant. As a result, during the first etching process, BS ESL 114B is etched at a higher etch rate than the substrate portions 101w and 101n, and the substrate portions 101w and 101n are etched at a higher etch rate than the second intermediate structures 105w and 105n.

[0069] In some embodiments, after the formation of BS contact structures 122Bw and 122Bn, BS power rails (not shown) can be formed on BS ESL 114B and BS contact structures 122Bw and 122Bn.

[0070] In some embodiments, the following references may be made: Figures 16A to 16C and Figures 17A to 17C Instead Figures 10A to 10C and Figures 11A to 11C The execution operation 230 is used to form a... Figures 1L to 1N The cross-sectional view of semiconductor device 100.

[0071] refer to Figure 2 In operation 230, the nanostructure layer of the second superlattice portion is modified. For example, as referenced... Figures 16A to 16C and Figures 17A to 17C The nanostructure layer 606n of the superlattice portion 307n is modified to form the nanostructure channel region 106n. In some embodiments, the modification of the nanostructure layer 606n may include (i) in Figure 9A and Figure 9B A patterned mask layer 1040 with openings 1041 is formed in the structure, such as Figure 16A and Figure 16B As shown, (ii) the polycrystalline silicon structure 508n, oxide layer 509n, and sacrificial nanostructure layer 306n are removed to form opening 1642, as... Figure 16A and Figure 16C As shown, (iii) an isotropic wet etching process is performed on the portion of the nanostructure layer 606n not covered by the external spacer 110n to etch laterally along the Y-axis at distances D1 and D2, and perpendicularly along the Z-axis at distances D5 and D6, as shown. Figure 17A and Figure 17C As shown, and (iv) removing mask layer 1040. Figure 16C The dashed arrows in the diagram indicate the etching direction of the nanostructure layer 606n during the isotropic wet etching process. Lateral etching modifies (e.g., reduces) the width W3n of the nanostructure layer 606n not covered by the external spacer 110n to a width W4n, as shown. Figure 17C As shown. Vertical etching modifies (e.g., reduces) the thickness T1 of the nanostructure layer 606n not covered by the external spacer 110n to a thickness T1n, as... Figure 17A and Figure 17CAs shown. In some embodiments, distances D1, D2, D5, and D6 can be from about 2 nm to about 10 nm, and distances D1, D2, D5, and D6 can be substantially equal to each other when the etch rates of lateral and vertical etching are substantially equal to each other. In some embodiments, when the crystal orientation of the sidewalls of the nanostructure layer 606n (e.g., (110) crystal orientation) is different from the crystal orientation of the top and bottom surfaces of the nanostructure layer 606n (e.g., (100) crystal orientation), the etch rate of lateral etching can be greater than the etch rate of vertical etching. As a result, distances D1 and D2 can be greater than distances D5 and D6.

[0072] This disclosure provides example semiconductor devices (e.g., semiconductor device 100) with active regions of different widths and example methods of manufacturing semiconductor devices (e.g., method 200), wherein there is a reliable connection between BS contact structures (e.g., BS contact structures 122Bw and 122Bn) and S / D regions (e.g., S / D regions 102w2 and 102n1) in the active regions. Active regions of different widths can provide different device characteristics (e.g., drive current, power consumption, device speed) in different regions of the semiconductor device. In some embodiments, the semiconductor device may have a wide active region (e.g., wide active region 100w) and a narrow active region (e.g., narrow active region 100n) separated by an isolation structure (e.g., isolation structure 130) extending through a substrate structure having a first substrate portion and a second substrate portion (e.g., substrate portions 101w and 102n). The wide active region may include a first S / D region (e.g., S / D region 102w) and a first nanostructured channel region (e.g., nanostructured channel region 106w) disposed on a first substrate portion. The narrow active region may include a second S / D region (e.g., S / D region 102n) and a second nanostructured channel region (e.g., nanostructured channel region 106n) disposed on a second substrate portion. The widths of the first substrate portion, the first S / D region, and the first nanostructured channel region (e.g., W1w, W2w, and W3w) may be wider than the widths of the second substrate portion, the second S / D region, and the second nanostructured channel region (e.g., W1n, W2n, and W4n). In some embodiments, the first nanostructured channel region in the wide active region may achieve a higher drive current than the second nanostructured channel region in the narrow active region, while the second nanostructured channel region may achieve lower power consumption than the first nanostructured channel region.

[0073] In some embodiments, the second nanostructure channel region may be formed with a width of less than or equal to about 20 nm (e.g., about 5 nm to about 20 nm), less than or equal to about 30 nm (e.g., about 5 nm to about 30 nm), or less than or equal to 35 nm (e.g., about 5 nm to about 35 nm) (e.g., W4n) to achieve low power consumption. A second substrate portion located below the second nanostructure channel region and the second S / D region may be formed with a width larger than the width of the second nanostructure channel region (e.g., about 10 nm to about 40 nm). By using a second substrate portion wider than the second nanostructure channel region, a second S / D region with sufficient width can be grown on the second substrate portion to provide sufficient contact area for forming contact structures on the BS surface of the second S / D region. As a result, the electrical connection between the contact structure and the second S / D region in the narrow active region can be more reliable compared to semiconductor devices with equal widths of the second substrate region and the second nanostructure channel region in the narrow active region.

[0074] In some embodiments, the semiconductor device includes: a first substrate portion having a first width along a first direction; a second substrate portion having a second width along the first direction; a first source / drain region and a second source / drain region respectively disposed on the first substrate portion and the second substrate portion; a first nanostructure channel region having a third width along the first direction and disposed on the first substrate portion; a second nanostructure channel region having a fourth width along the first direction and disposed on the second substrate portion; a first contact structure disposed on the front surface of the first source / drain region; a second contact structure having a fifth width along the first direction and disposed on the back surface of the first source / drain region; and a third contact structure having a sixth width along the first direction and disposed on the back surface of the second source / drain region. The fourth width is smaller than the second width, and the sixth width is smaller than the fifth width. Along the cross-section, the thickness of the first source / drain region is different from the width of the first source / drain region, and the first contact structure has a silicide layer with a curved profile.

[0075] In some embodiments, the second width of the second base portion is smaller than the first width of the first base portion.

[0076] In some embodiments, the vertical dimension of the second nanostructure channel region is smaller than the vertical dimension of the first nanostructure channel region.

[0077] In some embodiments, the semiconductor device further includes: a gate structure surrounding a first channel portion of the second nanostructure channel region; and a spacer surrounding a second channel portion of the second nanostructure channel region, wherein the vertical dimension of the first channel portion is smaller than the vertical dimension of the second channel portion.

[0078] In some embodiments, the first channel portion includes a fourth width, which is smaller than the width of the second channel portion along the first direction.

[0079] In some embodiments, the first nanostructure channel region includes a rectangular cross-sectional profile along a vertical cross-section; and wherein the second nanostructure channel region includes an I-shaped cross-sectional profile along the vertical cross-section.

[0080] In some embodiments, the first nanostructure channel region includes a rectangular cross-sectional profile along a horizontal cross-section; and wherein the second nanostructure channel region includes an I-shaped cross-sectional profile along the horizontal cross-section.

[0081] In some embodiments, the second contact structure and the third contact structure include sidewalls having a stepped cross-sectional profile.

[0082] In some embodiments, the semiconductor device further includes a deep isolation structure disposed between the first substrate portion and the second substrate portion and between the first source / drain region and the second source / drain region, wherein the sidewalls of the deep isolation structure are in contact with the first substrate portion and the second substrate portion.

[0083] In some embodiments, the semiconductor device further includes a dielectric layer disposed on the back surfaces of the first substrate portion and the second substrate portion, wherein the dielectric layer surrounds portions of the first contact structure and the second contact structure extending beneath the first substrate portion and the second substrate portion.

[0084] In some embodiments, a method includes: forming a superlattice structure comprising a first nanostructure layer, a second nanostructure layer, and a sacrificial nanostructure layer on a substrate structure; forming a polycrystalline silicon structure on the superlattice structure; epitaxially growing an intermediate structure in the substrate structure, wherein the intermediate structure is adjacent to the superlattice structure; forming source / drain regions on the intermediate structure; removing the polycrystalline silicon structure to expose the top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; performing an etching process on the exposed top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; and replacing the polycrystalline silicon structure and the sacrificial nanostructure layer with a gate structure comprising a gate dielectric layer and a gate metal layer. The first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer are arranged in an alternating configuration. Along a cross-section, the thickness of the source / drain regions is different from the width of the source / drain regions. The gate metal layer comprises a titanium-based material.

[0085] In some embodiments, a method of forming a semiconductor device includes: forming a superlattice structure on a substrate structure, the superlattice structure including a first nanostructure layer, a second nanostructure layer, and a sacrificial nanostructure layer, wherein the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer are arranged alternately; forming a polycrystalline silicon structure on the superlattice structure; forming source / drain regions on the substrate structure, wherein, along a cross-section, the thickness of the source / drain regions is different from the width of the source / drain regions; removing the polycrystalline silicon structure to expose the top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; performing a trimming process on the exposed top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; and replacing the polycrystalline silicon structure and the sacrificial nanostructure layer with a gate structure including a gate dielectric layer and a gate metal layer, wherein the gate metal layer comprises a titanium-based material.

[0086] In some embodiments, performing the trimming process includes performing an isotropic wet etching process on the exposed top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer.

[0087] In some embodiments, the method further includes: etching a portion of the substrate structure below the source / drain regions; and forming a contact structure on the back side of the source / drain regions.

[0088] In some embodiments, the method further includes: epitaxially growing an intermediate structure in the substrate structure prior to forming the source / drain regions, wherein the intermediate structure is adjacent to the superlattice structure; and depositing a dielectric layer on the intermediate structure prior to forming the source / drain regions.

[0089] In some embodiments, performing the trimming process includes: reducing the thickness of the first nanostructure layer without reducing the thickness of the second nanostructure layer and the sacrificial nanostructure layer; and reducing the width of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer.

[0090] In some embodiments, epitaxial growth of the intermediate structure includes epitaxial growth of an undoped semiconductor layer.

[0091] In some embodiments, a method includes: forming a substrate structure on a substrate having a first substrate portion and a second substrate portion having widths different from each other along a first direction; and forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer. The nanostructure layer includes a first nanostructure layer portion having a first width along the first direction and a second nanostructure layer portion having a second width along the first direction. The second width is smaller than the first width. The method further includes forming a top surface with a curved profile and an isolation region surrounding the superlattice structure; forming a first polysilicon structure and a second polysilicon structure on the first and second nanostructure layer portions, respectively; forming spacers along the sidewalls of the first and second polysilicon structures; depositing a mask layer on the first polysilicon structure; removing the second polysilicon structure to expose the second nanostructure layer portion; modifying the dimensions of the second nanostructure layer portion; and forming a gate structure surrounding the modified second nanostructure layer portion. The thickness of the gate dielectric layer of the gate structure is smaller than the thickness of the spacer.

[0092] In some embodiments, modifying the dimensions of the second nanostructure layer portion includes performing isotropic wet etching on the second nanostructure layer portion.

[0093] In some embodiments, modifying the size of the second nanostructure layer portion includes reducing the second width to a third width; and further includes reducing the width of the sacrificial nanostructure layer during the modification of the size of the second nanostructure layer portion.

[0094] In some embodiments, modifying the dimensions of the second nanostructure layer portion includes reducing the thickness of the second nanostructure layer portion.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: The first base portion has a first width along a first direction; The second base portion has a second width along the first direction; A first source / drain region and a second source / drain region are respectively disposed on the first substrate portion and the second substrate portion, wherein, along the cross-section, the thickness of the first source / drain region is different from the width of the first source / drain region; A first nanostructure channel region having a third width along the first direction and disposed on the first substrate portion; A second nanostructured channel region having a fourth width along the first direction and disposed on the second substrate portion, wherein the fourth width is smaller than the second width; A first contact structure is disposed on the front surface of the first source / drain region, wherein the first contact structure includes a silicide layer with a curved profile. A second contact structure, the second contact structure having a fifth width along the first direction and disposed on the back surface of the first source / drain region; and A third contact structure having a sixth width along the first direction and disposed on the back surface of the second source / drain region, wherein the sixth width is smaller than the fifth width.

2. The semiconductor device according to claim 1, wherein, The second width of the second base portion is smaller than the first width of the first base portion.

3. The semiconductor device according to claim 1, wherein, The vertical dimension of the second nanostructure channel region is smaller than the vertical dimension of the first nanostructure channel region.

4. The semiconductor device according to claim 1, further comprising: A gate structure surrounding a first channel portion of the second nanostructure channel region; as well as A spacer surrounding a second channel portion of the second nanostructure channel region, wherein the vertical dimension of the first channel portion is smaller than the vertical dimension of the second channel portion.

5. The semiconductor device according to claim 4, wherein, The first channel portion includes a fourth width, which is smaller than the width of the second channel portion along the first direction.

6. The semiconductor device according to claim 1, wherein, The first nanostructured channel region includes a rectangular cross-sectional profile along a vertical cross-section; and The second nanostructure channel region includes an I-shaped cross-sectional profile along the vertical cross-section.

7. The semiconductor device according to claim 1, wherein, The first nanostructured channel region includes a rectangular cross-sectional profile along a horizontal cross-section; and The second nanostructure channel region includes an I-shaped cross-sectional profile along the horizontal cross-section.

8. The semiconductor device according to claim 1, wherein, The second contact structure and the third contact structure include sidewalls with stepped cross-sectional profiles.

9. A method for forming a semiconductor device, comprising: A superlattice structure is formed on a substrate structure, the superlattice structure comprising a first nanostructure layer, a second nanostructure layer, and a sacrificial nanostructure layer, wherein the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer are arranged alternately. A polycrystalline silicon structure is formed on the superlattice structure; A source / drain region is formed on the substrate structure, wherein, along the cross-section, the thickness of the source / drain region is different from the width of the source / drain region; Remove the polycrystalline silicon structure to expose the top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; A trimming process is performed on the exposed top surface of the first nanostructure layer and the sidewalls of the first nanostructure layer, the second nanostructure layer, and the sacrificial nanostructure layer; and The polysilicon structure and the sacrificial nanostructure layer are replaced with a gate structure comprising a gate dielectric layer and a gate metal layer, wherein the gate metal layer comprises a titanium-based material.

10. A method of forming a semiconductor device, comprising: A substrate structure having a first substrate portion and a second substrate portion is formed on a substrate, the first substrate portion and the second substrate portion having widths along a first direction and different from each other; A superlattice structure is formed, the superlattice structure comprising a nanostructure layer and a sacrificial nanostructure layer, wherein the nanostructure layer comprises a first nanostructure layer portion having a first width along the first direction and a second nanostructure layer portion having a second width along the first direction, wherein the second width is smaller than the first width; An isolation region is formed, the isolation region including a top surface with a curved profile and surrounding the superlattice structure; A first polycrystalline silicon structure and a second polycrystalline silicon structure are formed on the first nanostructure layer portion and the second nanostructure layer portion, respectively. Spacers are formed along the sidewalls of the first polysilicon structure and the second polysilicon structure; A mask layer is deposited on the first polysilicon structure; Remove the second polycrystalline silicon structure to expose a portion of the second nanostructure layer; Modify the dimensions of the second nanostructure layer portion; and A gate structure is formed around the modified second nanostructure layer portion, wherein the thickness of the gate dielectric layer of the gate structure is less than the thickness of the spacer.

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