A silicon carbide gate source diode integrated sgt device and method of manufacturing the same

Abstract

This invention discloses an integrated silicon carbide gate-source diode (SGT) device and its manufacturing method. By using a PN junction depletion layer instead of an interlayer oxide layer, the original polysilicon gate-oxide-polysilicon separated gate structure within the trench is transformed into a PIN diode structure of the same thickness: an N-type polysilicon gate-low-doped N-type silicon carbide-P-type silicon carbide separated gate. This structure allows the SGT device to improve short-circuit withstand capability during short-circuit withstand tests by utilizing the positive temperature characteristic of the gate-source diode's reverse current. When a short circuit occurs, the local temperature rise leads to an increase in the gate-source leakage current of the integrated PIN diode. This increased leakage current automatically reduces the gate voltage using the gate resistance, thus improving its short-circuit withstand capability. Furthermore, simulation results show that the forward conduction and withstand voltage characteristics of the replaced structure are essentially consistent with the conventional structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, specifically to an SGT device integrating a silicon carbide gate-source diode and its manufacturing method. Background Technology

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs), as core switching devices in power electronic systems, have long been subject to performance optimization revolving around the trade-off between on-resistance and switching losses. Split-gate trench transistors (SGTs), by introducing a unique shielded gate structure, generate a lateral electric field component within the drift region, effectively decoupling the strong correlation between on-resistance and gate-drain charge. This achieves a superior trade-off between on-resistance and switching performance that is difficult to attain with traditional device structures. With this significant advantage, SGTs have become the mainstream technology in the low-to-medium voltage power MOSFET field, and with the continuous maturation of silicon carbide (SiC) materials and processes, they are gradually expanding into high-voltage applications, demonstrating increasingly broad application prospects.

[0003] However, in practical power conversion systems, fault conditions such as load short circuits are difficult to completely avoid. At the moment of a short circuit, devices must simultaneously withstand surge currents several times their rated value and high bus voltages. The intense electrothermal stress within a very short time poses a severe test to the reliability of the devices, making short-circuit withstand capability a key indicator for evaluating the safety and robustness of power devices. While optimizing normal performance, the shielding gate structure of SGTs also alters the internal electric field distribution, carrier transport behavior, and temperature field evolution under short-circuit conditions, making the failure mechanism during short circuits more complex and presenting new physical limitations to improving short-circuit withstand performance. Summary of the Invention

[0004] The purpose of this invention is to provide an SGT device with integrated silicon carbide gate-source diode, comprising: a substrate, an epitaxial layer, a doped region, a gate trench region, a source metal layer, and a drain metal layer.

[0005] The epitaxial layer is located on the substrate.

[0006] The doped region is located in the epitaxial layer.

[0007] The gate trench region is located at the center of the epitaxial layer.

[0008] The source metal layer is located on the top layer of the device.

[0009] The drain metal layer is located below the substrate.

[0010] Furthermore, the doped region includes a P-type well region, a P-type source region, and an N-type source region.

[0011] Furthermore, the sidewalls of the P-type well region are in contact with the sidewalls of the P-type source region.

[0012] The N-type source region is located above the P-type source region and is in contact with the P-type well region.

[0013] Furthermore, the gate trench region is composed of an integrated gate-source diode encapsulated by an oxide layer.

[0014] Furthermore, the gate-source diode includes an N-type polycrystalline silicon carbide gate, a lightly doped N-type silicon carbide, and a P-type silicon carbide split gate.

[0015] Furthermore, the lightly doped N-type silicon carbide is located above the P-type silicon carbide detached gate.

[0016] The N-type polycrystalline silicon carbide gate is located on a lightly doped N-type silicon carbide.

[0017] Furthermore, the thickness of the lightly doped N-type silicon carbide ranges from 0.15 μm to 1.0 μm, with a concentration range of [missing information]. .

[0018] Furthermore, the thickness of the p-type silicon carbide separation gate ranges from 0.1 μm to 1.0 μm, with a concentration range of [missing information]. .

[0019] A method for manufacturing the SGT device, comprising the steps of:

[0020] Step 1, providing a substrate having a front side and a back side disposed opposite to each other;

[0021] Step 2: Fabricate an epitaxial layer on the front side of the substrate;

[0022] Step 3: Etch trenches in the epitaxial layer and form an oxide layer inside the trenches by thermo-oxidative growth and deposition;

[0023] Step 4: P-type silicon carbide and N-type silicon carbide are deposited in stages and etched to form a P-type silicon carbide detached gate and a lightly doped N-type silicon carbide structure in the lower part of the trench.

[0024] Step 5: An oxide layer is formed by combining thermal oxygen growth and deposition, and then dry etching is performed to selectively remove the oxide layer above the lightly doped N-type silicon carbide.

[0025] Step 6: Deposit silicon carbide to form an N-type polycrystalline silicon carbide gate;

[0026] Step 7: Deposit a protective oxide layer to cover the gate polysilicon carbide, and perform ion implantation to form a P-type well region and an N-type source region;

[0027] Step 8: Deposit an oxide layer, perform etching and drilling, and then perform ion implantation to form a P-type source region;

[0028] Step 9: Fill the front side of the substrate with metal to form a source metal region and the back side to form a drain metal region.

[0029] This invention, based on the traditional SGT device structure, transforms the original polysilicon gate-oxide-polysilicon separated gate structure within the trench into a PIN diode structure of the same thickness: an N-type polysilicon carbide gate-lightly doped N-type silicon carbide-P-type silicon carbide separated gate. When the SGT short-circuits, localized heat generation causes the device temperature to rise, and under the influence of the positive temperature coefficient of the diode's reverse leakage current, the current also gradually increases. Since the diode leakage current path passes through the drive circuit, the increased current leads to an increase in the voltage drop across the gate resistance, thereby reducing the device's gate voltage and improving its short-circuit withstand capability. This design fundamentally alleviates the problem of sacrificing device on-resistance to reduce saturation current and improve short-circuit withstand capability.

[0030] Due to the limitations of the PIN diode structure, the concentration of the inductor region (I-region) in traditional silicon-based PIN diodes is highly susceptible to carrier diffusion caused by thermal processes. This necessitates a long and low-concentration I-region to withstand the forward voltage drop between the gate and source during normal conduction, making it impossible to achieve normal PIN diode functionality in small-size, short-trench devices. This invention proposes replacing conventional polycrystalline silicon gate material with silicon carbide. Silicon carbide has an extremely low thermal diffusivity, making it difficult for impurities to diffuse. This allows the PIN diode's shape to be less affected and enables near-perfect direct thickness replacement without compromising electrical performance.

[0031] The SGT device structure with integrated silicon carbide gate-source diode proposed in this invention has almost identical static parameters to the traditional SGT device with the same critical dimensions and all critical process parameters, but has better short-circuit withstand capability. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a traditional SGT structure;

[0033] Figure 2 This is a schematic cross-sectional view of the SGT structure of the integrated silicon carbide gate-source diode proposed in this invention.

[0034] Figure 3 This is a schematic diagram of the device circuit described in this invention;

[0035] Figure 4 This is a simulation diagram of the concentration distribution of the integrated silicon carbide gate-source diode in the final structure described in this invention;

[0036] Figure 5 The diagram shows a simulation of the electric field gradient distribution of the conventional structure (left figure) and the integrated silicon carbide gate-source diode structure (right figure) described in this invention.

[0037] Figure 6 This is a comparison diagram of the electric field magnitudes near the oxide layer surface of the traditional structure and the integrated silicon carbide gate-source diode structure described in this invention.

[0038] Figure 7-10 for Figure 2 A cross-sectional schematic diagram showing the manufacturing process of the integrated silicon carbide gate-source diode corresponding to the structure.

[0039] Figure 11 for Figure 2 The manufacturing method corresponding to the structure.

[0040] Explanation of reference numerals in the attached figures: 000-substrate, 001-epitaxy layer, 003-polysilicon gate, 004-polysilicon split gate, 006-P-type well region, 007-N-type source region, 008-P-type source region, 009-source metal layer, 010-drain metal layer, 203-P-type silicon carbide split gate, 204-low-doped N-type silicon carbide, 205-N-type polysilicon carbide gate. Detailed Implementation

[0041] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0042] Example 1:

[0043] An SGT device integrating a silicon carbide gate-source diode includes: a substrate 000, an epitaxial layer 001, a doped region, a gate trench region, a source metal layer 009, and a drain metal layer 010.

[0044] The epitaxial layer 001 is located on the substrate 000.

[0045] The doped region is located in epitaxial layer 001.

[0046] The gate trench region is located at the center of epitaxial layer 001.

[0047] The source metal layer 009 is located on the top layer of the device.

[0048] The drain metal layer 010 is located below the substrate 000.

[0049] Example 2:

[0050] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as in Embodiment 1, further comprising a P-type well region 006, a P-type source region 008, and an N-type source region 007.

[0051] Example 3:

[0052] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as any one of embodiments 1-2, further wherein the sidewall of the P-type well region 006 is in contact with the sidewall of the P-type source region 008.

[0053] The N-type source region 007 is located above the P-type source region 008 and is in contact with the P-type well region 006.

[0054] Example 4:

[0055] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as any one of embodiments 1-3, further wherein the gate trench region is composed of an integrated gate-source diode encapsulated by an oxide layer 002.

[0056] The oxide layer 002 wraps from top to bottom around an N-type polycrystalline silicon carbide gate 205, a lightly doped N-type silicon carbide 204, and a P-type silicon carbide delimiter gate 203.

[0057] Example 5:

[0058] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as any one of embodiments 1-4, further comprising an N-type polycrystalline silicon carbide gate 205, a lightly doped N-type silicon carbide 204, and a P-type silicon carbide split gate 203.

[0059] The thickness and density of the N-type polysilicon carbide gate 205 are comparable to those of conventional SGT devices. The simulation material used is a 25V SGT device; reference values ​​are: thickness between 0.3µm and 0.6µm, and density greater than [missing value]. For SGT devices with higher voltage specifications, the thickness will be appropriately increased.

[0060] Example 6:

[0061] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as any one of embodiments 1-5, further wherein a low-doped N-type silicon carbide 204 is located above a P-type silicon carbide discrete gate 203.

[0062] The N-type polycrystalline silicon carbide gate 205 is located on top of the lightly doped N-type silicon carbide 204.

[0063] Example 7:

[0064] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as any one of embodiments 1-6, further wherein the thickness of the lightly doped N-type silicon carbide 204 is from 0.15 μm to 1.0 μm, and the concentration range is [missing information]. .

[0065] Example 8:

[0066] An SGT device integrating a silicon carbide gate-source diode, with the same technical content as any one of embodiments 1-7, further wherein the thickness of the P-type silicon carbide separated gate 203 is from 0.1 μm to 1.0 μm, and the concentration range is [not specified]. .

[0067] Example 9:

[0068] A method for manufacturing an SGT device according to any one of embodiments 1-8, comprising the following steps:

[0069] Step 1, providing a substrate having a front side and a back side disposed opposite to each other;

[0070] Step 2: Fabricate an epitaxial layer on the front side of the substrate;

[0071] Step 3: Etch trenches within the epitaxial layer, and form an oxide layer inside the trenches through thermal oxidation growth and deposition, such as... Figure 7 As shown;

[0072] Step 4: P-type silicon carbide and N-type silicon carbide are deposited in stages and etched to form a P-type silicon carbide detached gate and a lightly doped N-type silicon carbide structure in the lower part of the trench.

[0073] Step 5: An oxide layer is formed by a combination of thermal oxygen growth and deposition, followed by dry etching to selectively remove the oxide layer above the lightly doped N-type silicon carbide, such as... Figure 9 As shown, the oxide layer is a thin oxide layer on the upper sidewall;

[0074] Step 6: Deposit silicon carbide to form an N-type polycrystalline silicon carbide gate;

[0075] Step 7, deposit a protective oxide layer (e.g.) Figure 10 As shown, a thin oxide layer is applied to the top surface, covering the gate polysilicon carbide, and ion implantation is performed to form a P-type well region and an N-type source region.

[0076] Step 8, deposit oxide layer (e.g.) Figure 2 As shown, the thick oxide layer on top is etched and drilled, followed by ion implantation to form a P-type source region;

[0077] Step 9: Fill the front side of the substrate with metal to form a source metal region and the back side to form a drain metal region.

[0078] Example 10:

[0079] An integrated silicon carbide gate-source diode (SGT) device includes: a substrate, an epitaxial layer on the substrate, a doped region in the epitaxial layer, a gate trench region at the center of the epitaxial layer, a source metal layer, and a drain metal layer.

[0080] The doped regions include P-type well regions, P-type source regions, and N-type source regions.

[0081] The gate trench region is composed of an integrated gate-source diode encapsulated in an oxide layer. The gate-source diode consists of three parts: an N-type polycrystalline silicon carbide gate, a lightly doped N-type silicon carbide gate, and a P-type silicon carbide separator gate, all in contact with each other. The gate material is silicon carbide.

[0082] The integrated silicon carbide gate-source diode in the trench region has a lightly doped N-type silicon carbide thickness ranging from 0.15 μm to 1.0 μm, with a concentration range of [missing information]. .

[0083] The integrated silicon carbide gate-source diode in the trench region has a P-type silicon carbide split gate thickness ranging from 0.1 to 1.0 μm, with a concentration range of [missing information]. .

[0084] The thickness of the low-doped N-type silicon carbide is comparable to the thickness of the inter-gate oxide layer in a conventional SGT device, and the thickness of the P-type silicon carbide split gate is comparable to the thickness of the split gate in a conventional SGT device.

Claims

1. An SGT device integrating a silicon carbide gate-source diode, characterized in that: include: Substrate (000), epitaxial layer (001), doped region, gate trench region, source metal layer (009), drain metal layer (010); The epitaxial layer (001) is located on the substrate (000); The doped region is located in the epitaxial layer (001); The gate trench region is located at the center of the epitaxial layer (001); The source metal layer (009) is located on the top layer of the device; The drain metal layer (010) is located below the substrate (000).

2. The SGT device with integrated silicon carbide gate-source diode according to claim 1, characterized in that, The doped region includes a P-type well region (006), a P-type source region (008), and an N-type source region (007).

3. The SGT device with integrated silicon carbide gate-source diode according to claim 2, characterized in that, The sidewalls of the P-type well region (006) and the P-type source region (008) are in contact; The N-type source region (007) is located above the P-type source region (008) and is in contact with the P-type well region (006).

4. The SGT device with integrated silicon carbide gate-source diode according to claim 1, characterized in that, The gate trench region is composed of an integrated gate-source diode encapsulated by an oxide layer (002).

5. The SGT device with integrated silicon carbide gate-source diode according to claim 4, characterized in that, The gate-source diode includes an N-type polycrystalline silicon carbide gate (205), a lightly doped N-type silicon carbide (204), and a P-type silicon carbide split gate (203).

6. The SGT device with integrated silicon carbide gate-source diode according to claim 5, characterized in that, The lightly doped N-type silicon carbide (204) is located above the P-type silicon carbide detached gate (203); The N-type polycrystalline silicon carbide gate (205) is located on top of the lightly doped N-type silicon carbide (204).

7. The SGT device with integrated silicon carbide gate-source diode according to claim 5, characterized in that, The thickness of lightly doped N-type silicon carbide (204) ranges from 0.15 μm to 1.0 μm, with a concentration range of [missing value]. .

8. The SGT device with integrated silicon carbide gate-source diode according to claim 5, characterized in that, The thickness of the P-type silicon carbide separation gate (203) ranges from 0.1 μm to 1.0 μm, and the concentration range is [missing information]. .

9. A method for manufacturing an SGT device according to any one of claims 1-8, characterized in that the step include: Step 1, providing a substrate having a front side and a back side disposed opposite to each other; Step 2: Fabricate an epitaxial layer on the front side of the substrate; Step 3: Etch trenches in the epitaxial layer and form an oxide layer inside the trenches by thermo-oxidative growth and deposition; Step 4: P-type silicon carbide and N-type silicon carbide are deposited in stages and etched to form a P-type silicon carbide detached gate and a lightly doped N-type silicon carbide structure in the lower part of the trench. Step 5: An oxide layer is formed by combining thermal oxygen growth and deposition, and then dry etching is performed to selectively remove the oxide layer above the lightly doped N-type silicon carbide. Step 6: Deposit silicon carbide to form an N-type polycrystalline silicon carbide gate; Step 7: Deposit a protective oxide layer to cover the gate polysilicon carbide, and perform ion implantation to form a P-type well region and an N-type source region; Step 8: Deposit an oxide layer, perform etching and drilling, and then perform ion implantation to form a P-type source region; Step 9: Fill the front side of the substrate with metal to form a source metal region and the back side to form a drain metal region.

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