A GaN HEMT fully integrated basic logic gate circuit module and its fabrication method

Abstract

This invention discloses a fully integrated GaN HEMT basic logic gate module and its fabrication method, belonging to the field of semiconductor device technology. Specifically, it includes fabricating one depletion-mode GaN HEMT transistor and three enhancement-mode GaN HEMT transistors on the same substrate and epitaxial layer, with electrical isolation between the devices achieved through isolation trenches. The epitaxial layer adopts a stacked structure of a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer, and a capping layer, wherein the P-GaN layer is removed in the depletion-mode device region. By designing specified source, drain, and gate metal interconnect structures, NOT, NAND, NOR, and AND-OR-NOT gate logic functions can be implemented respectively. This invention fully integrates different types of HEMT devices on the same substrate and utilizes standardized module array arrangement. Different logic functions can be achieved simply by adjusting the metal interconnect layout, effectively solving the problems of high driver circuit specificity and high development cost in existing technologies, and significantly improving the response speed and voltage withstand capability of logic gates.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a GaN HEMT fully integrated basic logic gate circuit module and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a representative of third-generation wide-bandgap semiconductor materials, possesses significant advantages such as a large bandgap (3.4 eV), a high critical breakdown electric field (approximately 3 MV / cm), and excellent thermal conductivity (approximately 130 W / m·K), making it a promising candidate for high-voltage, high-frequency, and high-temperature power electronics. In particular, high-electron-mobility transistors (HEMTs) based on AlGaN / GaN heterojunction structures can utilize the strong spontaneous polarization and piezoelectric polarization effects at the heterojunction interface to form a high-concentration, high-mobility two-dimensional electron gas (2DEG, with a mobility reaching 1500 cm⁻¹). 2 This characteristic enables GaN HEMT devices to achieve extremely low on-resistance and ultra-high switching speed, and they are widely used in cutting-edge fields such as RF power amplifiers, DC-DC converters, power management chips, and LiDAR drivers.

[0003] However, to fully leverage the superior performance of GaN HEMT power devices, the performance of their peripheral drive and control circuits is equally crucial. Currently, the drive circuits of most commercial GaN power devices are still implemented using traditional silicon-based (Si) MOSFETs or integrated circuits. This heterogeneous integration between silicon-based drive circuits and GaN power devices introduces significant parasitic inductance and capacitance, severely limiting the system's switching speed. Furthermore, the low breakdown voltage of silicon makes it difficult to directly match GaN devices under high-voltage conditions. Therefore, achieving monolithic full integration of the drive circuit and power device on the same GaN chip has become a key technological path to overcome system performance bottlenecks.

[0004] Currently, many research institutions and companies have shifted their R&D focus to GaN monolithic fully integrated technology. As the basic unit of digital and mixed-signal control circuits, the performance of basic logic gates such as NOT, NAND, and NOR gates directly determines the response speed, power consumption, and reliability of the entire drive control system. However, most of the GaN logic gate circuits reported so far are customized circuits designed for specific application scenarios. Once product specifications or performance requirements change, such as the logic function needs to be adjusted or the drive capability needs to be increased or decreased, the entire drive circuit must be redesigned, the transistor size optimized, and even re-fabricated for verification. This traditional development model of "design once, fabricate once, and perform one function" results in a lengthy chip development cycle and high mask costs, seriously hindering the promotion of GaN fully integrated chips in multi-variety, small-batch, and rapidly iterating applications (such as automotive electronics, reconfigurable power supplies, and RF front-end modules).

[0005] Therefore, there is an urgent need for a GaN-based logic gate circuit solution that is versatile, reconfigurable, and rapidly deployable, in order to solve the problems of long development cycles and high tape-out costs caused by the strong specificity and poor reusability of the driving circuit in the existing technology. Summary of the Invention

[0006] To address the problems of high specialization, poor design flexibility, high development cost, and difficulty in matching device performance in existing GaN fully integrated logic circuits, this invention provides a GaN HEMT fully integrated basic logic gate circuit module and its fabrication method. By integrating one depletion-mode and three enhancement-mode GaN HEMT transistors on a shared substrate and epitaxial layer to form a standard transistor array, and utilizing the back-end metal interconnect layer on the same physical layout, various basic logic functions such as NOT gates, NAND gates, and NOR gates can be implemented by changing the interconnect pattern, thereby significantly reducing the development cost and time-to-market of fully integrated GaN control chips.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A GaN HEMT fully integrated basic logic gate module includes:

[0009] Substrate;

[0010] An epitaxial layer is formed on the substrate, the epitaxial layer comprising, from bottom to top, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer and a capping layer;

[0011] An isolation trench formed on the epitaxial layer penetrates the capping layer, the P-GaN layer, the barrier layer, the insertion layer, the channel layer and extends into a portion of the buffer layer, dividing the epitaxial layer into several electrically isolated active regions;

[0012] One depletion-type GaN HEMT transistor and three enhancement-type GaNHEMT transistors are formed in the active region, respectively; wherein, the P-GaN layer and capping layer in the active region corresponding to the depletion-type GaN HEMT transistor are removed, while the P-GaN layer and capping layer are retained in the active region corresponding to the enhancement-type GaN HEMT transistor.

[0013] A dense gate dielectric layer formed on the surface of the epitaxial layer;

[0014] Passivation layers formed on the source, drain, and gate of the depletion-type GaN HEMT transistor and the enhancement-type GaN HEMT transistor; and

[0015] Metal interconnects, which penetrate the passivation layer and the dense gate dielectric layer and connect the electrodes of each transistor, electrically connect the depletion-type GaN HEMT transistor and the enhancement-type GaN HEMT transistor to form a basic logic gate circuit.

[0016] Specifically, in the epitaxial layer, the insertion layer is an AlN material with a thickness ranging from 2 to 5 nm; the barrier layer is an AlxGa(1-x)N material with gradually decreasing Al composition, where 0.25 ≤ x ≤ 0.75, and a thickness ranging from 15 to 30 nm; the P-GaN layer is a Mg-doped P-type GaN material with a thickness ranging from 30 to 70 nm; and the capping layer is an AlN material with a thickness ranging from 3 to 10 nm.

[0017] Specifically, the ratio of the gate length of the depletion-type GaN HEMT transistor to the gate length of the enhancement-type GaN HEMT transistor is 2 / 1 to 5 / 1; the ratio of the channel length of the depletion-type GaN HEMT transistor to the channel length of the enhancement-type GaN HEMT transistor is 5 / 1 to 10 / 1; and the ratio of the gate width of the depletion-type GaN HEMT transistor to the gate width of the enhancement-type GaN HEMT transistor is 1 / 5 to 1 / 50.

[0018] Specifically, the basic logic gate is an NOT gate, and the connection relationship of the metal interconnects is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, the source of the depletion-type GaN HEMT transistor is connected to the drain of one of the enhancement-type GaN HEMT transistors and serves as a signal output terminal, the gate of the depletion-type GaN HEMT transistor is connected to the source of the enhancement-type GaN HEMT transistor and grounded, and the gate of the enhancement-type GaN HEMT transistor serves as a signal input terminal.

[0019] Specifically, the basic logic gate circuit is a NAND gate, and the connection relationship of the metal interconnect is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, its source is connected to the drain of the first enhancement-type GaN HEMT transistor as an output terminal, the source of the first enhancement-type GaN HEMT transistor is connected to the drain of the second enhancement-type GaN HEMT transistor, the gate of the depletion-type GaN HEMT transistor is connected to the source of the second enhancement-type GaN HEMT transistor and grounded, and the gates of the two enhancement-type GaN HEMT transistors serve as the first and second signal input terminals, respectively.

[0020] Specifically, the basic logic gate circuit is a NOR gate, and the connection relationship of the metal interconnect is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, its source is connected to the drain of the first and third enhancement-type GaN HEMT transistors as the output terminal, the gate of the depletion-type GaN HEMT transistor is connected to the source of the first and third enhancement-type GaN HEMT transistors and grounded, and the gates of the two enhancement-type GaN HEMT transistors are respectively used as signal input terminals.

[0021] Specifically, the basic logic gate circuit is an AND, OR, or NOT gate, and the connection relationship of the metal interconnects is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, its source is connected to the drain of the first enhancement-type GaN HEMT transistor as an output terminal, the gate of the depletion-type GaN HEMT transistor is connected to the source of the second and third enhancement-type GaN HEMT transistors and grounded, the source of the first enhancement-type GaN HEMT transistor is connected to the drain of the second and third enhancement-type GaN HEMT transistors, and the gates of the three enhancement-type GaN HEMT transistors are respectively used as signal input terminals.

[0022] Furthermore, based on the above structure, the present invention also provides a method for fabricating the above-mentioned GaN HEMT fully integrated basic logic gate circuit module, comprising the following steps:

[0023] S1. Provide a substrate, and sequentially grow a core layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer and a capping layer on the substrate to form an epitaxial layer;

[0024] S2. An etch protection layer is formed on the epitaxial layer, the etch protection layer is patterned and the epitaxial layer is etched to a portion of the buffer layer to form an isolation trench. The isolation trench divides the epitaxial layer into several active regions and the remaining etch protection layer is removed.

[0025] S3. By selective etching, the capping layer and the P-GaN layer on the active region corresponding to the depletion-type GaN HEMT transistor are removed, while the capping layer and the P-GaN layer on the active region corresponding to the enhancement-type GaN HEMT transistor are retained.

[0026] S4. Form source and drain grooves on the epitaxial layer, deposit ohmic metal in the grooves and perform rapid annealing to form source and drain ohmic contacts.

[0027] S5. Deposit a dense gate dielectric layer on the surface of the epitaxial layer;

[0028] S6. Deposit gate metal on the dense gate dielectric layer at the positions corresponding to each transistor channel;

[0029] S7. A passivation layer is formed on the gate metal and the dense gate dielectric layer, and the passivation layer is planarized.

[0030] S8. Pattern the passivation layer and the dense gate dielectric layer to expose the electrodes of each transistor. Deposit metal interconnects on the exposed electrodes to realize the electrical connection between each transistor and form a basic logic gate circuit module.

[0031] Specifically, the ohmic metal adopts a stacked structure of one or more metals selected from Ti / Al / Ni / Pt / Au / Pd / W, with a thickness ranging from 100 to 300 nm; the rapid annealing temperature is 800℃ to 900℃, the time is 30s to 40s, and the annealing atmosphere is nitrogen.

[0032] The dense gate dielectric layer is prepared by atomic layer deposition and the material is Al2O3 or HfO2, with a thickness ranging from 5 to 20 nm; the gate metal adopts one or more metal stacking structures selected from Ni / Pt / Au / Pd / W, with a thickness ranging from 50 to 200 nm.

[0033] Specifically, the metal interconnects are made of Al or Cu metal layers prepared by sputtering process; the basic logic gate circuit module includes NOT gates, NAND gates, NOR gates or AND-OR-NOT gates, and different logic gate circuits are connected by changing the patterned layout of the metal interconnects.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] (1) This invention improves the response capability of the control circuit of GaN HEMT power device by integrating depletion-mode GaN HEMT transistors and enhancement-mode GaN HEMT transistors on the same substrate, and forms a standardized logic gate module structure containing four transistors with specific configurations. Through different layout designs of the last metal interconnect process, multiple logic functions such as NOT gate, NAND gate, and NOR gate can be realized. This effectively solves the problem in the prior art that a complete set of layouts and tape-outs need to be redrawn for different products, greatly reduces the layout design cost and tape-out cost, and accelerates the development progress of fully integrated GaNHEMT chips.

[0036] (2) This invention optimizes the size ratio of depletion-type GaN HEMT transistors and enhancement-type GaN HEMT transistors E1 / E2 / E3, especially by increasing the channel length of the depletion-type transistor to improve the withstand voltage level and increasing the gate width of the enhancement-type transistor to improve the current driving capability, thereby achieving the best balance between withstand voltage, response speed and logic conversion capability of the logic gate circuit module.

[0037] (3) The present invention introduces an AlN insertion layer and an AlN capping layer in the epitaxial structure. The AlN insertion layer enhances the piezoelectric polarization effect at the interface and significantly increases the drain current. At the same time, it serves as a buffer layer to reduce lattice mismatch stress. The AlN capping layer effectively passivates surface defects, suppresses defect diffusion, and reduces the interface state density, thereby improving the overall electrical performance and reliability of the device. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the device structure of a non-logic gate in an embodiment of the present invention.

[0039] Figure 2 This is a schematic diagram of the metal interconnection distribution of non-logic gates in an embodiment of the present invention.

[0040] Figure 3 This is a circuit schematic diagram of a non-logic gate in an embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram of the device structure of the NAND gate in an embodiment of the present invention.

[0042] Figure 5 This is a schematic diagram of the metal interconnection distribution of AND and NOT logic gates in an embodiment of the present invention.

[0043] Figure 6 This is a circuit diagram of a NAND gate in an embodiment of the present invention.

[0044] Figure 7 This is a schematic diagram of the device structure of the NOR logic gate in an embodiment of the present invention.

[0045] Figure 8 This is a schematic diagram of the metal interconnection distribution of NOR logic gates in an embodiment of the present invention.

[0046] Figure 9 This is a circuit diagram of a NOR logic gate in an embodiment of the present invention.

[0047] Figure 10 This is a schematic diagram of the device structure of AND, OR, and NOT logic gates in an embodiment of the present invention.

[0048] Figure 11 This is a schematic diagram of the metal interconnection distribution of AND, OR, and NOT logic gates in an embodiment of the present invention.

[0049] Figure 12 This is a circuit diagram of AND, OR, and NOT logic gates in an embodiment of the present invention.

[0050] Figure 13 This is a schematic diagram of the structure of the epitaxial layer prepared in an embodiment of the present invention.

[0051] Figure 14 This is a schematic diagram of the structure for preparing the etching protective layer in an embodiment of the present invention.

[0052] Figure 15 This is a schematic diagram of the structure for preparing the isolation groove in an embodiment of the present invention.

[0053] Figure 16 This is a schematic diagram of the P-GaN layer etching structure in an embodiment of the present invention.

[0054] Figure 17 This is a schematic diagram of the structure of the ohmic metal prepared in an embodiment of the present invention.

[0055] Figure 18 This is a schematic diagram of the structure for preparing a dense gate dielectric layer in an embodiment of the present invention.

[0056] Figure 19 This is a schematic diagram of the structure of the gate fabricated in an embodiment of the present invention.

[0057] Figure 20 This is a schematic diagram of the structure for preparing the passivation layer in an embodiment of the present invention.

[0058] In the above figures, the component names corresponding to the reference numerals are as follows:

[0059] 101-Substrate, 102-Nucleation layer, 103-Buffer layer, 104-Channel layer, 105-Insertion layer, 106-Barrier layer, 107-P-GaN layer, 108-Capping layer, 109-Etching protection layer, 110-Isolation trench, 111-Two-dimensional electron gas layer, 112-D1 drain, 113-D1 source, 114-E1 drain, 115-E1 source, 116-E2 drain, 117-E2 source, 118-E3 source, 119-E3 drain, 120-Dense gate dielectric layer, 121-D1 gate, 122-E1 gate, 123-E2 gate, 124-E3 gate, 125-Passivation layer, 126-First metal interconnect layer, 127-Second metal interconnect layer, 128-Third metal interconnect layer, 129-Fourth metal interconnect layer. Detailed Implementation

[0060] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0061] Example

[0062] like Figures 1 to 20 As shown, this embodiment provides a GaN HEMT fully integrated basic logic gate circuit module, aiming to provide a general-purpose reconfigurable logic unit to realize a high-quality GaN control circuit monolithically integrated with GaN power devices and reduce chip development costs. Its specific circuit structure includes a depletion-mode GaN HEMT transistor and three enhancement-mode GaN HEMT transistors fabricated on the same substrate and epitaxial layer. Specific logic gates are implemented through arrayed arrangement and metal interconnects, thereby enabling flexible adjustment of the control circuit and improving the signal conversion capability of the logic gates. The depletion-mode GaN HEMT transistor is labeled D1, and the three enhancement-mode GaN HEMT transistors are labeled E1, E2, and E3, respectively.

[0063] In the shared substrate and epitaxial layer design, substrate 101 can be silicon, sapphire, silicon carbide, gallium nitride, gallium oxide, diamond, etc., with a thickness of 300μm-800μm. The epitaxial layer is grown on one side of the substrate, and from bottom to top consists of a nucleation layer 102, a buffer layer 103, a channel layer 104, an insertion layer 105, a barrier layer 106, a P-GaN layer 107, and a capping layer 108. The nucleation layer 102 is made of AlN material with a thickness ranging from 10 to 50 nm; the buffer layer 103 is intentionally doped high-resistivity GaN material with a thickness ranging from 300 to 1000 nm; the channel layer 104 is unintentionally doped intrinsic GaN material with a thickness ranging from 100 to 300 nm; the insertion layer 105 is made of AlN material with a thickness ranging from 2 to 5 nm; and the barrier layer 106 is AlxGa(1-x)N with gradually decreasing Al composition. The material has a thickness of 0.25 ≤ x ≤ 0.75 and a thickness range of 15~30 nm. The P-GaN layer 107 is a P-type GaN layer with a high concentration of Mg ions doped and a thickness range of 30~70 nm. The capping layer 108 is an AlN material with a thickness range of 3~10 nm.

[0064] An etching protection layer 109, made of Si3N4 material and with a thickness ranging from 50 to 100 nm, is provided above the capping layer 108 to protect the epitaxial layer from damage during deep etching. The area where the etching protection layer 109 is removed is etched to the buffer layer 103 to form an isolation trench 110, which blocks the electrical connection between transistors in the epitaxial layer.

[0065] After the isolation trench 110 is etched, the protective layer 109 is removed. The capping layer 108 and the P-GaN layer 107 are removed by selective etching, leaving only the capping layer 108 and the P-GaN layer 107 at the gates of the enhancement-mode GaN HEMT transistors E1, E2, and E3. Due to the polarization effect of the barrier layer 106 and the channel layer 104, a large number of electrons are generated near the top of the channel layer 104 between the two interfaces in the region where the P-GaN layer 107 is removed, forming a two-dimensional electron gas layer 111.

[0066] The drain 112 and source 113 of the depletion-type GaN HEMT transistor D1, the drain 114 and source 115 of the enhancement-type GaN HEMT transistor E1, the drain 116 and source 117 of the enhancement-type GaN HEMT transistor E2, and the source 118 and drain 119 of the enhancement-type GaN HEMT transistor E3 are disposed in the groove at the bottom of the selectively etched barrier layer 106. The source and drain metals adopt one or more metal stacking structures selected from Ti / Al / Ni / Pt / Au / Pd / W, with a thickness ranging from 100 to 300 nm, and form ohmic contact metal electrodes at the bottom of the barrier layer 106 after high-temperature rapid annealing.

[0067] A dense gate dielectric layer 120 is covered on the wafer on which the ohmic contact metal electrode is fabricated. The dielectric material is a high-k dielectric material, such as Al2O3 or HfO2, with a thickness ranging from 5 to 20 nm.

[0068] The gate 121 of transistor D1 is fabricated above the dense gate dielectric layer 120 between the drain 112 and the source 113. The gate 122 of transistor E1 is fabricated above the dense gate dielectric layer 120 with a P-GaN layer between the drain 114 and the source 115. The gate 123 of transistor E2 is fabricated above the dense gate dielectric layer 120 with a P-GaN layer between the drain 116 and the source 117. The gate 124 of transistor E3 is fabricated above the dense gate dielectric layer 120 with a P-GaN layer between the source 118 and the drain 119. The gate metal adopts one or more metal stacking structures of metals such as Ni / Pt / Au / Pd / W, with a thickness ranging from 50 to 200 nm.

[0069] A passivation layer 125, made of SiO2 or Si3N4 material, with a thickness ranging from 300 to 800 nm, is prepared on the wafer on which the gate metal electrode is prepared. The surface of the passivation layer 125 after deposition is planarized by chemical mechanical polishing (CMP).

[0070] Specifically, the ratio of the gate length of the depletion-type GaN HEMT transistor to that of the enhancement-type GaN HEMT transistor is 2 / 1 to 5 / 1; the ratio of the channel length of the depletion-type GaN HEMT transistor to that of the enhancement-type GaN HEMT transistor is 5 / 1 to 10 / 1; and the ratio of the gate width of the depletion-type GaN HEMT transistor to that of the enhancement-type GaN HEMT transistor is 1 / 5 to 1 / 50. Transistors E1, E2, and E3 have the same gate length / channel length / gate width ratio (Lg / L / W). The depletion-type GaN HEMT transistor D1, acting as the load (pull-up resistor) of the logic gate, has a relatively long channel length L and a relatively narrow gate width W to limit current and increase voltage withstand capability. The enhancement-type GaN HEMT transistor, acting as the switching transistor (pull-down transistor), has a short channel and a large gate width to provide a strong drive current, thereby ensuring that the logic gate has sufficient drive capability when outputting a low level and can quickly pull up to the power supply voltage when outputting a high level.

[0071] In this embodiment, the NOT gate in the basic logic gate circuit removes the passivation layer 125 and the dense gate dielectric layer 120 above the metal electrodes of transistors D1 and E1, respectively, to form electrode openings. A first interconnect metal layer 126 is then deposited in the openings to complete the fabrication of the NOT gate. The device structure diagram and the distribution diagram of the first metal interconnect layer 126 are shown below. Figure 1 and Figure 2 As shown, the NOT gate circuit diagram is as follows: Figure 3 As shown; where the drain 112 of transistor D1 is connected to the power supply voltage VCC, the source 113 of transistor D1 and the drain 114 of transistor E1 are connected and serve as the signal output terminal out, the gate 121 of transistor D1 and the source 115 of transistor E1 are connected and grounded, and the gate 122 of transistor E1 serves as the signal input terminal in1; as Figure 3 As shown, transistor D1, being a depletion-type transistor, has its gate connected to ground, meaning it is always in the ON state. Therefore, it bears the main voltage drop of the NOT logic gate. When the voltage at the in1 signal terminal is less than the turn-on threshold voltage V of the enhancement-type transistor E1... thE1 When E1 is off, since the power supply voltage VCC is usually much greater than the transistor threshold voltage, the voltage at the out output terminal is approximately VCC, i.e., the output is high, and the logic value is 1; when the voltage at the in1 signal terminal is greater than the turn-on threshold voltage VCC of the enhancement-mode transistor E1, the output voltage is approximately VCC. thE1 When the voltage is high, E1 is turned on. At this time, the voltage at the out output terminal is approximately grounded, which is 0V, that is, the output is low level and the logic value is 0. Based on the above analysis, this NOT logic gate can realize the NOT logic function.

[0072] In this embodiment, the passivation layer 125 and dense gate dielectric layer 120 above the metal electrodes of transistors D1, E1, and E2 are removed to form electrode openings, and a second interconnect metal layer 127 is deposited in the openings to complete the fabrication of the NAND gate. The device structure diagram and the distribution diagram of the second metal interconnect layer 127 are shown below. Figure 4 and Figure 5 As shown, the circuit diagram is as follows: Figure 6 As shown; the drain of transistor D1 is connected to the power supply voltage VCC, the source of transistor D1 is connected to the drain of transistor E1 and serves as the signal output terminal out, the source of transistor E1 is connected to the drain of transistor E2, the gate of transistor D1 is connected to the source of transistor E2 and grounded, the gate of transistor E1 serves as the signal input terminal in1, and the gate of transistor E2 serves as the signal input terminal in2; as shown. Figure 6 As shown, the NAND gate adds an enhancement-mode transistor E2 to the NOT gate. Transistors E2 and E1 are connected in series on the output terminal out. Since the gate of transistor D1 is connected to ground, it is always in the ON state. When the voltage value at either the IN1 or IN2 signal terminal is less than the transistor's turn-on threshold voltage, the transistor cannot be turned on, and the circuit is in an open-circuit state. At this time, the voltage at the out output terminal is approximately VCC, i.e., the output is high, and the logic value is 1. When the voltage values ​​at both the IN1 and IN2 signal terminals are greater than the transistor's turn-on threshold voltage, E1 and E2 are turned on. At this time, the voltage at the out output terminal is approximately grounded, which is 0V, i.e., the output is low, and the logic value is 0. Based on the above analysis, this circuit can realize the NAND logic function.

[0073] In this embodiment, the NOR gate in the basic logic gate circuit removes the passivation layer 125 and the dense gate dielectric layer 120 above the metal electrodes of transistors D1, E1, and E3, respectively, to form electrode openings. A third interconnect metal layer 128 is then deposited in the openings to complete the fabrication of the NOR gate. The device structure diagram and the distribution diagram of the third metal interconnect layer 128 are shown below. Figure 7 and Figure 8 As shown, the circuit diagram is as follows: Figure 9 As shown; the drain of transistor D1 is connected to the power supply voltage VCC, the source of transistor D1 is connected to the drains of transistors E1 and E3 and serves as the signal output terminal out, the gate of transistor D1 is connected to the sources of transistors E1 and E3 and grounded, the gate of transistor E1 serves as the signal input terminal in1, and the gate of transistor E3 serves as the signal input terminal in3; as shown. Figure 9 As shown, the NOR gate adds an enhancement-mode transistor E3 to the NOT gate. Transistor E3 and transistor E1 are connected in parallel on the output terminal out. Since the gate of transistor D1 is connected to ground, it is always in the ON state. When the voltage values ​​of both the in1 and in3 signal terminals are less than the transistor's turn-on threshold voltage, the transistor cannot be turned on, and the circuit is in an open circuit state. At this time, the voltage at the out output terminal is approximately VCC, that is, the output is high, and the logic value is 1. When one or both of the voltage values ​​of the in1 and in3 signal terminals are greater than the transistor's turn-on threshold voltage, E1 and E2 are turned on. At this time, the voltage at the out output terminal is approximately grounded, which is 0V, that is, the output is low, and the logic value is 0. Based on the above analysis, this circuit can realize the NOR logic function.

[0074] In this embodiment, the basic logic gate circuit may also include AND, OR, and NOT logic gates. The passivation layer 125 and dense gate dielectric layer 120 above the metal electrodes of transistors D1, E1, E2, and E3 are removed to form electrode openings. A fourth interconnect metal layer 129 is then deposited in the openings to complete the fabrication of the AND, OR, and NOT logic gates. The device structure diagram and the distribution diagram of the fourth metal interconnect layer 129 are shown below. Figure 10 and Figure 11 As shown, the circuit diagram is as follows: Figure 12 As shown; the drain of transistor D1 is connected to the power supply voltage VCC, the source of transistor D1 is connected to the drain of transistor E1 and serves as the signal output terminal out, the source of transistor E1 is connected to the drains of transistors E2 and E3, the gate of transistor D1 is connected to the source of transistors E2 and E3 and grounded, the gate of transistor E1 serves as the signal input terminal in1, the gate of transistor E2 serves as the signal input terminal in2, and the gate of transistor E3 serves as the signal input terminal in3; as shown. Figure 12As shown, the AND-OR-NOT gate adds a pair of source-drain parallel enhancement transistors E2 and E3 to the source side of the enhancement transistor E1 of the NOT gate. Since the gate of transistor D1 is connected to ground, it is always in the ON state. When the voltage values ​​at the in2 and in3 signal terminals are both less than the turn-on threshold voltage of its transistors, transistors E2 and E3 cannot be turned on, and the circuit is in an open circuit state. At this time, regardless of whether the input voltage in1 of transistor E1 is greater than its threshold voltage, the voltage at the out output terminal is approximately VCC, that is, the output is high, and the logic value is 1. When one or both of the voltage values ​​at the in1 and in3 signal terminals are greater than the turn-on threshold voltage of its transistors, E1 and E2 are turned on. At this time, when the input voltage in1 of transistor E1 is greater than its threshold voltage, the circuit from the out output terminal to the ground electrode is turned on, and the voltage at the out output terminal is approximately 0V, that is, the output is low, and the logic value is 0. Based on the above analysis, this circuit can realize the AND-OR-NOT logic function.

[0075] Specifically, the first, second, third, and fourth metal interconnects mentioned above are made of Al or Cu metal materials.

[0076] like Figures 13 to 20 As shown, this embodiment also provides a method for preparing the above module, the specific steps of which are as follows:

[0077] Step S1: Select substrate 101. Substrate 101 can be any of the following substrates: silicon, sapphire, silicon carbide, gallium nitride, gallium oxide, diamond, etc. In this embodiment, silicon is preferred as the substrate. After organic and inorganic cleaning of substrate 101, it is placed in the MOCVD cavity and the following layers are grown sequentially: AlN nucleation layer 102 with a thickness of 20 nm, high-resistivity GaN buffer layer 103 with a thickness of 800 nm, unintentionally doped intrinsic GaN channel layer 104 with a thickness of 150 nm, AlN insertion layer 105 with a thickness of 2 nm, AlxGa(1-x)N (0.25≤x≤0.75) barrier layer 106 with a thickness of 30 nm and gradually decreasing Al composition, P-GaN layer 107 with a thickness of 70 nm and heavily doped with Mg ions, and AlN capping layer 108 with a thickness of 5 nm, to obtain the epitaxial layer of the logic gate circuit module.

[0078] Step S2: Take the wafer with the AlN capping layer 108 grown from the MOCVD growth chamber, remove the surface contaminants from the transfer process by organic and inorganic cleaning, and then transfer the cleaned wafer to the PECVD chamber. Introduce the reaction gases SiH4 and NH3, adjust the reaction temperature and gas pressure, and deposit a 50nm thick Si3N4 etching protective layer 109.

[0079] Step S3: The wafer with the Si3N4 etching protective layer 109 deposited is taken out of the PECVD cavity. The surface contamination during the wafer transfer process is removed by organic and inorganic cleaning. The wafer surface is then coated, exposed, and developed using photolithography to form a mask in a certain area of ​​the wafer. The protective layer 109 and the epitaxial layer are selectively etched into the buffer layer 103 using an inductively coupled plasma etching (ICP) device to obtain the isolation trench 110. The unetched wafer area is surrounded by the isolation trench 110 to form an isolation island, which is used to fabricate transistors, thereby achieving electrical isolation between transistors in the lateral direction of the epitaxial layer of the wafer.

[0080] Step S4: Remove the Si3N4 etching protective layer 109 by HF acid immersion, and then remove residual stains by organic and inorganic cleaning; again, perform photolithography on the wafer surface for homogenization, exposure and development, forming a mask in a certain area of ​​the wafer isolation island, and selectively etch the cap layer 108 and the P-GaN layer 107 using ICP etching. Due to the polarization effect of the barrier layer 106 and the channel layer 104, a large amount of two-dimensional electron gas 111 is generated at the top of the channel layer 104, and the two-dimensional electron gas (2DEG) below the epitaxial layer of the P-GaN layer is depleted, thereby realizing the P-GaN enhancement-mode GaN HEMT device.

[0081] Step S5: Immerse the wafer after etching the cap layer 108 and the P-GaN layer 107 in a solution of dilute HCl (15%) and ultrapure water diluted at a ratio of 1:10 to remove etching residues. Then, clean the wafer surface with low-power plasma to passivate etching defects. Perform photolithography on the wafer surface, including photoresist coating, exposure, and development, to form a mask for the barrier layer 106 in a portion of the isolation island. Etch the barrier layer 106 in the masked area to the bottom using ICP to form the source and drain trenches for transistors D1, E1, E2, and E3. Remove etching residues using low-power oxygen plasma, and then immerse the wafer with photoresist in the aforementioned dilute HCl solution. In a Cl solution, oxide residues in the etched source and drain trenches are removed. The wafer is then placed in an electron beam evaporation (E-beam) chamber, where a Ti / Al / Pt / Pd metal stack structure (20 / 130 / 50 / 100 nm thick) is deposited in the trenches. Subsequently, a metal lift-off process is used to obtain the source and drain metals. The wafer is then rapidly annealed at 850 °C in a nitrogen atmosphere for 35 s to achieve ohmic contact between the source and drain metals and the bottom of the 106 trench of the barrier layer, resulting in the source 113 and drain 112 of transistor D1, the source 115 and drain 114 of transistor E1, the source 117 and drain 116 of transistor E2, and the source 118 and drain 119 of transistor E3.

[0082] Step S6: Remove residual contaminants on the wafer with deposited source and drain metals by organic and inorganic cleaning. Transfer the cleaned wafer to the atomic layer deposition (ALD) cavity. Under low temperature and low pressure conditions, control the number of cycles to react the precursor tetra(dimethylamino)hafnium (TDMAH) and deionized water (H2O) to generate a dense HfO2 gate dielectric layer 120 with a thickness of 5 nm.

[0083] Step S7: Apply photolithography to the wafer surface for photoresist homogenization, exposure, and development. Form a mask for the dense gate dielectric layer 120 between the source and drain electrodes of transistors D1, E1, E2, and E3. Transfer the wafer with the mask photoresist to the E-beam cavity. Apply a metal evaporation process to deposit a Ni / Pd (thickness of 50 / 100nm) metal stack structure. After a metal stripping process, obtain the gate 121 of transistor D1, the gate 122 of E1, the gate 123 of E2, and the gate 124 of E3.

[0084] Step S8: Remove residual contaminants on the wafer with deposited gate metal by organic and inorganic cleaning. Transfer the cleaned wafer to a PECVD chamber, introduce reaction gases SiH4 and NH3, adjust the reaction temperature and pressure, and deposit a 600nm thick Si3N4 passivation layer 125. Then, use photolithography to perform homogenization, exposure, and development on the surface of the passivation layer 125. Form a mask on the passivation layer 125 above the electrodes of the corresponding transistors according to the circuits of different logic gates. Use ICP to etch the passivation layer 125 above the electrodes and the dense gate dielectric. Etching is performed at step 120 to form electrode openings. After electrode opening, the wafer is immersed in the dilute HCl solution described in step 15 to remove etching residue. Then, photolithography is used again to perform photoresist homogenization, exposure, and development on the wafer surface. The wafer with the photoresist mask is transferred to a magnetron sputtering (PVD) cavity, where Al metal is sputtered using a metal sputtering process to form metal interconnect layers. The circuit connections according to different logic gates are the first metal interconnect layer 126, the second metal interconnect layer 127, the third metal interconnect layer 128, and the fourth metal interconnect layer 129, as follows: Figure 1 , 4 As shown in the schematic diagrams of devices 7 and 10, the fabrication of the GaN HEMT fully integrated basic logic gate circuit module is completed.

[0085] This implementation fabricates depletion-mode and enhancement-mode GaN HEMT devices on the same substrate and epitaxial layer, achieving full integration of logic gate circuits. Furthermore, it optimizes the basic logic gate circuit modules through device arrangement and interconnection metal line layout. The output signals of these basic logic gates achieve a full swing output from ground voltage 0V to power supply voltage VDD, adapting to the high-frequency and high-speed response capabilities of GaN HEMT power devices. This enables more efficient application in high-end fields such as RF modulation circuits, automotive power module protection logic, and aerospace reconfigurable mixed-signal chips.

[0086] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A GaN HEMT fully integrated basic logic gate module, characterized in that, include: Substrate; An epitaxial layer is formed on the substrate, the epitaxial layer comprising, from bottom to top, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer and a capping layer; An isolation trench formed on the epitaxial layer penetrates the capping layer, the P-GaN layer, the barrier layer, the insertion layer, the channel layer and extends into a portion of the buffer layer, dividing the epitaxial layer into several electrically isolated active regions; One depletion-type GaN HEMT transistor and three enhancement-type GaN HEMT transistors are formed in the active region, respectively; wherein, the P-GaN layer and capping layer in the active region corresponding to the depletion-type GaN HEMT transistor are removed, while the P-GaN layer and capping layer are retained in the active region corresponding to the enhancement-type GaN HEMT transistor. A dense gate dielectric layer formed on the surface of the epitaxial layer; Passivation layers formed on the source, drain, and gate of the depletion-type GaN HEMT transistor and the enhancement-type GaN HEMT transistor; and Metal interconnects, which penetrate the passivation layer and the dense gate dielectric layer and connect the electrodes of each transistor, electrically connect the depletion-type GaN HEMT transistor and the enhancement-type GaN HEMT transistor to form a basic logic gate circuit.

2. The GaN HEMT fully integrated basic logic gate module according to claim 1, characterized in that, In the epitaxial layer, the insertion layer is AlN material with a thickness ranging from 2 to 5 nm; the barrier layer is AlxGa(1-x)N material with gradually decreasing Al composition, where 0.25 ≤ x ≤ 0.75, and a thickness ranging from 15 to 30 nm; the P-GaN layer is Mg-doped P-type GaN material with a thickness ranging from 30 to 70 nm; and the capping layer is AlN material with a thickness ranging from 3 to 10 nm.

3. The GaN HEMT fully integrated basic logic gate module according to claim 1, characterized in that, The ratio of the gate length of the depletion-type GaN HEMT transistor to the gate length of the enhancement-type GaN HEMT transistor is 2 / 1 to 5 / 1; the ratio of the channel length of the depletion-type GaN HEMT transistor to the channel length of the enhancement-type GaN HEMT transistor is 5 / 1 to 10 / 1; and the ratio of the gate width of the depletion-type GaN HEMT transistor to the gate width of the enhancement-type GaN HEMT transistor is 1 / 5 to 1 / 50.

4. The GaN HEMT fully integrated basic logic gate module according to claim 1, characterized in that, The basic logic gate is a NOT gate. The connection relationship of the metal interconnects is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage; the source of the depletion-type GaN HEMT transistor is connected to the drain of one of the enhancement-type GaN HEMT transistors and serves as the signal output terminal; the gate of the depletion-type GaN HEMT transistor is connected to the source of the enhancement-type GaN HEMT transistor and grounded; and the gate of the enhancement-type GaN HEMT transistor serves as the signal input terminal.

5. The GaN HEMT fully integrated basic logic gate module according to claim 1, characterized in that, The basic logic gate circuit is a NAND gate. The connection relationship of the metal interconnect is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, its source is connected to the drain of the first enhancement-type GaN HEMT transistor as the output terminal, the source of the first enhancement-type GaN HEMT transistor is connected to the drain of the second enhancement-type GaN HEMT transistor, the gate of the depletion-type GaN HEMT transistor is connected to the source of the second enhancement-type GaN HEMT transistor and grounded, and the gates of the two enhancement-type GaN HEMT transistors are respectively used as signal input terminals.

6. The GaN HEMT fully integrated basic logic gate module according to claim 1, characterized in that, The basic logic gate circuit is a NOR gate, and the connection relationship of the metal interconnect is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, its source is connected to the drain of the first and third enhancement-type GaN HEMT transistors as the output terminal, the gate of the depletion-type GaN HEMT transistor is connected to the source of the first and third enhancement-type GaN HEMT transistors and grounded, and the gates of the two enhancement-type GaN HEMT transistors are respectively used as signal input terminals.

7. The GaN HEMT fully integrated basic logic gate module according to claim 1, characterized in that, The basic logic gate circuit is an AND, OR, or NOT gate. The connection relationship of the metal interconnect is configured as follows: the drain of the depletion-type GaN HEMT transistor is connected to the power supply voltage, its source is connected to the drain of the first enhancement-type GaN HEMT transistor as an output terminal, the gate of the depletion-type GaN HEMT transistor is connected to the source of the second and third enhancement-type GaN HEMT transistors and grounded, the source of the first enhancement-type GaN HEMT transistor is connected to the drain of the second and third enhancement-type GaN HEMT transistors, and the gates of the three enhancement-type GaN HEMT transistors are respectively used as signal input terminals.

8. The method for fabricating a GaN HEMT fully integrated basic logic gate module as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1. Provide a substrate, and sequentially grow a core layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer and a capping layer on the substrate to form an epitaxial layer; S2. An etch protection layer is formed on the epitaxial layer, the etch protection layer is patterned and the epitaxial layer is etched to a portion of the buffer layer to form an isolation trench. The isolation trench divides the epitaxial layer into several active regions and the remaining etch protection layer is removed. S3. By selective etching, the capping layer and the P-GaN layer on the active region corresponding to the depletion-type GaN HEMT transistor are removed, while the capping layer and the P-GaN layer on the active region corresponding to the enhancement-type GaN HEMT transistor are retained. S4. Form source and drain grooves on the epitaxial layer, deposit ohmic metal in the grooves and perform rapid annealing to form source and drain ohmic contacts. S5. Deposit a dense gate dielectric layer on the surface of the epitaxial layer; S6. Deposit gate metal on the dense gate dielectric layer at the positions corresponding to each transistor channel; S7. A passivation layer is formed on the gate metal and the dense gate dielectric layer, and the passivation layer is planarized. S8. Pattern the passivation layer and the dense gate dielectric layer to expose the electrodes of each transistor. Deposit metal interconnects on the exposed electrodes to realize the electrical connection between each transistor and form a basic logic gate circuit module.

9. The method for fabricating a GaN HEMT fully integrated basic logic gate module according to claim 8, characterized in that, The ohmic metal adopts a stacked structure of one or more metals selected from Ti / Al / Ni / Pt / Au / Pd / W, with a thickness ranging from 100 to 300 nm; the rapid annealing temperature is 800℃ to 900℃, the time is 30s to 40s, and the annealing atmosphere is nitrogen. The dense gate dielectric layer is prepared by atomic layer deposition and the material is Al2O3 or HfO2, with a thickness ranging from 5 to 20 nm; the gate metal adopts one or more metal stacking structures selected from Ni / Pt / Au / Pd / W, with a thickness ranging from 50 to 200 nm.

10. The method for fabricating a GaN HEMT fully integrated basic logic gate module according to claim 8, characterized in that, The metal interconnects are made of Al or Cu metal layers prepared by sputtering process; the basic logic gate circuit module includes NOT gates, NAND gates, NOR gates or AND-OR-NOT gates, and different logic gate circuits can be connected by changing the patterned layout of the metal interconnects.

Images