GaN-based monolithic integrated gate drive anti-crosstalk circuit and preparation method thereof

Abstract

This invention discloses a GaN-based monolithically integrated gate drive anti-crosstalk circuit and its fabrication method, belonging to the field of semiconductor device technology. Specifically, it includes an enhancement-mode GaN HEMT power device and an anti-crosstalk circuit integrated on the same substrate and epitaxial layer. The anti-crosstalk circuit includes a first resistor, a second resistor, a diode, and a ferrite bead. The second resistor, diode, and ferrite bead are connected in series between the pre-stage drive circuit and the gate of the enhancement-mode GaN HEMT power device. The first resistor is connected in parallel across the series connection of the second resistor and diode. This invention eliminates packaging parasitic parameters through monolithic integration technology. By utilizing the unidirectional conductivity of the diode in conjunction with the resistor, it achieves low-impedance drive during normal power device conduction and high-impedance suppression during reverse ringing, effectively preventing gate false turn-on and device burnout. The integrated ferrite bead array further filters out high-frequency interference signals, significantly improving the high-frequency stability and reliability of the circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a GaN-based monolithic integrated gate drive anti-crosstalk circuit and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors, as representative devices of third-generation semiconductors, have shown broad application potential in high-speed, high-frequency, and high-power-density power conversion systems due to their significant advantages such as wide bandgap, high electron saturation velocity, high breakdown field strength, and low on-resistance. In power electronic systems, P-GaN enhancement-mode GaN HEMTs are typically chosen as power switching devices to meet safety and reliability requirements; however, these devices inherently have low threshold voltages and narrow gate voltage safety windows, which impose extremely stringent requirements on the stability of the drive circuit.

[0003] In practical applications of GaN power devices, the extremely high switching speed leads to extremely high voltage and current change rates. This high-frequency switching behavior is highly sensitive to the parasitic parameters of the drive circuit. In existing technologies, the drive circuit and power device are typically packaged separately or in a system-in-package (SiP). Discrete drive solutions, due to their long package leads, exhibit significant parasitic inductance and capacitance. These parasitic parameters, along with the device's junction capacitance, easily form an LC oscillating circuit, generating a high-frequency oscillating voltage during switching and causing severe ringing in the gate waveform. While SiP shortens the interconnect path and reduces some parasitic parameters, the drive chip and power device remain on different substrates connected by bonding wires, meaning parasitic parameters still exist.

[0004] More importantly, with the increase in power density, monolithic integration technology has emerged. Monolithic integration integrates the drive circuit or part of the protection circuitry with the power device on the same GaN substrate, significantly eliminating parasitic parameters introduced by packaging and improving system integration. However, monolithic integration also brings new challenges: due to the extremely close spacing between devices, crosstalk between the drive circuit and the power device becomes particularly prominent. During high-frequency switching, severe voltage fluctuations generated at the source or drain of the power device can couple to the gate drive circuit through parasitic capacitance or introduce interference through inductive coupling on the common source ground line. This crosstalk can not only cause misjudgment of the gate drive signal, leading to mis-turn-on or turn-off failure of the power device, but in severe cases, it can even generate high-frequency oscillating voltages sufficient to break down the gate oxide layer or cause permanent burn-out of the device. Therefore, how to effectively suppress crosstalk and oscillation in the gate circuit under a monolithic integration architecture, and protect the power device and the preceding drive circuit, has become a key technical problem that urgently needs to be solved in the current GaN power integrated circuit field.

[0005] To address the aforementioned issues, relevant patent documents have proposed technical solutions. US Patent 10686411 B2 discloses a gate driver and voltage regulator for GaN power transistors and devices. This patent monolithically integrates a D-mode HEMT (acting as a variable resistor) and an E-mode HEMT (acting as a Zener diode) on a chip, capable of stably providing a gate drive voltage of approximately 6V. However, the HEMT device in this gate drive circuit increases the chip's static power consumption and chip area, and is detrimental to the high-frequency response of the power device. Additionally, Chinese Patent CN 214850956 U discloses a drive circuit for GaN MOS transistors. This circuit consists of a capacitor C, a resistor R, a diode D, and a ferrite bead FB, enabling dynamic adjustment of the output gate input voltage and a clamping function. However, the presence of a capacitor in the gate input circuit increases the gate capacitance, thereby affecting the device's turn-on and turn-off speeds. Summary of the Invention

[0006] To address the problems of LC loop oscillation, gate ringing, signal crosstalk, and easy device burnout caused by parasitic parameters and high-frequency switching in existing monolithic integrated GaN power devices and driving circuits, this invention provides a GaN-based monolithic integrated gate drive anti-crosstalk circuit and its fabrication method. By integrating a specific anti-crosstalk network between the driving end and the gate of the power device, and using monolithic integration technology to eliminate packaging parasitic parameters, effective suppression of high-frequency oscillation and protection of the power device are achieved.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A GaN-based monolithic integrated gate drive anti-crosstalk circuit includes:

[0009] Substrate;

[0010] An epitaxial layer formed on the substrate;

[0011] An enhanced GaN HEMT power device formed on the epitaxial layer;

[0012] And an anti-crosstalk circuit formed on the epitaxial layer;

[0013] The anti-crosstalk circuit includes a first resistor, a second resistor, a diode, and a ferrite bead. The second resistor, diode, and ferrite bead are connected in series between the output terminal of the pre-stage drive circuit and the gate of the enhancement-mode GaN HEMT power device. The first resistor is connected in parallel across the two ends of the second resistor and the diode. The enhancement-mode GaN HEMT power device and the anti-crosstalk circuit are fabricated on the substrate using the same process.

[0014] Specifically, the epitaxial layer, from the side closest to the substrate upwards, includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer, and a capping layer.

[0015] An isolation trench is provided in the epitaxial layer, extending into the buffer layer, for isolating the electrical connections of the enhancement-type GaN HEMT power device, the first resistor, the second resistor, the diode, and the ferrite bead in the lateral direction.

[0016] Specifically, the diode is a hybrid anode diode, including a P-GaN gate enhancement-mode HEMT device with the gate and source shorted;

[0017] The anode of the hybrid anode diode is connected to one end of the second resistor, the cathode of the hybrid anode diode is connected to one end of the magnetic bead, and the gate of the hybrid anode diode is short-circuited to the anode.

[0018] The P-GaN layer of the hybrid anode diode and the P-GaN layer of the enhancement-mode GaN HEMT power device are located at the same level and are formed simultaneously.

[0019] Specifically, the first resistor is a polycrystalline silicon resistor, and the second resistor is a metal-two-dimensional electron gas-metal resistor;

[0020] The resistance ratio of the first resistor to the second resistor ranges from 50:1 to 50000:1;

[0021] Both the first resistor and the second resistor are disposed within the isolation region or the effective region on the epitaxial layer, and electrical isolation is achieved by etching the barrier layer to remove the underlying two-dimensional electron gas layer.

[0022] Specifically, the magnetic beads are an integrated magnetic bead array, including a magnetic core disposed on a dense dielectric layer and a dense insulating layer covering the magnetic core;

[0023] The magnetic core is composed of regularly arranged bumps in an array formed by etching a magnetic thin film, and the dense insulating layer covers the sidewalls and top of the magnetic core.

[0024] Furthermore, based on the above structure, the present invention also provides a method for fabricating the above-mentioned GaN-based monolithic integrated gate drive anti-crosstalk circuit, comprising the following steps:

[0025] S1. Provide a substrate, and sequentially grow a core layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer and a capping layer on the substrate to form an epitaxial layer;

[0026] S2. Selectively etch the epitaxial layer to remove the capping layer and P-GaN layer in some areas, leaving only the P-GaN layer and capping layer in the gate region of the enhancement GaN HEMT power device and the gate region of the diode.

[0027] S3. An isolation trench is formed in a portion of the epitaxial layer to achieve electrical isolation between devices;

[0028] S4. An ohmic metal electrode is fabricated in the region where the barrier layer is retained to form the electrode of the second resistor, the source and drain electrodes of the diode, and the source and drain electrodes of the enhancement-mode GaN HEMT power device.

[0029] S5. A dense dielectric layer is deposited to cover the epitaxial layer and the electrode;

[0030] S6. Fabricate a first resistor, a gate of a power device, a gate of a diode, and a magnetic bead array on the dense dielectric layer;

[0031] S7. Prepare a passivation layer and an interconnect metal layer to realize the electrical connection of each device and form the monolithic integrated gate drive anti-crosstalk circuit.

[0032] Specifically, the process of forming the isolation trench in step S3 includes:

[0033] The isolation trench extends into the buffer layer by employing ion implantation or epitaxial layer etching processes to process a portion of the epitaxial layer.

[0034] The area where the isolation tank is located is a passive region, and the area where no ion implantation is performed is an active region.

[0035] The power devices and diodes are disposed in the active region, and the first resistor and magnetic bead array are disposed in the passive region or at a location within the active region after the barrier layer has been etched.

[0036] Specifically, the process of fabricating the first resistor, the gate of the power device, and the gate of the diode on the dense dielectric layer in step S6 includes:

[0037] A polycrystalline silicon layer is deposited on a dense dielectric layer using a low-pressure chemical vapor deposition process.

[0038] The polycrystalline silicon layer is doped using an ion implantation process;

[0039] By selective etching, polysilicon gates are formed in the gate region of power devices and the gate region of diodes, and strip-shaped polysilicon structures are formed in the resistor region as the first resistor.

[0040] The gate and anode of the diode are shorted by an interconnecting metal to form a hybrid anode diode structure with gate-source shorting.

[0041] Specifically, the process of preparing the magnetic bead array in step S6 includes:

[0042] A magnetic thin film is deposited on top of the dense dielectric layer in the magnetic bead region using a magnetron sputtering process, and an array of magnetic cores is formed by an etching process.

[0043] A dense insulating layer is deposited on the surface and sidewalls of the magnetic core using atomic layer deposition (ALD) technology to form a magnetic bead array with a protective structure.

[0044] Specifically, the process of preparing the passivation layer and interconnect metal layer in step S7 includes:

[0045] A passivation layer is deposited to cover the magnetic bead array and the polysilicon structure, and planarization is performed using a chemical mechanical polishing process.

[0046] The passivation layer and the dense dielectric layer are etched to form contact holes, and the first interconnect metal is deposited to bring out the internal electrodes of each device.

[0047] A protective layer is deposited, electrode openings are etched, and a second interconnect metal is deposited to complete the circuit connection between the anti-crosstalk circuit and the power device, as well as the lead-out of the external electrodes.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] (1) By integrating the anti-crosstalk circuit and the GaN power device on the same substrate, the present invention completely eliminates the parasitic inductance and parasitic capacitance caused by traditional packaging (such as SIP or discrete packaging), blocks the generation path of LC oscillation from the physical level, significantly improves the high-frequency characteristics, and enhances the energy density and response speed of the circuit.

[0050] (2) The anti-crosstalk circuit designed in this invention utilizes the unidirectional conductivity of the diode and the resistance value configuration of the resistor to achieve intelligent dynamic adjustment: when the power device is normally turned on or off, the diode is turned on, the first resistor and the second resistor are connected in parallel, the total resistance of the circuit is reduced, and the driving current is larger, thereby ensuring that the device has a very fast switching speed and reducing switching losses; when the circuit has reverse ringing or a false turn-on tendency, the diode is turned off, and the current can only flow through the high resistance value of the first resistor, which greatly reduces the gate oscillation current and voltage amplitude, effectively preventing the front-end driver chip from outputting incorrect signals and the power device gate from burning out due to overvoltage, thus solving the reverse crosstalk problem.

[0051] (3) The diode used in this invention is a P-GaN gate HEMT structure with gate and source shorted. This structure is fully compatible with the fabrication process of enhancement-mode power devices and does not require additional process steps. Moreover, the diode can withstand high reverse bias voltage, has low on-resistance, and has excellent performance.

[0052] (4) The present invention introduces a monolithically integrated magnetic bead array, which is directly fabricated inside the chip. As a high-frequency suppressor, it can effectively filter out ultra-high frequency oscillation signals excited by parasitic parameters without significantly increasing the DC on-resistance, thereby further enhancing the anti-interference capability of the circuit and the stability of the system. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the device structure according to an embodiment of the present invention.

[0054] Figure 2 This is a top view of the device structure according to an embodiment of the present invention.

[0055] Figure 3 This is a circuit schematic diagram of an embodiment of the present invention.

[0056] Figure 4 This is a schematic diagram of the structure of the epitaxial layer prepared in an embodiment of the present invention.

[0057] Figure 5 This is a schematic diagram of the P-GaN layer etching and isolation trench fabrication in an embodiment of the present invention.

[0058] Figure 6 This is a schematic diagram of the structure for preparing the ohmic metal and dense dielectric layer in an embodiment of the present invention.

[0059] Figure 7 This is a schematic diagram of the structure for fabricating the resistor and gate in an embodiment of the present invention.

[0060] Figure 8 This is a schematic diagram of the structure of the magnetic beads prepared in an embodiment of the present invention.

[0061] Figure 9 This is a schematic diagram of the structure for preparing the passivation layer and the first interconnect metal layer in an embodiment of the present invention.

[0062] Figure 10 This is a schematic diagram of the structure for preparing the protective layer and the second interconnect metal layer in an embodiment of the present invention.

[0063] Figure 11 This is another circuit schematic diagram in an embodiment of the present invention.

[0064] In the above figures, the component names corresponding to the reference numerals are as follows:

[0065] 001 - Integrated circuit, 100 - Enhanced GaN HEMT power device, 200-Anti-crosstalk circuit, 300-Pre-stage driver circuit, 101-Substrate, 102-Nucleation layer, 103-Buffer layer, 104-Channel layer, 105-Insertion layer, 106-Barrier layer, 107-P-GaN layer, 108-Cap layer, 109-Two-dimensional electron gas layer, 110-Device isolation region, 111-Q1 source, 112-Q1 drain, 113-D1 anode, 114-D1 cathode, 115-R2 first electrode, 116-R2 second electrode, 117-Dense dielectric layer, 118-D1 gate, 119-Q1 gate, 120-R1 first electrode, 121-R1 second electrode, 122-Magnetic core, 123-Dense insulating layer, 124-Passivation layer, 125-First interconnect metal layer, 126-Protective layer, 127-Second interconnect metal layer. Detailed Implementation

[0066] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0067] Example

[0068] like Figures 1 to 11As shown, this embodiment provides a GaN-based monolithically integrated gate driver anti-crosstalk circuit, aiming to solve problems such as gate ringing, signal crosstalk, and device susceptibility in existing GaN power integrated circuits. It adds an anti-crosstalk circuit between the gate driver chip and the gate of the power device, and uses a monolithically integrated process with the power device to fabricate the anti-crosstalk circuit and the power device on the same substrate. The circuit connection is completed through metal interconnection, eliminating the resonance phenomenon caused by parasitic capacitance and inductance on the gate line, and blocking signal crosstalk between the reverse ringing of the power device and the gate driver chip, thus protecting the power device and the preceding gate driver chip. The GaN-based monolithic integrated gate drive anti-crosstalk circuit mainly consists of an enhancement-mode GaN HEMT power device 100 and an anti-crosstalk circuit 200. The enhancement-mode GaN HEMT power device is labeled Q1. The anti-crosstalk circuit includes a first resistor, a second resistor, a diode, and a ferrite bead. The first resistor is labeled R1, the second resistor is labeled R2, the diode is labeled D1, and the ferrite bead is labeled Lbead. The second resistor R2, the diode D1, and the ferrite bead Lbead are connected in series between the output terminal Vdrv of the pre-stage drive circuit 300 and the gate G of the enhancement-mode GaN HEMT power device Q1. The first resistor R1 is connected in parallel across the second resistor R2 and the diode D1. The specific connection relationship is as follows: one end of the second resistor R2 is connected to the drive signal input terminal, and the other end is connected to the anode of the diode D1. The cathode of the diode D1 is connected to one end of the ferrite bead Lbead, and the other end of the ferrite bead Lbead is connected to the gate of the enhancement-mode GaN HEMT power device Q1. One end of the first resistor R1 is connected between the drive signal input terminal and the second resistor R2, and the other end is connected between the diode D1 and the ferrite bead Lbead.

[0069] The working principle of this embodiment is to use the unidirectional conductivity of diode D1 and the resistance difference between the first resistor and the second resistor to achieve the crosstalk prevention function. Specifically, the resistance value of the first resistor R1 is set to be much larger than the resistance value of the second resistor R2. For example, the ratio of R1 to R2 can be set between 50:1 and 50000:1.

[0070] When the enhancement-mode GaN HEMT power device Q1 is normally turned on or off, the front-end drive circuit outputs a forward drive voltage, and diode D1 is in the on state. At this time, because the resistance of R1 is extremely large, the total resistance after parallel connection is mainly determined by R2. The total resistance of the drive circuit is approximately equal to the second resistor R2, resulting in a low circuit impedance and a large drive current. This ensures that the enhancement-mode GaN HEMT power device Q1 can complete the turn-on or turn-off operation at an extremely fast speed, meeting the requirements of high-frequency applications.

[0071] When the circuit experiences reverse ringing due to parasitic inductance or capacitance—that is, when the source voltage of power device Q1 momentarily exceeds the gate voltage, or when a reverse high-voltage pulse appears at the gate—diode D1 is turned off due to the reverse voltage. At this time, the drive circuit is disconnected, but because an oscillating current path exists, the current is forced to flow through the high-resistance first resistor R1. Due to the extremely high resistance of R1, this circuit forms a high-impedance path, greatly attenuating the reverse oscillation current, thereby reducing the gate oscillation voltage amplitude, blocking the impact of the reverse crosstalk signal on the preceding drive circuit, preventing power device Q1 from breaking down and burning out due to excessively high gate voltage, and also preventing the preceding drive chip from outputting incorrect logic signals due to interference.

[0072] In terms of specific physical structure design, such as Figure 1 As shown, this embodiment adopts a fully monolithic integrated solution. The enhanced GaNHEMT power device 100 and the anti-crosstalk circuit 200 share a substrate 101 and an epitaxial layer. The substrate 101 can be silicon, sapphire, silicon carbide, gallium nitride, gallium oxide, diamond, etc., with a thickness of 300μm-800μm. The epitaxial layer is grown on one side of the substrate and, from bottom to top, consists of a nucleation layer 102, a buffer layer 103, a channel layer 104, an insertion layer 105, a barrier layer 106, a P-GaN layer 107, and a capping layer 108. The nucleation layer 102 is made of AlN material with a thickness ranging from 10 to 50 nm; the buffer layer 103 is intentionally doped high-resistivity GaN material with a thickness ranging from 300 to 1000 nm; the channel layer 104 is unintentionally doped intrinsic GaN material with a thickness ranging from 100 to 300 nm; the insertion layer 105 is made of AlN material with a thickness ranging from 2 to 5 nm; and the barrier layer 106 is an AlN layer with gradually decreasing Al content. x Ga (1-x) The material is N (0.25≤x≤0.75) with a thickness ranging from 15 to 30 nm. The P-GaN layer 107 is a P-type GaN layer with a high concentration of Mg ions doped with a thickness ranging from 30 to 70 nm. The capping layer 108 is an AlN material with a thickness ranging from 3 to 10 nm.

[0073] The capping layer 108 and P-GaN layer 107 of a portion of the wafer are removed by selective etching, leaving only the capping layer 108 and P-GaN layer 107 at the gates of diode D1 and power device Q1. After etching, a large number of electrons are generated at the top of the channel layer 104 due to the polarization between the barrier layer 106 and the channel layer 104, forming a two-dimensional electron gas layer 109. The portion of the wafer where the capping layer 108 and P-GaN layer 107 have been etched is then implanted into the buffer layer 103 to form a device isolation region 110, blocking the electrical connection between circuit elements in the epitaxial layer.

[0074] The source 111 and drain 112 of the power device Q1, the anode 113 and cathode 114 of the diode D1, and the first electrode 115 and second electrode 116 of the two-dimensional electron gas resistor R2 are respectively disposed in the bottom groove of the selectively etched barrier layer 106. The electrode metal adopts one or more metal stacking structures of metals such as Ti / Al / Ni / Pt / Au / Pd / W, with a thickness ranging from 100 to 300 nm, and forms an ohmic contact with the bottom of the barrier layer 106 after high-temperature rapid annealing.

[0075] A dense dielectric layer 117 is covered on the wafer on which the ohmic contact metal electrode is fabricated. This layer is made of silicon material with good insulating properties, such as Si3N4 or SiO2, with a thickness ranging from 5 to 20 nm.

[0076] A polysilicon layer is deposited above the dense dielectric layer 117. A strip-shaped polysilicon resistor R1, along with its first electrode 120 and second electrode 121, is formed in a portion of the wafer region by selective ion implantation and etching. A gate 118 for diode D1 and a gate 119 for Q1 are formed on the dense dielectric layer 117 of the unetched capping layer 108 and the P-GaN layer 107 of power device Q1. The polysilicon deposition thickness is 50~200nm. The ion implantation concentration of the first electrode 120 and the second electrode 121 of polysilicon resistor R1 is lower than that of gate 118 and gate 119, and the resistance value is much higher than that of gate 118 and gate 119.

[0077] On the wafer, a magnetic alloy bump array, called magnetic core 122, is prepared above a portion of the dense dielectric layer 117 in the magnetic bead region. This array is obtained by selective deposition. The core is made of FeCo, Ni, or CoFeB magnetic material and has a thickness ranging from 300 to 800 nm. A uniform dense insulating layer 123 is covered on the surface and sidewalls of the core to form a magnetic bead array.

[0078] A passivation layer 124, made of SiO2 or Si3N4 material, with a thickness ranging from 300 to 1000 nm, is also fabricated on the wafer. The wafer surface is smoothed using chemical mechanical polishing (CMP). Electrode openings are formed by etching the passivation layer 124, dense insulating layer 123, and dense dielectric layer 117 above all electrodes of resistors R1 and R2, diode D1, ferrite beads Lbead, and transistor Q1, as well as the magnetic core 122. A first interconnect metal layer 125, made of Al or Cu metal material, is fabricated in the openings. The strip resistors of resistors R1 and R2 are connected in a serpentine series through the first interconnect metal layer 125 to prepare resistors with specific resistance values. The ferrite bead Lbead array is connected in a serpentine manner through the first interconnect metal layer 125. The anode and gate of diode D1 are connected through the first interconnect metal layer 125, completing the electrode lead-out of the device.

[0079] A protective layer 126, made of SiO2 or Si3N4 material with a thickness ranging from 300 to 1000 nm, is also fabricated on the wafer on which the first interconnect metal layer 125 is prepared. The wafer surface is smoothed using chemical mechanical polishing (CMP). By etching the protective layer 126 above the device electrodes brought out in the previous step, electrode openings are formed again, and a second interconnect metal layer 127, made of Al or Cu metal material, is prepared in the openings. Resistors R1 and R2, diode D1, ferrite bead Lbead, and transistor Q1 are electrically connected through the second interconnect metal layer 127, and electrodes that need to be connected to external driving circuits are brought out, completing the fabrication of integrated circuit 001. The top view of this circuit is shown in the figure. Figure 2 As shown, the second electrode 121 of resistor R1 and the first electrode 115 of resistor R2 are both connected to the output signal terminal Vdrv of the pre-stage drive circuit 300. The drain of transistor Q1 is connected to the power supply voltage VCC, and the source of transistor Q1 is connected to the ground electrode.

[0080] The gate length Lg ratio of diode D1 and transistor Q1 is 1:1 to 1:10, the channel length L ratio is 1:1 to 1:10, and the gate width W ratio is 3:1 to 1:10. Resistor R1 is a polysilicon resistor, and resistor R2 is a metal-two-dimensional electron gas-metal resistor. The resistance of R1 is much larger than that of R2, and their ratio can be 50:1 to 50000:1. The ferrite bead, as a high-frequency suppressor, has a negligible resistance compared to R1 and R2. When the gate rings at high frequency due to common-mode interference from parasitic parameters, the ferrite bead can filter out this high-frequency signal to reduce the gate voltage oscillation and prevent transistor Q1 from burning out under high voltage.

[0081] like Figures 4 to 10 As shown, this embodiment also provides a method for fabricating the aforementioned integrated circuit, the specific steps of which are as follows:

[0082] Step S1: Select substrate 101. Substrate 101 can be any of the following substrates: silicon, sapphire, silicon carbide, gallium nitride, gallium oxide, diamond, etc. In this embodiment, silicon is preferred as the substrate. After organic and inorganic cleaning of substrate 101, it is placed in the MOCVD chamber, and the following layers are grown sequentially: a 20 nm thick AlN nucleation layer 102, an 800 nm thick high-resistivity GaN buffer layer 103, a 150 nm thick unintentionally doped intrinsic GaN channel layer 104, a 2 nm thick AlN insertion layer 105, and a 30 nm thick Al layer with gradually decreasing Al composition. x Ga (1-x)A wafer with an epitaxial layer of integrated circuit 001 is obtained by forming an N (0.25≤x≤0.75) barrier layer 106, a Mg ion heavily doped P-GaN layer with a thickness of 70nm 107, and an AlN capping layer with a thickness of 5nm 108.

[0083] Step S2: The wafer surface with the epitaxial layer is coated, exposed, and developed using photolithography. The capping layer 108 and the P-GaN layer 107 are selectively etched using ICP (Inductively Coupled Plasma) etching, leaving only the capping layer 108 and the P-GaN layer 107 at the gates of diode D1 and transistor Q1. The epitaxial layer retaining the P-GaN layer 107 will deplete the two-dimensional electron gas (2DEG) generated by the polarization effect of the barrier layer 106 and the channel layer 104, thus realizing a P-GaN enhancement-mode GaN device. Due to the polarization effect of the barrier layer 106 and the channel layer 104, a large amount of two-dimensional electron gas (2DEG) is generated on the top of the channel layer 104 in the etched epitaxial layer, forming a two-dimensional electron gas. Layer 109; The etched wafer is immersed in a solution of dilute HCl (15%) and ultrapure water diluted at a ratio of 1:10 to remove etching residues, and the wafer surface is cleaned by low-power plasma to passivate the etched defects; The wafer surface is then coated, exposed, and developed using photolithography to form a mask; High-energy ion implantation is performed on the epitaxial layer of the mask area, followed by high-temperature annealing to activate the ions, thereby achieving electrical isolation of the devices subsequently fabricated on the wafer in the lateral direction of the epitaxial layer, resulting in device isolation region 110; Subsequent device fabrication takes place in the un-ion-implanted region, i.e., the active region of the wafer, and device isolation region 110 is referred to as the passive region of the wafer.

[0084] Step S3: The wafer is cleaned with organic and inorganic methods to remove surface contaminants and impurities from the ion implantation process. Photolithography is used to perform photoresist homogenization, exposure, and development on the wafer surface to form a mask for the barrier layer 106 in a portion of the active region on the wafer. ICP etching is then used to etch the barrier layer 106 in the masked area down to the bottom, forming an ohmic metal groove. Low-power oxygen plasma is used to remove etching residues. The wafer with photoresist is then immersed in the dilute HCl solution described in step S2 to remove oxide residues in the ohmic metal groove after etching. The wafer is then placed in an electron beam evaporation (E-beam) chamber, where a Ti / Al / Ni / Au metal stack structure (thickness 20 / 130 / 50 / 100nm) is deposited in the groove. Subsequently, a metal lift-off process is used to obtain... The metal electrodes are then rapidly annealed in a nitrogen atmosphere at 850°C for 35 seconds to achieve ohmic contact between the metal electrodes and the bottom of the groove in the barrier layer 106, resulting in the first electrode 115 and the second electrode 116 of resistor R2, the anode 113 and the cathode 114 of diode D1, and the source 111 and the drain 112 of transistor Q1. The wafer with the ohmic electrodes is then cleaned using organic and inorganic cleaning methods. The cleaned wafer is then transferred to the vacuum chamber of an atomic layer deposition (ALD) device for atomic layer deposition. Under low temperature and low pressure conditions, the reaction is carried out by controlling the number of pulse cycles of the gaseous silicon-based precursor (tris(dimethylamino)silane) (TDMAS) and O2 to generate a dense SiO2 dielectric layer 117 with a thickness of 5 nm.

[0085] Step S4: The wafer with the SiO2 dense dielectric layer 117 grown is transferred to the high-temperature furnace tube of a low-pressure chemical vapor deposition (LPCVD) system. Silane (SiH4) gas is introduced, and silicon atoms are deposited on the wafer surface through thermal decomposition reaction to complete the preparation of the polycrystalline silicon layer. During this deposition process, a small dose of phosphine (PH3) or borane (B2H6) is simultaneously introduced to achieve doping of the high-resistivity polycrystalline silicon layer, thereby preparing the subsequent high-resistivity polycrystalline silicon resistor R1. The wafer surface is then subjected to photolithography for homogenization, exposure, and development. A mask is formed to preserve the position of the P-GaN layer 107 for diode D1 and transistor Q1. The wafer is then transferred to an ion implanter for high-dose ion implantation (phosphorus or boron ions). This process ensures that the ion doping concentration in this region is much higher than that in the resistor R1 region. After ion implantation, the photoresist on the wafer surface is removed using organic and inorganic cleaning methods, followed by high-temperature rapid annealing (RTA) at 1000℃. This process repairs the damage caused to the polysilicon by ion implantation and activates impurity ions to achieve higher conductivity. Finally, photolithography is used to coat the wafer surface again, expose and develop it, forming a mask for the gate positions of resistor R1, diode D1 and transistor Q1. The polysilicon resistor R1 (including the first electrode 120 and the second electrode 121 of R1), the polysilicon gate 118 of diode D1, and the polysilicon gate 119 of transistor Q1 are obtained by ICP etching.

[0086] Step S5: Using photolithography, the wafer surface is coated, exposed, and developed to form a mask for a portion of the dense dielectric layer 117 in the magnetic bead Lbead region. The wafer is then transferred to the magnetron sputtering (PVD) chamber, where FeCo target material is sputtered in an argon atmosphere to obtain an array of high-quality FeCo magnetic thin film bumps. The magnetic properties are then improved through subsequent low-temperature annealing to obtain the magnetic core 122. Using photolithography, the wafer surface is coated, exposed, and developed to form a mask for the magnetic core 122 region. The wafer is then transferred to the ALD equipment, where the number of cycles of silane (SiH4) and O2 is controlled under low-temperature and low-pressure conditions to generate a high-quality SiO2 dense insulating layer 123, which protects the magnetic core 122 from environmental electromagnetic interference. The SiO2 dense insulating layer 123 uniformly covers the surface and sidewalls of the magnetic core 122 with a thickness of 5 nm.

[0087] Step S6: After cleaning the wafer with organic and inorganic methods to remove residual contaminants, the wafer is transferred to a PECVD chamber. Reaction gases SiH4 and O2 are introduced, and the reaction temperature and pressure are adjusted to deposit a 600nm thick SiO2 passivation layer 124. Chemical mechanical polishing (CMP) is then used to smooth the wafer surface. Subsequently, photolithography is used to perform homogenization, exposure, and development on the surface of the passivation layer 124, forming a mask for the passivation layer 124 above the area requiring metal electrode openings. ICP etching is then used to etch the passivation layer 124, the dense insulating layer 123, and the dense dielectric layer 117 above the electrodes to form the electrode openings. The wafer with the electrode openings is then immersed in step S6. In the dilute HCl solution described in section 2, etching residues are removed; then, photolithography is used again to perform homogenization, exposure, and development on the wafer surface, and the wafer with the photoresist mask is transferred to a magnetron sputtering (PVD) cavity, where Al metal is sputtered using a metal sputtering process to form a first interconnect metal layer 125; wherein resistors R1, R2, and ferrite beads Lbead are connected end-to-end in a serpentine manner through the first interconnect metal layer 125 to complete the connection of resistors and ferrite beads with specific resistance values, and the anode 113 and gate 118 of diode D1 are connected through the first interconnect metal layer 125 to form a hybrid anode diode D1 formed by a P-GaN gate enhancement type HEMT with the gate and source shorted.

[0088] Step S7: After cleaning the wafer with organic and inorganic methods to remove metal particles and other impurities, the wafer is transferred to a PECVD chamber. Reaction gases SiH4 and NH3 are introduced, and the reaction temperature and pressure are adjusted to deposit an 800nm ​​thick Si3N4 protective layer 126. Chemical mechanical polishing (CMP) is then used to smooth the wafer surface. Next, photolithography is used to coat, expose, and develop the protective layer 126, forming a mask above the metal electrodes of the first interconnect metal layer 125. ICP etching is then used to etch the protective layer 126 above the electrodes to form electrode openings. The wafer with the electrode openings is then immersed in the dilute HCl solution described in step S2 to remove etching residues. Finally, photolithography is used again to coat the wafer surface. Exposure and development are performed to transfer the wafer with the photoresist mask into the magnetron sputtering (PVD) cavity. Al metal is sputtered using a metal sputtering process to form the second interconnect metal layer 127, thus completing the fabrication of the integrated circuit. The second electrode 121 of resistor R1 is connected to the first electrode 115 of resistor R2 and connected to the output terminal Vdrv of the front-end gate drive circuit. The first electrode 120 of resistor R1 is connected to the cathode 114 of diode D1 and one end of the ferrite bead. The second electrode 116 of resistor R2 is connected to the anode 113 of diode D1. The other electrode of the ferrite bead is connected to the gate 119 of transistor Q1. The source 111 and drain 112 of transistor Q1 are connected to the ground electrode and the power supply voltage VCC, respectively.

[0089] This implementation fabricates circuit components such as resistors, diodes, and ferrite beads, along with enhancement-mode GaN HEMT power devices, on the same substrate and epitaxial layer. This achieves full integration of the gate anti-crosstalk circuit, significantly reducing parasitic parameters introduced by system integration and packaging methods. It also solves the signal interference problem of gate ringing on the front-end driver chip and power devices, and protects the GaN HEMT power devices to operate normally in high-frequency, fast-response circuits, preventing them from turning on accidentally and burning out. This allows for more efficient application in high-end applications such as automotive power modules and aerospace chips.

[0090] In another embodiment, the present invention also provides a simplified GaN-based monolithic integrated gate drive anti-crosstalk circuit, such as... Figure 11As shown, the anti-crosstalk circuit 200 only includes resistors R1 and R2 and diode D1. The rest of the structure is the same as in the previous embodiment. The only difference is that there is no ferrite bead (Lbead). That is, the integrated circuit does not have a high-frequency suppressor to block high-frequency voltage signals. The gate terminal G of the enhancement GaN HEMT power device 100 may experience a high voltage, causing the transistor to be unstable or fail. However, since the electromagnetic effect of the ferrite bead itself may cause electromagnetic crosstalk in the circuit, and its own resistance is also non-negligible for GaN HEMT devices that require extremely fast turn-on and turn-off speeds, the addition of the ferrite bead will inevitably increase the on-resistance of the GaN device and prolong the device's on-time.

[0091] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A GaN-based monolithic integrated gate drive anti-crosstalk circuit, characterized in that, include: Substrate; An epitaxial layer formed on the substrate; The epitaxial layer, from the side closest to the substrate upwards, includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer, and a capping layer. An enhanced GaN HEMT power device formed on the epitaxial layer; And an anti-crosstalk circuit formed on the epitaxial layer; The anti-crosstalk circuit includes a first resistor, a second resistor, a diode, and a ferrite bead. The second resistor, diode, and ferrite bead are connected in series between the output terminal of the pre-stage drive circuit and the gate of the enhancement-mode GaN HEMT power device. The first resistor is connected in parallel across the two ends of the second resistor and the diode. The enhancement-mode GaN HEMT power device and the anti-crosstalk circuit are fabricated on the substrate using the same process. The diode is a hybrid anode diode, comprising a P-GaN gate enhancement-mode HEMT device with gate and source shorted; the anode of the hybrid anode diode is connected to one end of the second resistor, the cathode of the hybrid anode diode is connected to one end of the magnetic bead, and the gate of the hybrid anode diode is shorted to the anode; The P-GaN layer of the hybrid anode diode and the P-GaN layer of the enhancement-mode GaN HEMT power device are located at the same level and are formed simultaneously.

2. The GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 1, characterized in that, An isolation trench is provided in the epitaxial layer, extending into the buffer layer, for isolating the electrical connections of the enhancement-type GaN HEMT power device, the first resistor, the second resistor, the diode, and the ferrite bead in the lateral direction.

3. The GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 1, characterized in that, The first resistor is a polycrystalline silicon resistor, and the second resistor is a metal-two-dimensional electron gas-metal resistor; The resistance ratio of the first resistor to the second resistor ranges from 50:1 to 50000:1; Both the first resistor and the second resistor are disposed within the isolation region or the effective region on the epitaxial layer, and electrical isolation is achieved by etching the barrier layer to remove the underlying two-dimensional electron gas layer.

4. The GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 1, characterized in that, The magnetic beads are an integrated magnetic bead array, including a magnetic core disposed on a dense dielectric layer and a dense insulating layer covering the magnetic core; The magnetic core is composed of regularly arranged bumps in an array formed by etching a magnetic thin film, and the dense insulating layer covers the sidewalls and top of the magnetic core.

5. The method for fabricating a GaN-based monolithic integrated gate drive anti-crosstalk circuit as described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1. Provide a substrate, and sequentially grow a core layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, a P-GaN layer and a capping layer on the substrate to form an epitaxial layer; S2. Selectively etch the epitaxial layer to remove the capping layer and P-GaN layer in some areas, leaving only the P-GaN layer and capping layer in the gate region of the enhancement GaN HEMT power device and the gate region of the diode. S3. An isolation trench is formed in a portion of the epitaxial layer to achieve electrical isolation between devices; S4. An ohmic metal electrode is fabricated in the region where the barrier layer is retained to form the electrode of the second resistor, the source and drain electrodes of the diode, and the source and drain electrodes of the enhancement-mode GaN HEMT power device. S5. A dense dielectric layer is deposited to cover the epitaxial layer and the electrode; S6. Fabricate a first resistor, a gate of a power device, a gate of a diode, and a magnetic bead array on the dense dielectric layer; S7. Prepare a passivation layer and an interconnect metal layer to realize the electrical connection of each device and form the monolithic integrated gate drive anti-crosstalk circuit.

6. The method for fabricating a GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 5, characterized in that, The process of forming the isolation groove in step S3 includes: The isolation trench extends into the buffer layer by employing ion implantation or epitaxial layer etching processes to process a portion of the epitaxial layer. The area where the isolation tank is located is a passive region, and the area where no ion implantation is performed is an active region. The power devices and diodes are disposed in the active region, and the first resistor and magnetic bead array are disposed in the passive region or at a location within the active region after the barrier layer has been etched.

7. The method for fabricating a GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 6, characterized in that, The process of fabricating the first resistor, the gate of the power device, and the gate of the diode on the dense dielectric layer in step S6 includes: A polycrystalline silicon layer is deposited on a dense dielectric layer using a low-pressure chemical vapor deposition process. The polycrystalline silicon layer is doped using an ion implantation process; By selective etching, polysilicon gates are formed in the gate region of power devices and the gate region of diodes, and strip-shaped polysilicon structures are formed in the resistor region as the first resistor. The gate and anode of the diode are shorted by an interconnecting metal to form a hybrid anode diode structure with gate-source shorting.

8. The method for fabricating a GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 7, characterized in that, The process of preparing the magnetic bead array in step S6 includes: A magnetic thin film is deposited on top of the dense dielectric layer in the magnetic bead region using a magnetron sputtering process, and an array of magnetic cores is formed by an etching process. A dense insulating layer is deposited on the surface and sidewalls of the magnetic core using atomic layer deposition (ALD) technology to form a magnetic bead array with a protective structure.

9. The method for fabricating a GaN-based monolithic integrated gate drive anti-crosstalk circuit according to claim 8, characterized in that, The process of preparing the passivation layer and interconnect metal layer in step S7 includes: A passivation layer is deposited to cover the magnetic bead array and the polysilicon structure, and planarization is performed using a chemical mechanical polishing process. The passivation layer and the dense dielectric layer are etched to form contact holes, and the first interconnect metal is deposited to bring out the internal electrodes of each device. A protective layer is deposited, electrode openings are etched, and a second interconnect metal is deposited to complete the circuit connection between the anti-crosstalk circuit and the power device, as well as the lead-out of the external electrodes.

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