Semiconductor device including intermediate insulating structure and method of manufacturing semiconductor device

Abstract

A semiconductor device is provided, having a lower structure, an upper structure, and an intermediate insulating structure between the lower and upper structures. The lower structure includes a lower source / drain region, a lower active layer, and a lower gate structure disposed above the lower active layer. The upper structure includes an upper source / drain region, an upper active layer, and an upper gate structure disposed below the upper active layer and vertically overlapping the lower gate structure. The intermediate insulating structure includes an insulating structure located below the upper structure and a barrier structure on the lower structure. The barrier structure has a barrier insulating layer and a barrier pattern disposed above the barrier insulating layer, the barrier pattern surrounding the insulating structure and contacting the lower surface of the upper source / drain region.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0047452, filed on April 11, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0003] To meet the demands for high integration and miniaturization of semiconductor devices, the size of semiconductor components has also shrunk. Therefore, semiconductor devices, including stacked transistors (such as complementary field-effect transistor (CFET) stacks), have been studied. Summary of the Invention

[0004] The present invention provides a semiconductor device with improved reliability and enhanced performance.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising a lower structure, an upper structure, and an intermediate insulating structure between the lower structure and the upper structure. The lower structure may include: lower source / drain regions spaced apart from each other in a first direction; lower active layers spaced apart from each other in a vertical direction, the lower active layers being disposed between the lower source / drain regions and connected to the lower source / drain regions; and a lower gate structure extending in a second direction perpendicular to the first direction, the lower gate structure including portions respectively disposed above the lower active layers. The upper structure may include: upper source / drain regions spaced apart from each other in the first direction, the upper source / drain regions vertically overlapping the lower source / drain regions; upper active layers spaced apart from each other in a vertical direction, the upper active layers being disposed between and connected to the upper source / drain regions, the upper active layers vertically overlapping the lower active layers; and an upper gate structure extending in the second direction, the upper gate structure including portions respectively disposed below the upper active layers, the upper gate structure vertically overlapping the lower gate structure. The intermediate insulation structure may include: an insulation structure below the upper structure; and a barrier structure including a barrier insulation layer on the lower structure and a barrier pattern disposed above the barrier insulation layer, the barrier pattern surrounding the insulation structure and contacting the lower surface of the upper source / drain region.

[0006] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first structure, a barrier structure on the first structure, an insulating structure on the barrier structure, and a second structure on the insulating structure. The first structure may include: first source / drain regions spaced apart from each other in a first direction; a first active layer spaced apart from each other in a vertical direction, the first active layer being disposed between the first source / drain regions and connected to the first source / drain regions; and a first gate structure extending in a second direction perpendicular to the first direction, the first gate structure including portions respectively disposed above the first active layers. The second structure may include: second source / drain regions spaced apart from each other in the first direction, the second source / drain regions vertically overlapping the first source / drain regions; a second active layer spaced apart from each other in a vertical direction, the second active layer being disposed between and connected to the second source / drain regions, the second active layer vertically overlapping the first active layer; and a second gate structure extending in the second direction, the second gate structure including portions respectively disposed below the second active layers, the second gate structure vertically overlapping the first gate structure. The barrier structure may include a barrier pattern and a barrier insulating layer surrounding the barrier pattern on the first structure. The insulating layer structure may include an insulating pattern and an insulating pad surrounding the insulating pattern on the barrier structure.

[0007] According to another aspect of the present invention, a semiconductor device is provided, including a lower structure, an upper structure, and an intermediate insulating structure between the lower structure and the upper structure. The lower structure may include: lower source / drain regions spaced apart from each other in a first direction; lower active layers spaced apart from each other in a vertical direction, the lower active layers being disposed between and connected to the lower source / drain regions; and a lower gate structure extending in a second direction perpendicular to the first direction, the lower gate structure including portions respectively disposed above the lower active layers. The upper structure may include: upper source / drain regions spaced apart from each other in the first direction, the upper source / drain regions vertically overlapping the lower source / drain regions; upper active layers spaced apart from each other in a vertical direction, the upper active layers being disposed between and connected to the upper source / drain regions, the upper active layers vertically overlapping the lower active layers; and an upper gate structure extending in the second direction, the upper gate structure including portions respectively disposed below the upper active layers, the upper gate structure vertically overlapping the lower gate structure. The intermediate insulation structure may include: a barrier structure disposed on the lower structure, the barrier structure including a barrier pattern and a barrier insulation layer surrounding the barrier pattern; and an insulation structure disposed between the barrier structure and the upper structure, the insulation structure including an insulation pattern and an insulating pad surrounding the insulation pattern. The thickness of the barrier structure may be greater than the thickness of the insulation structure. Attached Figure Description

[0008] The above and other aspects, features, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a plan view of a semiconductor device according to an example embodiment;

[0010] Figures 2A to 2C This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0011] Figures 3A to 3C This is a schematic partial enlarged view of a semiconductor device according to an example embodiment;

[0012] Figure 4A and Figure 4B This is a schematic partial enlarged view of a semiconductor device according to an example embodiment;

[0013] Figure 5A and Figure 5B This is a schematic partial enlarged view of a semiconductor device according to an example embodiment; and

[0014] Figure 6A and Figure 6B , Figure 7A and Figure 7B , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18C , Figures 19A to 19C , Figures 20A to 20C , Figures 21A to 21C , Figures 22A to 22C , Figures 23A to 23C and Figures 24A to 24C This is a cross-sectional view of a sequential process in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0015] In the following text, in addition to the reference numerals in the accompanying drawings, terms such as “top,” “upper,” “upper surface,” “above,” “bottom,” “lower,” “lower surface,” “below,” and “side surface” may also be understood as references based on the accompanying drawings. Terms such as “upper,” “middle,” and “lower” may be replaced by other terms (e.g., “first,” “second,” and “third”) and may be used to describe components as used herein. Terms such as “first,” “second,” and “third” may be used to describe various components, but the aforementioned components are not limited by the aforementioned terms, and “first component” may also be referred to as “second component.”

[0016] In the following description, preferred exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0017] Figure 1 This is a plan view of a semiconductor device according to an example embodiment.

[0018] Figures 2A to 2C This is a schematic cross-sectional view of a semiconductor device according to an example embodiment.

[0019] Figure 2A It shows along Figure 1 A cross-sectional view of the region intercepted by line I-I'. Figure 2B It shows along Figure 1 A cross-sectional view of the region intercepted by line II-II'. Figure 2C It shows along Figure 1 A cross-sectional view of the region intercepted by line III-III'.

[0020] Figures 3A to 3C This is a schematic partial enlarged view of a semiconductor device according to an example embodiment. Figure 3A yes Figure 2A A magnified view of a portion of region "A". Figure 3B yes Figure 2B A magnified view of a portion of region "B", and Figure 3C yes Figure 2C A magnified view of a portion of region "C".

[0021] Reference Figures 1 to 3C The semiconductor device 100 may include a lower structure, an intermediate insulating structure MD on the lower structure, and an upper structure on the intermediate insulating structure MD. The semiconductor device 100 may also include a contact structure 180, a gate contact structure 190, and upper and lower interlayer insulating layers 191, 192, 193, 194, 195, 196, 197, and 198.

[0022] As used herein, the first direction may refer to the X direction and the second direction may refer to the Y direction, but the inventive concept is not limited thereto. For example, in an exemplary embodiment, the first direction may refer to the Y direction and the second direction may refer to the X direction.

[0023] As used herein, the “first structure” and “second structure” described in the claims may be referred to as the “lower structure” and “upper structure”, respectively; the “first gate structure” and “first source / drain region” may be referred to as the “lower gate structure” and “lower source / drain region”; and the “second gate structure” and “second source / drain region” may be referred to as the “upper gate structure” and “upper source / drain region”.

[0024] The lower structure may include: a lower gate structure 160L extending in a second direction Y; a lower channel layer 140L spaced apart from each other in a third direction Z perpendicular to the first direction X and the second direction Y, the lower channel layer 140L being surrounded by the lower gate structure 160L; and a lower source / drain region 150A disposed on at least one side of the lower channel layer 140L, the lower source / drain region 150A being connected to the lower channel layer 140L. In an example embodiment, the lower channel layer 140L may be referred to as the lower active layer.

[0025] The upper structure may include: an upper gate structure 160U disposed on a lower gate structure 160L and an intermediate insulating structure MD, the upper gate structure 160U extending in a second direction Y; upper channel layers 140U spaced apart from each other in a third direction Z, the upper channel layers 140U being surrounded by the upper gate structure 160U; and upper source / drain regions 150B disposed on at least one side of the upper channel layer 140U, the upper source / drain regions 150B being connected to the upper channel layer 140U. In an example embodiment, the upper channel layer 140U may be referred to as an upper active layer.

[0026] The lower gate structure 160L and the upper gate structure 160U can be collectively referred to as gate structure 160. The lower channel layer 140L and the upper channel layer 140U can be collectively referred to as channel layer 140. The lower source / drain region 150A and the upper source / drain region 150B can be collectively referred to as source / drain region 150.

[0027] Semiconductor device 100 may include a transistor having a multi-bridge channel FET (MBCFET™) structure, which is a fully all-around gate field-effect transistor. According to an example embodiment, the semiconductor device may include a transistor having a complementary FET (CFET) structure.

[0028] The gate structure 160 may include a lower gate structure 160L and an upper gate structure 160U.

[0029] The gate structure 160 may be disposed on the channel structure 140 to intersect the channel structure 140 and extend in a second direction (e.g., the Y direction).

[0030] The lower gate structure 160L may include a lower gate electrode 163L, a lower gate dielectric layer 162L between the lower gate electrode 163L and the first to third lower channel layers 141L, 142L, and 143L, and a lower gate spacer layer 164L on the side surface of the lower gate electrode 163L. The lower gate structure 160L may extend in a second direction Y perpendicular to the first direction X, and may include portions disposed above the lower channel layers 140L. The lower gate electrode 163L may include portions disposed above the first to third lower channel layers 141L, 142L, and 143L.

[0031] The upper gate structure 160U may include an upper gate electrode 163U, an upper gate dielectric layer 162U between the upper gate electrode 163U and the first to third upper channel layers 141U, 142U, and 143U, and an upper gate spacer layer 164U on the side surface of the upper gate electrode 163U. The upper gate structure 160U may vertically overlap with the lower gate structure 160L. The upper gate structure 160U may extend in the second direction Y and may include portions disposed below the upper channel layers 140U. The gate spacer layer 164U may be disposed on both sides of the upper gate electrode 163U on the upper channel layer 140U. The upper gate electrode 163U may include portions disposed below the first to third upper channel layers 141U, 142U, and 143U.

[0032] The lower gate dielectric layer 162L can be disposed between the intermediate insulating structure MD and the lower gate electrode 163L, and between the lower channel layer 140L and the lower gate electrode 163L.

[0033] The upper gate dielectric layer 162U can be disposed between the intermediate insulating structure MD and the upper gate electrode 163U, and between the upper channel layer 140U and the upper gate electrode 163U.

[0034] The lower gate dielectric layer 162L and the upper gate dielectric layer 162U may comprise oxides, nitrides, or high-k materials. High-k materials can refer to dielectric materials with a dielectric constant higher than that of silicon oxide (SiO2). High-k materials may be one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3). In an example embodiment, the lower gate dielectric layer 162L and the upper gate dielectric layer 162U may be formed as multilayer films.

[0035] The lower gate electrode 163L can be disposed below the intermediate insulating structure MD to fill the space between the first lower channel layer to the third lower channel layer 141L, 142L and 143L, and extend onto the lower channel layer 140L. The lower gate electrode 163L can be spaced apart from the first lower channel layer to the third lower channel layer 141L, 142L and 143L by the lower gate dielectric layer 162L.

[0036] The upper gate electrode 163U can be disposed above the intermediate insulating structure MD to fill the space between the first upper channel layer to the third upper channel layer 141U, 142U and 143U, and extend onto the upper channel layer 140U. The upper gate electrode 163U can be spaced apart from the first upper channel layer to the third upper channel layer 141U, 142U and 143U by the upper gate dielectric layer 162U.

[0037] The lower gate electrode 163L and the upper gate electrode 163U may comprise conductive materials, such as metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), and / or metallic materials (e.g., aluminum (Al), tungsten (W), or molybdenum (Mo)), or semiconductor materials (e.g., doped polycrystalline silicon). In some example embodiments, the lower gate electrode 163L and the upper gate electrode 163U may be formed as two or more multilayers. According to example embodiments, the lower gate electrode 163L and the upper gate electrode 163U may be formed of materials having suitable work functions, taking into account the desired threshold voltage. The lower gate electrode 163L may comprise an N-type work function layer, and the upper gate electrode 163U may comprise a P-type work function layer, but the inventive concept is not limited thereto. According to another example embodiment, the lower gate electrode 163L may comprise a P-type work function layer, and the upper gate electrode 163U may comprise an N-type work function layer.

[0038] A lower gate spacer layer 164L may be disposed below the lower channel layer 140L on both side surfaces of the lower gate electrode 163L. The lower gate spacer layer 164L may insulate the lower source / drain region 150A from the lower gate electrode 163L. In some example embodiments, the lower gate spacer layer 164L may have a multilayer structure. The lower gate spacer layer 164L may be formed of oxides, nitrides, and oxide oxynitrides, and specifically, may be formed of a low-k dielectric film.

[0039] The upper gate spacer layer 164U can insulate the upper source / drain region 150B and the upper gate electrode 163U from each other. In some example embodiments, the upper gate spacer layer 164U can have a multilayer structure. The upper gate spacer layer 164U can be formed of oxides, nitrides, and oxide oxynitrides, and specifically, it can be formed of a low-k dielectric film.

[0040] The channel structure 140 may include a lower channel layer 140L and an upper channel layer 140U.

[0041] The lower channel layer 140L may include a first to a third lower channel layer 141L, 142L, and 143L, which are a plurality of channel layers arranged sequentially and spaced apart from each other in a third direction (e.g., in the Z direction perpendicular to the first direction X and the second direction Y). The first to third lower channel layers 141L, 142L, and 143L may be disposed between and connected to the lower source / drain region 150A.

[0042] The upper channel layer 140U may include first to third upper channel layers 141U, 142U, and 143U, which are a plurality of channel layers sequentially disposed on the intermediate insulation structure MD and spaced apart from each other in a direction perpendicular to the upper surface of the intermediate insulation structure MD (e.g., in the Z direction). The first to third upper channel layers 141U, 142U, and 143U may be connected to the upper source / drain region 150B. The upper channel layer 140U may vertically overlap with the lower channel layer 140L.

[0043] The first upper channel layer to the third upper channel layer 141U, 142U and 143U may have a width in the first direction X that is substantially the same as or similar to the width of the upper gate structure 160U. The first lower channel layer to the third lower channel layer 141L, 142L and 143L may have a width in the first direction X that is substantially the same as or similar to the width of the lower gate structure 160L.

[0044] The first to third lower channel layers 141L, 142L, and 143L, and the first to third upper channel layers 141U, 142U, and 143U, can be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge). In exemplary embodiments, the number and shape of the first to third lower channel layers 141L, 142L, and 143L, and the first to third upper channel layers 141U, 142U, and 143U can be varied in various ways.

[0045] The source / drain region 150 may include a lower source / drain region 150A and an upper source / drain region 150B on the lower source / drain region 150A. The upper source / drain regions 150B may be spaced apart from each other in the first direction X and may vertically overlap with the lower source / drain region 150A.

[0046] The source / drain region 150 can be configured as either the source or drain region of the transistor. The source / drain region 150 can be disposed on both sides of the gate structure 160. The source / drain region 150 can be configured to cover the side surfaces of each of the lower channel layer 140L and the upper channel layer 140U.

[0047] Source / drain regions 150 may be semiconductor layers comprising silicon (Si) and / or silicon-germanium (SiGe). Source / drain regions 150 may include impurities of different types and / or concentrations. Lower source / drain regions 150A and upper source / drain regions 150B may have different conductivity types. According to an example embodiment, lower source / drain region 150A may include N-type doped silicon (Si), and upper source / drain region 150B may include P-type doped silicon-germanium (SiGe). However, the inventive concept is not limited thereto. According to another example embodiment, lower source / drain region 150A may include P-type doped silicon-germanium (SiGe), and upper source / drain region 150B may include N-type doped silicon (Si). In example embodiments, source / drain regions 150 may include multiple regions with different concentrations of elements and / or dopants.

[0048] The intermediate insulation structure MD may include an insulation structure M1 and a barrier structure M2 disposed between the lower and upper structures. See reference... Figure 3A , Figure 3B and Figure 3C To describe the insulation structure M1 and the barrier structure M2.

[0049] Reference Figure 3A An insulating structure M1 can be disposed below the upper structure. The insulating structure M1 may include an insulating pad 171 and an insulating pattern 172. The insulating pad 171 includes an upper portion 171_1 on the lower surface of the upper structure and a lower portion 171_2 below the upper portion 171_1. The insulating pattern 172 is located between the upper portion 171_1 and the lower portion 171_2 of the insulating pad 171. The side surfaces of the insulating pad 171 and the insulating pattern 172 can be aligned with each other. The upper portion 171_1 can contact the upper gate dielectric layer 162U. The side surface of the insulating structure M1 can be aligned with the side surface of the upper gate dielectric layer 162U.

[0050] like Figure 3A As shown, the barrier structure M2 may include a barrier insulating layer 173 and a barrier pattern 174. The barrier insulating layer 173 includes a first portion 173_1 extending in a first direction X on the upper surface of the lower structure, and a second portion 173_2 surrounding the lower surface and side surface of the insulating structure M1. The barrier pattern 174 is on the barrier insulating layer 173. Figure 3A As shown, the blocking pattern 174 can be configured to surround the insulating structure M1. A first portion 173_1 can contact the upper surface of the lower source / drain region 150A and the upper surface of the lower gate dielectric layer 162L. A second portion 173_2 can contact at least a portion of the lower surface of the upper source / drain region 150B. At least a portion of the blocking pattern 174 can contact at least a portion of the lower surface of the upper source / drain region 150B.

[0051] like Figure 3BAs shown, the insulating structure M1 can be disposed between the upper structure and the barrier structure M2. The insulating pad 171 can surround the upper surface, lower surface, and side surface of the insulating pattern 172. The insulating pad 171 can contact the upper gate dielectric layer 162U. The side surface of the insulating structure M1 can be aligned with the side surface of the upper gate dielectric layer 162U. In an example embodiment, the height H1 of the insulating structure M1 in the third direction Z can be about 10 nm or less. In an example embodiment, the height H1 of the insulating structure M1 in the third direction Z can be in the range of about 5 nm to about 10 nm. In an example embodiment, the height H1 of the insulating structure M1 in the third direction Z can be in the range of about 8 nm to about 10 nm.

[0052] like Figure 3B As shown, the barrier structure M2 can be disposed between the lower structure and the insulating structure M1. The barrier insulating layer 173 can surround the upper surface, lower surface, and side surface of the barrier pattern 174. The barrier insulating layer 173 can contact the lower gate dielectric layer 162L. The side surface of the barrier structure M2 can be aligned with the side surface of the insulating structure M1 and the side surface of the lower gate dielectric layer 162L. In the example embodiment, the height H2 of the barrier structure M2 in the third direction Z can be greater than the height H1 of the insulating structure M1 in the third direction Z. From another perspective, the insulating structure M1 can be disposed at the upper end of the intermediate insulating structure MD. Here, the height H2 of the barrier structure M2 in the third direction Z can refer to the height of the barrier structure M2 between the lower structure and the insulating structure M1.

[0053] Reference Figure 3B The thickness d1 of the insulating pattern 172 can be smaller than the thickness d2 of the blocking pattern 174. The relationship between the thickness d1 of the insulating pattern 172 and the thickness d2 of the blocking pattern 174 can be applied in essentially the same manner. Figure 3A and Figure 3C The semiconductor device shown. The width of the insulating pattern 172 in the second direction Y can be greater than the width of the blocking pattern 174 in the second direction Y. The fact that the width of the insulating pattern 172 in the second direction Y is greater than the width of the blocking pattern 174 in the second direction Y can be understood as because the thickness d1 of the insulating pattern 172 is less than the thickness d2 of the blocking pattern 174.

[0054] Reference Figure 3C The barrier insulating layer 173 may surround the lower and side surfaces of the barrier pattern 174 between the lower source / drain region 150A and the upper source / drain region 150B. An insulating pad 171 may be disposed on the barrier insulating layer 173, and an insulating pattern 172 may be disposed on the insulating pad 171.

[0055] The insulating structure M1 and the barrier structure M2 may include insulating materials. For example, the insulating structure M1 and the barrier structure M2 may include silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. In an example embodiment, the insulating pad 171 may include silicon nitride. In an example embodiment, the insulating pattern 172 may include silicon carbonitride. In an example embodiment, the barrier insulating layer 173 may include silicon nitride. In an example embodiment, the barrier pattern 174 may include silicon oxide.

[0056] The contact structure 180 may include a lower contact structure 180L electrically connected to the lower source / drain region 150A and an upper contact structure 180U electrically connected to the upper source / drain region 150B.

[0057] Contact structure 180 may be disposed on source / drain region 150. In some example embodiments, contact structure 180 may be configured to have a length in the second direction Y that is greater than the length of source / drain region 150 in the second direction Y. Contact structure 180 may be configured to recess source / drain region 150 to a predetermined depth.

[0058] The lower contact structure 180L can penetrate at least a portion of the interlayer insulation layer 195, can contact the lower source / drain region 150A, and can apply an electrical signal to the lower source / drain region 150A.

[0059] The upper contact structure 180U may include a first upper contact structure 180U1 and a second upper contact structure 180U2. The first upper contact structure 180U1 may penetrate at least a portion of the interlayer insulating layer 191, may contact a first upper source / drain region in the upper source / drain region 150B, and may apply an electrical signal to the first upper source / drain region. The second upper contact structure 180U2 may penetrate at least a portion of the interlayer insulating layer 191, a second upper source / drain region in the upper source / drain region 150B, and the intermediate insulating structure MD, may contact a lower source / drain region 150A, and may apply an electrical signal to the lower source / drain region 150A. The second upper contact structure 180U2 may include a conductive material layer and a barrier layer on the outer surface of the conductive material layer.

[0060] The contact structure 180 may also include a contact via structure 180C on the upper contact structure 180U and the lower contact structure 180L. For example, at least a portion of the contact via structure 180C may be disposed above the upper contact structure 180U, and a portion of the contact via structure 180C may be disposed below the lower contact structure 180L.

[0061] The gate contact structure 190 may include a lower gate contact structure 190L and an upper gate contact structure 190U. The lower gate contact structure 190L may contact the lower gate electrode 163L, and the upper gate contact structure 190U may contact the upper gate electrode 163U. The shape and material of the gate contact structure 190 may be similar to those of the contact structure 180, but the inventive concept is not limited thereto. According to an example embodiment, each of the lower gate contact structure 190L and the upper gate contact structure 190U may include a conductive material layer and a barrier layer on the outer surface of the conductive material layer. The upper surface of the gate contact structure 190 may be substantially coplanar with the upper surface of the contact via structure 180C.

[0062] The first to fourth upper interlayer insulating layers 191, 192, 193 and 194 may include at least one of, for example, oxides, nitrides, oxynitrides and low-k dielectrics.

[0063] The first to third upper interlayer insulating layers 191, 192, and 193 can be configured to cover the upper source / drain region 150B and the upper gate structure 160U. The fourth upper insulating layer 194 can cover the first to third upper interlayer insulating layers 191, 192, and 193.

[0064] The first to fourth lower interlayer insulating layers 195, 196, 197 and 198 may include at least one of, for example, oxides, nitrides, oxynitrides and low-k dielectrics.

[0065] The first to third lower interlayer insulating layers 195, 196, and 197 can be configured to cover the lower source / drain region 150A and the lower gate structure 160L. A fourth lower interlayer insulating layer 198 can cover the first to third lower interlayer insulating layers 195, 196, and 197.

[0066] The semiconductor device 100 of this invention may further include interconnect structures disposed above the contact via structure 180C and the gate contact structure 190, respectively. For example, the interconnect structure may be defined as including a first interconnect on the contact via structure 180C and a second interconnect on the gate contact structure 190.

[0067] In this invention, an intermediate insulating structure MD with a predetermined thickness or less can be disposed between the lower and upper structures to prevent potential degradation between the intermediate insulating structure MD and the lower structure, and between the intermediate insulating structure MD and the upper structure. In this invention, degradation can include degradation due to lattice differences between adjacent structures. For example, to minimize and prevent degradation, the thickness of the insulating structure M1 of the intermediate insulating structure MD can be less than the thickness of the blocking structure M2 of the intermediate insulating structure MD. The thickness of the insulating structure M1 can be about 10 nm or less; for example, the thickness of the insulating structure M1 can be in the range of about 5 nm to about 10 nm.

[0068] Figure 4A and Figure 4B This is a schematic partial enlarged view of the semiconductor device 100A according to an example embodiment. Figure 4A yes Figure 2A A magnified view of a portion of region "A", and Figure 4B yes Figure 2B A magnified view of a portion of region "B".

[0069] Reference Figure 4A and Figure 4B In addition to the semiconductor device 100A including the insulating structure M1 with curved side surfaces, the semiconductor device 100A can be compared with the reference... Figures 1 to 3C The semiconductor devices described are essentially the same or similar.

[0070] In this example embodiment, the side surface of the insulating structure M1 may have a curved shape. For example, the side surface of the insulating structure M1 may have a concave shape toward the center of the insulating structure M1. Therefore, at least a portion of the barrier insulating layer 173 may also have a curved cross-sectional shape (see [link]). Figure 4A For example, the portion of the second part 173_2 of the barrier insulation layer 173 that contacts the side surface of the insulation structure M1 may have a curved cross-sectional shape.

[0071] Figure 5A and Figure 5B This is a schematic partial enlarged view of the semiconductor device 100B according to an example embodiment. Figure 5A yes Figure 2A A magnified view of a portion of region "A", and Figure 5B yes Figure 2C A magnified view of a portion of region "C".

[0072] Reference Figure 5A and Figure 5B In addition to the blocking pattern 174 including a recessed portion having a downward-facing structure, the semiconductor device 100B can be compared with a reference. Figures 1 to 3C The semiconductor devices described are essentially the same or similar.

[0073] In this example embodiment, at least a portion of the upper surface of the blocking pattern 174 of the blocking structure M2 may have a recessed shape facing the lower structure. This recessed portion may vertically overlap with the lower source / drain region 150A and the upper source / drain region 150B. In this example embodiment, the lower surface of the upper source / drain region 150B may have a convex shape facing the lower structure.

[0074] Figure 6A and Figure 6B , Figure 7A and Figure 7B , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18C , Figures 19A to 19C , Figures 20A to 20C , Figures 21A to 21C , Figures 22A to 22C , Figures 23A to 23C and Figures 24A to 24C This is a cross-sectional view of a sequential process in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0075] Reference Figure 6A and Figure 6B A lower stack LS, an intermediate stack MS on the lower stack LS, and an upper stack US on the intermediate stack MS can be sequentially formed on the substrate 101.

[0076] Substrate 101 may have an upper surface extending in a first direction X and a second direction Y. Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may be configured as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a SeOI (SEM) layer, etc.

[0077] The lower stack LS may include alternately stacked lower sacrificial layer 120L and lower channel layer 140L. The intermediate stack MS may include alternately stacked first buffer layer 140B1, intermediate sacrificial layer 120M, and second buffer layer 140B2. The upper stack US may include alternately stacked upper sacrificial layer 120U and upper channel layer 140U. In an example embodiment, the lower sacrificial layer 120L, intermediate sacrificial layer 120M, and upper sacrificial layer 120U may be collectively referred to as sacrificial layer 120.

[0078] The sacrificial layer 120 may have etch selectivity relative to the first to third lower trench layers 141L, 142L, and 143L, the first buffer layer 140B1 and the second buffer layer 140B2, and the first to third upper trench layers 141U, 142U, and 143U. In an example embodiment, the first to third lower trench layers 141L, 142L, and 143L, the first buffer layer 140B1 and the second buffer layer 140B2, and the first to third upper trench layers 141U, 142U, and 143U may comprise silicon (Si), and the sacrificial layer 120 may comprise silicon germanium (SiGe).

[0079] The first germanium concentration of the intermediate sacrificial layer 120M can be different from the second germanium concentration of each of the upper sacrificial layer 120U and the lower sacrificial layer 120L. For example, the first germanium concentration of the intermediate sacrificial layer 120M can be greater than the second germanium concentration of each of the upper sacrificial layer 120U and the lower sacrificial layer 120L.

[0080] In an example embodiment, the first germanium concentration can be from about 20 at% to 60 at%.

[0081] In an example embodiment, the first germanium concentration can be from about 30 at% to 50 at%.

[0082] In an example embodiment, the first germanium concentration may be from about 35 at% to 45 at%.

[0083] In an example embodiment, the second germanium concentration can be from about 15 at% to 20 at%.

[0084] In this invention, the intermediate sacrificial layer 120M can be configured as a single layer. Alternatively, the intermediate sacrificial layer 120M may not include multiple layers.

[0085] In this invention, the intermediate sacrificial layer 120M can be disposed between the first buffer layer 140B1 and the second buffer layer 140B2. Therefore, the intermediate sacrificial layer 120M may not contact the channel layers (e.g., 140U and 140L). Thus, potential degradation due to lattice differences between the intermediate sacrificial layer 120M and the channel layers (e.g., 140U and 140L) can be minimized or prevented.

[0086] A sacrificial layer 120, first to third lower channel layers 141L, 142L, and 143L, a first buffer layer 140B1 and a second buffer layer 140B2, and first to third upper channel layers 141U, 142U, and 143U can be formed by performing an epitaxial growth process using a substrate 101 as a seed. The thickness of the first buffer layer 140B1 can be greater than the thickness of each of the first to third lower channel layers and the first to third upper channel layers 141L, 142L, 143L, 141U, 142U, and 143U. The thickness of the second buffer layer 140B2 can be less than the thickness of each of the first to third lower channel layers and the first to third upper channel layers 141L, 142L, 143L, 141U, 142U, and 143U. The thickness of the second buffer layer 140B2 can be less than the thickness of the intermediate sacrificial layer 120M, and the thickness of the first buffer layer 140B1 can be greater than the thickness of the intermediate sacrificial layer 120M. The thickness of the intermediate sacrificial layer 120M can be about 10 nm or less. For example, the thickness of the intermediate sacrificial layer 120M can be about 5 nm to about 10 nm.

[0087] A mask M can be formed on the upper stack US. Subsequently, the mask M can be used to remove at least a portion of the lower stack LS, the intermediate stack MS, and the upper stack US and expose the upper surface of the substrate 101 to form a trench T1.

[0088] Reference Figure 7A and Figure 7B An isolation layer 110 defining an active region 105 can be formed in the trench T1, and an etch stop layer 202 covering the stacked US and the isolation layer 110 can be formed.

[0089] The isolation layer 110 can be formed using, for example, a shallow trench isolation (STI) process. The isolation layer 110 can expose the upper surface of the active region 105, and can partially expose the upper portion of the active region 105. The isolation layer 110 can be formed of an insulating material. The isolation layer 110 can be, for example, an oxide, a nitride, or a combination thereof.

[0090] The etch stop layer 202 can be formed to conformally cover the upper surface of the isolation layer 110, the side surface of the lower stacked LS, the side surface of the middle stacked MS, and the side and upper surfaces of the upper stacked US.

[0091] Reference Figures 8A to 8C A mask HM can be formed on the etch stop layer 202, and an opening region OR can be formed through the etch stop layer 202, which exposes at least a portion of the stacked US.

[0092] The mask HM may include a hard mask. The mask HM may include multiple layers, including a first layer HM1 and a second layer HM2 on top of the first layer HM1. At least a portion of the uppermost channel layer 143U in the upper channel layer 140U may be exposed through an opening region OR.

[0093] Reference Figures 9A to 9C The intermediate sacrificial layer 120M can be selectively removed, and an insulating pad 171 and an insulating pattern 172 can be formed.

[0094] Due to etching selectivity, the intermediate sacrificial layer 120M can be selectively removed. Subsequently, insulating pads 171 and insulating patterns 172 covering the mask HM can be formed. At least a portion of each of the insulating pads 171 and insulating patterns 172 can fill the portion where the intermediate sacrificial layer 120M has been removed. Subsequently, a molded structure 115 can be formed and partially removed to give it a top surface substantially identical to the top surface of the upper stack US.

[0095] Reference Figures 10A to 10C A first recessed portion RC1 may be formed through the upper stack US, insulating pad 171, and insulating pattern 172, exposing the second buffer layer 140B2. An insulating layer 177 may be formed covering the outer surface of the first recessed portion RC1.

[0096] The insulating structure M1, including the remaining insulating pad 171 and the insulating pattern 172, can be defined by the first recessed portion RC1.

[0097] Reference Figures 11A to 11C The first buffer layer can be removed through the first recessed portion RC1. Figure 10A (140B1) to form the second recessed portion RC2 exposed under the stacked LS.

[0098] Because the second recessed portion RC2 is formed, the horizontal portion of the insulating layer 177 can be removed.

[0099] Reference Figures 12A to 12C It can remove the insulation layer ( Figure 11A 177 in the middle).

[0100] Reference Figures 13A to 13C An insulating layer 179 may be formed covering the surfaces of the first recessed portion RC1 and the second recessed portion RC2, and a third recessed portion RC3 may be formed penetrating the under-stacked LS and the substrate 101. The third recessed portion RC3 may vertically overlap with the first recessed portion RC1. In an example embodiment, the first recessed portion to the third recessed portions RC1, RC2 and RC3 may be collectively referred to as recessed RC.

[0101] Because the third recessed portion RC3 is formed, a portion of the insulating layer 179 can be removed.

[0102] Reference Figures 14A to 14C It can be found in the third recessed part ( Figure 13A Impurity region 150H and lower source / drain region 150A are sequentially formed in RC3.

[0103] Reference Figures 15A to 15C It can remove the insulation layer ( Figure 14A (179).

[0104] Reference Figures 16A to 16C A barrier insulating layer 173 can be formed to cover the surfaces of the first recessed portion RC1 and the second recessed portion RC2.

[0105] Reference Figures 17A to 17C Insulating material can be filled into a portion of the first recessed portion RC1 and a portion of the second recessed portion RC2, and a blocking pattern 174 can be formed by removing a portion of the blocking insulating layer 173 and a portion of the insulating material.

[0106] Therefore, the barrier structure M2 can be defined to include the remaining barrier insulation layer 173 and the barrier pattern 174.

[0107] Reference Figures 18A to 18C It can be in the first recessed part ( Figure 17A The upper source / drain region 150B is formed in RC1. Subsequently, an insulating layer 175 covering the upper source / drain region 150B can be conformally formed on the mask HM.

[0108] Reference Figures 19A to 19C An opening area that can be defined between mask HMs ( Figure 18A Insulating layers 191 and 199 are formed in the OR, and the mask HM can be removed. Therefore, multiple opening portions OP1 can be defined to expose multiple channel layers 140. Insulating layer 191 may include silicon oxide, and insulating layer 199 may include silicon nitride.

[0109] Since the mask HM is removed, the upper and lower sacrificial layers can be exposed. Figure 18A (120U and 120L), and can use etch selectivity to remove the exposed upper and lower sacrificial layers ( Figure 18A (120U and 120L).

[0110] Reference Figures 20A to 20CThe dielectric layer 162U can be formed by depositing an insulating material on the surface of the multiple openings OP1, and the gate electrode 163 can be formed by filling the multiple openings OP1 with a conductive material. In the example embodiment, the gate electrode below the upper channel layers 141U, 142U, and 143U can be referred to as the upper gate electrode 163U, and the gate electrode above the lower channel layers 141L, 142L, and 143L can be referred to as the lower gate electrode 163L.

[0111] In an example embodiment, the upper gate electrode 163U may include an N-type work function layer. Specifically, the upper gate electrode 163U below the upper channel layers 141U, 142U, and 143U may include an N-type work function layer. An upper gate structure 160U may be defined, including an upper gate dielectric layer 162U, an upper gate electrode 163U, and an upper gate spacer layer 164U.

[0112] In an example embodiment, the lower gate electrode 163L may include a P-type work function layer. Specifically, the lower gate electrode 163L above the lower channel layers 141L, 142L, and 143L may include a P-type work function layer.

[0113] Subsequently, the remaining portion of the multiple openings OP1 can be filled with an insulating material to form an insulating layer 193. A portion of the insulating layer 193 can pass through the gate electrode 163 and extend into the isolation layer 110.

[0114] The insulation layer can be removed. Figure 19A A portion of (191 and 199) is used to expose the upper surfaces of insulating layers 191 and 193. Insulating layer 193 may include silicon nitride.

[0115] Reference Figures 21A to 21C It can form an upper contact structure 180U and an upper gate contact structure 190U.

[0116] A first upper contact structure 180U1 may be formed through insulating layers 191 and 175, and this first upper contact structure 180U1 contacts the upper source / drain region 150B. A second upper contact structure 180U2 may be formed through insulating layers 191 and 175 and the upper source / drain region 150B, and this second upper contact structure 180U2 contacts the lower source / drain region 150A.

[0117] Subsequently, an insulating layer 194 covering the upper contact structure 180U can be formed, and a contact via structure 180C passing through the insulating layer 194 and an upper gate contact structure 190U passing through the insulating layers 193 and 194 can be formed. The contact via structure 180C is connected to the upper contact structure 180U, and the upper gate contact structure 190U is connected to the upper gate electrode 163U.

[0118] Reference Figures 22A to 22CThe lower region of substrate 101 can be removed to expose the lower surface 150H_LS of impurity region 150H.

[0119] Reference Figures 23A to 23C An insulating layer 195 can be formed by removing the impurity region 150H and filling it with insulating material.

[0120] The insulating layer 195 may include silicon oxide.

[0121] Reference Figures 24A to 24C This can form the bottom gate structure 160L.

[0122] The substrate can be removed ( Figure 23A The lower gate dielectric layer 162L is exposed (101). Subsequently, a lower gate spacer layer 164L, a lower gate dielectric layer 162L, and a lower gate electrode 163L can be formed to form the lowermost gate structure 160L. An insulating layer 196 can then be formed covering the lowermost gate structure 160L.

[0123] Then, return to the reference. Figure 2A This can form a lower contact structure 180L and a lower gate contact structure 190L.

[0124] A lower contact structure 180L can be formed through the insulating layer 195, and the lower contact structure 180L contacts the lower source / drain region 150A.

[0125] Subsequently, an insulating layer 198 covering the lower contact structure 180L can be formed, and a contact via structure 180C passing through the insulating layer 198 and a lower gate contact structure 190L passing through the insulating layers 198 and 196 can be formed. The contact via structure 180C is connected to the lower contact structure 180L, and the lower gate contact structure 190L is connected to the lower gate electrode 163L.

[0126] According to exemplary embodiments of the present invention, a semiconductor device with improved reliability and enhanced performance, as well as a method for manufacturing the semiconductor device, can be provided.

[0127] Specifically, according to exemplary embodiments of the present invention, a semiconductor device including an intermediate insulating structure having a predetermined thickness or less can be provided.

[0128] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: sequentially forming a lower stack having an alternately stacked lower sacrificial layer and a lower channel layer, an intermediate stack having a first buffer layer, an intermediate sacrificial layer and a second buffer layer, and an upper stack having an alternately stacked upper sacrificial layer and an upper channel layer on a substrate; removing the intermediate sacrificial layer of the intermediate stack and forming a preliminary insulating structure including an insulating pad and an insulating pattern; sequentially forming a first recessed portion through the upper stack and the preliminary insulating structure and exposing the first buffer layer, removing the first buffer layer and exposing a second recessed portion of the lower stack, and a third recessed portion through the lower stack and the substrate—the first recessed portion defining the insulating structure from the preliminary insulating structure, and the third recessed portion vertically overlapping the first recessed portion; forming a lower source / drain region in the third recessed portion; forming a barrier structure including a barrier insulating layer and a barrier pattern in the second recessed portion; and forming an upper source / drain region in the first recessed portion.

[0129] The germanium concentration in the intermediate sacrificial layer can be greater than that in the lower and upper trench layers.

[0130] The thickness of the intermediate sacrificial layer can be in the range of about 5 nm to about 10 nm.

[0131] The thickness of the first buffer layer can be less than the thickness of each of the upper sacrificial layers, and the thickness of the second buffer layer can be greater than the thickness of each of the lower sacrificial layers.

[0132] The insulating pad may cover the upper and lower surfaces of the insulating pattern and may surround at least a portion of the side surfaces of the insulating pattern.

[0133] The barrier insulation layer may cover the upper surface of the lower stack, as well as the lower and side surfaces of the insulation structure, and may surround at least a portion of the barrier pattern.

[0134] At least a portion of the upper surface of the blocking pattern can contact the lower surface of the upper source / drain region.

[0135] The insulating pad may include silicon nitride, and the insulating pattern may include silicon carbonitride.

[0136] The barrier insulating layer may include silicon nitride, and the barrier pattern may include silicon oxide.

[0137] The method may also include removing the upper and lower sacrificial layers and forming a gate structure.

[0138] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Lower structure; Upper structure; as well as An intermediate insulating structure is located between the lower structure and the upper structure. The lower structure includes: The lower source / drain regions are spaced apart from each other in the first direction; Lower active layers, vertically spaced apart, are disposed between the lower source / drain regions and connected to the lower source / drain regions; and The lower gate structure extends in a second direction perpendicular to the first direction, and the lower gate structure includes portions respectively disposed above the lower active layer. The upper structure includes: The upper source / drain regions are spaced apart from each other in the first direction, and the upper source / drain regions vertically overlap with the lower source / drain regions; An upper active layer is spaced apart from each other in the vertical direction, the upper active layer is disposed between and connected to the upper source / drain regions, and the upper active layer vertically overlaps the lower active layer; and An upper gate structure extends in the second direction, the upper gate structure including portions respectively disposed below the upper active layer, the upper gate structure vertically overlapping the lower gate structure, and... The intermediate insulation structure includes: An insulating structure is located below the upper structure; and A barrier structure includes a barrier insulating layer on the lower structure and a barrier pattern disposed above the barrier insulating layer, the barrier pattern surrounding the insulating structure and contacting the lower surface of the upper source / drain region.

2. The semiconductor device according to claim 1, wherein, The insulating structure includes: An insulating liner, comprising an upper portion on the lower surface of the upper structure and a lower portion below the upper portion; and An insulating pattern is located between the upper and lower portions of the insulating liner.

3. The semiconductor device according to claim 1, wherein, The side surface of the insulating structure has a concave shape facing the center of the insulating structure.

4. The semiconductor device according to claim 2, wherein, The insulating pad comprises silicon nitride, and The insulating pattern comprises silicon carbonitride.

5. The semiconductor device according to claim 1, wherein, The thickness of the insulating structure is in the range of 5 nm to 10 nm.

6. The semiconductor device according to claim 1, wherein, The barrier insulating layer of the barrier structure includes a first portion extending in the first direction and disposed on the upper surface of the lower structure.

7. The semiconductor device according to claim 6, wherein, The barrier insulation layer further includes a second portion disposed between the insulation structure and the barrier pattern, the second portion covering the side surface and the bottom surface of the insulation structure.

8. The semiconductor device according to claim 7, wherein, The second portion of the barrier insulating layer contacts the lower surface of the upper source / drain region.

9. The semiconductor device according to claim 1, wherein, At least a portion of the upper surface of the blocking pattern of the blocking structure has a recessed shape facing the lower structure.

10. The semiconductor device according to claim 1, wherein, The barrier insulating layer comprises silicon nitride, and The blocking pattern comprises silicon oxide.

11. The semiconductor device according to claim 1, wherein, The upper source / drain region and the lower source / drain region have different conductivity types.

12. The semiconductor device according to claim 1, further comprising: A first upper contact structure is disposed on the first upper source / drain region within the upper source / drain region, and the first upper contact structure is connected to the first upper source / drain region; as well as A lower contact structure is disposed below the lower source / drain region, and the lower contact structure is connected to the lower source / drain region.

13. The semiconductor device according to claim 12, further comprising: A second upper contact structure is disposed on the second upper source / drain region within the upper source / drain region. The second upper contact structure passes through the second upper source / drain region and the blocking structure, and is connected to the lower source / drain region.

14. The semiconductor device according to claim 12, further comprising: An upper gate contact structure is disposed on the upper gate structure, and the upper gate contact structure is electrically connected to the upper gate electrode of the upper gate structure; as well as A lower gate contact structure is disposed below the lower gate structure, and the lower gate contact structure is electrically connected to the lower gate electrode of the lower gate structure.

15. A semiconductor device, comprising: First structure; A blocking structure is provided on the first structure; An insulating structure on the barrier structure; as well as The second structure, on the insulating structure The first structure includes: The first source / drain regions are spaced apart from each other in the first direction; First active layers, vertically spaced apart, are disposed between the first source / drain regions and connected to the first source / drain regions; and A first gate structure extends in a second direction perpendicular to the first direction, and the first gate structure includes portions respectively disposed above the first active layer. The second structure includes: The second source / drain regions are spaced apart from each other in the first direction, and the second source / drain regions vertically overlap with the first source / drain regions; A second active layer, spaced apart from each other in the vertical direction, is disposed between and connected to the second source / drain regions, and vertically overlaps the first active layer; and A second gate structure extends in the second direction and includes portions disposed below the second active layer. The second gate structure vertically overlaps the first gate structure. The blocking structure includes: Blocking patterns; and A barrier insulating layer surrounds the barrier pattern on the first structure, and The insulating structure includes: Insulating patterns; and An insulating pad surrounds the insulating pattern on the barrier structure.

16. The semiconductor device according to claim 15, wherein, The barrier insulating layer surrounds the lower surface, side surface, and upper surface of the barrier pattern. The insulating pad surrounds the lower surface, side surface, and upper surface of the insulating pattern, and The upper surface of the barrier insulation layer is in contact with the lower surface of the insulating pad.

17. The semiconductor device according to claim 15, wherein, The thickness of the barrier insulation layer is greater than the thickness of the insulating pad.

18. The semiconductor device according to claim 15, wherein, The width of the insulating pattern in the second direction is greater than the width of the blocking pattern in the second direction.

19. A semiconductor device, comprising: Lower structure; Upper structure; as well as An intermediate insulating structure is located between the lower structure and the upper structure. The lower structure includes: The lower source / drain regions are spaced apart from each other in the first direction; Lower active layers, vertically spaced apart, are disposed between and connected to the lower source / drain regions; and The lower gate structure extends in a second direction perpendicular to the first direction, and the lower gate structure includes portions respectively disposed above the lower active layer. The upper structure includes: The upper source / drain regions are spaced apart from each other in the first direction, and the upper source / drain regions vertically overlap with the lower source / drain regions; An upper active layer is spaced apart from each other in the vertical direction, the upper active layer is disposed between and connected to the upper source / drain regions, and the upper active layer vertically overlaps the lower active layer; and An upper gate structure extends in the second direction, the upper gate structure including portions respectively disposed below the upper active layer, the upper gate structure vertically overlapping the lower gate structure. The intermediate insulation structure includes: A barrier structure, disposed on the lower structure, the barrier structure comprising a barrier pattern and a barrier insulating layer surrounding the barrier pattern; and An insulating structure is disposed between the barrier structure and the upper structure, the insulating structure comprising an insulating pattern and an insulating pad surrounding the insulating pattern, and The thickness of the barrier structure is greater than the thickness of the insulation structure.

20. The semiconductor device of claim 19, further comprising: A first insulating layer is located between the lower structure and the barrier structure; as well as A second insulating layer is located between the upper structure and the insulating structure.

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