Integrated circuit (ic) devices and methods of forming the same

Abstract

Embodiments of the present invention provide an integrated circuit device, comprising: a semiconductor layer portion having a front side surface and a back side surface, wherein the back side surface is spaced apart from the front side surface in a first direction, and the front side surface and the back side surface each extend in a second direction at least laterally to the first direction; and a first diode, comprising: a first doped region disposed in the semiconductor layer portion; a second doped region disposed in the semiconductor layer portion and spaced apart from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region; wherein the first doped region is closer to the front side surface than the second doped region, and the first doped region and the second doped region are offset from each other in the second direction. Embodiments of the present invention also provide a method for forming an integrated circuit device.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to integrated circuit (IC) devices and methods of forming the same. Background Technology

[0002] To fabricate vertical diodes in a complementary field-effect transistor (CFET) process, implantation techniques from CMOS processes can be utilized. However, limitations in layer spacing can affect diode performance, including its breakdown voltage. Summary of the Invention

[0003] An embodiment of the present invention provides an integrated circuit device, comprising: a semiconductor layer portion having a front side surface and a back side surface, wherein the back side surface is spaced apart from the front side surface in a first direction, and the front side surface and the back side surface each extend in a second direction at least laterally to the first direction; and a first diode, comprising: a first doped region disposed in the semiconductor layer portion; a second doped region disposed in the semiconductor layer portion and spaced apart from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region; wherein the first doped region is closer to the front side surface than the second doped region, and the first doped region and the second doped region are offset from each other in the second direction.

[0004] Another embodiment of the present invention provides an integrated circuit (IC) device, comprising: a semiconductor layer having a top surface and a bottom surface, the top surface and the bottom surface being oriented in a first direction and extending in at least a second direction perpendicular to the first direction; a complementary field-effect transistor (CFET) formed in the semiconductor layer, the CFET including a top field-effect transistor and a bottom field-effect transistor disposed below the top field-effect transistor along the first direction; and a semiconductor device formed in the semiconductor layer, the semiconductor device comprising: a first doped region disposed in the semiconductor layer; a second doped region disposed in the semiconductor layer and separated from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region; the first doped region being disposed at the top surface and the second doped region being disposed at the bottom surface, the first doped region and the second doped region being offset from each other in the second direction.

[0005] Another embodiment of the present invention provides a method for forming an integrated circuit (IC) device, comprising: forming a semiconductor layer having a top surface and a bottom surface, the semiconductor layer comprising a sequence of semiconductor layers stacked along a first direction, the semiconductor layer extending at least in a second direction transverse to the first direction; forming a first semiconductor device in the semiconductor layer by: doping a first portion of the semiconductor layer at the top of the stacked semiconductor layer sequence; and doping a second portion of the semiconductor layer at the bottom of the stacked semiconductor layer sequence, the second portion being offset from the first portion in a direction parallel to the semiconductor layer; and forming a second semiconductor device comprising complementary field-effect transistors by forming a plurality of channels, the plurality of channels being respectively derived from corresponding layers of a subset of the stacked semiconductor layer sequence. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best provide a comprehensive understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A diode according to some embodiments is illustrated.

[0008] Figure 2 A diode according to certain additional embodiments is illustrated schematically.

[0009] Figure 3 A diode according to certain additional embodiments is illustrated schematically.

[0010] Figure 4 A diode according to certain additional embodiments is illustrated schematically.

[0011] Figure 5 The illustration schematically shows a configuration including multiple diodes according to certain additional embodiments.

[0012] Figure 6 , Figures 7A to 7H , Figure 7I , Figure 7J , Figure 7K , Figures 7A' to 7H' , Figure 7I' , Figure 7J' and Figure 7K' The schematic illustration shows the formation according to certain additional embodiments. Figure 2 The steps shown are to form a diode and simultaneously create a pair of complementary field-effect transistors (CFETs).

[0013] Figure 8A and Figure 8BThe process of forming a diode and simultaneously forming at least one field-effect transistor (FET, such as CFET) according to certain additional embodiments is outlined.

[0014] Figure 9 A bipolar junction transistor (BJT) according to certain additional embodiments is illustrated schematically. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component is formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] Diodes are used in certain circuits implemented by integrated circuits (ICs). In such ICs, diodes can be constructed within a semiconductor layer. Other semiconductor devices, such as transistors, can be formed in the same layer as the diode. In some IC structures with three-dimensional (3D) semiconductor devices, such as complementary field-effect transistors (CFETs), diodes (e.g., PIN diodes) can be formed along the thickness direction of the semiconductor layer, for example, where p-regions and n-regions are arranged opposite each other, spanning at least a portion of the semiconductor layer thickness. The semiconductor portion between the p-regions and n-regions can be intrinsic or lightly doped.

[0018] In some embodiments, the diode includes a p-region and an n-region, both disposed in a semiconductor layer having a top surface and a bottom surface. The top and bottom surfaces of the semiconductor layer extend substantially laterally in two dimensions (e.g., along the x and y directions) and are oriented along a third dimension (e.g., the z direction). The p-region and the n-region are disposed at different distances from the top surface (or bottom surface). That is, the top surface and the bottom surface are offset from each other in the third dimension (e.g., along the z direction). For example, one of the p-region and the n-region may be disposed at the top surface, while the other of the p-region and the n-region may be disposed at the bottom surface. In some embodiments, the top surface and the bottom surface are further offset from each other in a first and / or second dimension (e.g., along the x and / or y directions).

[0019] Figure 1 An example of a diode according to some embodiments is shown. The diode 100 in this example includes a laterally extending semiconductor layer 120, i.e., extending along the x and y directions. An n-region (heavily doped N+ region 130 in this example) is formed in the semiconductor layer 120 and located at the top surface of the semiconductor layer 120. A p-region (heavily doped P+ region 150 in this example) is formed in the semiconductor layer 120 and located at the bottom surface of the semiconductor layer 120. The diode 100 further includes a first conductive contact 140 connected to the N+ region 130 and a second conductive contact 160 connected to the P+ region 150 for connecting the diode 100 to other devices.

[0020] In this example, in addition to being offset from each other in the vertical direction (i.e., the z-direction), N+ region 130 and P+ region 150 are also offset from each other in the horizontal direction (x-direction in this case).

[0021] In this example, the semiconductor layer 120 of diode 100 includes stacked semiconductor wafers 122 and 124 with alternating compositions. In this example, semiconductor wafer 122 is silicon (Si), while semiconductor wafer 124 is made of silicon-germanium alloy (SiGe). Other compositions may be used depending on the application. Such structures can be used to fabricate a variety of devices, including, for example, gate-all-around (GAA) transistors and CFETs, as shown in other examples of this disclosure.

[0022] In some embodiments of this disclosure, certain drawbacks of diodes with directly perpendicularly arranged p- and n-regions can be mitigated by offsetting the p- and n-regions of the diode both vertically and laterally. For example, in some IC manufacturing processes, the p- and n-regions of a diode are formed by ion implantation. Limitations in the ability to control the implantation depth can lead to unacceptable uncertainty in the p- and n-region spacing (pn-pitch), or even punch-through. Furthermore, considering the number of semiconductor wafers in a semiconductor layer, the design choices for diodes with directly perpendicularly arranged p- and n-regions may be limited by pn-pitch requirements. Diodes with diagonally offset (i.e., vertically and laterally) p- and n-regions offer a wider range of design options and reduce the negative impact of process variations.

[0023] refer to Figure 2 Diode 200 is fabricated in semiconductor layer 220 using a process compatible with CFET, as described below. Diode 200 includes a positive (or bottom) electrode 130, in this example a heavily doped N+ region 130, formed in semiconductor layer 220 and located at the bottom surface of semiconductor layer 220. Diode 200 further includes a back-side (or top) electrode, in this example a heavily doped P+ region 150, formed in semiconductor layer 220 and located at the top surface of semiconductor layer 220. Diode 100 further includes a first conductive contact structure 240 connected to N+ region 130 and a second conductive contact structure 260 connected to P+ region 150 for connecting diode 200 to other devices. The first conductive contact structure 240 may include any suitable conductive material; in this example, it includes a metal-semiconductor alloy layer 242, vias 244 and 246, and contact pads 248. Similarly, the second conductive contact structure 260 may comprise any suitable conductive material; in this example, it includes a metal-semiconductor alloy layer 262, vias 264, 266, and contact pads 268. The diode 200 in this example further includes isolation regions 272, 274, 276 located at the bottom (or positive side) and isolation regions 292, 294, 296 located at the top (or back side).

[0024] In this example, semiconductor layer 220 is similar to Figure 1The semiconductor layer 120 shown includes stacked semiconductor sheets with alternating compositions. For example, sheet 222 may be silicon (Si), and sheet 224 may be a silicon-germanium alloy (SiGe). However, in this example, semiconductor layer 220 further includes a pseudo-semiconductor layer 226, which in some embodiments is germanium (Ge) or a silicon-germanium alloy (SiGe) with a higher germanium content than SiGe sheet 124. The sheets 222, 224 (frontside sheets) below the pseudo-semiconductor layer 226 may be substantially intrinsic, or at least a portion of the frontside sheets (e.g., Si sheet 122) may be doped, for example, with n-type doping. Similarly, the sheets 222, 224 (backside sheets) above the pseudo-semiconductor layer 226 may be substantially intrinsic, or at least a portion of the backside sheets (e.g., Si sheet 222) may be doped, for example, with p-type doping.

[0025] exist Figure 2 In the example shown, diode 200 nominally occupies a width W, which is twice the spacing between laterally adjacent vias 244, 246, 264, and 266. In some embodiments, the lateral via spacing of the diode (e.g., diode 200) is the same as or a multiple thereof as the spacing between vias connecting to the source or drain of a transistor (e.g., a CFET) manufactured in the same IC. Therefore, the process for manufacturing diodes (including tooling) is more compatible with the manufacturing processes of other devices (e.g., transistors). This allows for certain manufacturing and / or design efficiencies.

[0026] In some other embodiments, for example Figure 3 The example shown is similar to diode 300. Figure 2 The diode 200 shown is an example of a diode 200, but wider. In this example, the n-region and p-regions 130, 150 are spaced three (3) via spacings laterally, instead of one spacing as in diode 200. The increased spacing provides the advantage of reducing the probability of junction breakdown and lowering parasitic capacitance.

[0027] In some further embodiments, for example Figure 4 The example shown is similar to diode 400. Figure 2 The diode shown is 200, but the n+ and p+ regions 130 and 150 are smaller. The dimensions can be selected based on the desired electrical characteristics of the diode. Variations in the dimensions of the n-region and / or p-region can be achieved by any suitable method. For example, when the n-region and / or p-region are formed by ion implantation, the implantation energy and / or dose and / or number of implantation cycles can be selected to achieve the desired characteristics of the n-region and / or p-region.

[0028] In some further embodiments, for example Figure 5 The example shown, device 500 is similar to Figure 3 The diode 300 shown includes two diodes 502 and 504, each with different sizes for its n-region and p-region. In diode 502, the size of the N+ region 130 is smaller than the corresponding P+ region 150; in diode 504, the size of the p-region 530 is larger than the corresponding n-region 550. Such a configuration can be achieved through a more complex process than for uniformly sized n-regions and p-regions. For example, for n-regions and / or p-regions formed by ion implantation, any given side (front or back side) may require multiple implantation cycles: first forming smaller n-regions and / or p-regions, then blocking them to prevent further implantation to form larger n-regions and / or p-regions.

[0029] In some further embodiments, devices such as those exemplified above can be... Figure 6 , Figures 7A to 7H , Figure 7I , Figure 7J , Figure 7K , Figures 7A' to 7H' , Figure 7I' , Figure 7J' and Figure 7K' As shown and Figure 8A and Figure 8B Overview of the manufacturing process. Figure 6 The process 800 for manufacturing diodes is shown. Figure 8A and Figure 8B ) and the process for manufacturing CFETs 850 ( Figure 8A and Figure 8B The shared starting structure is 600. Figures 7A to 7H , Figure 7I , Figure 7J and Figure 7K The structures corresponding to each step of process 800 are shown; Figures 7A' to 7H' , Figure 7I' , Figure 7J' and Figure 7K' The structure corresponding to each step of process 850 is shown.

[0030] It should be noted that, although Figures 7A to 7H , Figure 7I , Figure 7J , Figure 7K , Figures 7A' to 7H' , Figure 7I' , Figure 7J' and Figure 7K' as well as Figure 8A and Figure 8B The schematic diagram illustrates and outlines the processes for manufacturing diodes and CFETs in a largely parallel manner, but the two devices can be manufactured substantially simultaneously or independently.

[0031] The processes for manufacturing diodes according to certain embodiments of this disclosure share several common steps with certain processes for manufacturing CFETs. Examples of CFET manufacturing processes (partially including obtaining...) Figure 2 The steps of the starting structure 600 shown can be found in U.S. Patent Nos. 12,119,271, 12,131,954, and 12,132,079. U.S. Patent Nos. 12,119,271, 12,131,954, and 12,132,079 are incorporated herein by reference in their entirety.

[0032] Figure 6 A common starting structure 600 for fabricating diodes and CFETs according to some embodiments is schematically illustrated. Structure 600 includes a substrate 610, which may be a silicon wafer extending substantially laterally in the xy plane. Strips or fins 612 are formed on the substrate 610, extending substantially vertically in the zx plane, each strip including a base 614 and a multilayer stack 620. The base 614 and the substrate 610 are covered by an isolation region 640. The top of the isolation region 640 and the multilayer stack 620 is covered by a dummy gate stack 650, which in this example includes a dummy gate dielectric layer 652, a dummy gate layer 654, and a mask layer 656.

[0033] The multilayer stack 620 in this example includes semiconductor wafers with alternating compositions. In this example, semiconductor wafer 622 is silicon (Si), while semiconductor wafer 624 is made of silicon-germanium alloy (SiGe). Other compositions may be used depending on the application. The multilayer stack 620 in this example further includes a dummy semiconductor layer 626, which in some embodiments is germanium (Ge) or a silicon-germanium alloy (SiGe) with a higher germanium content than SiGe wafer 624. The wafers 622, 624 (front-side wafers) below the dummy semiconductor layer 626 may be substantially intrinsic, or at least a portion of the front-side wafers (e.g., Si wafer 622) may be doped, for example, n-type doping. Similarly, the wafers 622, 624 (back-side wafers) above the dummy semiconductor layer 626 may be substantially intrinsic, or at least a portion of the back-side wafers (e.g., Si wafer 622) may be doped, for example, p-type doping. Doping may be performed during the formation of wafers 622, 624, or by other methods (e.g., ion implantation).

[0034] In this example, the common starting structure 600 can be used to fabricate diodes and CFETs. For example, the diodes and CFETs can be fabricated on the same multilayer stack 620 or different multilayer stacks 620.

[0035] Figures 7A to 7H , Figure 7I , Figure 7J , Figure 7K , Figures 7A' to 7H' , Figure 7I' , Figure 7J' and Figure 7K' The illustration in the image shows Figure 6 The A-A' cross section marked in the middle is the cross section taken along the zx plane passing through strip 612.

[0036] refer to Figure 7A , Figure 7A' and Figure 8A In steps 802 and 852, a channel is etched in the dummy gate stack 650, and a gate spacer layer 702 is deposited on the remaining portion of the dummy gate stack 650 of the diode fabrication process 800 and the CFET fabrication process 850.

[0037] refer to Figure 7B , Figure 7B' and Figure 8A In steps 804 and 854, for the CFET manufacturing process 850, the source and drain channels 706 are etched through the multilayer stack 620, but this is not done for the diode manufacturing process 800. For the diode manufacturing process 800, the device region is protected from etching by a protective layer (e.g., photoresist layer 704).

[0038] refer to Figure 7C , Figure 7C' and Figure 8A In steps 806 and 856, for diode fabrication process 800, ion implantation (N+ in this example) is performed in one channel of dummy gate stack 650 to form one electrode region of the diode; the other channel is covered by a hard mask 708 to prevent implantation under the opening.

[0039] For CFET fabrication process 850, semiconductor layer 624 is partially removed, for example, by etching, and the removed space is filled with insulating material to form spacer 712. Furthermore, dummy semiconductor layer 626 is completely removed, for example, by etching, and the removed space is filled with insulating material to form isolation layer 726. The source / drain region 710 of the back-side transistor of the CFET is formed in channel 706. Subsequently, a contact etch stop layer (CESL) 716 and an interlayer dielectric (ILD) layer 718 are formed on the source / drain region 710. Subsequently, the source / drain region 714 of the front-side transistor of the CFET is formed.

[0040] refer to Figure 7D , Figure 7D' and Figure 8A For both diode manufacturing process 800 and CFET manufacturing process 850, in steps 808 and 858, CESL 730 and ILD layer 732 are formed in the channel of dummy gate stack 650, and the top of the structure is planarized by, for example, chemical mechanical polishing (CMP).

[0041] refer to Figure 7E, Figure 7E' and Figure 8A For both diode manufacturing process 800 and CFET manufacturing process 850, in steps 810 and 860, the remainder of the pseudo stack 650 is removed by an etching process, for example called PORM or IORM, to form an opening 734 on top of the multilayer stack 620.

[0042] refer to Figure 7F , Figure 7F' and Figure 8A In steps 812 and 862, for the CFET manufacturing process 850, the remaining portion of the semiconductor layer 624 is removed, for example, by etching, to form the opening 738. For the diode manufacturing process 800, a protective layer (e.g., a photoresist layer 736) is applied to prevent any material removal.

[0043] refer to Figure 7G , Figure 7G' and Figure 8B In steps 814 and 864, for both diode fabrication process 800 and CFET fabrication process 850, a metal gate (MG) 740 and a self-aligned gate cap (MG SAC) 742 are formed in the opening 734 at the top of the multilayer stack 620. Furthermore, for CFET fabrication process 850, a gate isolation layer 744 is deposited around the semiconductor wafer 622 in the opening created by removing the semiconductor layer 624. MG 740 is also formed in the remaining space vacated by the semiconductor wafer 624. Therefore, each gate 740 surrounds a FET channel formed by the semiconductor wafer 622.

[0044] refer to Figure 7H , Figure 7H' and Figure 8B In steps 816 and 866, for both diode manufacturing process 800 and CFET manufacturing process 850, the CESL 730 and ILD layer 732 are removed by etching, for example, to form the opening 746.

[0045] refer to Figure 7I , Figure 7I' and Figure 8B In steps 818 and 868, a first (positive) conductive contact structure 240 is formed for both diode manufacturing process 800 and CFET manufacturing process 850. In this example, the positive conductive contact structure 240 includes a metal-semiconductor alloy layer 242, vias 244 and 246, and contact pads 248. Furthermore, positive isolation regions 272, 274, and 276 are formed over the layer containing the gate spacer and opening 746. The metal-semiconductor alloy layer 242 and via 244 are formed in the opening 746; the via 246 is formed through the isolation regions 272 and 274; and the isolation region 276 is formed between the contact pads 248.

[0046] refer to Figure 7J , Figure 7J' and Figure 8B In steps 820 and 870, for both diode manufacturing process 800 and CFET manufacturing process 850, the base 614 of the strip or fin 612 is removed by, for example, polishing and / or etching. Subsequently, a gate structure 748, similar to the metal gate 740, is formed in steps similar to steps 814 and 864. Furthermore, an opening 750 is formed in an MD etching step similar to steps 816 and 866.

[0047] Furthermore, for diode manufacturing process 800, ion implantation (P+ in this example) is performed in one of the openings 750 to form the back electrode region of the diode; the other opening 750 is covered by a hard mask 752 to prevent implantation under the channel.

[0048] Finally, refer to Figure 7K , Figure 7K' and Figure 8B In steps 822 and 872, a second (back-side) conductive contact structure 260 is formed for both diode manufacturing process 800 and CFET manufacturing process 850. In this example, the back-side conductive contact structure 260 includes a metal-semiconductor alloy layer 262, vias 264 and 266, and contact pads 268. Furthermore, back-side isolation regions 292, 294, and 296 are formed below the layer containing the gate structure 748 and the opening 750 (relative to the orientation at the start of processes 800 and 850). The metal-semiconductor alloy layer 262 and the via 264 are formed in the opening 750; the via 266 is formed through the isolation regions 292 and 294; and the isolation region 296 is formed between the contact pads 268.

[0049] At the end of processes 800 and 850, the product is manufactured. Figure 7K , Figure 7K The diode 200 and CFET 790 are shown.

[0050] In other exemplary embodiments (not shown in the figures), the doped regions on both the front and back sides are connected to corresponding conductive contact structures located on the same side (front or back) of the semiconductor layer. For example, Figure 2 The doped region 150 on the back side of the diode 200 shown can be connected to the back contact pad through a through-hole that penetrates the thickness of the multilayer stack 220.

[0051] The principles illustrated in the above example can be applied to other embodiments. For example, in Figure 9In the illustrative example, other devices can be fabricated in a similar manner to those shown above. For example, a bipolar junction transistor (BJT) 900 can be fabricated substantially in the same manner as the PIN diode described above. For example, the ion implantations in steps 806 and 820 can be of the same type (both N+ or both P+), instead of having the front and back electrodes 930 and 950 of opposite types (e.g., N+ on the front and P+ on the back). Additional steps (not shown) can be performed to form (e.g., by ion implantation) a third doped region of the opposite type to regions 930 and 950 between regions 930 and 950, and to connect this third region via a conductive contact structure (e.g., conductive contact structure 990).

[0052] In summary, according to various aspects of this disclosure, an integrated circuit device includes: a semiconductor layer portion having a front side and a back side spaced apart from the front side in a first direction, the front side and the back side each extending in a second direction at least laterally to the first direction; and a first diode including: a first doped region disposed in the semiconductor layer portion; a second doped region disposed in the semiconductor layer portion and spaced apart from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region; the first doped region being closer to a top surface than the second doped region, and the first doped region and the second doped region being offset from each other in the second direction.

[0053] In some embodiments, the semiconductor layer portion includes a multilayer stack having layers with alternating compositions; the first doped region is an n-type or p-type doped region disposed on the front side surface of the multilayer stack; and the second doped region is a doped region of the opposite doping type to the first doped region disposed on the back side surface of the multilayer stack.

[0054] In some embodiments, the integrated circuit device further includes a field-effect transistor (FET) formed in the semiconductor layer portion, wherein the FET and the first diode share at least one subset of the layers of the multilayer stack.

[0055] In some embodiments, the alternating layers in the multilayer stack are first-type semiconductor layers; and the field-effect transistor includes a plurality of channels formed by respective first-type semiconductor layers.

[0056] In some embodiments, the integrated circuit device further includes: a complementary field-effect transistor (CFET) formed in a first portion of the semiconductor layer portion, the complementary field-effect transistor including a pair of field-effect transistors stacked in the first direction, wherein the semiconductor layer portion includes a multilayer stack having a first plurality of layers of a first type of semiconductor, the complementary field-effect transistor including a plurality of channels, each channel respectively including a portion of a corresponding layer of the first plurality of layers of the first type of semiconductor.

[0057] In some embodiments, the multilayer stack further includes a second portion comprising a second plurality of layers arranged alternately with the first plurality of layers, and the first diode is formed in the second portion.

[0058] In some embodiments, the first plurality of layers are silicon (Si) layers, and the second plurality of layers are silicon-germanium alloy layers.

[0059] In some embodiments, the first conductive contact connection structure includes a first contact pad disposed on the front side surface of the semiconductor layer, and the second contact connection structure includes a second contact pad disposed on the back side surface of the semiconductor layer.

[0060] In some embodiments, the semiconductor layer portion includes: a first plurality of layers; a second plurality of layers; and a third layer; the first plurality of layers, the second plurality of layers, and the third layer are formed in a stacked sequence, the third layer separating the first plurality of layers and the second plurality of layers, the first plurality of layers including alternating layers of a first semiconductor and a second semiconductor; the second plurality of layers including alternating layers of the first semiconductor and the second semiconductor; and the third layer being a third semiconductor.

[0061] In some embodiments, the first semiconductor is silicon (Si); the second semiconductor is a silicon-germanium alloy (SiGe); and the third semiconductor is germanium (Ge) or a silicon-germanium alloy with a higher germanium content than the second semiconductor.

[0062] In some embodiments, the first doped region and the second doped region have different sizes.

[0063] In some embodiments, the integrated circuit device further includes: a second diode, comprising: a third doped region disposed in the semiconductor layer portion; a fourth doped region disposed in the semiconductor layer portion and separate from the third doped region; a third conductive contact structure connected to the third doped region; and a fourth conductive contact structure connected to the fourth doped region; wherein the third doped region is closer to the positive side surface than the fourth doped region, and the third doped region and the fourth doped region are offset from each other in a second direction, wherein: the offset of the third doped region and the fourth doped region in the second direction is different from the offset of the first doped region and the second doped region in the second direction, or the first doped region and the third doped region have different dimensions. According to certain other aspects of this disclosure, an integrated circuit (IC) device includes: a semiconductor layer having a top surface and a bottom surface, the top surface and the bottom surface being substantially oriented along a first direction and extending substantially laterally in a second direction at least transverse to the first direction; a complementary field-effect transistor (CFET) formed in the semiconductor layer and including a top FET and a bottom FET disposed below the top FET along the first direction; and a semiconductor device formed in the semiconductor layer and including: a first doped region disposed in a portion of the semiconductor layer; a second doped region disposed in the portion of the semiconductor layer and spaced apart from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region; the first doped region being disposed at the top surface and the second doped region being disposed at the bottom surface, the first doped region and the second doped region being offset from each other in the second direction.

[0064] In some embodiments, the first doped region is an n-doped or p-doped region, and the second doped region is a doped region with a doping type opposite to that of the first doped region.

[0065] In some embodiments, the first doped region is an n-doped or p-doped region, and the second doped region is a doped region of the same doping type as the first doped region.

[0066] In some embodiments, the semiconductor device further includes a third doped region with a doping type opposite to that of the first doped region and the second doped region.

[0067] In some embodiments, the semiconductor layer includes a first plurality of layers of a first semiconductor, wherein the complementary field-effect transistor includes a plurality of channels, each channel comprising a portion of a corresponding layer of the first semiconductor.

[0068] According to certain further aspects of this disclosure, a method includes: forming a semiconductor layer having a top surface and a bottom surface, the semiconductor layer including a sequence of semiconductor layers stacked along a first direction, the semiconductor layer extending in a second direction at least laterally to the first direction; forming a first semiconductor device in the semiconductor layer by: doping a first portion of the semiconductor layer at the top of the stacked semiconductor layer sequence; and doping a second portion of the semiconductor layer at the bottom of the stacked semiconductor layer sequence, the second portion being offset from the first portion in a direction substantially parallel to the semiconductor layer; and forming a second semiconductor device including a CFET by forming a plurality of channels from a subset of the stacked semiconductor layer sequence.

[0069] In some embodiments, the formation of the first semiconductor device and the formation of the second semiconductor device are performed substantially simultaneously.

[0070] In some embodiments, the method further includes: forming a first conductive contact structure connected to the first portion on the top surface of the semiconductor layer, and forming a second conductive contact structure connected to the second portion on the top surface of the semiconductor layer.

[0071] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: The semiconductor layer portion has a front side surface and a back side surface, wherein the back side surface is spaced apart from the front side surface in a first direction, and the front side surface and the back side surface each extend in a second direction at least laterally to the first direction; as well as The first diode includes: A first doped region is disposed in the semiconductor layer portion; The second doped region is disposed in the semiconductor layer portion and spaced apart from the first doped region; A first conductive contact structure is connected to the first doped region; and A second conductive contact structure is connected to the second doped region; The first doped region is closer to the positive side surface than the second doped region, and the first doped region and the second doped region are offset from each other in the second direction.

2. The integrated circuit device according to claim 1, wherein: The semiconductor layer portion includes a multilayer stack, wherein the layers of the multilayer stack have an alternating composition; The first doped region is an n-type or p-type doped region and is disposed on the front side surface of the multilayer stack. as well as The second doped region is a doped region of the opposite type to the first doped region and is disposed on the back surface of the multilayer stack.

3. The integrated circuit device according to claim 2, further comprising: A field-effect transistor (FET) is formed in the semiconductor layer portion, and the FET and the first diode share at least one subset of the layers of the multilayer stack.

4. The integrated circuit device according to claim 3, wherein: The alternating layers in the multilayer stack are first-type semiconductor layers; and The field-effect transistor includes a plurality of channels formed by corresponding first-type semiconductor layers.

5. The integrated circuit device according to claim 1, further comprising: A complementary field-effect transistor (CFET) is formed in a first portion of the semiconductor layer portion, the complementary field-effect transistor comprising a pair of field-effect transistors stacked in the first direction. The semiconductor layer portion includes a multilayer stack having a first plurality of layers of a first type of semiconductor. The complementary field-effect transistor includes multiple channels, each channel comprising a portion of a corresponding layer of the first plurality of layers of the first type of semiconductor.

6. An integrated circuit (IC) device, comprising: A semiconductor layer having a top surface and a bottom surface, the top surface and the bottom surface being oriented in a first direction and extending in at least a second direction perpendicular to the first direction; A complementary field-effect transistor (CFET) is formed in the semiconductor layer, the complementary field-effect transistor including a top field-effect transistor and a bottom field-effect transistor disposed below the top field-effect transistor along the first direction; as well as A semiconductor device is formed in the semiconductor layer, the semiconductor device comprising: A first doped region is disposed in the semiconductor layer; The second doped region is disposed in the semiconductor layer and is separate from the first doped region; A first conductive contact structure is connected to the first doped region; and A second conductive contact structure is connected to the second doped region; The first doped region is disposed at the top surface, and the second doped region is disposed at the bottom surface, the first doped region and the second doped region being offset from each other in the second direction.

7. The integrated circuit (IC) device according to claim 13, wherein, The first doped region is an n-doped or p-doped region, and the second doped region is a doped region with the opposite doping type to the first doped region.

8. A method for forming an integrated circuit (IC) device, comprising: A semiconductor layer having a top surface and a bottom surface is formed, the semiconductor layer comprising a sequence of semiconductor layers stacked along a first direction, the semiconductor layer extending at least in a second direction transverse to the first direction; The first semiconductor device is formed in the semiconductor layer by doping a first portion of the semiconductor layer at the top of the stacked semiconductor layer sequence. The bottom surface of the stacked semiconductor layer sequence is doped with a second portion of the semiconductor layer, the second portion being offset from the first portion in a direction parallel to the semiconductor layer; as well as A second semiconductor device comprising complementary field-effect transistors is formed by forming multiple channels, the multiple channels being respectively derived from corresponding layers of a subset of the stacked semiconductor layer sequence.

9. The method according to claim 8, wherein, The formation of the first semiconductor device and the formation of the second semiconductor device are carried out substantially simultaneously.

10. The method of claim 8, further comprising: A first conductive contact structure connected to the first portion is formed on the top surface of the semiconductor layer, and a second conductive contact structure connected to the second portion is formed on the top surface of the semiconductor layer.

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