Integrated circuit die and method of forming the same

Abstract

An integrated circuit die and a method for forming the same are provided. The integrated circuit die may include an active region and a sealing ring region. The active region may include active circuitry. The sealing ring region may include a first epitaxial structure, a first interconnect structure located above a first side of the first epitaxial structure, and a second interconnect structure located on a second side of the first epitaxial structure. The first interconnect structure may include a first conductive tower extending through the first interconnect structure, and the second interconnect structure may include a second conductive tower extending through the second interconnect structure. The integrated circuit die may further include a first conductive contact electrically connecting the first conductive tower to the first side of the first epitaxial structure and a second conductive contact electrically connecting the second conductive tower to the second side of the first epitaxial structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to integrated circuit dies and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] By continuously reducing the minimum component size, the semiconductor industry is constantly improving the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), which allows more components to be integrated into a given area. However, as the minimum component size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] One embodiment of this application provides an integrated circuit die, comprising:

[0005] Active region, wherein the active region includes active circuitry; and

[0006] A sealing ring region, wherein the sealing ring region surrounds the active region in a top view, the sealing ring region comprising: a first epitaxial structure; a first interconnect structure located above a first side of the first epitaxial structure, wherein the first interconnect structure includes a first conductive tower extending through the first interconnect structure; a first conductive contact electrically connecting the first conductive tower to the first side of the first epitaxial structure; a second interconnect structure located on a second side of the first epitaxial structure, wherein the second side of the first epitaxial structure is opposite to the first side of the first epitaxial structure, and wherein the second interconnect structure includes a second conductive tower extending through the second interconnect structure; a second conductive contact electrically connecting the second conductive tower to the second side of the first epitaxial structure; a first semiconductor nanostructure along a sidewall of the first epitaxial structure; a gate structure located below the first semiconductor nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric layer, and wherein the gate electrode includes a titanium-based material; and a gate spacer along a sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer.

[0007] Another embodiment of this application provides an integrated circuit die, including: an active region, wherein the active region includes an active circuit; and

[0008] A sealing ring region, wherein the sealing ring region surrounds the active region in a top view, and wherein the sealing ring region is electrically isolated from the active region, the sealing ring region comprising: a first semiconductor structure; a first interconnect structure located above a first side of the first semiconductor structure, wherein the first interconnect structure includes a first conductive tower and a second conductive tower extending through the first interconnect structure, and wherein the conductive pads of the first conductive tower and the conductive pads of the second conductive tower are connected by a first conductive line; a first epitaxial structure located below a second side of the first semiconductor structure, wherein the first epitaxial structure is doped with a first dopant, wherein the first epitaxial structure includes a first portion and a second portion, wherein... The first portion has a first concentration of the first dopant, and the second portion has a second concentration of the first dopant that is different from the first concentration of the first dopant; a first contact etch stop layer is located below the first epitaxial structure; a first interlayer dielectric layer is located below the first contact etch stop layer, wherein the first contact etch stop layer and the first interlayer dielectric layer comprise different materials; and a second interconnect structure is located below the first interlayer dielectric layer, wherein the second interconnect structure includes a third conductive tower and a fourth conductive tower extending through the second interconnect structure, wherein the third conductive tower is electrically connected to the first conductive tower, and wherein the fourth conductive tower is electrically connected to the second conductive tower.

[0009] In another aspect, embodiments of this application provide a method for forming an integrated circuit die, comprising forming a sealing ring region surrounding an active region in a top view, wherein the active region includes an active circuit, and forming the sealing ring region comprises: forming a first semiconductor nanostructure over a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor base and a first semiconductor fin, and wherein, in a first cross-sectional view, the first semiconductor fin protrudes from the semiconductor base toward the first semiconductor nanostructure; forming a first dielectric layer over the semiconductor base, wherein, in the first cross-sectional view, the first semiconductor fin extends through the first dielectric layer; growing a first epitaxial structure over the first semiconductor fin, wherein, in a second cross-sectional view, the first epitaxial structure is located on a sidewall of the first semiconductor nanostructure, wherein, the second cross-sectional view is perpendicular to the first cross-sectional view, wherein, in a third cross-sectional view, the first epitaxial structure is suspended over the first dielectric layer, and wherein, the third cross-sectional view is parallel to the first cross-sectional view; forming a first conductive contact over the first epitaxial structure, wherein the first conductive contact is electrically connected to a first side of the first epitaxial structure, and wherein, the first... A conductive contact has a conductivity greater than that of the first epitaxial structure; a first interconnect structure is formed above the first conductive contact, wherein the first interconnect structure includes a first conductive tower and a second conductive tower extending through the first interconnect structure, wherein the first conductive tower includes a first conductive pad, wherein the first conductive tower is electrically connected to the first conductive contact, wherein the second conductive tower includes a second conductive pad located in the same layer as the first conductive pad in the first interconnect structure, and wherein the first conductive pad and the second conductive pad are connected by a first conductive line; a second conductive contact is formed electrically connected to a second side of the first epitaxial structure; and a second interconnect structure is formed above the second conductive contact, wherein the second interconnect structure includes a third conductive tower and a fourth conductive tower extending through the second interconnect structure, wherein the third conductive tower includes a third conductive pad, wherein the third conductive tower is electrically connected to the second conductive contact, wherein the fourth conductive tower includes a fourth conductive pad located in the same layer as the third conductive pad in the second interconnect structure, and wherein the third conductive pad and the fourth conductive pad are connected by a second conductive line. Attached Figure Description

[0010] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0011] Figure 1A three-dimensional view of a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown.

[0012] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 24C and Figure 24D This is a cross-sectional view of an intermediate stage in the fabrication of an integrated circuit die including a nanoFET, according to some embodiments.

[0013] Figure 25A and Figure 25B This is a top view of an integrated circuit die including a nanoFET according to some embodiments.

[0014] Figure 26A , Figure 26B and Figure 26C These are top and cross-sectional views of portions of an integrated circuit die including a nanoFET, according to some embodiments.

[0015] Figure 27A and Figure 27B These are top and cross-sectional views of portions of an integrated circuit die including a nanoFET, according to some embodiments.

[0016] Figure 28A and Figure 28B These are top and cross-sectional views of portions of an integrated circuit die including a nanoFET, according to some embodiments.

[0017] Figure 29A , Figure 29B and Figure 29C This is a top view of an integrated circuit die including a nanoFET according to some embodiments.

[0018] Figure 30A , Figure 30B , Figure 30C and Figure 30D This is a top view of a portion of an integrated circuit die including a nanoFET, according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0021] Various embodiments provide integrated circuit dies and methods of forming the same. An integrated circuit die may include various active transistors located in an active region. In a cross-sectional view, the various active transistors may be located between a front-side interconnect structure and a back-side interconnect structure. The front-side interconnect structure and the back-side interconnect structure may electrically connect the various active transistors to form the active circuitry of the integrated circuit die. The integrated circuit die may also include a sealing ring region surrounding the active region in a top view, which may be electrically isolated from the active region. The sealing ring region may include one or more die crack monitoring circuits. Each of the one or more die crack monitoring circuits may be open-circuited and have two external connectors as two terminals above the back-side interconnect structure. As the one or more DCM circuits extend along the corners and edges of the active region, the one or more die crack monitoring circuits may extend repeatedly through the back-side interconnect structure 136 and the front-side interconnect structure 120 in a serpentine pattern. Cracks in the front-side interconnect structure and the back-side interconnect structure in the sealing ring region 204 can be detected by crack testing, during which the one or more DCM circuits may be connected to an external voltage. As a result, the reliability of integrated circuit dies that pass the crack test can be improved.

[0022] Some embodiments discussed herein are described in the context of integrated circuit dies including nanoFETs (such as super power rail (SPR) dies). However, various embodiments can be applied to dies including other types of transistors (e.g., FinFETs, VFETs, CFETs, planar transistors, etc.) instead of or in combination with nanoFETs. Additionally, embodiments discussed herein are described in the context of interconnect structures bonding a support substrate to an integrated circuit die. However, various embodiments can be applied to bonding within other structures, such as 3D integrated circuit (3DIC) packages, integrated fan-out (InFO) packages, power distribution networks (PDNs), chiplets, wafer stacks, etc.

[0023] Figure 1A three-dimensional view of a nanoFET (e.g., nanowire FET, nanosheet FET, etc.) according to some embodiments is shown. The nanoFET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) located above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and from between adjacent STI regions 68. Although the STI regions 68 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an STI region. Furthermore, although the bottom portion of the fin 66 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68. The gate dielectric layer 100 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0024] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to, for example, the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the multiple nanoFETs. Cross section C-C' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 66 and in, for example, the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0025] Figures 2 to 24D This is a cross-sectional view of an intermediate stage in the fabrication of an integrated circuit die including a nanoFET, according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It shows along with Figure 1 A cross-sectional view of a reference cross-section A-A' similar to the one shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11D , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 24D It shows along with Figure 1 A cross-sectional view of a reference cross-section B-B' similar to the one shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C and Figure 24C It shows along with Figure 1 A cross-sectional view of a reference cross-section C-C' similar to the one shown.

[0026] exist Figure 2In this embodiment, a multilayer stack 64 is formed on a substrate 50. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0027] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. As shown by separator 20, the n-type region 50N can be physically separated from the p-type region 50P, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0028] The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, the multilayer stack 64 is shown as three layers comprising each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material, such as silicon, carbon-doped silicon, etc.

[0029] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0030] exist Figure 3 In this process, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. Fins 66 can be considered part of or separate from substrate 50. Fins 66 can be located on the front side of substrate 50. By patterning the top portion of multilayer stack 64 and substrate 50, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively. Forming nanostructures 55 by patterning multilayer stack 64 can also define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55. Patterning can include a range of suitable etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. The etching process can be anisotropic.

[0031] In the embodiments discussed in more detail below, the first nanostructure 52 is a sacrificial layer and is removed in the n-type region 50N and the p-type region 50P, while the second nanostructure 54 is retained to form the channel region of the nanoFET in the n-type region 50N and the p-type region 50P. In other embodiments, the first nanostructure 52 is retained and forms the channel region of the nanoFET in the n-type region 50N and / or the p-type region 50P, while the first nanostructure 52 is retained to form the channel region or is removed.

[0032] For the purpose of explanation, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be greater than or less than the width of the fin 66 in the p-type region 50P. Additionally, while each fin 66 is shown to always have a consistent width, and the nanostructure 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 increases continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0033] exist Figure 4 In this embodiment, a shallow trench isolation (STI) region 68 is formed over the substrate 50 and between adjacent fins 66. The fins 66 may extend through the STI region 68. The STI region 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material may be an oxide (such as silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructure 55. A filler material, such as those discussed above, may then be formed over the liner.

[0034] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be utilized. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surfaces of the nanostructure 55 and the insulating material are coplanar. The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type regions 50N and p-type regions 50P protrude from between adjacent STI regions 68. Additionally, the top surface of the STI regions 68 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof, as shown. The top surface of the STI regions 68 may be formed as flat, convex, and / or concave by appropriate etching. The STI regions 68 may be recessed using acceptable etching processes, such as etching processes that are selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructure 55). For example, dilute hydrofluoric acid (dHF) can be used to remove oxides.

[0035] In addition, Figure 4 In this process, suitable wells (not shown) can be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different well types, photoresist or other masks (not shown) can be used to implement different implantation steps for n-type region 50N and p-type region 50P. For example, photoresist can be formed over fin 66 and STI region 68 in n-type region 50N and p-type region 50P. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type dopant implantation is performed in p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type dopant implantation into n-type region 50N. The n-type dopant can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration ranging from about 10 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the range. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0036] After or before implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50N and n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type dopant implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type dopant implantation into the p-type region 50P. The p-type dopant can be boron, boron fluoride, indium, etc., implanted into the region, with a concentration ranging from approximately 10... 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0037] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type dopants. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation; however, in-situ doping and implantation doping can be used together.

[0038] exist Figure 5 In the process, a pseudo-dielectric layer 70 is formed on fin 66 and nanostructure 55. A pseudo-gate layer 72 is formed above the pseudo-dielectric layer 70, and a mask layer 74 is formed above the pseudo-gate layer 72. The pseudo-dielectric layer 70 may include silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown. The pseudo-gate layer 72 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The pseudo-gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The pseudo-gate layer 72 may be made of other materials with high etch selectivity for etching the isolation region. The pseudo-gate layer 72 may then be planarized, such as by CMP, etc. The mask layer 74 may include silicon nitride, silicon oxynitride, etc. The mask layer 74 may be formed by a suitable deposition process. For illustrative purposes, the pseudo-dielectric layer 70 is... Figure 5 The diagram shows a covering fin 66 and a nanostructure 55. In some embodiments, a dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, and such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0039] Figures 6A to 28B Various additional intermediate stages in the fabrication of an integrated circuit die including a nanoFET, according to some embodiments, are illustrated. Figures 6A to 28B The components in n-type region 50N or p-type region 50P are shown. Figures 6A to 6C In the middle, the mask layer 74 can be patterned (e.g., Figure 5 (As shown) to form a mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 may cover portions of the nanostructure 55 that can subsequently be used to form the channel region. The pattern of mask 78 can be used to physically separate the dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding fin 66. The mask layer 74 can be patterned using an acceptable photolithography process.

[0040] exist Figures 7A to 7C In this process, a first spacer 81 and a second spacer 83 are formed over the STI region 68 and the nanostructure 55. The first spacer 81 and the second spacer 83 can be aligned with the subsequently formed source / drain regions and protect the sidewalls of the fin 66 during subsequent processing. The first spacer 81 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer 83 can be formed of a material having a different etch rate than the material of the first spacer 81, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The first spacer 81 and the second spacer 83 can be formed by first forming a conformal layer using a series of suitable deposition processes (such as CVD, ALD, etc.). The conformal layer can then be patterned using a series of suitable etching processes, such as isotropic etching processes (e.g., wet etching), anisotropic etching processes (e.g., dry etching), combinations thereof, etc.

[0041] like Figure 7B As shown, the first spacer 81 and the second spacer 83 are located on the sidewalls of the fin 66 and the nanostructure 55, and on the top surface of the STI region 68. Figure 7C As shown, in some embodiments, a first spacer 81 is formed over the nanostructure 55, and a second spacer 83 is not formed over the nanostructure 55. The first spacer 81 may be located on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, both the first spacer 81 and the second spacer 83 are formed over the nanostructure 55. The first spacer 81 may be located on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the second spacer 83 may be located on the first spacer 81.

[0042] exist Figures 8A to 8CIn the process, a first groove 86 is formed. An epitaxial source / drain region can then be formed in the first groove 86. The first groove 86 can extend through the first nanostructure 52 and the second nanostructure 54. The first groove 86 can be formed by a series of suitable anisotropic etching processes, such as RIE, NBE, etc. During the etching process, the first spacer 81, the second spacer 83, and the STI region 68 can remain substantially intact.

[0043] exist Figures 9A to 9C In the process, a portion of the sidewall of the first nanostructure 52 exposed by the first groove 86 is etched to form a sidewall groove 88. Although the sidewall of the first nanostructure 52 adjacent to the sidewall groove 88 is... Figure 9C The sidewall is shown as straight, but it can be concave or convex. The sidewall can be etched using an isotropic etching process (such as wet etching). In embodiments where the first nanostructure 52 comprises silicon-germanium and the second nanostructure 54 comprises silicon or silicon carbide, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the sidewall of the first nanostructure 52.

[0044] exist Figures 10A to 10C In this process, a first internal spacer 90 is formed on the sidewall of the first nanostructure 52. The first internal spacer 90 can serve as an isolation component between the subsequently formed source / drain regions and the gate structure. The first internal spacer 90 can be formed by first depositing an internal spacer layer (not shown separately) using a conformal deposition process (such as CVD, ALD, etc.). The internal spacer layer can include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low dielectric constant (low k) material with a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. The internal spacer layer can be etched using anisotropic etching processes (such as RIE, NBE, etc.). Although the outer sidewall of the first internal spacer 90 is in Figure 10C The diagram shows the first internal spacer 90 as flush with the sidewall of the second nanostructure 54, but the outer wall of the first internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanomaterial 54. Although the outer wall of the first internal spacer 90 is... Figure 10C It is shown as straight, but the outer wall of the first inner spacer 90 may be concave or convex.

[0045] exist Figures 11A to 11D In this configuration, epitaxial source / drain regions 92 are formed above fin 66 and fill the first groove 86. Depending on the context, each epitaxial source / drain region 92 may individually or collectively refer to a source or drain. In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructure 54, thereby improving performance. Figure 11CAs shown, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of corresponding epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the first nanostructure 52 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate structure.

[0046] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0047] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by masking the n-type region 50N (e.g., NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material to which compressive strain is applied to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0048] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing process. The source / drain region can have a size of approximately 1 x 10⁻⁶. 19 atoms / cm 3 1x10 21 atoms / cm 3 The dopant concentrations between these values. The n-type and / or p-type dopants used for the source / drain regions can be any of the dopants discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0049] The epitaxial source / drain region 92 may include one or more semiconductor material layers. In some embodiments, the epitaxial source / drain region 92 includes a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. The first semiconductor material layer 92A may be in contact with (e.g., in contact with) the second nanostructure 54, and the second semiconductor material layer 92B may be spaced apart from the second nanostructure 54 by the first semiconductor material layer 92A. The first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and / or may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0050] As a result of the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper portion of the epitaxial source / drain regions has a small plane that extends laterally outward beyond the sidewalls of the nanostructure 55 and hangs above the STI region 68. In some embodiments, such as Figure 11B As shown, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge. In other embodiments, such as Figure 11D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Figure 11B and Figure 11D In the illustrated embodiment, the first spacer 81 may be formed on the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the etching process used to form the first spacer 81 may be modified to remove spacer material to allow the epitaxial growth region to extend to the top surface of the STI region 68.

[0051] exist Figures 12A to 12C In Figures 11A to 11CA first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material different from that of the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc. CESL 94 and the first ILD 96 may have different etch rates during subsequent etch processes.

[0052] exist Figures 13A to 13C In this process, a planarization process (such as CMP) can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are coplanar within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0053] exist Figures 14A to 14C In one or more etching processes, the dummy gate dielectric 71, dummy gate 76, and mask 78 (if present) are removed to form a third recess 98. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by one or more anisotropic dry etching processes. The third recess 98 may expose a second nanostructure 54, which may be disposed between adjacent pairs of epitaxial source / drain regions 92 and serve as a channel region for a nanoFET in a subsequently formed integrated circuit die. During the etching process, the dummy gate dielectric 71 may serve as an etch stop layer when the dummy gate 76 is etched. After the dummy gate 76 is removed, the dummy gate dielectric 71 may then be removed.

[0054] exist Figures 15A to 15CIn this process, the first nanostructure 52 is removed, which extends the third groove 98. The first nanostructure 52 can be removed by performing an isotropic etching process (such as wet etching) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises silicon-germanium and the second nanostructures 54A-54C comprise silicon or silicon carbide, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52.

[0055] exist Figures 16A to 16C In this process, a gate dielectric layer 100 and a gate electrode 102 are formed. The gate dielectric layer 100 is conformally deposited in the third groove 98. The gate dielectric layer 100 can be formed on the exposed surfaces of the second nanostructure 54, the first internal spacer 90, and the first spacer 81. Figure 16A As shown, the gate structure may enclose a second nanostructure 54, which can serve as a channel region for a nano-FET in a subsequently formed integrated circuit die. The gate dielectric layer 100 may include one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric constant of the gate dielectric layer 100 may be greater than the dielectric constant of the first spacer 81. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The gate dielectric layer 100 may be formed by ALD, CVD, or the like.

[0056] Gate electrodes 102 are deposited over gate dielectric layer 100 and fill the remaining portion of third trench 98. Gate electrodes 102 may comprise metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although Figure 16A and Figure 16C A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of pad layers, any number of power function conditioning layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50.

[0057] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions. After filling the third recess 98, a planarization process (such as CMP) can be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 above the top surface of the first ILD 96. The remaining portion of the material of the gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the gate structure.

[0058] exist Figures 17A to 17C In this process, the gate structure (including the gate dielectric layer 100 and the gate electrode 102) is recessed, and a gate mask 104 is formed in the recess. The recess can be formed directly above the gate structure and between opposing portions of the first spacer 81. The gate mask 104 may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc. A planarization process (such as CMP) can then be performed to remove excess dielectric material above the first ILD 96. The subsequently formed gate contacts can extend through the gate mask 104 to contact the top surface of the recessed gate electrode 102. Figures 17A to 17C As further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. The second ILD 106 can be formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, FCVD, PECVD, etc. In some embodiments, the gate mask 104 can be omitted.

[0059] exist Figures 18A to 18CIn the process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a fourth recess 108, which exposes the front surface of the epitaxial source / drain region 92 and / or the gate electrode 102. The fourth recess 108 can be formed by etching using anisotropic etching processes such as RIE, NBE, etc. In some embodiments, the fourth recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the fourth recess 108 can be etched through the gate mask 104 using a second etching process; and then the fourth recess 108 can be etched through the CESL 94 using a third etching process. A mask (such as photoresist) can be formed over the second ILD 106 and the mask can be patterned to shield portions of the second ILD 106 from the effects of the first and second etching processes. Although Figure 18C The fourth recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short circuits in the subsequently formed contacts.

[0060] After the fourth groove 108 is formed, a first silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 over the exposed portion of the epitaxial source / drain region 92 to form a silicide region or a germanide region, and then performing an annealing process to form the first silicide region 110. Unreacted portions of the deposited metal are then removed by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon-germanium region (e.g., a region comprising both silicide and germanide).

[0061] exist Figures 19A to 19CIn the fourth recess 108, source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed. Each of the source / drain contacts 112 and gate contacts 114 may include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. The first silicide region 110 can be considered as part of the source / drain contact 112. The material of the source / drain contact 112 may have a higher conductivity than the material of the underlying epitaxial source / drain region 92. The gate contact 114 is electrically connected to the gate electrode 102, and the source / drain contact 112 is electrically connected to the first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, molybdenum, rhodium, etc. A planarization process (such as CMP) may be performed to remove excess material from the surface of the second ILD 106.

[0062] The epitaxial source / drain region 92, the second nanostructure 54 (e.g., a channel region), and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) can be collectively referred to as device layer 109, having a first interconnect structure (such as a front-side interconnect structure to be formed above its front side) and a second interconnect structure (such as a back-side interconnect structure to be formed above its back side). Device layer 109 may include various transistors, such as nanoFETs.

[0063] exist Figures 20A to 20C In this process, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 may be referred to as a front-side interconnect structure because it is formed on the front side of the device layer 109 (e.g., the side of the device layer 109 where active devices are formed). The front-side interconnect structure 120 may include a first conductive component 122 formed in the first dielectric layer 124. The first conductive component 122 may be electrically connected to the gate contact 114 and the source / drain contact 112. As a result, the front-side interconnect structure 120 may electrically connect to the nano-FETs formed in the device layer 109 to form the active circuitry of an integrated circuit die. The first dielectric layer 124 may include a dielectric material, such as a low-k dielectric material, an extremely low-k (ELK) dielectric material, etc. The first dielectric layer 124 may be deposited using appropriate processes, such as CVD, ALD, PVD, PECVD, etc. The first conductive component 122 may include conductive lines and conductive vias in the layer that interconnect the conductive lines. Conductive vias can extend through the corresponding first dielectric layer 124 to provide vertical connections between conductive lines. The first conductive component 122 can be formed by any acceptable process, such as damascene, dual damascene, etc.

[0064] In some embodiments, the first conductive component 122 may be formed using an damascene process, wherein a corresponding first dielectric layer 124 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to a desired pattern of the first conductive component 122. An optional diffusion barrier layer and / or optional adhesive layer may be formed using a suitable deposition process, and the trenches may then be filled with a conductive material by electroplating. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, combinations thereof, etc., and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, etc. Planarization processes (such as CMP) may be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124 and planarize the surfaces of the first dielectric layer 124 and the first conductive component 122 for subsequent processing.

[0065] Also Figures 20A to 20C As shown, a first bonding layer 152A can be deposited over the front interconnect structure 120. The first bonding layer 152A facilitates subsequent bonding to the carrier substrate and transfers heat generated by the device layer 109 during operation of the integrated circuit die to the carrier substrate. Example materials for the first bonding layer 152A may include titanium oxide, aluminum oxide, nickel oxide, zinc oxide, etc. The first bonding layer 152A can be deposited by any suitable method, such as PVD, CVD, ALD, etc. Planarization processes (such as CMP) can be used to remove excess material from the surface of the first bonding layer 152A and planarize the surface of the first bonding layer 152 for subsequent processing.

[0066] exist Figures 21A to 21C In this process, the carrier substrate 150 is bonded to the front interconnect structure 120 by bonding a first bonding layer 152A and a second bonding layer 152B onto the carrier substrate 150. After bonding with the first bonding layer 152A, the second bonding layer 152B can also transfer heat generated by the device layer 109 during the operation of the integrated circuit die to the carrier substrate 150. The carrier substrate 150 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 150 can provide structural support during subsequent processes and in the finished device. The second bonding layer 152B can be formed of the same or similar material as the first bonding layer 152A and by the same or similar process as the first bonding layer 152A. The carrier substrate 150 can be bonded to the front interconnect structure 120 by bonding the first bonding layer 152A and the second bonding layer 152B using any suitable method, such as dielectric-to-dielectric bonding.

[0067] The dielectric-to-dielectric bonding process may include applying a surface treatment to a first bonding layer 152A and / or a second bonding layer 152B to align the first bonding layer 152A and the second bonding layer 152B, and pressing the first bonding layer 152A and the second bonding layer 152B together to initiate bonding between the first bonding layer 152A and the second bonding layer 152B. Annealing may then be performed to strengthen the bonding between the first bonding layer 152A and the second bonding layer 152B. After bonding, the first bonding layer 152A and the second bonding layer 152B may be collectively referred to as bonding layer 152.

[0068] exist Figures 22A to 22C In the process, substrate 50 is thinned, and a fifth groove 128 is formed. The fifth groove 128 may extend through substrate 50 and fin 66 to expose the back surface of epitaxial source / drain region 92. Substrate 50 may be thinned by CMP, etch-back processes, etc. The fifth groove 128 may be formed by first forming a patterned mask on substrate 50, and then performing a suitable etching process through openings in the patterned mask. After the etching process, the back surface of epitaxial source / drain region 92 may be exposed. The patterned mask may be removed after the etching process.

[0069] exist Figures 23A to 23C In this design, a dielectric pad 131 is formed on the sidewall of the fifth groove 128, and a second silicide region 129 is formed on the back surface of the epitaxial source / drain region 92. Source / drain contacts 130 are formed on the dielectric pad 131 and the second silicide region 129, which can fill the fifth groove 128. The source / drain contacts 130 can be electrically connected to the epitaxial source / drain region 92 through the second silicide region 129. The second silicide region 129 can be considered as part of the source / drain contacts 130. The dielectric pad 131 can include a suitable dielectric material, such as silicon nitride, and is formed by a suitable deposition process, such as CVD, ALD, etc. The second silicide region 129 can be formed by the same process described above. Figures 18A to 18C The first silicide region 110 described herein is formed of the same or similar material and through the same or similar process. The source / drain contact 130 may be formed of the same material as described above. Figures 19A to 19C The source / drain contacts 112 described are formed of the same or similar materials and by the same or similar methods. The material of the source / drain contacts 130 may have a higher conductivity than the material of the epitaxial source / drain regions 92 below.

[0070] exist Figures 24A to 24DIn this process, a back-side interconnect structure 136 is formed over the substrate 50 and the source / drain contacts 130. Then, a passivation layer 144, a UBM 146, and an external interconnect 148 are formed over the back-side interconnect structure 136. The back-side interconnect structure 136 may be referred to as a back-side interconnect structure because it is formed on the back side of the device layer 109. The back-side interconnect structure 136 may include a second conductive component 140 formed in the second dielectric layer 138. The second conductive component 140 may be a power rail that can electrically connect to the epitaxial source / drain regions 92 to provide a reference voltage, power supply voltage, etc. As a result, the back-side interconnect structure 136 can electrically connect to nanoFETs formed in the device layer 109 to form the active circuitry of an integrated circuit die.

[0071] The second conductive component 140 can be made of the same material as described above. Figures 20A to 20C The first conductive component 122 described is formed of the same or similar material and by the same or similar method. The second dielectric layer 138 may be formed of the same material as described above. Figures 20A to 20C The first dielectric layer 124 is formed of the same or similar material and by the same or similar method. Then, a passivation layer 144 can be formed over the back-side interconnect structure 136. The passivation layer 144 may comprise a polymer (such as PBO, polyimide, BCB, etc.) or an inorganic dielectric material (such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc.). The passivation layer 144 can be formed by a suitable deposition method, such as CVD, ALD, etc.

[0072] UBM 146 can be formed through passivation layer 144 to electrically connect to a second conductive component 140 in back-side interconnect structure 136. UBM 146 may include one or more layers of copper, nickel, gold, etc., and can be formed by plating processes, etc. External connectors 148 can be formed on UBM 146. Forming external connectors 148 may include placing solder balls on exposed portions of UBM 146 and reflowing solder balls. UBM 146 and external connectors 148 can be used to provide input / output connections to other electronic components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc. UBM 146 and external connectors 148 may also be referred to as back-side input / output pads, which can provide signal, power supply voltage, and / or ground connections to nanoFETs in device layer 109.

[0073] Then, a die dicing process can be applied along the scribing lines to separate the structure above the carrier substrate 150 and the carrier substrate 150 into individual integrated circuit dies 200. Figures 24A to 24CThe structure shown can be referred to as the first portion 203 of an integrated circuit die 200. Each integrated circuit die 200 may include various nano-FETs located in the device layer 109. Each nano-FET may include a second nanostructure 54 as a channel region, a gate structure including a gate electrode 102 and a gate dielectric layer 100 and enclosing the second nanostructure 54, and a stack of epitaxial source / drain regions 92 located on both sides of each second nanostructure 54.

[0074] Figure 24D A cross-sectional view of the first part 203 according to some embodiments is shown, which is similar to Figure 24B The embodiment of the first part 203 shown, wherein the same reference numerals refer to the same parts formed by the same process. Figure 24D In the illustrated embodiment, adjacent epitaxial source / drain regions 92 are separated, which can be consistent with... Figure 11D Similar to the diagram. Each separate epitaxial source / drain region 92 can be electrically connected to a corresponding source / drain contact 130. Adjacent epitaxial source / drain regions 92 can be electrically connected to the same source / drain contact 112. CESL 94 and the first ILD 96 can be located between adjacent epitaxial source / drain regions 92.

[0075] Figure 25A and Figure 25B A top view of an integrated circuit die 200 according to some embodiments is shown. For illustrative purposes, Figure 25A and Figure 25B Some components of the integrated circuit die 200 are omitted. Figure 25A and Figure 25B The above text shows about Figures 2 to 24D The reference cross-sections A-A', B-B', and C-C' are described. Figure 25A and Figure 25B A reference cross-section D-D' is also shown, which may be parallel to the reference cross-section C-C'. For example... Figure 25A As shown, the integrated circuit die 200 may include an active region 202 and a sealing ring region 204. The active region 202 may include various active nanoFETs in the device layer 109, which are connected by a first conductive component 122 of the front-side interconnect structure 120 and a second conductive component 140 of the back-side interconnect structure 136, thereby forming the active circuitry of the integrated circuit die 200. A first portion 203 may be a representative portion of the active region 202, and... Figures 24A to 24C The structural details of the first part 203 shown can also be applied to other parts of the active region 202.

[0076] A sealing ring region 204 may surround the active region 202. The sealing ring region 204 may be located between the active region 202 and the edge of the integrated circuit die 200. As described in more detail below, the sealing ring region 204 may include components similar to those in the active region 202. Components in the sealing ring region 204 can be connected via... Figures 2 to 24D The same process described is performed simultaneously, during which the corresponding components in active region 202 are formed. Sealing ring region 204 can be electrically isolated from active region 202. As an example, Figure 25A A sealing ring region 204 with an octagonal shape is shown, but the sealing ring region 204 can have other shapes. The sealing ring region 204 can have a width W1 between its inner and outer edges. For example... Figure 25B As shown, the sealing ring region 204 may include a die crack monitoring (DCM) region 204A and a non-DCM region 204B. The DCM region 204A may have a similar shape to the sealing ring region 204, but with smaller dimensions. The non-DCM region 204B may have a similar shape to the sealing ring region 204, but with smaller dimensions.

[0077] exist Figure 25B In the illustrated embodiment, DCM region 204A is located between active region 202 and non-DCM region 204B, and DCM region 204A extends along the edge of active region 202. Figure 25B In the illustrated embodiment, DCM region 204A is an octagonal ring surrounding active region 202, and non-DCM region 204B is an octagonal ring surrounding DCM region 204A. DCM region 204A may have a width W2 between its inner and outer edges. The ratio R1 of width W2 to width W1 may range from about 0.2 to about 0.5.

[0078] DCM region 204A may include DCM circuitry, which may be open-circuited, with two external connectors 148 above passivation layer 144 serving as two terminals. The DCM circuitry may be electrically isolated from active region 202 in the active circuitry of integrated circuit die 200. Figure 25BIn the illustrated embodiment, the DCM circuitry extends from one external connector 148 around the active region 202 and to another external connector 148. After the die dicing process, a crack test can be performed on each integrated circuit die 200 to detect cracks that may have formed along the edges of the integrated circuit die 200 during the dicing process. The crack test can be performed by connecting the external connector 148 of the DCM circuitry to an external voltage. The second portion 205 may be a part of the sealing ring region 204 and is used to describe the sealing ring region 204 and the DCM circuitry in more detail below. The second portion 205 may be a representative portion of the sealing ring region 204, and the structural details described below can also be applied to other portions of the sealing ring region 204.

[0079] Figure 26A A top view of the second part 205, with more detail according to some embodiments, is shown. For illustrative purposes, Figure 26A Some components in the second part 205 are omitted. The first conductive component 122 in the front interconnect structure 120 may have the same characteristics as... Figure 26A The second conductive components 140 in the back-side interconnect structure 136 shown have a similar number, size, shape, and arrangement. The third portion 207 may be a portion of the DCM region 204A within the second portion 205. Figure 26B A cross-sectional view of a third part 207 according to some embodiments is shown, the cross-sectional view being able to be along... Figure 26A The reference cross section D-D' shown is obtained. Figure 26B The cross-sectional view in the middle can be compared with Figure 24C The cross-sectional diagrams are similar, where the same numbers refer to the same parts formed by the same process.

[0080] In the sealing ring region 204, the second conductive component 140 may include a conductive tower 140A, an inter-tower conductive line 140B, and a conductive wall 140C, which may be electrically isolated from the second conductive structure 140 in the active region 202. The DCM region 204A may include the conductive tower 140A and the inter-tower conductive line 140B, but may not include the conductive wall 140C. The non-DCM region 204B may include the conductive tower 140A and the conductive wall 140C, but may not include the inter-tower conductive line 140B. Figure 26A and Figure 26B The quantity, size, shape, and arrangement of the conductive tower 140A, the inter-tower conductive line 140B, and the conductive wall 140C shown are provided as examples, and other quantities, sizes, shapes, and arrangements of the conductive tower 140A, the inter-tower conductive line 140B, and the conductive wall 140C are contemplated.

[0081] Conductive tower 140A may extend through the second dielectric layer 138 of the back-side interconnect structure 136. Conductive tower 140A may have a height H1, which may also be the height of the back-side interconnect structure 136. Conductive tower 140A may include conductive pads and conductive vias located in the respective second dielectric layer 138 and stacked in an alternating pattern. The top conductive pad of conductive tower 140A may contact the passivation layer 144, and the bottom conductive via of conductive tower 140A may contact the source / drain contacts 130. Adjacent conductive pads of each conductive tower 140A may be connected via one or more conductive vias. The conductive pads of each conductive tower 140A may be electrically isolated from the conductive pads of adjacent conductive towers 140A. Conductive towers 140A in non-DCM region 204B and selected conductive towers 140A in DCM region 204A may be electrically isolated from each other.

[0082] Selected adjacent conductive towers 140A in DCM region 204A can be electrically connected via inter-tower conductive lines 140B. The top conductive pads of such conductive towers 140A can be connected to the inter-tower conductive lines 140B. The inter-tower conductive lines 140B can contact the passivation layer 144. The conductive wall 140C can be a continuous and uniform structure extending through the second dielectric layer 138 of the back-side interconnect structure 136. The conductive wall 140C can be a concentric ring surrounding the active region 202. The conductive towers 140A can form rows that extend along the conductive wall 140C and around the active region 202.

[0083] In the sealing ring region 204, the first conductive component 122 may include a conductive tower 122A, an inter-tower conductive line 122B, and a conductive wall (not shown), which may be electrically isolated from the first conductive component 122 in the active region 202. The DCM region 204A may include the conductive tower 122A and the inter-tower conductive line 122B, but may not include the conductive wall. The non-DCM region 204B may include the conductive tower 122A and the conductive wall, but may not include the inter-tower conductive line 122B. Figure 26A and Figure 26B The quantity, size, shape, and arrangement of the conductive tower 122A and the inter-tower conductive line 122B shown are provided as examples, and other quantities, sizes, shapes, and arrangements of the conductive tower 122A and the inter-tower conductive line 122B are contemplated.

[0084] Conductive tower 122A may extend through the first dielectric layer 124 of the front interconnect structure 120. Conductive tower 122A may have a height H2, which may also be the height of the front interconnect structure 120. Height H1 may be less than height H2, and the ratio of height H1 to height H2 may range from about 0.7 to about 1. Conductive tower 122A may include conductive pads and conductive vias located in the respective first dielectric layer 124 and stacked in an alternating pattern. The bottom conductive pad of conductive tower 122A may contact the bonding layer 152, and the top conductive via of conductive tower 122A may contact the source / drain contact 112. Adjacent conductive pads of each conductive tower 122A may be connected via one or more conductive vias. The conductive pads of each conductive tower 122A may be electrically isolated from the conductive pads of adjacent conductive towers 122A. Conductive towers 122A in non-DCM region 204B and selected conductive towers 122A in DCM region 204A may be electrically isolated from each other.

[0085] Selected adjacent conductive towers 122A in DCM region 204A can be electrically connected via inter-tower conductive lines 122B. The bottom conductive pads of such conductive towers 122A can be connected to the inter-tower conductive lines 122B. The inter-tower conductive lines 122B can contact the bonding layer 152. Conductive walls in the front interconnect structure 120 can extend through the first dielectric layer 124 of the front interconnect structure 120. The conductive walls in the front interconnect structure 120 can be concentric rings surrounding the active region 202. Conductive towers 122A can form rows that extend along the conductive walls in the front interconnect structure 120 and around the active region 202.

[0086] In the sealing ring region 204, the various nanoFETs in the device layer 109 can be passive nanoFETs and are electrically isolated from the nanoFETs in the active region 202 of the device layer 109. Figure 26B In the illustrated embodiment, the conductive tower 140A in the back-side interconnect structure 136 can be electrically connected to the corresponding conductive tower 122A in the front-side interconnect structure 120 via the source / drain contact 130, the second silicide region 129, the epitaxial source / drain region 92, the first silicide region 110, and the source / drain contact 112 between the conductive tower 140A and the corresponding conductive tower 122A. This electrical connection between the conductive tower 140A and the corresponding conductive tower 122A via the device layer 109 can be referred to as a first device connection. Figure 26A and Figure 26B An electrical path 154 according to some embodiments is shown. Electrical path 154 may include a first device connection and electrical connections between adjacent conductive towers 140A via respective inter-tower conductor lines 140B and between adjacent conductive towers 122A via respective inter-tower conductor lines 122B. Electrical path 154 may be part of a DCM circuit.

[0087] Figure 26C A cross-sectional view of a third part 207 according to some embodiments is shown, which is similar to Figure 26B The embodiment of section 207 shown in the diagram, wherein the same reference numerals refer to the same parts formed by the same process. Figure 26C In the illustrated embodiment, the source / drain contact 130 extends through the epitaxial source / drain region 92 to contact the source / drain contact 112, and the dielectric pad 131 runs along the sidewall of the source / drain contact 130. The openings through the substrate 50, fin 66, and epitaxial source / drain region 92 can be formed first by a series of suitable etching processes. Figure 26C The source / drain contact 130 is shown. The etching process can also remove the first silicide region 110 (see...). Figure 26B Then, a dielectric pad 131 and a source / drain contact 130 can be formed in the opening.

[0088] exist Figure 26C In the illustrated embodiment, the conductive tower 140A in the back-side interconnect structure 136 can be electrically connected to the corresponding conductive tower 122A in the front-side interconnect structure 120 via the source / drain contacts 130 and 112 between the conductive tower 140A and the corresponding conductive tower 122A. This electrical connection between the conductive tower 140A and the corresponding conductive tower 122A via the device layer 109 can be referred to as a second device connection. Figure 26C In the illustrated embodiment, electrical path 154 includes a second device connection and electrical connections between adjacent conductive towers 140A via respective inter-tower conductive lines 140B and between adjacent conductive towers 122A via respective inter-tower conductive lines 122B.

[0089] Figure 27A A top view of a second part 205 according to some embodiments is shown, which is similar to Figure 26A The embodiment of the second part 205 shown, wherein the same reference numerals refer to the same parts formed by the same process. The fourth part 209 may be a portion of the DCM region 204A within the second part 205. Figure 27B A cross-sectional view of a fourth part 209 according to some embodiments is shown, the cross-sectional view being able to be viewed along... Figure 27A The reference cross section D-D' shown is obtained. Figure 27B The cross-sectional view of part 209 in the fourth section can be compared with Figure 26B The cross-sectional view of the third part 207 is similar, where the same numbers refer to the same parts formed by the same process.

[0090] exist Figure 27BIn the illustrated embodiment, conductive contact 132 extends through substrate 50, fin 66, gate structure, and second nanostructure 54 to contact gate contact 114, and dielectric pad 133 runs along the sidewall of conductive contact 132. The openings through substrate 50, fin 66, gate structure, and second nanostructure 54 can be formed first by a series of suitable etching processes. Figure 27B The conductive contact 132 and dielectric pad 133 are shown. Then, it can be connected with... Figures 23A to 23C The process for forming dielectric pad 131 and source / drain contact 130 described herein is similar to the process for forming dielectric pad 133 and conductive contact 132 in the opening.

[0091] exist Figure 27B In the illustrated embodiment, the conductive tower 140A in the back-side interconnect structure 136 can be electrically connected to the corresponding conductive tower 122A in the front-side interconnect structure 120 via the conductive contact 132 and the gate contact 114 between the conductive tower 140A and the corresponding conductive tower 122A. This electrical connection between the conductive tower 140A and the corresponding conductive tower 122A through the device layer 109 can be referred to as a third device connection. Figure 27A and Figure 27B An electrical path 156 according to some embodiments is shown. Electrical path 156 may include a third device connection and electrical connections between adjacent conductive towers 140A via respective inter-tower conductor lines 140B and between adjacent conductive towers 122A via respective inter-tower conductor lines 122B. Electrical path 156 may be part of a DCM circuit.

[0092] Figure 28A A top view of a second part 205 according to some embodiments is shown, which is similar to Figure 26A The embodiment of the second part 205 shown, wherein the same reference numerals refer to the same parts formed by the same process. The fifth part 211 may be a portion of the DCM region 204A within the second part 205. Figure 28B A cross-sectional view of a fifth part 211 according to some embodiments is shown, the cross-sectional view being able to be viewed along... Figure 28A The reference cross section B-B' shown is obtained. Figure 28B The device layer 109 in the cross-sectional view of the fifth part 211 can be similar to Figure 24D Device layer 109 in the cross-sectional view of the first part 203, where the same numbers refer to the same components formed by the same process. Figure 28B The front interconnect structure 120 and the back interconnect structure 136 in the cross-sectional view of the fifth part 211 can be similar to Figure 26B The front interconnect structure 120 and the back interconnect structure 136 in the cross-sectional view of the third part 207, wherein the same numbers refer to the same parts formed by the same process.

[0093] exist Figure 28B In the illustrated embodiment, conductive contact 134 extends through substrate 50, STI region 68, CESL 94, and first ILD 96 to contact source / drain contact 112, and dielectric pad 135 runs along the sidewall of conductive contact 134. The openings through substrate 50, STI region 68, CESL 94, and first ILD 96 can be formed first by a series of suitable etching processes. Figure 28B The conductive contact 134 and dielectric pad 135 are shown. Then, it can be connected via... Figures 23A to 23C The process described for forming dielectric pad 131 and source / drain contact 130 is similar to the process for forming dielectric pad 135 and conductive contact 134 in the opening.

[0094] exist Figure 28B In the illustrated embodiment, the conductive tower 140A in the back-side interconnect structure 136 can be electrically connected to the corresponding conductive tower 122A in the front-side interconnect structure 120 via the conductive contact 134 and the source / drain contact 112 between the conductive tower 140A and the corresponding conductive tower 122A. This electrical connection between the conductive tower 140A and the corresponding conductive tower 122A via the device layer 109 can be referred to as a fourth device connection. Figure 28A and Figure 28B An electrical path 158 according to some embodiments is shown. Electrical path 158 may include a fourth device connection and electrical connections between adjacent conductive towers 140A via respective inter-tower conductor lines 140B and between adjacent conductive towers 122A via respective inter-tower conductor lines 122B. Electrical path 158 may be part of a DCM circuit.

[0095] The aforementioned electrical path 154, including a first or second device connection, electrical path 156, including a third device connection, and electrical path 158, including a fourth device connection, may be part of an electrically connected DCM circuit and are provided as an example. The DCM circuit may include any combination of first, second, third, and / or fourth device connections electrically connected by a first conductive component 122 and a second conductive component 140 in the DCM region 204A. Since the DCM circuit can repeatedly extend in a serpentine pattern through the back-side interconnect structure 136 and the front-side interconnect structure 120 as it extends within the sealing ring region 204 and around the active region 202, cracks in the back-side interconnect structure 136 and the front-side interconnect structure 120 in the sealing ring region 202 can be detected by crack testing. As a result, the reliability of the integrated circuit die 200 that passes the crack test can be improved.

[0096] Figure 29AA top view of an integrated circuit die 200 according to some embodiments is shown, which is similar to Figure 25B The embodiment of the integrated circuit die 200 shown refers to the same reference numerals indicating the same components formed by the same process. Figure 29A In the illustrated embodiment, the sealing ring region 204 includes a plurality of DCM regions 204A disposed near the corner of the active region 202, and the DCM regions 204A may have a curved strip shape. Each DCM region 204A may have a DCM circuit having two external connectors 148 as two terminals. As the DCM circuit extends from one end of the DCM region 204A to the other end, the DCM circuit may extend repeatedly through the back-side interconnect structure 136 and the front-side interconnect structure 120 in a serpentine pattern, which may be similar to the above description regarding... Figures 26A to 28B An embodiment of the described DCM circuit.

[0097] Figure 29B A top view of an integrated circuit die 200 according to some embodiments is shown, which is similar to Figure 25B The embodiment of the integrated circuit die 200 shown refers to the same reference numerals indicating the same components formed by the same process. Figure 29B In the illustrated embodiment, the sealing ring region 204 includes a plurality of DCM regions 204A disposed along the edge of the active region 202, and the DCM regions 204A may have a linear strip shape. Each DCM region 204A may have a DCM circuit having two external connectors 148 as two terminals. As the DCM circuit extends from one end of the DCM region 204A to the other end, the DCM circuit may extend repeatedly through the back-side interconnect structure 136 and the front-side interconnect structure 120 in a serpentine pattern, which may be similar to the above description regarding... Figures 26A to 28B An embodiment of the described DCM circuit.

[0098] Figure 29C A top view of an integrated circuit die 200 according to some embodiments is shown, which is similar to Figure 25B The embodiment of the integrated circuit die 200 shown refers to the same reference numerals indicating the same components formed by the same process. Figure 29BIn the illustrated embodiment, the sealing ring region 204 includes a plurality of DCM regions 204A in the shape of curved strips disposed near the corners of the active region 202, and a plurality of DCM regions 204A in the shape of linear strips disposed along the edge of the active region 202. The plurality of DCM regions 204A can form a segmented ring around the active region 202. Each DCM region 204A can have a DCM circuit having two external connectors 148 as two terminals. As the DCM circuit extends from one end of the DCM region 204A to the other end, the DCM circuit can extend repeatedly through the back-side interconnect structure 136 and the front-side interconnect structure 120 in a serpentine pattern, similar to the above description regarding... Figures 26A to 28B An embodiment of the described DCM circuit.

[0099] Figure 30A A top view of the second portion 205 of the sealing ring region 204 according to some embodiments is shown, which is similar to Figure 26A The second portion 205 of the sealing ring region 204 is shown, where the same reference numerals refer to the same parts formed by the same process. Figure 30A In the illustrated embodiment, the non-DCM region 204B is located between the active region 202 and the DCM region 204A, and the DCM region 204A extends along the edge of the integrated circuit die 200.

[0100] Figure 30B A top view of the second portion 205 of the sealing ring region 204 according to some embodiments is shown, which is similar to Figure 26A The second portion 205 of the sealing ring region 204 is shown, where the same reference numerals refer to the same parts formed by the same process. Figure 30B In the illustrated embodiment, the first portion of the non-DCM region 204B is located between the active region 202 and the DCM region 204A, and the DCM region 204A is located between the conductive wall 140C in the first portion of the non-DCM region 204B and the conductive wall 140C in the second portion of the non-DCM region 204B.

[0101] Figure 30C A top view of the second portion 205 of the sealing ring region 204 according to some embodiments is shown, which is similar to Figure 26A The second portion 205 of the sealing ring region 204 is shown, where the same reference numerals refer to the same parts formed by the same process. Figure 30CIn the embodiment shown, the first portion of the non-DCM region 204B is located between the active region 202 and the DCM region 204A, and the DCM region 204A is located between a row of conductive towers 140A in the first portion of the non-DCM region 204B and a row of conductive towers 140A in the second portion of the non-DCM region 204B.

[0102] Figure 30D A top view of the second portion 205 of the sealing ring region 204 according to some embodiments is shown, which is similar to Figure 26A The second portion 205 of the sealing ring region 204 is shown, where the same reference numerals refer to the same parts formed by the same process. Figure 30D In the embodiment shown, the first portion of the non-DCM region 204B is located between the active region 202 and the DCM region 204A, and the DCM region 204A is located between the conductive wall 140C in the first portion of the non-DCM region 204B and a row of conductive towers 140A in the second portion of the non-DCM region 204B.

[0103] The embodiments of this disclosure have several advantageous features. By forming one or more DCM circuits in the sealing ring region 204, the DCM circuits can extend repeatedly through the back-side interconnect structure 136 and the front-side interconnect structure 120 in a serpentine pattern as they extend along the corners and edges of the active region 202. Cracks in the back-side interconnect structure 136 and the front-side interconnect structure 120 in the sealing ring region 204 can be detected by crack testing. As a result, the reliability of the integrated circuit die 200 that passes the crack test can be improved.

[0104] In an embodiment, the integrated circuit die includes: an active region, wherein the active region includes active circuitry; and a sealing ring region, wherein the sealing ring region surrounds the active region in a top view, the sealing ring region including: a first epitaxial structure; a first interconnect structure located above a first side of the first epitaxial structure, wherein the first interconnect structure includes a first conductive tower extending through the first interconnect structure; a first conductive contact electrically connecting the first conductive tower to the first side of the first epitaxial structure; a second interconnect structure located on a second side of the first epitaxial structure, wherein the second side of the first epitaxial structure is opposite to the first side of the first epitaxial structure, and wherein the second interconnect structure includes a second conductive tower extending through the second interconnect structure; a second conductive contact electrically connecting the second conductive tower to the second side of the first epitaxial structure; a first semiconductor nanostructure along a sidewall of the first epitaxial structure; a gate structure located below the first semiconductor nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric layer, and wherein the gate electrode includes a titanium-based material; and a gate spacer along a sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer. In one embodiment, the sealing ring region is electrically isolated from the active region. In another embodiment, the first conductive tower includes first conductive pads and first conductive vias stacked in an alternating pattern, wherein the top first conductive pad of the first conductive tower contacts the first conductive line. In another embodiment, the first interconnect structure further includes a third conductive tower extending through the first interconnect structure, wherein the third conductive tower includes third conductive pads and third conductive vias stacked in an alternating pattern, and wherein the top third conductive pad of the third conductive tower contacts the first conductive line. In another embodiment, the sealing ring region further includes: a second epitaxial structure located between the first interconnect structure and the second interconnect structure, wherein a first semiconductor nanostructure is located between the first epitaxial structure and the second epitaxial structure; and a third conductive contact electrically connecting the third conductive tower and the second epitaxial structure. In another embodiment, the second conductive tower includes second conductive pads and second conductive vias stacked in an alternating pattern, wherein the bottom second conductive pad of the second conductive tower contacts the first conductive line. In one embodiment, the second interconnect structure further includes a third conductive tower extending through the second interconnect structure, wherein the third conductive tower includes third conductive pads and third conductive vias stacked in an alternating pattern, and wherein the bottom third conductive pad of the third conductive tower contacts the first conductive line. In another embodiment, the sealing ring region further includes: a second epitaxial structure located between the first interconnect structure and the second interconnect structure, wherein the first semiconductor nanostructure is located between the first epitaxial structure and the second epitaxial structure; and a third conductive contact electrically connecting the third conductive tower and the second epitaxial structure.

[0105] In an embodiment, the integrated circuit die includes an active region, wherein the active region includes an active circuit; and a sealing ring region, wherein the sealing ring region surrounds the active region in a top view, and wherein the sealing ring region is electrically isolated from the active region. The sealing ring region includes: a first semiconductor structure; a first interconnect structure located above a first side of the first semiconductor structure, wherein the first interconnect structure includes a first conductive tower and a second conductive tower extending through the first interconnect structure, and wherein the conductive pads of the first conductive tower and the conductive pads of the second conductive tower are connected by a first conductive line; and a first epitaxial structure located below a second side of the first semiconductor structure, wherein the first epitaxial structure is doped with a first dopant. The epitaxial structure includes a first portion and a second portion, wherein the first portion has a first concentration of a first dopant, and wherein the second portion has a second concentration of a first dopant different from the first concentration of the first dopant; a first contact etch stop layer located below the first epitaxial structure; a first interlayer dielectric layer located below the first contact etch stop layer, wherein the first contact etch stop layer and the first interlayer dielectric layer comprise different materials; and a second interconnect structure located below the first interlayer dielectric layer, wherein the second interconnect structure includes a third conductive tower and a fourth conductive tower extending through the second interconnect structure, wherein the third conductive tower is electrically connected to the first conductive tower, and wherein the fourth conductive tower is electrically connected to the second conductive tower. In an embodiment, the sealing ring region further includes: a second epitaxial structure located below a second side of the first semiconductor structure; a first conductive contact extending through the first semiconductor structure, wherein the first conductive contact electrically connects the first conductive tower to a first side of the first epitaxial structure; and a second conductive contact extending through the first semiconductor structure, wherein the second conductive contact electrically connects the second conductive tower to a first side of the second epitaxial structure. In one embodiment, the sealing ring region further includes: a second contact etch stop layer located below the second epitaxial structure; a second interlayer dielectric layer located below the second contact etch stop layer; a third conductive contact extending through the first interlayer dielectric layer and the first contact etch stop layer, wherein the third conductive contact electrically connects a third conductive tower to a second side of the first epitaxial structure; and a fourth conductive contact extending through the second interlayer dielectric layer and the second contact etch stop layer, wherein the fourth conductive contact electrically connects a fourth conductive tower to a second side of the second epitaxial structure. In another embodiment, the sealing ring region further includes: a second epitaxial structure located below a second side of the first semiconductor structure; a first conductive contact extending through the first semiconductor structure and the first epitaxial structure, wherein the first conductive contact is electrically connected to a first conductive tower; and a second conductive contact extending through the first semiconductor structure and the second epitaxial structure, wherein the second conductive contact is electrically connected to a second conductive tower.In one embodiment, the sealing ring region further includes: a second contact etch stop layer located below the second epitaxial structure; a second interlayer dielectric layer located below the second contact etch stop layer; a third conductive contact extending through the first interlayer dielectric layer and the first contact etch stop layer, wherein the third conductive contact electrically connects the third conductive tower to the first conductive contact; and a fourth conductive contact extending through the second interlayer dielectric layer and the second contact etch stop layer, wherein the fourth conductive contact electrically connects the fourth conductive tower to the second conductive contact. In another embodiment, the sealing ring region further includes: a first semiconductor nanostructure along a first sidewall of the first epitaxial structure; a first gate structure located below the first semiconductor nanostructure; a first conductive contact extending through the first semiconductor structure, the first semiconductor nanostructure, and the first gate structure, wherein the first conductive contact is electrically connected to the first conductive tower; a second semiconductor nanostructure along a second sidewall of the first epitaxial structure; a second gate structure located below the second semiconductor nanostructure; and a second conductive contact extending through the first semiconductor structure, the second semiconductor nanostructure, and the second gate structure, wherein the second conductive contact is electrically connected to the second conductive tower. In an embodiment, the sealing ring region further includes: a third conductive contact that electrically connects the third conductive tower to the first conductive contact; and a fourth conductive contact that electrically connects the fourth conductive tower to the second conductive contact.

[0106] In an embodiment, a method of forming an integrated circuit die includes: forming a sealing ring region surrounding an active region in a top view, wherein the active region includes an active circuit, and wherein forming the sealing ring region includes: forming a first semiconductor nanostructure over a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor base and a first semiconductor fin, and wherein, in a first cross-sectional view, the first semiconductor fin protrudes from the semiconductor base toward the first semiconductor nanostructure; forming a first dielectric layer over the semiconductor base, wherein, in the first cross-sectional view, the first semiconductor fin extends through the first dielectric layer; growing a first epitaxial structure over the first semiconductor fin, wherein, in a second cross-sectional view, the first epitaxial structure is located on a sidewall of the first semiconductor nanostructure, wherein, the second cross-sectional view is perpendicular to the first cross-sectional view, wherein, in a third cross-sectional view, the first epitaxial structure is suspended over the first dielectric layer, and wherein, the third cross-sectional view is parallel to the first cross-sectional view; forming a first conductive contact over the first epitaxial structure, wherein the first conductive contact is electrically connected to a first side of the first epitaxial structure, and wherein, the first... The conductivity of the conductive contact is greater than that of the first epitaxial structure; a first interconnect structure is formed above the first conductive contact, wherein the first interconnect structure includes a first conductive tower and a second conductive tower extending through the first interconnect structure, wherein the first conductive tower includes a first conductive pad, wherein the first conductive tower is electrically connected to the first conductive contact, wherein the second conductive tower includes a second conductive pad located in the same layer as the first conductive pad in the first interconnect structure; and wherein the first conductive pad and the second conductive pad are connected by a first conductive line; a second conductive contact is formed electrically connected to a second side of the first epitaxial structure; and a second interconnect structure is formed above the second conductive contact, wherein the second interconnect structure includes a third conductive tower and a fourth conductive tower extending through the second interconnect structure, wherein the third conductive tower includes a third conductive pad, wherein the third conductive tower is electrically connected to the second conductive contact, wherein the fourth conductive tower includes a fourth conductive pad located in the same layer as the third conductive pad in the second interconnect structure, and wherein the third conductive pad and the fourth conductive pad are connected by a second conductive line. In one embodiment, the sealing ring region includes a test circuit electrically isolated from the active circuitry of the active region, wherein the test circuit extends through the sealing ring region in a serpentine pattern in a second cross-sectional view, and wherein the test circuit is a die crack monitor. In one embodiment, the test circuit includes a first epitaxial structure, a first conductive contact, a first conductive tower, a second conductive tower, a first conductive line, a second conductive contact, a third conductive tower, a fourth conductive tower, and a second conductive line. In one embodiment, the test circuit surrounds the active region. In one embodiment, the first interconnect structure has a first height, and the second interconnect structure has a second height, wherein the second height is less than the first height.

[0107] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit die, comprising: An active region, wherein the active region includes an active circuit; and a sealing ring region, wherein the sealing ring region surrounds the active region in a top view, the sealing ring region comprising: First extensional structure; A first interconnect structure is located above a first side of the first epitaxial structure, wherein the first interconnect structure includes a first conductive tower extending through the first interconnect structure; The first conductive contact electrically connects the first conductive tower to the first side of the first extensional structure; A second interconnect structure is located on a second side of the first epitaxial structure, wherein the second side of the first epitaxial structure is opposite to the first side of the first epitaxial structure, and wherein the second interconnect structure includes a second conductive tower extending through the second interconnect structure; A second conductive contact electrically connects the second conductive tower to the second side of the first epitaxial structure; a first semiconductor nanostructure is located along the sidewall of the first epitaxial structure. A gate structure is located below the first semiconductor nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric layer, and wherein the gate electrode comprises a titanium-based material; and A gate spacer along the sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer.

2. The integrated circuit die according to claim 1, wherein, The sealing ring region is electrically isolated from the active region.

3. The integrated circuit die according to claim 1, wherein, The first conductive tower includes first conductive pads and first conductive vias stacked in an alternating pattern, wherein the top first conductive pad of the first conductive tower is in contact with a first conductive line.

4. The integrated circuit die according to claim 3, wherein, The first interconnect structure further includes a third conductive tower extending through the first interconnect structure, wherein the third conductive tower includes third conductive pads and third conductive vias stacked in an alternating pattern, and wherein the top third conductive pad of the third conductive tower contacts the first conductive line.

5. The integrated circuit die according to claim 4, wherein, The sealing ring region also includes: A second epitaxial structure is located between the first interconnect structure and the second interconnect structure, wherein the first semiconductor nanostructure is located between the first epitaxial structure and the second epitaxial structure; and The third conductive contact electrically connects the third conductive tower and the second extensional structure.

6. The integrated circuit die according to claim 1, wherein, The second conductive tower includes second conductive pads and second conductive vias stacked in an alternating pattern, wherein the bottom second conductive pad of the second conductive tower is in contact with the first conductive line.

7. The integrated circuit die according to claim 6, wherein, The second interconnect structure further includes a third conductive tower extending through the second interconnect structure, wherein the third conductive tower includes third conductive pads and third conductive vias stacked in an alternating pattern, and wherein the bottom third conductive pad of the third conductive tower contacts the first conductive line.

8. The integrated circuit die according to claim 7, wherein, The sealing ring region also includes: A second epitaxial structure is located between the first interconnect structure and the second interconnect structure, wherein the first semiconductor nanostructure is located between the first epitaxial structure and the second epitaxial structure; and The third conductive contact electrically connects the third conductive tower and the second extensional structure.

9. An integrated circuit die, comprising: An active region, wherein the active region includes an active circuit; and a sealing ring region, wherein the sealing ring region surrounds the active region in a top view, and wherein the sealing ring region is electrically isolated from the active region, the sealing ring region comprising: First semiconductor structure; A first interconnect structure is located above a first side of the first semiconductor structure, wherein the first interconnect structure includes a first conductive tower and a second conductive tower extending through the first interconnect structure, and wherein the conductive pads of the first conductive tower and the conductive pads of the second conductive tower are connected by a first conductive line. A first epitaxial structure is located below the second side of the first semiconductor structure, wherein the first epitaxial structure is doped with a first dopant, wherein the first epitaxial structure includes a first portion and a second portion, wherein the first portion has a first concentration of the first dopant, and wherein the second portion has a second concentration of the first dopant that is different from the first concentration of the first dopant; The first contact etch stop layer is located below the first epitaxial structure; A first interlayer dielectric layer is located below the first contact etch stop layer, wherein the first contact etch stop layer and the first interlayer dielectric layer comprise different materials; and A second interconnect structure is located below the first interlayer dielectric layer, wherein the second interconnect structure includes a third conductive tower and a fourth conductive tower extending through the second interconnect structure, wherein the third conductive tower is electrically connected to the first conductive tower, and wherein the fourth conductive tower is electrically connected to the second conductive tower.

10. A method for forming an integrated circuit die, comprising: A sealing ring region is formed in a top view surrounding an active region, wherein the active region includes an active circuit, and wherein forming the sealing ring region includes: A first semiconductor nanostructure is formed on a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor base and a first semiconductor fin, and wherein, in a first cross-sectional view, the first semiconductor fin protrudes from the semiconductor base toward the first semiconductor nanostructure; A first dielectric layer is formed over the semiconductor substrate, wherein, in the first cross-sectional view, the first semiconductor fin extends through the first dielectric layer; A first epitaxial structure is grown above the first semiconductor fin, wherein, in a second cross-sectional view, the first epitaxial structure is located on the sidewall of the first semiconductor nanostructure, wherein, the second cross-sectional view is perpendicular to the first cross-sectional view, wherein, in a third cross-sectional view, the first epitaxial structure is suspended above the first dielectric layer, and wherein, the third cross-sectional view is parallel to the first cross-sectional view; A first conductive contact is formed above the first epitaxial structure, wherein the first conductive contact is electrically connected to a first side of the first epitaxial structure, and wherein the conductivity of the first conductive contact is greater than the conductivity of the first epitaxial structure. A first interconnect structure is formed above the first conductive contact, wherein the first interconnect structure includes a first conductive tower and a second conductive tower extending through the first interconnect structure, wherein the first conductive tower includes a first conductive pad, wherein the first conductive tower is electrically connected to the first conductive contact, wherein the second conductive tower includes a second conductive pad located in the same layer as the first conductive pad in the first interconnect structure, and wherein the first conductive pad and the second conductive pad are connected by a first conductive line. Forming a second conductive contact electrically connected to the second side of the first epitaxial structure; and A second interconnect structure is formed above the second conductive contact, wherein the second interconnect structure includes a third conductive tower and a fourth conductive tower extending through the second interconnect structure, wherein the third conductive tower includes a third conductive pad, wherein the third conductive tower is electrically connected to the second conductive contact, wherein the fourth conductive tower includes a fourth conductive pad located in the same layer as the third conductive pad in the second interconnect structure, and wherein the third conductive pad and the fourth conductive pad are connected by a second conductive line.

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