Semiconductor device and method of manufacturing a semiconductor device

Abstract

According to various embodiments, a semiconductor device includes: a semiconductor substrate having a front side and a back side opposite to the front side; a first power supply circuit disposed on the front side of the semiconductor substrate and extending over an active region; a second power supply circuit disposed on the back side of the semiconductor substrate; a power tap unit including a feedthrough via coupled to the first power supply circuit and the second power supply circuit, and the power tap unit being configured to provide power from the first power supply circuit to the second power supply circuit; and an insulating layer disposed over the front side of the semiconductor substrate and extending over the power tap unit and a portion of the active region. An FTV (Functional Voltage Transmitter) is connected to a via contact through the insulating layer. Embodiments of this disclosure also relate to methods of manufacturing a semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] Driven by continuous technological advancements in materials and circuit design, the integrated circuit (IC) industry has experienced rapid growth. These advancements have enabled successive generations of ICs to be smaller and more complex than their predecessors. Over time, the functional density of ICs (i.e., the number of interconnect devices per unit chip area) typically increases, while the minimum geometry (the smallest component or line that can be formed using a given manufacturing process) decreases. This trend of device scaling has yielded significant benefits, including improved production efficiency and reduced manufacturing costs. However, continuous scaling has also introduced greater complexity into IC handling and manufacturing, requiring corresponding innovations in manufacturing technologies to fully realize the advantages of advanced IC designs. Summary of the Invention

[0003] One embodiment of this application provides a semiconductor device, comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first power supply circuit disposed on the front side of the semiconductor substrate and extending over an active region; a second power supply circuit disposed on the back side of the semiconductor substrate; a power tap unit including a feedthrough via coupled to the first power supply circuit and the second power supply circuit, and configured to provide power from the first power supply circuit to the second power supply circuit; and an insulating layer disposed over the front side of the semiconductor substrate and extending over the power tap unit and a portion of the active region, wherein: the insulating layer includes a first surface facing the semiconductor substrate and a second surface facing away from the semiconductor substrate; the feedthrough via extends from the back side of the semiconductor substrate toward the insulating layer in a direction from the back side to the front side; and the first power supply circuit includes a plurality of dielectric layers interleaved by a plurality of etch stop layers, and the first power supply circuit includes a plurality of metal lines disposed in the plurality of dielectric layers.

[0004] Another embodiment of this application provides a semiconductor device, comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first active region and a second active region located on the front side of the semiconductor substrate and extending longitudinally across the semiconductor substrate along a first direction; an isolation member located between the first active region and the second active region; a back-side circuit located on the back side of the semiconductor substrate and including a first conductor located in a first dielectric layer; a front-side circuit located on the front side of the semiconductor substrate and including a second conductor located in a second dielectric layer; a feedthrough via electrically connecting the first conductor to the second conductor; and an insulating layer disposed between the first dielectric layer and the second dielectric layer, wherein the insulating layer includes a first surface facing the semiconductor substrate and a second surface facing away from the semiconductor substrate, wherein the first surface is closer to the semiconductor substrate than at least a portion of a channel region of at least one of the first active region and the second active region.

[0005] This application embodiment further provides a method for manufacturing a semiconductor device, comprising: performing a processing operation to form a feedthrough via, the feedthrough via connecting a back-side circuit located above a back side of a substrate to a front-side circuit located on a front side of the substrate, wherein an active region is located above the front side of the substrate, and the active region extends longitudinally along a first direction, the processing operation comprising:

[0006] An insulating layer is deposited over the front side of the substrate such that the insulating layer is formed over the source / drain components of the field-effect transistor in the active region, and such that the insulating layer extends laterally from the field-effect transistor toward the power tap unit region of the substrate along a second direction intersecting the first direction.

[0007] Perform a first etching operation to form a first opening in the insulating layer above the source / drain components and a second opening in the insulating layer above the power tap unit region;

[0008] A metal silicide layer is formed in the first opening and above the source / drain components;

[0009] Conductive material is deposited in the first opening and over the metal silicide layer to form a conductive power / drain contact, which is electrically connected to the source / drain component through the metal silicide layer;

[0010] The conductive material is deposited in the second opening to form a through-hole contact;

[0011] A second etching operation is performed through the back side of the substrate to form a via opening extending from the back side of the substrate toward the insulating layer along a third direction from the back side to the front side; and

[0012] The conductive material is deposited in the via opening to form the feedthrough via.

[0013] Wherein: the insulating layer is an etch stop layer for the first etch operation and the second etch operation; the source / drain component includes an epitaxial semiconductor layer having a thickness along the third direction and a width along the first and second directions, and the thickness is different from the width; and the first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the conductive source / drain contact. Attached Figure Description

[0014] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0015] Figure 1 It is a block diagram of a semiconductor device according to various embodiments.

[0016] Figure 2 It is a vertical cross-sectional view of a semiconductor device according to various embodiments.

[0017] Figure 3A This is a vertical cross-sectional view showing the semiconductor device structure with front and back interconnect structures according to various embodiments.

[0018] Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of the components of a semiconductor device structure.

[0019] Figure 3C According to various embodiments Figure 3A A vertical cross-sectional view of the components of a semiconductor device structure.

[0020] Figure 4A This is a three-dimensional perspective view of a semiconductor device according to some embodiments, the semiconductor device including a power tap cell configured for power delivery.

[0021] Figure 4B This is a layout diagram showing a plan view of a semiconductor device according to some embodiments.

[0022] Figure 5AIt is a layout diagram of a portion of a semiconductor device including a power tap unit according to various embodiments.

[0023] Figure 5B , Figure 5C and Figure 5D According to various embodiments Figure 5A The layout diagram shows a vertical cross-sectional view of the semiconductor device.

[0024] Figure 6A It is a layout diagram of a portion of a semiconductor device including a power tap unit according to various embodiments.

[0025] Figure 6B and Figure 6C According to various embodiments Figure 6A The layout diagram shows a vertical cross-sectional view of the semiconductor device.

[0026] Figure 7A and Figure 7B It is a vertical cross-sectional view of a semiconductor device according to various embodiments.

[0027] Figure 8A and Figure 8B It is a vertical cross-sectional view of a semiconductor device according to various embodiments.

[0028] Figures 9A to 9D This is a vertical cross-sectional view of the structure used in the processing operation for manufacturing feedthrough holes according to various embodiments.

[0029] Figures 10A to 10D This is a vertical cross-sectional view of the structure used in the processing operation for manufacturing feedthrough holes according to various embodiments.

[0030] Figure 11A and Figure 11B It is a vertical cross-sectional view of the structure for forming source / drain and through-hole contacts according to various embodiments.

[0031] Figure 12 This is a flowchart of the operation of a method for manufacturing a semiconductor device according to various embodiments. Detailed Implementation

[0032] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0033] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. Spatial relative terms are intended to include different orientations of the device in use or operation, in addition to the orientations shown in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise described, does not mean an element from A, an element from B, and an element from C.

[0034] The disclosed embodiments advantageously provide a semiconductor device including an insulating layer that serves as an etch stop layer for both the front-side process of forming source / drain contacts and the back-side process of forming feedthrough vias. The use of the insulating layer improves the manufacturing process, resulting in increased contact depth consistency for the source / drain contacts and similar depth consistency for the feedthrough vias. According to various embodiments, the presence of the insulating layer results in the formation of feedthrough vias with similar depths, whether formed in a diced metal gate (CMG) region or a region without a CMG. The manufacturing process improvements provided by using the insulating layer exhibit improved processing yields and provide source / drain contacts and feedthrough vias, as well as via contacts with reduced contact resistance and correspondingly improved performance.

[0035] Figure 1 This is a block diagram of a semiconductor device 100 according to various embodiments. This block diagram is a simplified representation of the semiconductor device 100, in which many components are omitted or shown in a simplified form. Figure 1In this embodiment, the semiconductor device 100 includes processing circuitry 110 and memory circuitry 120, etc. In some embodiments, at least one of the processing circuitry 110 and memory circuitry 120 includes one or more circuit blocks. For example, memory circuitry 120 includes a first circuit block 122 corresponding to a memory cell array, a second circuit block 124 corresponding to a first portion of the control circuitry of memory circuitry 120, and a third circuit block 126 corresponding to a second portion of the control circuitry of memory circuitry 120.

[0036] In some embodiments, the second circuit block 124 includes a column decoder, a plurality of precharge drivers, a plurality of sense amplifiers, and / or a plurality of bit line drivers. The third circuit block 126 may include a row decoder and / or a plurality of word line drivers. Furthermore, in some embodiments, the second circuit block 124 and / or the third circuit block 126 may also include one or more clock generators configured to provide clock signals to various components of the memory circuit 120, one or more input / output (I / O) circuits for data exchange with external devices, and / or one or more control circuit blocks configured to control various operations within the memory circuit 120.

[0037] exist Figure 1 In this work, as a non-limiting example, memory circuitry 120 is shown comprising an array of memory cells, such as a first circuit block 122. In some embodiments, memory circuitry 120 includes a plurality of memory cells arranged to be accessible via respective control circuitry or a shared control circuitry. To form a set of pseudo-structures, two boundary regions 132 and 134 are defined on opposite sides of the first circuit block 122 (i.e., the memory cell array) along a first horizontal direction (e.g., the X direction). For example, in some embodiments, a plurality of pseudo-gate structures are disposed within boundary regions 132 and 134, located outside the memory cell array and adjacent to its respective boundaries. In some embodiments, one or more active regions extend across the boundary between the memory cell array and boundary regions 132 or 134. In some embodiments, pseudo-structures including pseudo-gate structures and extended active regions may be used to maintain the continuity of the layout pattern of the semiconductor device, reduce manufacturing complexity, and thereby improve the performance and manufacturing yield of the semiconductor device.

[0038] In some embodiments, the dummy gate structures and extended active regions within boundary regions 132 and 134 also define non-functional transistors. In some embodiments, the non-functional transistors are electrically disabled or electrically isolated from the memory cell array to reduce current leakage. In some embodiments, a gate-connected configuration is employed, wherein wires are electrically coupled to one or more dummy gate structures and configured to apply a reference voltage to turn off the corresponding non-functional transistor. This gate-connected configuration establishes a balanced gate setup for the non-functional transistors, thereby reducing the likelihood of plasma-induced damage, particularly in applications utilizing back-side power rail schemes (e.g., power rails located on the back side of the substrate, as referenced). Figures 2 to 3C (Further description). Furthermore, in other embodiments, as described in more detail below, a continuous polysilicon on diffusion edge (CPODE) structure is used to isolate non-functional transistors from the memory cell array.

[0039] Figure 2 This is a vertical cross-sectional view of a semiconductor device 200 according to various embodiments. In some embodiments, the cross-sectional view is a simplified representation of the semiconductor device 200, in which many components are omitted or depicted in a simplified form. In some embodiments. As a non-limiting example, the semiconductor device 200 ( Figure 2 ) corresponds to Figure 1 The semiconductor device 100 described herein.

[0040] Semiconductor Devices 200 ( Figure 2 The device includes a substrate 210 having an active region 212 and a gate structure 214 formed on or partially within the substrate 210. In this embodiment, the semiconductor device 200 includes a metal-to-drain / source (MD) structure 222 coupled to the active region 212. The device also includes a via-to-drain / source (VD) structure coupled to the MD structure 222, referred to as the via structure at the VD layer. Furthermore, a via-to-gate (VG) structure is coupled to the gate structure 214, referred to as the via structure at the VG layer. In some embodiments, the semiconductor device 200 also includes vias to metal-to-diffusion rails (VDRs) (e.g., see...). Figure 2 , Figure 3B and Figure 3C Each via is formed as a conductive segment or wire, configured to connect to one or more MD structures 222. These VDRs are also referred to as wires at the VDR layer. In some embodiments, the VD layer, VG layer, and VDR layer may overlap or merge with each other and are collectively referred to as the VD / VG / VDR layer.

[0041] In some embodiments, the semiconductor device 200 further includes a plurality of metallization layers (e.g., M0, M1, M2, ..., Mx-1 and Mx layers) and a plurality of via layers (e.g., V0, V1, V2, ..., Vx-2 and Vx-1 layers) disposed above the VD / VG / VDR layers and the substrate 210, where x is a positive integer. The metallization layers include corresponding dielectric layers, with conductive lines extending horizontally along a plane spanned by the X and Y directions and embedded within the dielectric layers. Similarly, the via layers include corresponding dielectric layers in which via structures are embedded. The metallization layers and via layers are stacked alternately along a vertical direction (e.g., the Z direction).

[0042] In some embodiments, the Vx-1 layer includes a via structure connecting wires in the Mx-1 and Mx layers. The M0 layer represents the lowest metallization layer located above the substrate 210. The plurality of metallization layers and via layers include conductive materials such as copper, aluminum, gold, tungsten, or combinations thereof. Figure 2 In this context, reference numeral 232 indicates a dielectric layer that overlaps with the metallization layer, via layer, VD / VG / VDR layer, and any dielectric layer present on the front side of the substrate 210. In some embodiments, these dielectric layers 232 include silicon dioxide, a low-k dielectric material (i.e., a material with a dielectric constant lower than that of silicon dioxide), and / or an air gap.

[0043] As a non-restrictive example, Figure 2 The semiconductor device 200 also includes conductive structures located beneath the substrate 210. For example, the device includes back-side metallization layers BMO and BM1, and back-side via layers BVD and BVO. In this embodiment, the BVD layer includes a back-side via structure connecting the active region 212 to back-side conductors in the BMO layer. The BVO layer includes a back-side via structure connecting back-side conductors in the BMO layer to those in the BM1 layer. In some embodiments, the BMO layer refers to the uppermost back-side metallization layer located beneath the substrate 210.

[0044] exist Figure 2 In some embodiments, the semiconductor device 200 includes two back-side metallization layers (BM0, BM1) and corresponding back-side via layers (BVD, BVO). In some embodiments, the number of back-side metallization layers beneath the substrate 210 ranges from 2 to 6. Some or all of these back-side conductive structures (such as the back-side metallization layers BM0 and BM1 and the back-side via layers BVD and BVO) may be at least partially embedded within the substrate 210. In other embodiments, the semiconductor device omits the back-side conductive structures entirely.

[0045] In some embodiments, the back-side metallization layers BMO and BM1, and the back-side via layers BVD and BV0, comprise conductive materials such as copper, aluminum, gold, tungsten, or combinations thereof. The back-side metallization layers include corresponding dielectric layers in which conductive wires are embedded, and the back-side via layers include corresponding dielectric layers in which via structures are embedded. Figure 2 In this context, reference numeral 234 denotes a dielectric layer associated with a back-side metallization layer, a back-side via layer, and any dielectric layer present on the back side of the substrate 210. In some embodiments, these dielectric layers 234 include silicon dioxide, a low-dielectric-constant material, and / or air gaps.

[0046] In some embodiments, the semiconductor device includes one or more redistribution layers and a conductive pad structure located above the redistribution layers. In some embodiments, the semiconductor device includes a conductive terminal structure, such as a conductive bump, copper pillar bump, solder bump, or similar structure, located above the conductive pad structure. Furthermore, in some embodiments, the semiconductor device includes one or more back-side redistribution layers and a back-side conductive pad structure located below the back-side redistribution layers. In some embodiments, the back-side conductive terminal structure (including conductive bumps, copper pillar bumps, solder bumps, or similar structures) is located below the back-side conductive pad structure.

[0047] In some embodiments, the semiconductor device 200 includes transistors formed based on active regions 212 and gate structures 214 in a front-end process (FEOL) portion of the device. For example, the channel of the transistor is defined by a portion of the active region overlapping the gate structure, and two drain / source regions are defined by adjacent portions of the active regions on either side of the channel. One or more functional circuit blocks (such as memory cells or control circuitry in a memory cell array) of the semiconductor device 200 are formed by electrically connecting transistors within the FEOL portion. In some embodiments, portions of the semiconductor device 200 located at and above a given metallization layer (e.g., M5 layer and above) correspond to back-end process (BEOL) portions. According to various embodiments, functional circuit blocks are formed by electrically connecting transistors, capacitors, and / or resistors formed in the BEOL portion.

[0048] Figure 3A This is a vertical cross-sectional view of a semiconductor device structure 300a showing the front and back interconnect structures according to various embodiments. Figure 3B and Figure 3C According to various embodiments Figure 3A Vertical cross-sectional view of the components (300b, 300c1, 300c2) of the semiconductor device structure 300a.

[0049] refer to Figure 3AThe semiconductor device structure 300a includes a transistor structure formed in a substrate 210, the transistor structure having a gate structure 214 formed over an active region 212. In this embodiment, the transistor structure is configured as a gate-all-around (GAA) field-effect transistor having a stacked channel region 216 extending longitudinally along a first direction (X direction) between a first source / drain (SD) region and a second source / drain (SD) region. The gate structure 214 surrounds the channel region 216, and the SD region is an epitaxial semiconductor layer electrically coupled to the channel region 216. The GAA transistor also includes an insulating internal spacer layer 220 that electrically insulates the gate from the SD region. Although Figure 3A The diagram shows three stacked channel regions 216, but this disclosure is not limited thereto, and various other embodiments include different numbers of channel regions 216, such that the number of channel regions 216 is ≥1. Figure 3A The embodiments (including GAA transistors) are provided by way of example only, and in other embodiments, various other semiconductor devices (e.g., planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), etc.) are possible.

[0050] Semiconductor device structure 300a includes an SD contact structure (MD) electrically connected to an SD region. A via (VD) is electrically connected to the SD contact structure MD. A front-side interconnect structure includes metallization layers (M0, M1, M2) embedded within a front-side dielectric layer 232. The via VD electrically connects the SD contact MD to the first metallization layer M0, and a via-to-gate (VG) structure electrically connects the gate structure 214 to the first metallization layer M0. Semiconductor device structure 300a also includes back-side metallization layers (BM0, BM1) configured to provide power to and route signals to and from a transistor structure formed in a substrate 210, as described below.

[0051] refer to Figure 3A and Figure 3B The semiconductor device structure 300a includes component 300b, wherein a back-side via (BVD) extends through the back layer of substrate 210 and electrically connects the SD region of the transistor structure to a first back-side metallization layer BMO. Therefore, component 300b is configured as an interconnect structure to provide power to the transistor structure. In this respect, the BVD connects the SD structure to a back-side power rail formed in the first back-side metallization layer BMO. Component 300b also includes an etch stop layer 218 and a metal-to-diffusion rail (VDR) structure electrically connecting the SD contact MD of the transistor structure to other circuit elements. A metal silicide layer 312 is also provided between the BVD and the SD structure, and between the SD structure and the SD contact MD. The metal silicide layer 312... Figure 3B The structures shown are identical, but according to various embodiments, the structures may have different components at different levels of the structure.

[0052] refer to Figure 3A and Figure 3C The semiconductor device structure 300a also includes components (300c1, 300c2) wherein feedthrough vias (FTVs) extend through the substrate 210 and various dielectric layers (232, 234) to electrically connect the first back-side metallization layer BMO to the first front-side metallization layer M0 via a contact MD structure. Therefore, component 300c1 or 300c2 is configured as an interconnect structure that provides signal vias connecting the transistor structure to the front-side interconnect structures (M0, M1, M2) and the back-side interconnect structures (BM0, BM1). Figure 3A and Figure 3C It was not drawn to scale, and for clarity, Figure 3C The structure (300c1, 300c2) was enlarged.

[0053] exist Figure 3A and Figure 3C In one embodiment, the first component 300c1 includes a first FTV electrically connecting the SD contact MD to the back-side interconnect structure (BM0, BM1), and the second component 300c2 includes a second FTV electrically connecting the gate structure 214 to the back-side interconnect structure (BM0, BM1). Components (300c1, 300c2) also include an etch stop layer 218 and a metal-to-diffusion-rail (VDR) structure electrically connecting the FTV to other circuit elements.

[0054] Figure 4A This is a three-dimensional perspective view of a semiconductor device 400 according to some embodiments, the semiconductor device 400 including a power tap unit 460 configured for power delivery. The semiconductor device 400 includes metal lines 110a, 110b and 110c, metal lines 120a, 120b and 120c, metal lines 130a and 130b, metal lines 140a, 440b and 140c, a CFET (unlabeled) and the power tap unit 460.

[0055] The power tap unit 460 of the semiconductor device 400 includes a feedthrough via (FTV). For example, the power tap unit 460 includes an FTV coupled between a metal line 110a on the back side and a metal line 120b on the front side. (Reference) Figure 4A FTV uses metal wire 440b (i.e. Figure 4A BM0 (V) SS The FTV is coupled to metal line 110a. The FTV is configured to couple a negative voltage level (i.e., V) to the metal line 110a. SSMetal lines 110a on the back side are transmitted to metal lines 440b and 120b on the front side. The back and front sides are located on opposite sides of the CFET of the semiconductor device 400.

[0056] In some embodiments, the power tap unit 460 includes a metal wire 110a coupled to the back side and a metal wire 130a coupled to the front side (i.e., Figure 4A M1 (V) SS A super FTV (SFTV) (not shown) between ) ) ). In such an embodiment, the SFTV is configured to transmit a negative voltage level (i.e. V ) ... SS The metal wire 110a at the back side is transmitted to the metal wire 130a at the front side. The metal wire 130a passes through through holes (i.e., Figure 4A V0 in the figure is coupled to metal lines 120a, 120b, and 120c. Negative power level V SS The power is transmitted from metal wire 130a to metal wires 120a, 120b, and 120c. Metal wires 120a, 120b, and 120c are configured to transmit the negative power level V when needed. SS Passed to CFET.

[0057] Figure 4B This is a layout diagram illustrating a plan view of a semiconductor device 400 according to some embodiments. The semiconductor device 400 includes a second metal layer (i.e., ...) located on the back side. Figure 4B Metal lines 110a, 110b, 110c, 110d, and 110e in BM1. Metal lines 110a, 110b, and 110c are configured to provide a negative voltage level (i.e., V) on the back side. SS Metal wires 110e and 110d are configured to provide a positive voltage level (i.e., V) at the back side. DD The semiconductor device 400 also includes a first metal layer located on the back side (i.e., Figure 4B Multiple metal lines in the first metal layer (BM0) on the back side. The metal lines in the first metal layer (BM0) on the back side are configured to provide a positive voltage level (i.e., V). DD The semiconductor device 400 also includes a first metal layer located on the front side (i.e., Figure 4B Multiple metal lines in the first metal layer (M0) at the front. The metal lines in the first metal layer (M0) at the front are configured to provide a negative voltage level (i.e., V). SS ).

[0058] refer to Figure 4B The semiconductor device 400 includes a plurality of power tap units 460 configured to tap negative voltage levels (i.e., V). SS Metal lines 110a, 110b, and 110c from the second metal layer (BM1) on the back side are transferred to the first layer on the front side (i.e., Figure 4A Multiple metal wires in M0 (of the model). Reference Figure 4A and Figure 4B Semiconductor device 400 has a power tap unit 460 every four unit heights, but in other embodiments, other configurations and spacing of power tap units 460 are possible.

[0059] Figure 5A This is a layout diagram of a portion of a semiconductor device including a power tap unit 460 according to various embodiments, as shown in plan view 500a. Layout view 500a includes layout patterns corresponding to an oxide diffusion (OD) layer (referred to as "OD" in the illustration) and a gate polysilicon (PO) layer (referred to as "PO" in the illustration). In some embodiments, the layout pattern included in the OD layer (referred to as the "OD layout pattern") represents the formation of various active regions of the semiconductor device, and the layout pattern included in the PO layer (referred to as the "PO layout pattern") represents the formation of a corresponding gate structure. In corresponding embodiments, the gate structure 214 (e.g., see...) Figure 3A This corresponds to a polysilicon gate structure or a metal gate structure formed using a polysilicon structure as a sacrificial placeholder.

[0060] exist Figure 5A In the diagram, layout diagram 500a includes OD layout patterns 502a, 502b, 502c, and 502d, which represent the active regions of the resulting semiconductor device. In this embodiment, the semiconductor device includes active regions corresponding to OD layout patterns 502a and 502b for forming p-type transistors, and active regions corresponding to OD layout patterns 502c and 502d for forming n-type transistors. In some embodiments, the active regions extend along a first horizontal direction (e.g., the X direction) and are located on or at least partially embedded in the substrate 210 of the semiconductor device (e.g., see...). Figure 2 The semiconductor device also includes pseudo-OD layout patterns 504a and 504b formed in the power tap unit 460 region. Each of the active regions (502a, 502b, 502c, 502d) and pseudo-OD layout patterns (504a, 504b) is surrounded by a front dielectric layer 232 that serves as an isolation component to separate adjacent OD layout patterns.

[0061] exist Figure 5ALayout 500a also includes PO layout patterns 506a, 506b, and 506c, which represent the gate structure of the resulting semiconductor device. In some embodiments, the gate structure extends along a second horizontal direction (e.g., the Y direction) and is located above the respective active regions (502a, 502b). Layout 500a also includes various metal-to-drain / source (MD) structures that electrically connect the source / drain structures SD of adjacent active layers (e.g., OD layout patterns 502a and 502b). Layout 500a also includes a CPODE structure within the power tap unit 460 region, which also serves as an isolation structure. In this respect, the CPODE region is generated by replacing the conductive material of the gate region with a non-conductive dielectric material.

[0062] In various embodiments, feedthrough vias (FTVs) are formed by first performing a cleaved metal gate (CMG) process on the front side of the semiconductor substrate. The CMG process includes selective etching to remove portions of the metal gate material in designated areas (e.g., removing portions of PO layout patterns 506a, 506b, and 506c). After performing the gate cleavage, an interlayer dielectric (ILD) is deposited to fill and isolate the cleaved areas (e.g., see...). Figure 5A (CMG shading in the figure, as shown in the legend). According to some embodiments, the ILD includes a conformal interlayer oxide (CIR), which provides gap-filling coverage over the non-planar topography produced during CMG etching. The CIR oxide enhances dielectric isolation and serves as a structural layer for subsequent bonding and back-side processing steps. According to various embodiments, the CMG process also includes planarizing the front-side dielectric to prepare a substrate for bonding and thinning operations. As described in more detail below, the FTV is then formed by etching via openings through the back side of the substrate and depositing conductive material in the via openings.

[0063] Figure 5B , Figure 5C and Figure 5D yes Figure 5A The layout diagram shows vertical cross-sectional views (500b, 500c, 500d) of the semiconductor devices. (Limited) Figure 5B , Figure 5C , Figure 5D The vertical planes of the cross-sectional view are respectively composed of Figure 5A The cross sections B-B', C-C', and D-D' in the figure are represented. (Reference) Figure 5BThe semiconductor device includes a semiconductor substrate 210 having a front side 508a (facing upward) and a back side 508b (facing downward) opposite to the front side 508a. The semiconductor device includes a plurality of active regions (502a, 502b, 502c, 502d), including a first active region 502a and a second active region 502b, which are formed on the front side of the semiconductor substrate 210 and extend longitudinally along a first direction (X direction) parallel to a plane (XY plane) of the semiconductor substrate 210. The semiconductor device also includes an isolation member 232a (e.g., a shallow trench isolation (STI) member) located between the first and second active regions.

[0064] The semiconductor device includes a back-side circuit on the back side of a semiconductor substrate 210 and a front-side circuit on the front side of the semiconductor substrate 210. The back-side circuit includes a first conductor BMO located in a first dielectric layer (234a, 234b), and the front-side circuit includes a second conductor M0 located in a second dielectric layer (232c, 232d). The semiconductor device also includes a feedthrough via (FTV) electrically connecting the first conductor BMO to the second conductor M0. As described above, the FTV is formed in the power tap unit 460 region, which is defined on both sides by pseudo-OD layout patterns (504a, 504b). According to various embodiments, at least one of the first conductor BMO or the second conductor M0 includes at least one of W, Ru, Co, Rh, Cu, TiN, TaN, or other materials containing Ti or Ta.

[0065] The semiconductor device further includes an insulating layer 510 disposed between a first dielectric layer (234a, 234b) and a second dielectric layer (232c, 232d), and includes a first surface 512a facing the semiconductor substrate 210 and a second surface 512b facing away from the semiconductor substrate 210. (Reference) Figure 5B The first surface 512a is closer to the semiconductor substrate 210 than at least a portion of the channel region 216 of at least one of the first active regions 502a and the second active region 502b. According to various embodiments, the insulating layer 510 is a hard mask layer or a multilayer structure comprising silicon nitride. The insulating layer 510 is formed over a first interlayer dielectric layer 232b, which is formed over the active regions (502a, 502b, 502c, 502d) and the pseudo-OD layout pattern (504a, 504b). Reference Figure 5B and Figure 5C The FTV is formed in the area corresponding to the area where the CMG operation has been performed, as described in more detail below.

[0066] refer to Figure 5A and Figure 5BThe active regions (502a, 502b, 502c, 502d) include field-effect transistors (FETs), which include source / drain components (SD), as shown in the reference below. Figure 5D Described in more detail. An insulating layer 510 is disposed on the source / drain component SD and extends laterally (e.g., along the Y direction) from the field-effect transistor (e.g., from the active regions (502a, 502b)) toward the FTV. The semiconductor device also includes a power / drain contact 514, which is an MD structure formed in the insulating layer 510 and electrically connected to the source / drain component SD. The semiconductor device also includes a via contact 516, which is also an MD structure formed in the insulating layer 510 and electrically connected to the FTV.

[0067] According to various embodiments, the through-hole contact 516 has a through-hole surface 520 facing the semiconductor substrate 210, such that the through-hole surface 520 is flush with the first surface 512a of the insulating layer 510. According to various embodiments, the power / drain contact 514 has a contact surface 522 facing the semiconductor substrate 210, which is flush with both the through-hole surface 520 and the first surface 512a of the insulating layer 510. This configuration of the through-hole surface 520 and the contact surface 522 is provided by way of example only, and this disclosure is not limited thereto. In this respect, according to other embodiments, the through-hole surface 520 and the contact surface 522 do not need to be flush with each other, or do not need to be flush with the first surface 512a of the insulating layer 510, as referenced below. Figure 8A and Figure 8B As stated above. (Reference) Figure 5B and Figure 5C The CMG region includes an insulating dielectric with a surface 524 that is flush with the via surface 520 and the first surface 512a of the insulating layer 510. However, in other embodiments, the surface 524 of the insulating dielectric does not need to be aligned with the first surface 512a of the insulating layer 510, as shown below. Figure 8A and Figure 8B A more detailed description.

[0068] In various embodiments, the interlayer dielectric 232b and the CMG dielectric structure comprise a single material layer or a composite of multiple dielectric layers. According to various embodiments, these dielectric stacks are designed to include materials such as silicon dioxide (SiO2), carbon-doped silicon oxide (SiCO), fluorinated silicon oxide (SiO2:F), silicon nitride, silicon nitride carbon (SiCN), and other oxide, nitrogen, or carbon-containing dielectric materials. The selection and sequential configuration of these layers are designed to achieve specific mechanical, electronic, or process integration goals, including improved gap-filling performance, stress control, etch selectivity, or adhesion to adjacent layers.

[0069] refer to Figure 5Band Figure 5C The semiconductor device also includes a via isolation structure 526 formed around the FTV, comprising a single dielectric layer or multilayer composite formed of one or more of silicon dioxide, carbon-doped silicon oxide, fluorinated silicon oxide, silicon nitride, silicon nitride carbon or other dielectric materials containing oxides, nitrogen or carbon.

[0070] Figure 5D According to various embodiments Figure 5A The layout diagram shows a vertical cross-sectional view of a semiconductor device (including a field-effect transistor). Figure 5D The vertical plane of the cross-section (i.e.) Figure 5D The XZ plane in the middle) is composed of Figure 5A The cross-section D-D' is represented by this plane. This plane cuts through a segment of the OD layout pattern 502b, which includes multiple transistor structures configured as a gate-all-around (GAA) transistor device. Figure 5D The embodiments (including GAA transistor devices) are provided by way of example only, and in other embodiments, various other semiconductor devices (e.g., planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), etc.) are possible.

[0071] Figure 5D Each GAA device includes multiple stacked semiconductor nanostructure layers configured as channel region 216. Although Figure 5D The diagram illustrates three stacked channel regions 216, but this disclosure is not limited thereto, and various other embodiments include different numbers of channel regions 216, such that the number of channel regions 216 is ≥1. The device also includes a gate structure 214 comprising a conductive gate electrode layer 215a surrounding the channel layers 216. The gate electrode layer 215a includes a conductive material separated from the plurality of channel layers 216 by a gate dielectric layer 215b.

[0072] The GAA transistor device also includes source / drain (SD) components formed above the ends of a plurality of channel layers 216. According to some embodiments, the SD components are of similar structure and are collectively referred to as source / drain components. In other words, a given SD structure can be used as either a source or a drain, depending on how it is configured in a given circuit. Each GAA device also includes an insulating internal spacer layer 220 that further electrically insulates the gate electrode 215a from the SD components.

[0073] According to various embodiments, a GAA transistor device is formed above a semiconductor substrate 210, which has a front side (in...) Figure 5D (Middle side up) and dorsal side (in) Figure 5D (Middle facing downwards). In this embodiment, Figure 5DThe plane intersects the semiconductor layer 210 along the longitudinal direction (i.e., along the

[110] crystal orientation of the SD component). In some embodiments, the SD component has a thickness T along a third direction (Z direction) and a width W along a first direction and a second direction, and the thickness T is different from the width W.

[0074] As described above, the GAA device further includes a front contact (e.g., a metal-to-drain / source (MD) structure) 514. Each front contact 514 includes a conductive material coupled to the SD component. Each front contact 514 also includes a metal silicide layer 312 formed between the contact structure 514 and the SD component. According to various embodiments, the SD component is formed of a doped semiconductor material (e.g., silicon, SiGe, etc.) and a conductive material of the front contact MD metal. Therefore, the silicide layer 312 is selected as a metal / semiconductor alloy, such as TiSi, TiSiGe, MoSi, MoSiGe, etc. According to various embodiments, the silicide layer 312 has a thickness between about 0.5 nm and about 10 nm. According to various embodiments, the first conductivity of the metal silicide layer 312 has a value between a second conductivity of the epitaxial semiconductor SD component and a third conductivity of the front contact 514.

[0075] The gate structure 214 further includes a first gate spacer layer 238a and a second gate spacer layer 238b. According to various embodiments, in some embodiments, the dielectric constant of the second gate spacer layer 238b exceeds the dielectric constant of the first gate spacer layer 238a, and the second gate spacer layer 238b exhibits greater etch resistance compared to the first gate spacer layer 238a. According to some embodiments, the dielectric constant of the gate dielectric layer 215b is greater than the dielectric constant of at least one of the gate spacers (238a, 238b). Additionally, according to some embodiments, the first thickness t1 of at least one of the gate spacers (238a, 238b) is greater than the second thickness t2 of the gate dielectric layer 215b.

[0076] According to various embodiments, in some embodiments, the first gate spacer layer 238a comprises silicon oxide, silicon carbide, or a suitable low-k dielectric material. In some embodiments, the second gate spacer layer 238b comprises silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. As described above, Figure 5D The structure also includes an insulating layer 510, which serves as an etch stop layer. Figure 5D The structure also includes a front dielectric layer 232c formed above the insulating layer 510. A power / drain contact 514, serving as the MD structure, is formed within the insulating layer 510 and is electrically connected to the SD component.

[0077] Figure 5DThe structure also includes a liner layer L0 and an isolation structure 242 formed between the SD component and the liner layer L0. According to some embodiments, the liner layer L0 is an epitaxially formed semiconductor layer. In some embodiments, the isolation structure 242 is a dielectric layer and is referred to as a “flexible bottom isolation” (FBI) structure. The isolation structure 242 reduces or substantially prevents current leakage between the SD component and the semiconductor layer 210. In some embodiments, the isolation structure 242 comprises silicon oxide, silicon nitride, SiCN, SiCON, SiOC, SiC, or other suitable materials and is formed by oxidation (e.g., forming silicon oxide) or by a conformal deposition process and subsequent further processing, as described below. In other embodiments, the isolation structure 242 is an epitaxial semiconductor layer.

[0078] Figure 6A It is a layout diagram of a portion of the semiconductor device including the power tap unit according to various embodiments, and Figure 6B and Figure 6C yes Figure 6A The layout diagram shows a vertical cross-sectional view of the semiconductor device. Figures 6A to 6C Corresponding to Figures 5A to 5C Those same structures, except for the absence of the CMG region. Used to form Figures 6A to 6C The processing operations for the structure are similar to those used to form Figures 5A to 5C The structures are as follows (see reference below). Figures 9A to 10D A more detailed description.

[0079] Figure 7A and Figure 7B It is a vertical cross-sectional view of a semiconductor device according to various embodiments. Figure 7A and Figure 7B have Figure 6B and Figure 6C The same component shown, except that the FTV rests on two through-hole contacts (516a, 516b) (e.g., on the slot MD), instead of... Figure 6B and Figure 6C On a single through-hole contact 516.

[0080] Figure 8A and Figure 8B It is a vertical cross-sectional view of a semiconductor device according to various embodiments. Figure 8A and Figure 8B With Figure 5B and Figure 5C The same components are shown, except that the through-hole contact 516 has a through-hole surface 520 facing the semiconductor substrate 210, which is closer to the semiconductor substrate 210 than the first surface 512a of the insulating layer 510. According to various embodiments, the displacement D between the through-hole surface 520 and the first surface 512a of the insulating layer 510 is in the range of greater than 0 nm to about 5 nm.

[0081] Figures 9A to 9D This is a vertical cross-sectional view of the structure used in the processing operation for manufacturing FTV according to various embodiments. Figures 9A to 9D Each element includes a right-hand structure and a left-hand structure. The right-hand structure includes the CMG region, while the left-hand structure omits the CMG region. The processing operations for both structures are the same. (See reference) Figure 9A An interlayer dielectric (ILD) is formed over an insulating layer 510 with through-hole contacts (MDs). According to some embodiments, the ILD in the CMG region comprises a conformal interlayer oxide (CIR), which provides gap-filling coverage over a non-planar topography produced during CMG etching. The CIR oxide enhances dielectric isolation and serves as a structural layer for subsequent bonding and back-side processing steps. The CMG process may also include planarizing the front-side dielectric to fabricate a substrate for bonding and thinning operations.

[0082] In various embodiments, each of the ILD and CMG dielectric structures may include a single material layer or a composite of multiple dielectric layers. These dielectric stacks may be designed to include materials such as silicon oxide, carbon-doped silicon oxide (SiCO), fluorinated silicon oxide (SiO2:F), silicon nitride, silicon nitride carbon (SiCN), and other oxide, nitrogen, or carbon-containing dielectric materials. The selection and order of these layers can be customized to achieve specific mechanical, electronic, or process integration goals, including improved gap-filling performance, stress control, etch selectivity, or adhesion to adjacent layers.

[0083] A bonding and thinning step (e.g., using chemical mechanical planarization (CMP)) is performed to expose the back side of the substrate. Following the back side cleaning operation is shallow trench isolation (STI) recessed etching and planarization, and subatmospheric pressure chemical vapor deposition (SACVD) of the silicon nitride layer 902 is performed to provide conformal coverage. CMP is then performed to planarize the SAC silicon nitride layer 902. After a second back side cleaning, a multilayer hard mask stack is deposited, including a plasma-enhanced oxide (PEOX) layer 904, a plasma-enhanced silicon nitride (PESIN) layer 906, and a second PEOX layer 908 (e.g., see...). Figure 9B ).

[0084] In some embodiments, layer 904 has a thickness between about 5 nm and 15 nm, layer 906 has a thickness between about 10 nm and about 20 nm, layer 908 has a thickness between about 25 nm and about 35 nm, and SAC silicon nitride layer 902 has a thickness between about 15 nm and 25 nm. In other embodiments, layer 904 has a thickness between about 8 nm and 10 nm, layer 906 has a thickness between about 11 nm and about 13 nm, layer 908 has a thickness between about 28 nm and about 30 nm, and SAC silicon nitride layer 902 has a thickness between about 17 nm and 19.1 nm.

[0085] The above operations are followed by a scrubbing and cleaning step. To define the hard mask, a thicker hard mask stack is formed on top of the oxide / nitride / oxide layer, including a base layer (BL), an intermediate layer (ML), and a patterned photoresist layer (PR) (e.g., see...). Figure 9C According to various embodiments, BL has a thickness of about 200 nm, ML has a thickness of about 26 nm, and PR has a thickness of about 120 nm. These thickness values ​​are provided by way of example only, but this disclosure is not limited thereto. In other embodiments, other thicknesses are possible. For example, in some embodiments, BL has a thickness between about 190 nm and about 210 nm, ML has a thickness between about 20 nm and about 30 nm, and PR has a thickness between about 120 nm and about 130 nm.

[0086] A pattern transfer is performed to form an opening corresponding to the FTV location. An anisotropic etching process is then used to form the FTV opening through the hard mask and the underlying dielectric layer. The material layers and thicknesses are provided only as examples, and in other embodiments, various other materials with different thicknesses are possible.

[0087] After etching the FTV opening, a via metallization process is performed. According to some embodiments, a liner layer is deposited along the sidewalls and bottom surface of the FTV opening to provide diffusion barrier and adhesion properties. According to various embodiments, the liner comprises one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable barrier metals. After liner deposition, a metal-filling process is performed to fill the FTV opening with a conductive material such as tungsten (W), cobalt (Co), or copper (Cu). Excess metal is removed using CMP to form a planarized metal FTV plug electrically coupled between the front and back metallization layers.

[0088] According to some embodiments, a silicon nitride removal (SNR) operation is performed before or after via metallization to selectively thin or pattern the silicon nitride layer surrounding the FTV. This SNR operation can form isolation regions surrounding or enclosing portions of the FTV to provide electrical isolation, structural support, or etch selectivity. After performing the SNR operation, isolation structures can be deposited in the isolation regions, comprising a single dielectric layer or a composite of multiple layers formed from materials such as silicon oxide, carbon-doped silicon oxide (SiCO), fluorinated silicon oxide (SiO2:F), silicon nitride, silicon nitride carbon (SiCN), or other oxide, nitrogen, or carbon-containing dielectric materials. The thickness, composition, and patterning of the isolation structure can be adjusted according to the desired electrical isolation, integration constraints, or reliability objectives of the device.

[0089] like Figures 9A to 9D The leftmost structure in each of these diagrams shows an FTV process formation operation performed in a region of the substrate where no CMG process was performed (e.g., see [link]). Figure 6A In this case, the front-side device layer does not include CIR oxide or other CMG-related dielectric structures. Therefore, the front-side bonding, thinning, and back-side processing steps are modified to account for the reduced topography and the absence of CMG material. These adjustments may include varying the STI trench etch depth, cleaning steps, or hard mask stack thickness to maintain etch selectivity and patterning control. Although there are no CMG components, the process operation still includes a SAC silicon nitride layer and a fully multilayer hard mask stack to support the formation of an FTV with a high aspect ratio, such as an FTV extending from a deeper metal level (e.g., M1 to BM1) or an FTV located in a region with limited lateral area for via formation. For example, in some embodiments, the FTV has a high aspect ratio ranging from about 2.5 to about 4.5 and a depth ranging from about 100 nm to about 125 nm.

[0090] Figures 10A to 10D This is a vertical cross-sectional view of the structure used in the processing operation for manufacturing feedthrough holes according to various embodiments. Figures 10A to 10D The structures (1000a, 1000b, 1000c, 1000d) correspond to simpler processing operations that omit... Figures 9A to 9D The process shown includes a subatmospheric pressure chemical vapor deposition (SACVD) silicon nitride layer and a plasma-enhanced oxide (PEOX) hard mask layer. Figures 10A to 10D The method shown reduces process complexity and overall film stack thickness, potentially reducing manufacturing time and costs. According to certain embodiments, Figures 10A to 10DThe process shown is used for a region of the substrate, where the front-side topography and the composition of the underlying layer allow for sufficient etch selectivity and pattern fidelity for feedthrough vias with aspect ratios of approximately 2 to approximately 3. This is applicable when a CMG process has already been performed on the front side (e.g., Figures 10A to 10D When this process is performed in the rightmost structure (in the diagram), the back-side processing steps are adapted to accommodate the presence of CIR and other front-side layers associated with CMG, including adjustments to cleaning, etching, and hard mask formation. Conversely, when no CMG process is performed (e.g., Figures 10A to 10D The leftmost structure in the image), the backside processing was modified to account for the absence of CIR layers and differences in the anterior morphology. Despite these differences, Figures 10A to 10D The process maintained sufficient etching selectivity and pattern fidelity under both conditions.

[0091] As described above, it includes SAC silicon nitride and oxide hard mask layers. Figures 9A to 9D The process flow is used to form feedthrough vias with higher aspect ratios, such as those extending from a second or higher metallization layer (e.g., M1 to BM1), where increased etch resistance and pattern control are desired due to the higher via geometry. According to certain embodiments, Figures 10A to 10D This process is used for applications where FTVs only connect lower metallization layers (e.g., M0 to BMO), or for applications where additional lateral regions can be used for via formation. In this case, the larger via footprint reduces the aspect ratio, allowing for etching and filling of the vias without the need for additional hard masks and SAC silicon layers. Figures 9A to 9D and Figures 10A to 10D The choices between the process flows shown can optimize manufacturing trade-offs such as process robustness, device performance, and cost efficiency.

[0092] Figure 11A and Figure 11B This is a vertical cross-sectional view of the structures (1100a, 1100b) for forming source / drain contacts 514 and via contacts 516 according to various embodiments. In this regard, metal-to-drain (MD) structures are formed to electrically connect semiconductor regions (such as epitaxial source / drain structures SD) to metal interconnect layers M0 within the device. The MD and VD structures provide a direct, low-resistance path between the active device regions (502a, 502b, 502c, 502d) and the metallized stack, enabling efficient current flow and signal routing.

[0093] refer to Figure 11AThe processing operations include patterning and etching openings (1102, 1104) in the dielectric material 232b and insulating layer 510 on the semiconductor region that serves as the target for contact formation. For the MD structure 514, opening 1102 is formed to expose the source / drain diffusion region SD for subsequent metallization. These etching steps are performed by a precision plasma or reactive ion etching (RIE) process, carefully controlled to stop or slightly recess the semiconductor surface while maintaining good profile control and etch selectivity. According to some embodiments, the openings (1102, 1104) have a depth ranging from about 20 nm to about 40 nm.

[0094] A silicide layer 312 is formed at the interface between the SD component and the source / drain contact 514 to reduce contact resistance. In some embodiments, the formation of the silicide layer 312 involves depositing a thin metal film, such as nickel (Ni), cobalt (Co), or titanium (Ti), on an exposed silicon or silicon-germanium surface, followed by rapid thermal annealing to form a low-resistance metal silicide (e.g., NiSi, CoSi2). Excess unreacted metal is removed by selective wet etching, leaving a self-aligned silicide contact that enhances conductivity between the semiconductor and the subsequently deposited metal.

[0095] Following silicide formation, an optional diffusion barrier layer or liner layer is deposited within the MD or VD opening to prevent metal diffusion and improve adhesion. Suitable liner materials include titanium nitride (TiN), tantalum nitride (TaN), or bilayer stacks such as Ti / TiN. The liner is typically deposited via physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) to ensure conformal coverage over high aspect ratio components.

[0096] Next, the openings (1102, 1104) are filled with a conductive metal such as tungsten (W), cobalt (Co), or copper (Cu) to form MD or VD contacts. According to various embodiments, the metal-filling process includes CVD for tungsten or electroplating for copper, depending on the geometry and integration requirements. Excess metal is removed by CMP, resulting in... Figure 11B The planarized MD and VD structures embedded within the insulating layer 510 are shown. These MD and VD contacts facilitate robust electrical interconnects between the semiconductor active regions and the metal routing layer. By integrating silicide contacts, liner / barrier layers, and optimized metal fill, this process ensures low-resistance, stable connections, supporting high-performance semiconductor devices.

[0097] Figure 12This is a flowchart of the operation of a method 1200 for manufacturing a semiconductor device according to various embodiments. Method 1200 includes performing processing operations (1202, 1204, 1206, 1208, 1210, 1212) to form a feedthrough via (FTV) that connects a back-side circuit BMO located above a back side 508b of a substrate 210 to a front-side 508a circuit M0 located on a front side 508a of the substrate 210, wherein active regions (502a, 502b) are located above the front side 508a of the substrate 210. According to various embodiments, the active regions (502a, 502b) extend longitudinally along a first direction (e.g., the X direction).

[0098] In operation 1202, method 1200 includes depositing an insulating layer 510 over the front side 508a of substrate 210, such that the insulating layer 510 is formed over the source / drain components SD of the field-effect transistor 500d in the active regions (502a, 502b), and such that the insulating layer 510 extends laterally from the field-effect transistor toward the power tap unit 460 region of substrate 210 along a second direction different from the first direction (e.g., the Y direction). In operation 1204, method 1200 includes performing a first etching operation to form a first opening 1102 in the insulating layer 510 over the source / drain components SD, and a second opening 1104 in the insulating layer 510 over the power tap unit 460 region.

[0099] In operation 1206, method 1200 includes depositing conductive material in a first opening 1102 to form a conductive power / drain contact 514 electrically connected to the source / drain component SD. In operation 1208, method 200 includes depositing conductive material in a second opening 1104 to form a via contact 516. In operation 1210, method 1200 includes performing a second etching operation through the back side 508b of substrate 210 to form a via opening extending from the back side 508b of substrate 210 toward insulating layer 510 along a third direction (e.g., the Z direction) from the back side 508b to the front side 508a (e.g., see...). Figures 9A to 10D In operation 1212, method 1200 includes depositing conductive material in the via opening to form a feedthrough via (FTV) (e.g., see...). Figures 9A to 10D ).

[0100] According to various embodiments, the insulating layer 510 is an etch stop layer for the first and second etch operations. The source / drain component SD includes an epitaxial semiconductor layer having a thickness T along a third direction (e.g., the Z direction) and a width W along a first direction (e.g., the X direction) and a second direction (e.g., the Y direction). In some embodiments, the thickness T is different from the width W. In some embodiments, the first conductivity of the metal silicide layer 312 formed between the power / drain contact 514 and the source / drain component SD has a conductivity value between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the power / drain contact 514.

[0101] According to various embodiments, the source / drain component SD is electrically connected to the channel region 216 of the field-effect transistor 500d. According to various embodiments, method 1200 further includes depositing an insulating layer 510 such that the insulating layer 510 includes a first surface 512a facing the substrate 210 and a second surface 512b facing away from the substrate 210, such that the first surface 512a is closer to the substrate 210 than at least a portion of the channel region.

[0102] According to various embodiments, method 1200 further includes performing a first etching operation, a second etching operation, and depositing conductive material in the first opening 1102 and the second opening 1104, such that the via contact 516 includes a via surface 520 facing the substrate 210, such that the via surface 520 is flush with the first surface 512a of the insulating layer 510, and the power / drain contact 514 includes a contact surface 522 facing the substrate 210, the contact surface 522 being flush with the via surface 520 and the first surface 512a of the insulating layer 510.

[0103] The disclosed embodiments advantageously provide a semiconductor device including an insulating layer 510 that serves as an etch stop layer for the front-side processes of forming source / drain contacts 514 and via contacts 516, and for the back-side processes of forming feedthrough vias (FTVs). The use of the insulating layer 510 improves the manufacturing process, resulting in increased contact depth consistency for the source / drain contacts 514 and similar consistency in the depth of the FTVs. According to various embodiments, the presence of the insulating layer 510 results in the formation of FTVs with similar depths, whether formed in a cleaved metal gate (CMG) region or a region without a CMG. The manufacturing process improvements provided by using the insulating layer 510 exhibit improved processing yields and provide source / drain contacts 514 and FTVs, as well as via contacts 516, with reduced contact resistance and correspondingly improved performance.

[0104] According to various embodiments, the semiconductor device includes: a semiconductor substrate having a front side and a back side opposite to the front side; a first power supply circuit disposed on the front side of the semiconductor substrate and extending over an active region; a second power supply circuit disposed on the back side of the semiconductor substrate; a power tap unit including a feedthrough via coupled to the first power supply circuit and the second power supply circuit, and configured to provide power from the first power supply circuit to the second power supply circuit; and an insulating layer disposed over the front side of the semiconductor substrate and extending over the power tap unit and a portion of the active region.

[0105] According to various embodiments, the insulating layer includes a first surface facing the semiconductor substrate and a second surface facing away from the semiconductor substrate, a feedthrough extending from the back side of the semiconductor substrate toward the insulating layer in a direction from the back side to the front side, and a first power circuit including a plurality of dielectric layers interleaved by a plurality of etch stop layers, and the first power circuit including a plurality of metal lines disposed in the plurality of dielectric layers.

[0106] According to various embodiments, the semiconductor device further includes: a field-effect transistor (FET), the FET including a source / drain component, wherein an insulating layer is disposed on the source / drain component and extends laterally from the FET toward the power tap unit; a power / drain contact formed in the insulating layer and electrically connected to the source / drain component; and a via contact formed in the insulating layer in the power tap unit and electrically connected to a feedthrough via.

[0107] According to various embodiments, the via contact includes a via surface facing the semiconductor substrate, such that the via surface is flush with a first surface of the insulating layer. According to various embodiments, the power / drain contact includes a contact surface facing the semiconductor substrate, which is flush with both the via surface and the first surface of the insulating layer. According to various embodiments, the via contact includes a via surface facing the semiconductor substrate, which is closer to the semiconductor substrate than the first surface of the insulating layer. According to various embodiments, the displacement of the via surface from the first surface of the insulating layer is in the range of greater than 0 nm to 5 nm.

[0108] According to various embodiments, the semiconductor device further includes: an interlayer dielectric layer formed above the front side of a semiconductor substrate, wherein an insulating layer is disposed above the interlayer dielectric layer; and a gate isolation region including an isolation dielectric formed in the interlayer dielectric layer. According to various embodiments, a feedthrough via is formed in the gate isolation region. According to various embodiments, the surface of the isolation dielectric is flush with the surface of the via and a first surface of the insulating layer. According to various embodiments, the surface of the via is closer to the semiconductor substrate than the surface of the isolation dielectric. According to various embodiments, at least one of the isolation dielectric and the interlayer dielectric layer comprises a single layer. According to various embodiments, at least one of the isolation dielectric and the interlayer dielectric layer comprises a multilayer structure.

[0109] According to various embodiments, the semiconductor device includes: a semiconductor substrate having a front side and a back side opposite to the front side; a first active region and a second active region located on the front side of the semiconductor substrate and extending longitudinally across the semiconductor substrate along a first direction; an isolation member located between the first active region and the second active region; a back-side circuit located on the back side of the semiconductor substrate and including a first conductor located in a first dielectric layer; a front-side circuit located on the front side of the semiconductor substrate and including a second conductor located in a second dielectric layer; and a feedthrough via electrically connecting the first conductor to the second conductor.

[0110] According to various embodiments, the semiconductor device further includes: an insulating layer disposed between the first dielectric layer and the second dielectric layer, and including a first surface facing the semiconductor substrate and a second surface facing away from the semiconductor substrate, wherein the first surface is closer to the semiconductor substrate than at least a portion of a channel region of at least one of the first active region and the second active region.

[0111] According to various embodiments, the semiconductor device further includes: a field-effect transistor formed in at least one of a first active region or a second active region and including source / drain components, wherein an insulating layer is disposed on the source / drain components and extends laterally from the field-effect transistor toward a feedthrough via; a conductive power / drain contact formed in the insulating layer and electrically connected to the source / drain components; and a via contact formed in the insulating layer and electrically connected to the feedthrough via. According to various embodiments, the via contact includes a via surface facing the semiconductor substrate, such that the via surface is flush with a first surface of the insulating layer.

[0112] According to various embodiments, the semiconductor device further includes: an interlayer dielectric layer formed over the front side of a semiconductor substrate, wherein an insulating layer is disposed over the interlayer dielectric layer; and a gate isolation region including an isolation dielectric formed in the interlayer dielectric layer. According to various embodiments, a feedthrough via is formed in the gate isolation region. According to various embodiments, the semiconductor device further includes: a via isolation structure formed around the feedthrough via, the via isolation structure comprising a single dielectric layer or multilayer composite formed of one or more of silicon dioxide, carbon-doped silicon oxide, fluorinated silicon oxide, silicon nitride, silicon nitride carbon, or other dielectric materials containing oxides, nitrogen, or carbon. According to various embodiments, at least one of the first or second conductors includes at least one of W, Ru, Co, Rh, Cu, TiN, TaN, or another material including Ti or Ta.

[0113] According to various embodiments, a method of manufacturing a semiconductor device includes performing a processing operation to form a feedthrough via that connects a back-side circuit located above a back side of a substrate to a front-side circuit located on a front side of the substrate, wherein an active region is located above the front side of the substrate and the active region extends longitudinally along a first direction.

[0114] According to various embodiments, the processing operations include depositing an insulating layer over the front side of a substrate, such that the insulating layer is formed over the source / drain components of a field-effect transistor in an active region, and such that the insulating layer extends laterally from the field-effect transistor toward a power tap region of the substrate along a second direction intersecting the first direction; performing a first etching operation to form a first opening in the insulating layer over the source / drain components and a second opening in the insulating layer over the power tap region; forming a metal silicide layer in the first opening and over the source / drain components; depositing a conductive material in the first opening and over the metal silicide layer to form a conductive power / drain contact, the conductive power / drain contact being electrically connected to the source / drain components through the metal silicide layer; and depositing a conductive material in the second opening to form a via contact.

[0115] According to various embodiments, the method further includes performing a second etching operation through the back side of the substrate to form a via opening extending from the back side of the substrate toward the insulating layer along a third direction from the back side to the front side, and depositing conductive material in the via opening to form a feedthrough via.

[0116] According to various embodiments, the insulating layer is an etch stop layer for the first etch operation and the second etch operation, the source / drain component includes an epitaxial semiconductor layer having a thickness along a third direction and a width along the first and second directions, and the thickness is different from the width, and the first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the power / drain contact.

[0117] According to various embodiments, the source / drain components are electrically connected to the channel region of the field-effect transistor, and the method further includes depositing an insulating layer such that the insulating layer includes a first surface facing the substrate and a second surface facing away from the substrate, such that the first surface is closer to the substrate than at least a portion of the channel region. According to various embodiments, the method further includes performing a first etching operation, a second etching operation, and depositing a conductive material in the first opening and the second opening such that a via contact includes a via surface facing the substrate, such that the via surface is flush with the first surface of the insulating layer, and a conductive source / drain contact includes a contact surface facing the substrate, such that the contact surface is flush with the via surface and the first surface of the insulating layer.

[0118] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a front side and a back side opposite to the front side; A first power supply circuit is disposed on the front side of the semiconductor substrate and extends above the active region; A second power supply circuit is disposed on the back side of the semiconductor substrate; A power tap unit including a feedthrough hole is coupled to the first power circuit and the second power circuit, and is configured to provide power from the first power circuit to the second power circuit; as well as An insulating layer is disposed above the front side of the semiconductor substrate and extends above the power tap unit and a portion of the active region. in: The insulating layer includes a first surface facing the semiconductor substrate and a second surface facing away from the semiconductor substrate; The feedthrough via extends from the back side of the semiconductor substrate toward the insulating layer in a direction from the back side to the front side; and The first power supply circuit includes multiple dielectric layers interleaved with multiple etch stop layers, and the first power supply circuit includes multiple metal lines disposed in the multiple dielectric layers.

2. The semiconductor device according to claim 1, further comprising: A field-effect transistor, including a source / drain component, wherein the insulating layer is disposed on the source / drain component and extends laterally from the field-effect transistor toward the power tap unit; Conductive power / drain contacts are formed in the insulating layer and electrically connected to the source / drain components; and A through-hole contact is formed in the insulating layer of the power tap unit and is electrically connected to the feedthrough through-hole.

3. The semiconductor device according to claim 2, wherein: The via contact includes a via surface facing the semiconductor substrate, such that the via surface is flush with the first surface of the insulating layer.

4. The semiconductor device according to claim 3, wherein: The power / drain contact includes a contact surface facing the semiconductor substrate, the contact surface being flush with the via surface and the first surface of the insulating layer.

5. The semiconductor device according to claim 2, wherein: The via contact includes a via surface facing the semiconductor substrate, the via surface being closer to the semiconductor substrate than the first surface of the insulating layer.

6. The semiconductor device according to claim 5, wherein: The displacement of the via surface from the first surface of the insulating layer is in the range of greater than 0 nm to 5 nm.

7. The semiconductor device according to claim 3, further comprising: An interlayer dielectric layer is formed above the front side of the semiconductor substrate, wherein the insulating layer is disposed above the interlayer dielectric layer; and The gate isolation region includes an isolation dielectric formed in the interlayer dielectric layer. The feedthrough via is formed in the gate isolation region.

8. The semiconductor device according to claim 7, wherein, The surface of the insulating dielectric is flush with the surface of the through hole and the first surface of the insulating layer.

9. A semiconductor device, comprising: A semiconductor substrate having a front side and a back side opposite to the front side; The first active region and the second active region are located on the front side of the semiconductor substrate and extend longitudinally across the semiconductor substrate along a first direction. An isolation component is located between the first active region and the second active region; A back-side circuit is located on the back side of the semiconductor substrate and includes a first wire located in the first dielectric layer; A front-side circuit is located on the front side of the semiconductor substrate and includes a second conductor located in the second dielectric layer; A feedthrough hole is used to electrically connect the first wire to the second wire; as well as An insulating layer is disposed between the first dielectric layer and the second dielectric layer, and the insulating layer includes a first surface facing the semiconductor substrate and a second surface facing away from the semiconductor substrate, wherein the first surface is closer to the semiconductor substrate than at least a portion of the channel region of at least one of the first active region and the second active region.

10. A method for manufacturing a semiconductor device, comprising: Performing a processing operation to form a feedthrough via connecting a back-side circuit located above the back side of the substrate to a front-side circuit located on the front side of the substrate, wherein an active region is located above the front side of the substrate and extends longitudinally along a first direction, the processing operation including: An insulating layer is deposited over the front side of the substrate such that the insulating layer is formed over the source / drain components of the field-effect transistor in the active region, and such that the insulating layer extends laterally from the field-effect transistor toward the power tap unit region of the substrate along a second direction intersecting the first direction. Perform a first etching operation to form a first opening in the insulating layer above the source / drain components and a second opening in the insulating layer above the power tap unit region; A metal silicide layer is formed in the first opening and above the source / drain components; Conductive material is deposited in the first opening and over the metal silicide layer to form a conductive power / drain contact, which is electrically connected to the source / drain component through the metal silicide layer; The conductive material is deposited in the second opening to form a through-hole contact; A second etching operation is performed through the back side of the substrate to form a via opening extending from the back side of the substrate toward the insulating layer along a third direction from the back side to the front side; and The conductive material is deposited in the via opening to form the feedthrough via. in: The insulating layer is an etch stop layer used for the first etch operation and the second etch operation; The source / drain component includes an epitaxial semiconductor layer having a thickness along the third direction and a width along the first and second directions, wherein the thickness is different from the width; and The first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the power / drain contact.

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