A folded channel CMOS device and method of manufacturing the same

Abstract

This application belongs to the field of device manufacturing technology and discloses a folded-channel CMOS device and its manufacturing method, including: a P-type substrate; a P-type well region and an N-type well region formed in the P-type substrate; a shallow trench formed on the surface of the P-type substrate; a CMOS device control gate polysilicon disposed in the lower part of the shallow trench; an N-doped region, a P-doped region, a P+ doped region, and an N+ doped region formed in the P-type well region and the N-type well region; a surface passivation layer covering the device surface; and an electrical lead-out metal layer. This application enables the flow path from the carrier source region to the drain region to be transformed from a planar transverse straight line to a longitudinal U-shaped folded path along the sidewalls and bottom of the shallow trench, which is beneficial for maintaining excellent capabilities and controlling manufacturing costs under miniaturization.

Description

Technical Field

[0001] This application relates to the field of device manufacturing technology, and in particular to a folded-channel CMOS device and its manufacturing method. Background Technology

[0002] As the integration density of semiconductor integrated circuits continues to increase, the feature size of devices on the chip is also continuously shrinking. In conventional planar transistors, doped regions such as source and drain regions are typically formed in the semiconductor substrate through processes such as photolithography, etching, and ion implantation. A gate dielectric layer and a gate are then formed on the substrate surface between the source and drain regions. Under the control of the gate voltage, charge carriers flow from the source region to the drain region in a linear path from left to right, essentially parallel to the substrate surface.

[0003] However, as device dimensions shrink, the boundary contours of doped regions are extremely difficult to control precisely due to limitations in lithography resolution and process variations, often resulting in non-ideal morphologies such as boundary curvature and roughness. Bending of doped region boundaries leads to a reduction in effective channel area, making it impossible to reliably guarantee channel length, exacerbating short-channel effects, and significantly increasing leakage current in the device's off-state. To address the severe leakage current problem caused by size reduction, the industry has been forced to continuously pursue higher-precision lithography machines to improve the flatness and alignment accuracy of doped region boundaries as much as possible. This has not only caused manufacturing costs to rise sharply but is also gradually approaching the physical limits of optical lithography, making it increasingly difficult to meet the demands simply by improving lithography precision.

[0004] Therefore, how to effectively increase the channel length, reduce device leakage current, and improve material utilization without over-reliance on high-precision lithography machines and without increasing the chip's footprint has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a folded-channel CMOS device and its fabrication method. It enables the formation of shallow trenches in a P-type substrate, creating polycrystalline control gate layers for the CMOS device, polycrystalline control gate layers for EEPROM cells, and gate insulating layers. These gate structures form an isolation band, transforming the carrier flow path from the source region to the drain region from a planar, horizontally straight line into a longitudinal U-shaped folded path along the sidewalls and bottom of the shallow trench. Without increasing the chip footprint, the equivalent channel length can be significantly increased, mitigating the short-channel effect and reducing leakage current. Furthermore, the internal region of the shallow trench is reused as a space for gate structure growth, improving material utilization efficiency, eliminating the reliance on extremely high photolithography precision, and facilitating the maintenance of excellent capabilities and cost control at miniaturized dimensions.

[0006] In a first aspect, embodiments of this application provide a folded-channel CMOS device, comprising: P-type substrate; P-type well regions and N-type well regions formed in a P-type substrate; Shallow trenches formed on the surface of a P-type substrate; The CMOS device control gate polysilicon is located in the lower part of the shallow trench; N-doped regions, P-doped regions, P+ doped regions, and N+ doped regions formed in P-type well regions and N-type well regions; A surface passivation layer covering the device surface; and an electrical lead-out metal layer.

[0007] Furthermore, the shallow trench also includes a control gate polycrystalline layer for the EEPROM cell.

[0008] Furthermore, the shallow trench also includes a gate insulating layer; the CMOS device control gate polysilicon is electrically isolated from the P-type well region and N-type well region at the bottom of the shallow trench by a gate insulating layer grown by thermal oxidation.

[0009] Furthermore, during the fabrication of the gate insulation layer, the shallow trench is first oxidized on the surface and a protective layer is grown on the sidewall. Then, it is etched clean and regrown to obtain the new layer.

[0010] Furthermore, the CMOS device control gate polysilicon is also used as a floating gate for EEPROM data storage.

[0011] Furthermore, in the EEPROM cell device, the control gate polycrystalline layer of the EEPROM cell is fabricated inside a shallow trench and located directly above the control gate polycrystalline layer of the CMOS device, achieving electrical isolation through the gate insulating layer.

[0012] Furthermore, the shallow trench also includes an insulating layer dielectric; in the EEPROM cell device, the control gate polycrystalline layer of the EEPROM cell, and the control gate polycrystalline layer of the CMOS device are both buried inside the shallow trench and electrically isolated from the outside through the insulating layer dielectric.

[0013] Furthermore, the N-doped region serves as a lightly doped region at the source and drain ends of N-channel MOS devices and EEPROM cell devices, thereby reducing the latch-up effect of N-channel MOS devices.

[0014] Furthermore, the P-doped region serves as a lightly doped region at the source and drain ends of a P-type channel MOS device, thereby reducing the latch-up effect of the P-type channel MOS device.

[0015] Furthermore, the N-doped region is not fabricated; instead, the self-locking effect is achieved by utilizing the concentration gradient difference from top to bottom of the N+ doped region.

[0016] Furthermore, the P-doped region is not fabricated; instead, the self-locking effect is achieved by utilizing the concentration gradient difference from top to bottom of the P+ doped region.

[0017] Furthermore, the N-doped region is not fabricated, so that the actual channel length of the N-channel MOS device is no longer determined by the length of the CMOS device control gate polysilicon inside the shallow trench, but by the combined length and thickness of the CMOS device control gate polysilicon inside the shallow trench.

[0018] Furthermore, the electrical lead-out metal layers of the source and drain electrodes pass over the shallow trench to improve the chip's integration density.

[0019] Furthermore, the electrical leads of the control gate polycrystalline layer of CMOS devices and the control gate polycrystalline layer of EEPROM cells are both located inside shallow trenches, and the electrical leads are achieved through an electrical lead-out metal layer.

[0020] Secondly, embodiments of this application provide a method for manufacturing a folded-channel CMOS device, the method comprising: Provide a P-type substrate; etch the P-type substrate to create multiple shallow trenches; The shallow trench undergoes surface corrosion cleaning, insulation medium filling, and leveling treatment. P-type well regions, N-type well regions, N-doped regions, and P-doped regions were fabricated using photomask and adhesive implantation methods. The shallow trench is cleaned by patterning, dry etching and wet etching; the insulating layer is grown in the trench by thermal oxidation; and the junction depth is advanced and impurities are activated by ion implantation in the P-type well region, N-type well region, N-doped region and P-doped region. Grow a silicon nitride dielectric layer or an aluminum nitride dielectric layer; remove the silicon nitride dielectric layer or aluminum nitride dielectric layer except for the inside of the shallow trench by dry etching; The insulating medium at the bottom and outside of the shallow trench is etched by wet etching, and the gate insulating layer is grown by low-temperature thermo-oxidation. The control gate polycrystalline layer of the CMOS device and the floating gate polycrystalline layer of the EEPROM cell are grown. After growth, the etch-back process is performed and doping implantation is carried out. The shallow grooves are filled with dielectric material, and the gate grooves required for the EEPROM cell are fabricated using a patterned photomask. The control gate polycrystalline layer of the EEPROM cell is grown, and after planarization, the polycrystalline layer is etched back to produce the control gate polycrystalline layer of the EEPROM cell with the required thickness. A surface passivation layer and an electrical lead-out metal layer are grown to obtain a folded-channel CMOS device.

[0021] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following: This application provides a folded-channel CMOS device that can form shallow trenches in a P-type substrate, creating polycrystalline control gate layers for the CMOS device, polycrystalline control gate layers for the EEPROM cells, and gate insulating layers. These gate structures form an isolation band, transforming the flow path from the source region to the drain region of the carriers from a planar, horizontally straight line to a longitudinal U-shaped folded path along the sidewalls and bottom of the shallow trench. Without increasing the chip's footprint, the equivalent channel length can be significantly increased, weakening the short-channel effect and reducing leakage current. Furthermore, the internal region of the shallow trench is reused as a space for gate structure growth, improving material utilization efficiency and reducing the strong dependence on extremely high photolithography precision. This is beneficial for maintaining excellent switching capabilities and controlling manufacturing costs even at miniaturized dimensions. Attached Figure Description

[0022] Figure 1 This is a structural diagram of a folded-channel CMOS device provided as an exemplary embodiment of this application.

[0023] Figure 2 This is a schematic diagram of the shallow trench fabrication process in this application.

[0024] Figure 3 This is a schematic diagram of the fabrication of the shallow trench insulating medium in the manufacturing process of this application.

[0025] Figure 4 This is a schematic diagram illustrating the fabrication of the N / P trap and N- / P- diffusion layer in the process described in this application.

[0026] Figure 5 This is a schematic diagram illustrating the smoothing process of the shallow groove and the fabrication of the insulating layer in the manufacturing process of this application.

[0027] Figure 6 This is a schematic diagram of the fabrication of the sidewall of the shallow trench in the manufacturing process of this application.

[0028] Figure 7 This is a schematic diagram of the fabrication process of the gate dielectric layer and the gate polycrystalline layer in this application.

[0029] Figure 8 This is a schematic diagram of the fabrication of the control gate slot of the EEPROM device in the process of this application.

[0030] Figure 9 This is a schematic diagram illustrating the fabrication of the control gate polysilicon of the EEPROM device in the process described in this application.

[0031] Figure 10 This is a schematic diagram of the fabrication process of embedding the control gate polysilicon dielectric of the EEPROM device in the manufacturing process of this application.

[0032] Figure 11 This is a schematic diagram illustrating the fabrication of lead holes and electrical lead-out metal layers in the manufacturing process of this application.

[0033] Figure 12 This is a schematic planar layout of the device used in the manufacturing process of this application.

[0034] Figure 13 This is a schematic diagram comparing the channel length of the device in this application with that of a planar CMOS device.

[0035] Figure 14 A flowchart illustrating a method for manufacturing a folded-channel CMOS device, provided as an exemplary embodiment of this application. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0037] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] Please see Figure 1 This application provides a folded-channel CMOS device, comprising: P-type substrate (1), P-type well region (2), N-type well region (3), CMOS device control gate polycrystalline layer (4), shallow trench (5), N-doped region (6), P-doped region (7), P+doped region (8), N+doped region (9), surface passivation layer (10), electrical lead-out metal layer (11), control gate polycrystalline layer of EEPROM cell (12), gate insulating layer (13), insulating layer dielectric (14), and gate trench (15).

[0039] Specifically, P-type well regions and N-type well regions are formed within a P-type substrate; shallow trenches are formed on the surface of a P-type substrate; a polycrystalline control gate for a CMOS device is disposed below the shallow trench; N-doped regions, P-doped regions, P+doped regions, and N+doped regions are formed within the P-type well regions and N-type well regions; a surface passivation layer and an electrical lead-out metal layer cover the device surface.

[0040] The folded-channel CMOS device provided in the above embodiments can form a shallow trench in a P-type substrate, and form a polycrystalline control gate layer for the CMOS device, a polycrystalline control gate layer for the EEPROM cell, and a gate insulating layer. These gate structures form an isolation band, transforming the flow path from the source region to the drain region of the carriers from a planar, horizontally straight line to a longitudinal U-shaped folded path along the sidewalls and bottom of the shallow trench. Without increasing the chip's footprint, the equivalent channel length can be significantly increased, weakening the short-channel effect and reducing leakage current. Furthermore, the internal region of the shallow trench is reused as a space for gate structure growth, improving material utilization efficiency and reducing the strong dependence on extremely high photolithography precision. This is beneficial for maintaining excellent switching capabilities and controlling manufacturing costs even at miniaturized dimensions.

[0041] Please see Figures 2-13 In some embodiments, the shallow trench also includes a control gate polycrystalline layer of an EEPROM cell.

[0042] In this design, the polycrystalline control gate layers of CMOS devices and EEPROM cells enable the integration of logic transistors and non-volatile memory cells on the same P-type substrate using a shallow trench process platform. The two types of control gates are adjacent to their respective channel regions, isolated from each other by well regions and shallow trench structures, suppressing signal crosstalk. Furthermore, the absence of additional polysilicon layers or photomasks simplifies the manufacturing process, reduces thermal budget, and results in a more compact embedded device. CMOS devices offer precise threshold adjustment, while EEPROM cells possess independent write and erase capabilities. The parameters of the two gate polycrystalline layers can be co-optimized in the same deposition step, ensuring on-chip matching. The final CMOS device can meet both high-speed logic processing and reliable offline data storage, enhancing application flexibility.

[0043] In some embodiments, the thickness of the control gate polycrystalline layer of a CMOS device is 1000 to 2000 angstroms. The thickness of the control gate polycrystalline layer of an EEPROM cell is 1000 to 2000 angstroms.

[0044] By setting the thickness of the polysilicon control gate layer in both the CMOS device and the EEPROM cell between 1000 and 2000 angstroms, the integrity of the shallow trench filling and the gate conductivity can be ensured simultaneously. The thickness range set in this application allows the polysilicon to fully fill the shallow trench, avoiding pinch-off or void defects and forming a continuous and strongly adhered gate body. The lower thickness limit ensures a sufficiently low gate sheet resistance, shortening the signal delay during gate charging and discharging, which is crucial for high-speed CMOS logic paths; the upper thickness limit prevents stress accumulation within the film layer and abnormal grain coarsening, ensuring a stable bond between the gate polysilicon layer and the underlying gate insulating layer or insulating dielectric, reducing the likelihood of microcracks. Furthermore, using the same thickness specification for both gates ensures a balanced load distribution during the chemical mechanical planarization step, improving the uniformity of gate height across the entire wafer. This creates favorable conditions for subsequent contact hole etching and metal lead-out, ultimately resulting in a CMOS device with long-term stable operation.

[0045] In some embodiments, the shallow trench further includes a gate insulating layer; the CMOS device control gate polycrystalline is fabricated in the lower part of the shallow trench, and is electrically isolated from the P-type well region and N-type well region at the bottom of the shallow trench by a gate insulating layer grown by thermal oxidation.

[0046] Among them, the gate insulating layer is grown at the bottom of the shallow trench by thermal oxidation. The resulting insulating medium is dense and has few interface defects, which can provide strict electrical isolation between the control gate polysilicon of CMOS devices and the P-type well region and N-type well region, reduce gate leakage current, and ensure precise voltage control. Furthermore, it improves the switching behavior of the device, avoids electric field concentration at the sharp corners at the bottom of the shallow trench, and improves the withstand voltage capability.

[0047] In some embodiments, when fabricating the gate insulating layer, the shallow trench is first oxidized on the surface and a sidewall protective layer is grown, then etched clean by etching and regrown to obtain the layer.

[0048] In the process of fabricating the gate insulating layer, a sacrificial oxide layer is first formed and a sidewall protective layer is grown before being etched clean. This process can completely eliminate the damage and defects introduced by shallow trench etching. The regrown gate insulating layer has a uniform thickness and pure texture, ensuring a high degree of consistency in threshold voltage and avoiding local leakage. This can support the long-term stable operation of the device.

[0049] In some embodiments, the CMOS device control gate polysilicon is used simultaneously as a floating gate for EEPROM data storage.

[0050] Among them, the floating gate, which uses the polycrystalline control gate of the CMOS device as the floating gate for storing data in the EEPROM, eliminates the process of separately depositing the floating gate layer, reduces mask and thin film deposition steps, thereby reducing manufacturing costs, making the device structure more compact, helping to reduce the size of the memory cell, improve chip integration, and simplify interconnection complexity.

[0051] In some embodiments, in an EEPROM cell device, the control gate polycrystalline layer of the EEPROM cell is fabricated inside a shallow trench and located directly above the control gate polycrystalline layer of the CMOS device, achieving electrical isolation through a gate insulating layer.

[0052] In this design, the control gate polycrystalline layer of the EEPROM cell is fabricated inside a shallow trench and located directly above the control gate polycrystalline layer of the CMOS device. The two layers are stacked vertically and share the shallow trench space, which greatly saves the lateral area. The upper and lower polycrystalline layers are isolated by a gate insulating layer, forming a tight capacitive coupling, which enhances the control capability of the floating gate potential, reduces the programming voltage, and speeds up the read and write speed.

[0053] In some embodiments, the shallow trench further includes an insulating layer medium; in the EEPROM cell device, the control gate polycrystalline layer of the EEPROM cell and the control gate polycrystalline layer of the CMOS device are both buried inside the shallow trench and electrically isolated from the outside through the insulating layer medium.

[0054] In this design, the control gate polycrystalline layer of the EEPROM cell and the control gate polycrystalline layer of the CMOS device are both buried inside a shallow trench and covered with an insulating layer, forming a fully enclosed gate structure. This structure can shield external charges and process disturbances, avoid the generation of parasitic channels, maintain the consistency and stability of the electrical parameters of the EEPROM cell device and the CMOS device, and enhance the overall structural strength.

[0055] In some embodiments, the thickness of the gate insulating layer is from 30 angstroms to 500 angstroms.

[0056] The gate insulating layer thickness is selected within the range of 30 to 500 angstroms, balancing the injection efficiency and charge retention capability of the EEPROM cell. Located within a shallow trench, when the thickness approaches the lower limit, a low voltage can induce sufficient tunneling current for rapid erasure and write operations, significantly reducing the circuit's operating voltage and dynamic power consumption. When the thickness reaches the upper limit, the charge storage potential well deepens, leakage paths are suppressed, and data retention time after power failure is greatly extended. The shallow trench structure ensures uniform growth thickness of the insulating layer on the trench sidewalls and bottom, minimizing the impact of pattern density. This allows for highly matched electrical behavior across the entire trench region, preventing premature breakdown at local weak points. Furthermore, this application allows for flexible selection of thickness within this window based on the emphasis on read / write speed and retention time, facilitating the adaptation of the same integrated solution to different application scenarios.

[0057] In some embodiments, the insulating layer medium is silicon dioxide or aluminum nitride.

[0058] The insulating layer uses either silicon dioxide or aluminum nitride as the dielectric, providing two optimized paths for isolation and coupling within the shallow trench. When silicon dioxide is used, there are fewer interface defects at the interface between the dielectric and the P-type and N-type well regions, parasitic leakage channels are suppressed, static power consumption remains low, the process is mature, and the integration with the subsequent gate insulating layer is smoother. When aluminum nitride is used, its higher relative permittivity allows for a suitable increase in physical thickness to mitigate electric field concentration, and its excellent thermal conductivity rapidly dissipates Joule heat generated in the active region of the device laterally, reducing parameter drift caused by self-heating. The wide bandgap and high breakdown strength of aluminum nitride also improve withstand voltage. Both dielectrics can be directly embedded in the shallow trench fabrication process, allowing CMOS devices to be selected as needed in different functional areas, expanding the freedom of integrated design and improving the overall cost-effectiveness of the chip.

[0059] In some embodiments, the N-doped region serves as a lightly doped region at the source and drain ends of an N-channel MOS device and an EEPROM cell device, thereby reducing the latch-up effect of the N-channel MOS device.

[0060] In particular, setting an N-doped region as a lightly doped region at the source and drain terminals of N-channel MOS devices and EEPROM cell devices can mitigate the electric field of the drain depletion region, suppress collisional ionization, reduce the self-locking effect, widen the safe operating area, reduce the gate-drain overlap electric field, improve the hot carrier injection condition, and enable the device to operate stably under high voltage conditions.

[0061] In some embodiments, the P-doped region serves as a lightly doped region at the source and drain ends of a P-channel MOS device, used to reduce the latch-up effect of the P-channel MOS device.

[0062] Introducing P-doped regions at the source and drain terminals of a P-channel MOS device can reduce the electric field strength near the drain, weaken the triggering possibility of parasitic bipolar transistors, suppress the self-locking effect, and alleviate the drain-induced barrier reduction, ensuring that the device can maintain stable driving capability over a wide voltage range.

[0063] In some embodiments, the N-doped region is not fabricated, and the self-locking effect is achieved by utilizing the concentration gradient difference from top to bottom of the N+ doped region.

[0064] In this method, the N-doped region is omitted, and a gradual junction is formed by the impurity concentration gradient from top to bottom in the N+ doped region. This replaces the lightly doped drain structure, which can also reduce the peak electric field at the drain end and suppress the self-locking effect. This saves one ion implantation and photolithography process, shortens the manufacturing cycle, reduces costs, and avoids alignment deviations caused by multi-step implantation.

[0065] In some embodiments, the P-doped region is not fabricated, and the self-locking effect is achieved by utilizing the concentration gradient difference from top to bottom of the P+ doped region.

[0066] In this process, the P-doped region is eliminated, and the gradual junction is obtained directly by relying on the vertical concentration gradient of the P+ doped region. This reduces the concentration of the drain electric field, suppresses the self-locking effect of the P-channel MOS device, simplifies the process, reduces the cost of fabrication, and eliminates the alignment tolerance between the light and heavy doped regions.

[0067] In some embodiments, such as Figure 13 As shown, the N-doped region is not fabricated, so the actual channel length of the N-channel MOS device is no longer controlled by the length L of the gate polysilicon controlled by the CMOS device inside the shallow trench. G The length L of the gate polysilicon is not determined by the CMOS device inside the shallow trench, but is controlled by the device. G Thickened T G The decision was made jointly. Essentially, it increased the channel length of both N-channel and P-channel MOS devices without increasing the area.

[0068] In this way, by not creating an N-doped region, the actual channel length of the N-type and P-type channel MOS devices is determined by the combined length and thickness of the CMOS device control gate polysilicon. The equivalent channel length is extended, which effectively suppresses the short-channel effect, reduces off-state leakage current, improves gate control capability, and maintains good device switching behavior without increasing the chip area.

[0069] In some embodiments, the electrical lead-out metal layers of the source and drain electrodes pass over the shallow trench to improve chip integration.

[0070] In this design, the electrical lead-out metal layers of the source and drain electrodes pass over the shallow trench. By using overlapping vertical traces, the layout area occupied by traditional lateral leads is saved, chip integration is improved, the source and drain lead-out paths are shortened, and the series resistance is reduced, which can improve the device's drive current and operating speed.

[0071] In some embodiments, the electrical leads of the control gate polycrystalline layer of the CMOS device and the control gate polycrystalline layer of the EEPROM cell are both located inside the shallow trench, and the electrical leads are achieved through the electrical lead-out metal layer.

[0072] In this design, the electrical leads of the control gate polycrystalline layer of the CMOS device and the control gate polycrystalline layer of the EEPROM cell are all integrated inside the shallow trench. The connection is completed through the buried electrical lead metal layer, eliminating the need for additional contact holes and top metal windings. This minimizes the cell area, reduces parasitic capacitance, improves circuit operating speed, and reduces signal crosstalk.

[0073] Please see Figure 14 This application provides a method for manufacturing a folded-channel CMOS device, which specifically includes the following steps: Step S1: Provide a P-type substrate; etch the P-type substrate to create multiple shallow trenches; perform surface etching cleaning, insulating dielectric filling, and planarization treatment on the shallow trenches.

[0074] Step S2 involves fabricating P-type well regions, N-type well regions, N-doped regions, and P-doped regions using a photomask and adhesive injection method.

[0075] Step S3 involves removing the dielectric material from the shallow trench using a patterned photomask, dry etching, and wet etching; growing the insulating dielectric layer in the trench using thermal oxidation; and advancing the junction depth and activating impurities through ion implantation into the P-type well region, N-type well region, N-doped region, and P-doped region.

[0076] Step S4: Grow a silicon nitride dielectric layer or an aluminum nitride dielectric layer; remove the silicon nitride dielectric layer or aluminum nitride dielectric layer except for the inside of the shallow trench by dry etching.

[0077] Step S5: The insulating medium at the bottom and outside of the shallow trench is etched by wet etching, and the gate insulating layer is grown by low-temperature thermo-oxidation.

[0078] Step S6: Grow the control gate polycrystalline layer of the CMOS device and the floating gate polycrystalline layer of the EEPROM cell. After growth, perform etch-back and doping implantation.

[0079] Step S7: Fill the shallow trench with dielectric material and create the gate trench required for the EEPROM cell using a patterned photomask.

[0080] Step S8: Grow the control gate polycrystalline layer of the EEPROM cell, perform planarization treatment, and then etch back the polycrystalline layer to create the control gate polycrystalline layer of the EEPROM cell with the required thickness.

[0081] Step S9: Grow a surface passivation layer and an electrical lead-out metal layer to obtain a folded channel CMOS device.

[0082] In some embodiments, the insulating layer medium is silicon dioxide or aluminum nitride.

[0083] In some embodiments, the thickness of the gate insulating layer is from 30 angstroms to 500 angstroms.

[0084] In one feasible implementation, shallow trenches with a depth of 0.4-4 micrometers and a width of 0.11-11 μm are fabricated on a P+ type substrate by etching.

[0085] The depth of the shallow trench determines the final channel length.

[0086] Furthermore, after surface corrosion cleaning, the shallow grooves at the fabricated locations are filled with an insulating medium and then flattened.

[0087] The insulating medium is silicon dioxide, aluminum nitride, or other insulating materials.

[0088] Furthermore, N-type well regions, P-type well regions, N-diffusion regions, and P-diffusion regions were fabricated using photomask and adhesive injection methods.

[0089] Furthermore, the shallow trench is cleaned by patterned photomasks and dry etching combined with wet etching, and an insulating layer is grown in the trench by thermal oxidation. At the same time, ion implantation in the N-type well region, P-type well region, N-diffusion region and P-diffusion region advances the junction depth and activates impurities.

[0090] Furthermore, a silicon nitride or aluminum nitride dielectric layer is grown, and the silicon nitride or aluminum nitride dielectric layer in all areas except the inside of the shallow trench is removed by dry etching.

[0091] Furthermore, the oxide layer at the bottom and outside of the shallow tank is etched away by wet etching, and a grid insulating layer with a thickness of 30 to 500 angstroms is grown by low-temperature thermo-oxidation.

[0092] The external oxide layer medium refers to the insulating layer medium grown in the tank through thermal oxidation.

[0093] Furthermore, the control gate polycrystalline layer of the CMOS device and the floating gate polycrystalline layer of the EEPROM are grown. Then, the control gate polycrystalline layer of the CMOS device and the floating gate polycrystalline layer of the EEPROM are etched back to the required thickness, from 1000 angstroms to 2200 Å, while regional doping implantation is performed.

[0094] Furthermore, the shallow trenches are refilled with dielectric material, and the control gate trenches required for the EEPROM device are fabricated using a patterned photomask.

[0095] The dielectric filling also uses the aforementioned insulating dielectric.

[0096] Furthermore, the control gate polycrystalline layer of the EEPROM is grown, and after planarization, the polycrystalline layer is etched back to produce the control gate polycrystalline layer of the EEPROM with the required thickness.

[0097] Furthermore, dielectric growth is performed on the entire chip to grow a surface passivation layer for the device.

[0098] Furthermore, lead holes for the device are fabricated, and an electrical lead-out metal layer is grown.

[0099] The specific limitations of the manufacturing method of the folded channel CMOS device provided in this embodiment can be found in the above embodiment of the folded channel CMOS device, and will not be repeated here.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A folded-channel CMOS device, characterized in that, include: P-type substrate; P-type well regions and N-type well regions formed within the P-type substrate; Shallow trenches formed on the surface of the P-type substrate; The CMOS device control gate polysilicon is disposed in the lower part of the shallow trench; N-doped regions, P-doped regions, P+ doped regions, and N+ doped regions formed within the P-type well region and N-type well region; A surface passivation layer covering the device surface; and an electrical lead-out metal layer.

2. The folded-channel CMOS device according to claim 1, characterized in that, The shallow trench also includes a control gate polycrystalline layer for the EEPROM unit.

3. The folded-channel CMOS device according to claim 2, characterized in that, The CMOS device's control gate polysilicon is electrically isolated from the P-type and N-type well regions at the bottom of the shallow trench by a gate insulating layer grown by thermal oxidation.

4. The folded-channel CMOS device according to claim 1, characterized in that, The shallow trench also includes a grid insulating layer; when the grid insulating layer is made, the surface of the shallow trench is first oxidized and a sidewall protective layer is grown, and then it is etched clean and regrown.

5. The folded-channel CMOS device according to claim 2, characterized in that, The CMOS device control gate polysilicon is also used as a floating gate for EEPROM data storage.

6. The folded-channel CMOS device according to claim 2, characterized in that, In EEPROM cell devices, the control gate polycrystalline layer of the EEPROM cell is fabricated inside a shallow trench and located directly above the control gate polycrystalline layer of the CMOS device, achieving electrical isolation through a gate insulating layer.

7. The folded-channel CMOS device according to claim 2, characterized in that, The shallow trench also includes an insulating layer medium; in the EEPROM cell device, the control gate polycrystalline layer of the EEPROM cell, and the control gate polycrystalline layer of the CMOS device are both buried inside the shallow trench and electrically isolated from the outside through the insulating layer medium.

8. The folded-channel CMOS device according to claim 2, characterized in that, The N-doped region serves as a lightly doped region at the source and drain ends of N-channel MOS devices and EEPROM cell devices, used to reduce the latch-up effect of N-channel MOS devices.

9. The folded-channel CMOS device according to claim 2, characterized in that, The P-doped region, as a lightly doped region at the source and drain ends of a P-type channel MOS device, is used to reduce the latch-up effect of the P-type channel MOS device.

10. The folded-channel CMOS device according to claim 1, characterized in that, The N-doped region is not fabricated; instead, the self-locking effect is achieved by utilizing the concentration gradient difference from top to bottom of the N+ doped region.

11. The folded-channel CMOS device according to claim 1, characterized in that, The P-doped region is not fabricated; instead, the self-locking effect is achieved by utilizing the concentration gradient difference from top to bottom of the P+ doped region.

12. The folded-channel CMOS device according to claim 2, characterized in that, The N-doped region is not fabricated, so the actual channel length of the N-channel MOS device is no longer determined by the length of the CMOS device control gate polysilicon inside the shallow trench, but by the combined length and thickness of the CMOS device control gate polysilicon inside the shallow trench.

13. The folded-channel CMOS device according to claim 1, characterized in that, The electrical lead-out metal layer of the source and drain electrodes passes over the shallow trench to improve the chip's integration density.

14. The folded-channel CMOS device according to claim 2, characterized in that, The electrical leads of the control gate polycrystalline layer in CMOS devices and EEPROM cells are both located inside shallow trenches, and are achieved through an electrical lead-out metal layer.

15. A method for manufacturing a folded-channel CMOS device, characterized in that, include: P-type substrates are provided; The P-type substrate is etched to create multiple shallow trenches; The shallow trench is subjected to surface corrosion cleaning, insulating medium filling, and planarization treatment; P-type well regions, N-type well regions, N-doped regions, and P-doped regions were fabricated using photomask and adhesive implantation methods. The shallow trench is subjected to dielectric removal by patterning mask, dry etching and wet etching; the insulating layer dielectric in the trench is grown by thermal oxidation; and the junction depth is advanced and impurities are activated by ion implantation in the P-type well region, N-type well region, N-doped region and P-doped region. Grow a silicon nitride dielectric layer or an aluminum nitride dielectric layer; remove the silicon nitride dielectric layer or aluminum nitride dielectric layer except for the inside of the shallow trench by dry etching; The insulating medium at the bottom and outside of the shallow trench is etched by wet etching, and the gate insulating layer is grown by low-temperature thermo-oxidation. The control gate polycrystalline layer of the CMOS device and the floating gate polycrystalline layer of the EEPROM cell are grown. After growth, the etch-back process is performed and doping implantation is carried out. The shallow grooves are filled with dielectric material, and the gate grooves required for the EEPROM cell are fabricated using a patterned photomask. The control gate polycrystalline layer of the EEPROM cell is grown, and after planarization, the polycrystalline layer is etched back to produce the control gate polycrystalline layer of the EEPROM cell with the required thickness. A surface passivation layer and an electrical lead-out metal layer are grown to obtain a folded-channel CMOS device.

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