Array substrate, display panel and display device

Abstract

An array substrate, a display panel, and a display device are disclosed. The array substrate includes: a substrate, a first thin-film transistor (TFT), signal traces, a first shielding layer, a second TFT, a second shielding layer, and driving traces. The first shielding layer is located between the first TFT and the signal traces. The second shielding layer is located between the second TFT and the signal traces. By isolating the first TFT from the signal traces through the first shielding layer, the signal transmitted in the signal traces can be prevented from affecting the normal operation of the first TFT. The first shielding layer can also prevent the first and second TFTs from interfering with each other, thereby enabling overlapping arrangement of TFTs and reducing the space occupied by the TFTs.

Description

Technical Field

[0001] This application belongs to the field of display device technology, and in particular relates to an array substrate, a display panel and a display device. Background Technology

[0002] Currently, organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used and have become the mainstream of display devices due to their advantages such as high image quality, power saving, thin body and wide range of applications. Summary of the Invention

[0003] The purpose of this application is to provide an array substrate, a display panel, and a display device to solve the problems existing in the prior art.

[0004] A first aspect of this application provides an array substrate, comprising: a substrate; a first thin-film transistor (TFT) located on one side of the substrate; a signal trace located on the side of the TFT away from the substrate; a first shielding layer located between the TFT and the signal trace; a second TFT located on the side of the first shielding layer away from the substrate; a second shielding layer located between the second TFT and the signal trace; and a driving trace located on the side of the second shielding layer closer to the substrate, the driving trace being electrically connected to the gate of the first TFT and the gate of the second TFT, respectively.

[0005] In one embodiment, the first thin-film transistor includes a first channel layer and a first gate layer; the first gate layer is located on the side of the first channel layer away from the substrate, and the overlapping portion of the orthographic projection of the first channel layer on the substrate and the orthographic projection of the first gate layer on the substrate cuts off the orthographic projection of the first channel layer on the substrate; preferably, the first thin-film transistor is a P-channel transistor.

[0006] In one embodiment, the first channel layer extends along a first direction, the first gate layer extends along a second direction, and the first direction intersects with the second direction; preferably, the first direction is perpendicular to the second direction.

[0007] In one embodiment, the first shielding layer is used for electrical connection with a constant voltage source; preferably, the constant voltage source includes a negative power source or a positive power source; preferably, the material of the first shielding layer includes at least one of titanium, copper and aluminum.

[0008] In one embodiment, the signal traces include clock traces, high-level traces, and low-level traces.

[0009] In one embodiment, the signal trace includes a clock trace, and the second shielding layer includes a high-level trace and a low-level trace; the clock trace is located on the side of the high-level trace and / or the low-level trace away from the substrate.

[0010] In one embodiment, the second thin-film transistor includes a second channel layer and a second gate layer; the second gate layer is disposed on the surface of the first shielding layer away from the substrate, and the overlapping portion of the orthographic projection of the second channel layer on the substrate and the orthographic projection of the second gate layer on the substrate cuts off the orthographic projection of the second channel layer on the substrate; preferably, the second thin-film transistor is an N-channel transistor; preferably, the second thin-film transistor further includes a third gate layer, the second gate layer is located on the side of the second channel layer away from the substrate, and the third gate layer is located on the side of the second channel layer close to the substrate.

[0011] In one embodiment, the array substrate includes a display area and a non-display area; the first thin-film transistor and the second thin-film transistor are both located in the non-display area.

[0012] A second aspect of this application provides a display panel including a pixel defining layer and an array substrate as described above, wherein the pixel defining layer is disposed on one side of the array substrate.

[0013] A third aspect of this application provides a display device, including the display panel as described above.

[0014] The beneficial effects of this application embodiment compared with the prior art are: by isolating the first thin-film transistor from the signal trace through the first shielding layer and the second thin-film transistor from the signal trace through the second shielding layer, the signal trace can be stacked with the first thin-film transistor and the second thin-film transistor, thereby reducing the overall area of ​​the array substrate and preventing the signal transmitted in the signal trace from affecting the normal operation of the first thin-film transistor.

[0015] The first shielding layer can also prevent the first and second thin-film transistors from interfering with each other, thereby enabling the stacking of thin-film transistors and further reducing the space occupied by the thin-film transistors. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of an array substrate provided in an embodiment of this application;

[0017] Figure 2A top view schematic diagram of a first thin-film transistor and a second thin-film transistor provided in an embodiment of this application;

[0018] Figure 3 This is another cross-sectional schematic diagram of an array substrate provided in an embodiment of this application;

[0019] Figure 4 Another cross-sectional schematic diagram of an array substrate provided in an embodiment of this application;

[0020] Figure 5 A schematic diagram of a display area and a non-display area provided in an embodiment of this application;

[0021] Figure 6 A cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0022] Figure 7 This is a schematic diagram of a display device provided in an embodiment of this application.

[0023] Explanation of reference numerals in the attached figures: 10, array substrate; 20, display panel; 21, pixel limiting layer; 30, display device; 100, substrate; 200, first thin-film transistor; 210, first channel layer; 220, first gate layer; 300, signal trace; 310, clock trace; 320, high-level trace; 330, low-level trace; 400, first shielding layer; 500, second thin-film transistor; 510, second channel layer; 520, second gate layer; 530, third gate layer; 600, second shielding layer; 700, driving trace; 800, via; 910, display area; 920, non-display area; 921, gate driving circuit; 922, ground trace. Detailed Implementation

[0024] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0025] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0026] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0028] Currently, existing displays typically employ a method of stacking some circuits to reduce overall size. However, when thin-film transistors (TFTs) overlap with other devices and traces, the TFTs and overlapping devices and traces will couple with each other, resulting in parasitic capacitance. Signal changes on the traces may affect the TFT's turn-on and turn-off, leading to problems such as leakage current and delays in turn-on and turn-off.

[0029] Figure 1 A cross-sectional schematic diagram of an array substrate according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0030] An array substrate 10 includes: a substrate 100, a first thin-film transistor 200, a signal trace 300, a first shielding layer 400, a second thin-film transistor 500, a second shielding layer 600, and a driving trace 700.

[0031] The first thin-film transistor 200 is located on one side of the substrate 100.

[0032] The signal trace 300 is located on the side of the first thin-film transistor 200 away from the substrate 100.

[0033] The first shielding layer 400 is located between the first thin-film transistor 200 and the signal trace 300.

[0034] The second thin-film transistor 500 is located on the side of the first shielding layer 400 away from the substrate 100.

[0035] The second thin-film transistor 500 may be disposed overlapping the first thin-film transistor 200. That is, the orthographic projection of the first thin-film transistor 200 on the substrate 100 and the orthographic projection of the second thin-film transistor 500 on the substrate 100 may at least partially overlap.

[0036] The second shielding layer 600 is located between the second thin-film transistor 500 and the signal trace 300.

[0037] The driving trace 700 is located on the side of the second shielding layer 600 near the substrate 100. The driving trace 700 is electrically connected to the gate of the first thin film transistor 200 and the gate of the second thin film transistor 500, respectively. The driving trace 700 can be used to realize the electrical connection between each thin film transistor, and can also transmit control signals to each thin film transistor to control the conduction and turn-off of each thin film transistor.

[0038] The drive trace 700 can be configured according to actual needs, and this embodiment does not limit it.

[0039] By isolating the first thin-film transistor 200 from the signal trace 300 through the first shielding layer 400, and the second thin-film transistor 500 from the signal trace 300 through the second shielding layer 600, the signal trace 300 can be stacked with the first thin-film transistor 200 and the second thin-film transistor 500. This reduces the overall area of ​​the array substrate 10 and prevents the signals transmitted in the signal trace 300 from affecting the normal operation of the first thin-film transistor 200 and the second thin-film transistor 500. The first shielding layer 400 also prevents the first thin-film transistor 200 and the second thin-film transistor 500 from interfering with each other, thereby enabling the overlapping arrangement of thin-film transistors and reducing the space occupied by the thin-film transistors.

[0040] It is understood that the array substrate 10 may include a plurality of first thin film transistors 200 and second thin film transistors 500, and a pixel array composed of light-emitting units may be disposed on the array substrate 10.

[0041] The first thin-film transistor 200 can be used as an output transistor to control the operating voltage supplied to the light-emitting unit, or as a driving transistor for the gate-in-panel (GIP) circuit. The second thin-film transistor 500 can be used as a driving transistor for the gate-in-panel circuit. Through the interaction of multiple first thin-film transistors 200 and multiple second thin-film transistors 500 with other devices and circuits, the corresponding pixel array is driven.

[0042] It is understandable that by stacking the signal trace 300 with the gate drive circuit consisting of the first thin film transistor 200, the second thin film transistor 500 and the drive trace 700, the overall area of ​​the array substrate 10 can be reduced.

[0043] The model, quantity, and location of the first thin-film transistor 200 and the second thin-film transistor 500 can be set according to actual needs.

[0044] The first shielding layer 400 can cover all the first thin-film transistors 200 and the substrate 100, or it can selectively cover a portion of the first thin-film transistors 200 and the substrate 100 according to actual needs.

[0045] For example, when a connection is required between the first thin-film transistor 200 and the signal trace 300 or other traces, the via 800 between the first thin-film transistor 200 and the signal trace 300 can pass through the first shielding layer 400.

[0046] In one embodiment, such as Figure 1 As shown, the first thin-film transistor 200 includes a first channel layer 210 and a first gate layer 220.

[0047] The first gate layer 220 is disposed on the surface of the first channel layer 210 away from the substrate 100. The overlapping portion of the orthographic projection of the first channel layer 210 on the substrate 100 and the orthographic projection of the first gate layer 220 on the substrate 100 is truncated.

[0048] It should be noted that the portion of the first channel layer 210 that overlaps with the first gate layer 220 is the channel region, and the remaining two portions are the source region and the drain region, respectively. The source region and the drain region of the first thin film transistor 200 can be connected to other circuits and traces through the corresponding vias 800.

[0049] In some embodiments, the source region and the drain region of the first thin-film transistor 200 can be connected to the drive trace 700 through corresponding vias 800, respectively.

[0050] In some embodiments, the source region and the drain region of the first thin-film transistor 200 can be connected to the signal trace 300 through corresponding vias 800, respectively.

[0051] The first channel layer 210 and the first gate layer 220 can be arranged at intervals.

[0052] It is understandable that the first gate layer 220 can be connected to the corresponding control circuit, and the conduction and turn-off of the first thin film transistor 200 can be controlled by controlling the voltage applied to the first gate layer 220.

[0053] Specifically, a dielectric material may be filled between the first channel layer 210 and the first gate layer 220.

[0054] Specifically, the first trench layer can be obtained by implanting P-type ions into a semiconductor material through ion implantation.

[0055] When the first thin-film transistor 200 is a P-channel transistor, the first thin-film transistor 200 can withstand a large voltage. For example, the first thin-film transistor 200 can specifically be used as an output transistor to transmit the operating voltage provided to the light-emitting unit.

[0056] It is understood that when the array substrate 10 includes a plurality of first thin film transistors 200, the first channel layer 210 of each first thin film transistor 200 can be disposed on the same layer, and the first gate layer 220 of each first thin film transistor 200 can be disposed on the same layer.

[0057] In one embodiment, such as Figure 2 As shown, the first channel layer 210 extends along a first direction, and the first gate layer 220 extends along a second direction, with the first direction intersecting the second direction.

[0058] It is understood that the width of the first gate layer 220 can be less than the length of the first channel layer 210. The two ends of the first channel layer 210 can be used as the source and drain, respectively. The two ends of the first channel layer 210 can also be connected to other circuits through corresponding vias 800. For example, the two ends of the first channel layer 210 can also be connected to the signal trace 300 through corresponding vias 800.

[0059] Preferably, the first direction is perpendicular to the second direction. This is to reduce the design and construction difficulty of the first channel layer 210 and the first gate layer 220.

[0060] In some embodiments, when the array substrate 10 includes a plurality of first thin film transistors 200, the plurality of first thin film transistors 200 can share the same first gate layer 220 to further reduce the space occupied by the first thin film transistors 200 on the array substrate 10.

[0061] Specifically, multiple first thin-film transistors 200 can be arranged sequentially at intervals along the second direction, and multiple first thin-film transistors 200 share the same first gate layer 220.

[0062] In one embodiment, the first shielding layer 400 is used for electrical connection to a constant voltage source.

[0063] Understandably, a constant voltage source can provide a stable voltage to the first shielding layer 400, keeping the potential of the first shielding layer 400 stable and avoiding affecting the operation of the first grinding transistor.

[0064] The constant voltage source includes either a negative power source or a positive power source.

[0065] Specifically, the negative power supply can provide the ELVSS voltage to the first shielding layer 400, and the positive power supply can provide the ELVDD voltage to the first shielding layer 400.

[0066] Preferably, the first shielding layer 400 can be connected to a negative power supply to obtain the ELVSS voltage.

[0067] Preferably, the material of the first shielding layer 400 includes at least one of titanium, copper, and aluminum.

[0068] Understandably, the material of the first shielding layer 400 can be a conductive metal.

[0069] When the material of the first shielding layer 400 is titanium, compared with other materials, the thickness of the first shielding layer 400 can be thinner, and the impact on the increase of the via 800 step is smaller.

[0070] In one embodiment, such as Figure 3 As shown, signal trace 300 includes clock trace 310, high-level trace 320, and low-level trace 330.

[0071] Clock trace 310 can be used to transmit clock signal CK, high-level trace 320 can be used to transmit high-level signal VGH, and low-level trace 330 can be used to transmit low-level signal VGL.

[0072] Understandably, since the voltage of the clock signal CK changes continuously, it will cause voltage changes in other traces and circuits through the coupling of parasitic capacitance. The first shielding layer 400 can reduce the impact of the clock signal CK on the first thin-film transistor 200.

[0073] In some embodiments, the clock signal CK is a square wave signal. The voltage of the high-level signal VGH is greater than the voltage of the low-level signal VGL.

[0074] In some embodiments, the clock trace 310, the high-level trace 320, and the low-level trace 330 are parallel to each other, extend along a first direction, and are arranged at intervals along a second direction.

[0075] In one embodiment, such as Figure 4As shown, the signal trace 300 includes a clock trace 310, and the second shielding layer 600 includes a high-level trace 320 and a low-level trace 330; the clock trace 310 is located on the side of the high-level trace 320 and / or the low-level trace 330 away from the substrate 100.

[0076] It is understandable that since the voltage of the high-level trace 320 and the low-level trace 330 is relatively stable, placing the high-level trace 320 and the low-level trace 330 between the clock trace 310 and the first thin-film transistor 200 can also serve as a signal shielding function.

[0077] In some embodiments, the orthogonal projection of clock trace 310 on substrate 100 lies within the orthogonal projection of high-level trace 320 on substrate 100 and / or the orthogonal projection of low-level trace 330 on substrate 100.

[0078] In one embodiment, such as Figure 4 As shown, the second thin-film transistor 500 includes a second channel layer 510 and a second gate layer 520.

[0079] The second gate layer 520 is disposed on the surface of the first shielding layer 400 away from the substrate 100. The overlapping portion of the orthogonal projection of the second channel layer 510 on the substrate 100 and the orthogonal projection of the second gate layer 520 on the substrate 100 is truncated.

[0080] It should be noted that the portion of the second channel layer 510 that overlaps with the second gate layer 520 is the channel region of the second thin film transistor 500, and the remaining two portions are the source region and the drain region, respectively. The source region and the drain region of the second thin film transistor 500 can be connected to other circuits and traces through the corresponding vias 800, respectively.

[0081] In some embodiments, the source region of the second thin-film transistor 500 and the drain region of the second thin-film transistor 500 can be connected to the drive trace 700 through corresponding vias 800, respectively.

[0082] In some embodiments, the source region of the second thin-film transistor 500 and the drain region of the second thin-film transistor 500 can be connected to the signal trace 300 through corresponding vias 800, respectively.

[0083] The second channel layer 510 and the second gate layer 520 can be arranged at intervals.

[0084] Specifically, a dielectric material may be filled between the second channel layer 510 and the second gate layer 520.

[0085] It is understandable that the second gate layer 520 can be connected to the corresponding control circuit, and the conduction and turn-off of the second thin film transistor 500 can be controlled by controlling the voltage applied to the second gate layer 520.

[0086] Preferably, the second thin-film transistor 500 is an N-channel transistor;

[0087] Specifically, the material of the second channel layer 510 can be one of IGZO, IGZTO, IZO, or IGO.

[0088] It should be noted that, considering the photoconductive effect, the electrical performance of the thin-film transistors in the array substrate 10 is deflected under illumination. For example, the active region generates leakage current when backlit, affecting the performance of the array substrate 10. At the same time, compared with P-channel transistors, N-channel transistors are more affected by illumination. Therefore, the second thin-film transistor 500, which is an N-channel transistor, is located on the side of the first shielding layer 400 away from the substrate 100, which can reduce the illumination received by the second thin-film transistor.

[0089] The first shielding layer 400 and the second shielding layer 600 can be light-shielding layers. The orthogonal projection of the first shielding layer 400 and the second shielding layer 600 on the substrate 100 covers the orthogonal projection of the second thin film transistor 500 on the substrate 100, that is, the light-shielding layer covers the second thin film transistor 500.

[0090] The first shielding layer 400 and the second shielding layer 600 are made of conductive materials that can block light. In this way, the first shielding layer 400 and the second shielding layer 600 can effectively block light and effectively reduce the influence of light on the second thin-film transistor 500 in the array substrate 10, thereby avoiding the influence of light on the electrical performance of the second thin-film transistor 500.

[0091] In one embodiment, the second thin-film transistor 500 further includes a third gate layer 530, wherein the second gate layer 520 is located on the side of the second channel layer 510 away from the substrate 100, and the third gate layer 530 is located on the side of the second channel layer 510 close to the substrate 100.

[0092] The third gate layer 530 can be connected to the second gate layer 520 to form a dual-gate structure, thereby enhancing the control of the second thin-film transistor 500.

[0093] The second channel layer 510 and the third gate layer 530 can be arranged at intervals.

[0094] Specifically, a dielectric material may be filled between the second channel layer 510 and the third gate layer 530.

[0095] It is understood that when the array substrate 10 includes a plurality of second thin film transistors 500, the second channel layer 510 of each second thin film transistor 500 can be disposed in the same layer, the second gate layer 520 of each second thin film transistor 500 can be disposed in the same layer, and the third gate layer 530 of each second thin film transistor 500 can be disposed in the same layer.

[0096] In some embodiments, the substrate 100 may be made of a light-transmitting material.

[0097] For example, the material of substrate 100 may include glass, resin, etc.

[0098] In one embodiment, such as Figure 5 As shown, the array substrate 10 includes a display area 910 and a non-display area 920.

[0099] The first thin-film transistor 200 and the second thin-film transistor 500 are both located in the non-display area 920. Specifically, the gate driving circuit 921, composed of the first thin-film transistor 200 and the second thin-film transistor 500, is located in the non-display area 920.

[0100] The non-display area 920 can be a border area. It is understood that the first thin-film transistor 200, the second thin-film transistor 500 and the signal trace 300 in this embodiment can be stacked to reduce the area ratio of the non-display area 920 on the array substrate 10, thereby reducing the area of ​​the border area and optimizing the display effect.

[0101] Specifically, the non-display areas 920 can be located on opposite sides of the display area 910. Both sides of the non-display areas 920 can be provided with gate drive circuits 921 and ground traces 922 for transmitting ELVSS voltage.

[0102] For the array substrate 10, with the display area 910 unchanged, the smaller the area of ​​the non-display area 920 (including the left, right and R-corner borders), the better the corresponding display effect.

[0103] While reducing the area of ​​the non-display area 920, it is necessary to ensure that the ground trace 922 used to transmit the ELVSS voltage in the non-display area 920 is not too narrow. Therefore, the space left for the gate drive circuit 921 is becoming increasingly limited. When the signal trace 300 and the gate drive circuit 921 are stacked, the impact of parasitic capacitance becomes greater, which can easily affect the normal operation of the thin-film transistors in the gate drive circuit 921, thereby affecting the signal output of the gate drive circuit 921.

[0104] In some embodiments, the orthographic projection of the gate drive circuit 921 on the substrate 100 lies within the orthographic projection of the second shielding layer 600 on the substrate 100.

[0105] In some embodiments, the orthogonal projection of the gate drive circuit 921 on the substrate 100 lies within the orthogonal projection of the high-level trace 320 on the substrate 100 and the orthogonal projection of the low-level trace 330.

[0106] In this embodiment, the first shielding layer 400 isolates the first thin-film transistor 200 from the signal trace 300, which can prevent the signal transmitted in the signal trace 300 from affecting the normal operation of the first thin-film transistor 200.

[0107] It should be noted that dielectric materials can be filled between the membrane layers. The filling dielectric materials can achieve isolation between the membrane layers, and the dielectric materials at different locations can be different or the same.

[0108] For example, one of the dielectric materials between the first shielding layer 400 and the substrate 100 and the dielectric materials between the first shielding layer 400 and the second shielding layer 600 is SiOx and the other is SiNx; or, both the dielectric materials between the first shielding layer 400 and the substrate 100 and the dielectric materials between the first shielding layer 400 and the second shielding layer 600 are SiOx layers or SiNx layers.

[0109] Figure 6 A cross-sectional schematic diagram of a display panel 20 according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0110] The display panel 20 includes a pixel defining layer 21 and an array substrate 10 as described in any of the above embodiments. The pixel defining layer 21 may be disposed on one side of the array substrate 10.

[0111] Since the display panel 20 includes the array substrate 10 of any of the above embodiments, the display panel 20 has the beneficial effects of the array substrate 10 of any of the above embodiments, which will not be described again here.

[0112] The pixel limiting layer 21 defines a pixel opening corresponding to the light-emitting unit, and a first electrode, a light-emitting functional layer and a second electrode are formed in sequence in each pixel opening.

[0113] The first electrode and the second electrode can be electrically connected to the array substrate 10 to obtain a driving voltage.

[0114] For example, one of the first electrode and the second electrode is the anode, and the other is the cathode. For instance, the first electrode is the anode, and the second electrode is the cathode.

[0115] The display panel 20 can specifically be a low-temperature polyoxide (LTPO) display panel 20. Compared to a low-temperature polysilicon (LTPS) display panel 20, the low-temperature polyoxide (LTPO) display panel 20 has the characteristics of low power consumption and good low-frequency display effect.

[0116] like Figure 1 As shown, the array substrate 10 includes: a substrate 100, a first thin-film transistor 200, a signal trace 300, a first shielding layer 400, a second thin-film transistor 500, a second shielding layer 600, and a driving trace 700.

[0117] The first thin-film transistor 200 is located on one side of the substrate 100.

[0118] The signal trace 300 is located on the side of the first thin-film transistor 200 away from the substrate 100.

[0119] The first shielding layer 400 is located between the first thin-film transistor 200 and the signal trace 300.

[0120] The second thin-film transistor 500 is located on the side of the first shielding layer 400 away from the substrate 100.

[0121] The second thin-film transistor 500 may be disposed overlapping the first thin-film transistor 200. That is, the orthographic projection of the first thin-film transistor 200 on the substrate 100 and the orthographic projection of the second thin-film transistor 500 on the substrate 100 may at least partially overlap.

[0122] The second shielding layer 600 is located between the second thin-film transistor 500 and the signal trace 300.

[0123] The driving trace 700 is located on the side of the second shielding layer 600 near the substrate 100. The driving trace 700 is electrically connected to the gate of the first thin film transistor 200 and the gate of the second thin film transistor 500, respectively. The driving trace 700 can be used to realize the electrical connection between each thin film transistor, and can also transmit control signals to each thin film transistor to control the conduction and turn-off of each thin film transistor.

[0124] The drive trace 700 can be configured according to actual needs, and this embodiment does not limit it.

[0125] By isolating the first thin-film transistor 200 from the signal trace 300 through the first shielding layer 400, and the second thin-film transistor 500 from the signal trace 300 through the second shielding layer 600, the signal trace 300 can be stacked with the first thin-film transistor 200 and the second thin-film transistor 500. This reduces the overall area of ​​the array substrate 10 and prevents the signals transmitted in the signal trace 300 from affecting the normal operation of the first thin-film transistor 200 and the second thin-film transistor 500. The first shielding layer 400 also prevents the first thin-film transistor 200 and the second thin-film transistor 500 from interfering with each other, thereby enabling the overlapping arrangement of thin-film transistors and reducing the space occupied by the thin-film transistors.

[0126] Figure 7 A schematic diagram of a display device 30 according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0127] A display device 30, wherein the display panel 20 of the display device 30 may be a display panel 20 as described in any of the above embodiments.

[0128] The display panel 20 may specifically be a low-temperature polycrystalline oxide (LTPO) display panel 20.

[0129] Since the display device 30 includes the display panel 20 of any of the above embodiments, the display device 30 has the beneficial effects of the display panel 20 of any of the above embodiments, which will not be described again here.

[0130] The display device 30 in this application embodiment includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0131] From the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0132] It should be understood that the apparatuses and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another device. In addition, some features may be omitted or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0133] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units. That is, it can be located in one place or distributed in multiple different locations. Depending on the actual needs, some or all of the units can be selected to achieve the purpose of this solution.

[0134] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit; they can also exist physically separately; or some units can be integrated into one unit while others exist physically separately. The integrated units described above can be implemented in hardware or as software functional units.

[0135] It should be noted that all or part of the above embodiments provided in this application (e.g., part or all of any feature) can be arbitrarily combined or combined with each other.

[0136] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate (10), characterized in that, include: Substrate (100); A first thin-film transistor (200) is located on one side of the substrate (100); Signal trace (300) is located on the side of the first thin-film transistor (200) away from the substrate (100); A first shielding layer (400) is located between the first thin-film transistor (200) and the signal trace (300); A second thin-film transistor (500) is located on the side of the first shielding layer (400) away from the substrate (100); A second shielding layer (600) is located between the second thin-film transistor (500) and the signal trace (300); A driving trace (700) is located on the side of the second shielding layer (600) near the substrate (100), and the driving trace (700) is electrically connected to the gate of the first thin film transistor (200) and the gate of the second thin film transistor (500), respectively.

2. The array substrate (10) as claimed in claim 1, characterized in that, The first thin-film transistor (200) includes a first channel layer (210) and a first gate layer (220); The first gate layer (220) is located on the side of the first channel layer (210) away from the substrate (100), and the overlapping portion of the orthographic projection of the first channel layer (210) on the substrate (100) and the orthographic projection of the first gate layer (220) on the substrate (100) is truncated. Preferably, the first thin-film transistor (200) is a P-channel transistor.

3. The array substrate (10) as described in claim 2, characterized in that, The first channel layer (210) extends along a first direction, and the first gate layer (220) extends along a second direction, the first direction intersecting the second direction; Preferably, the first direction is perpendicular to the second direction.

4. The array substrate (10) as claimed in claim 1, characterized in that, The first shielding layer (400) is used for electrical connection with a constant voltage source; Preferably, the constant voltage source includes a negative power supply or a positive power supply; Preferably, the material of the first shielding layer (400) includes at least one of titanium, copper and aluminum.

5. The array substrate (10) as claimed in claim 1, characterized in that, The signal traces (300) include clock traces (310), high-level traces (320), and low-level traces (330).

6. The array substrate (10) as claimed in claim 1, characterized in that, The signal trace (300) includes a clock trace (310), and the second shielding layer (600) includes a high-level trace (320) and a low-level trace (330); The clock trace (310) is located on the side of the high-level trace (320) and / or the low-level trace (330) away from the substrate (100).

7. The array substrate (10) as claimed in claim 1, characterized in that, The second thin-film transistor (500) includes a second channel layer (510) and a second gate layer (520); The second gate layer (520) is disposed on the surface of the first shielding layer (400) away from the substrate (100), and the overlapping portion of the orthographic projection of the second channel layer (510) on the substrate (100) and the orthographic projection of the second gate layer (520) on the substrate (100) is truncated. Preferably, the second thin-film transistor (500) is an N-channel transistor; Preferably, the second thin-film transistor (500) further includes a third gate layer (530), wherein the second gate layer (520) is located on the side of the second channel layer (510) away from the substrate (100), and the third gate layer (530) is located on the side of the second channel layer (510) close to the substrate (100).

8. The array substrate (10) as claimed in claim 1, characterized in that, The array substrate (10) includes a display area (910) and a non-display area (920); Both the first thin-film transistor (200) and the second thin-film transistor (500) are located in the non-display area.

9. A display panel (20), characterized in that, It includes a pixel defining layer (21) and an array substrate (10) as described in any one of claims 1-8, wherein the pixel defining layer (21) is disposed on one side of the array substrate (10).

10. A display device (30), characterized in that, Includes the display panel (20) as described in claim 9.

Images