Array substrate, preparation method thereof, display panel and display device

Abstract

This application relates to an array substrate and its fabrication method, a display panel, and a display device. The array substrate includes a substrate, multiple conductive layers, multiple performance-related layers, and a raised structure. The multiple conductive layers and multiple performance-related layers form pixel circuits arranged in an array in the display area. The raised structure is located in the boundary region and surrounds the display area. The multiple performance-related layers include a first related layer, which is located at least in the display area and the boundary region; the raised structure includes a first raised layer, which is located on the side of at least one first related layer near the back surface of the array substrate. And / or, the multiple performance-related layers include a second related layer, which is located in the display area; the raised structure includes a second raised layer, which is located on the side of at least one second related layer near the back surface of the array substrate, and / or, the second raised layer and at least one second related layer are located on the same film surface.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its preparation method, a display panel and a display device. Background Technology

[0002] With the development of display technology, achieving a higher screen-to-body ratio and reducing bezel size has become a crucial aspect of narrow-bezel products. In related technologies within the industry, the dummy pixel at the outermost edge of the display area is eliminated to further reduce bezel size.

[0003] However, this design causes an uneven visual effect between the edge and central areas of the display area. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate, its fabrication method, display panel, and display device that can improve the visual unevenness between the edge and central regions, in order to address the aforementioned technical problems.

[0005] An array substrate is provided, wherein a display area, a non-display area, and a boundary area are defined on the array substrate, the non-display area surrounds the display area, and the boundary area is located between the non-display area and the display area, the array substrate comprising:

[0006] Substrate;

[0007] Multiple conductive layers and multiple performance-related layers are located on one side of the substrate, and the multiple conductive layers and the multiple performance-related layers form a pixel circuit arranged in the display area array. The performance-related layers are film layers that affect the performance of the pixel circuit.

[0008] A raised structure is located in the boundary area and surrounds the display area;

[0009] The plurality of performance-related layers include a first related layer, which is located at least in the display area and the boundary area, and in the display area, the structure of the first related layer near the substrate is uneven; the protrusion structure includes a first protrusion layer, which is located on the side of at least one of the first related layers near the back surface of the array substrate.

[0010] And / or,

[0011] The plurality of performance-related layers include a second related layer located in the display area, and in the display area, the structure of the second related layer on the substrate side is uneven; the protrusion structure includes a second protrusion layer located on the side of at least one second related layer near the back of the array substrate, and / or, the second protrusion layer and at least one second related layer are located on the same film surface.

[0012] In one embodiment, the first associated layer includes a gate insulating layer and / or a capacitor insulating layer; and / or, the second associated layer includes an active layer.

[0013] In one embodiment, the maximum height of the first related layer located in the boundary area is the same as the maximum height of the first related layer located in the display area.

[0014] In one embodiment, the protrusion structure includes a plurality of protrusions spaced apart;

[0015] Optionally, the shape of the protrusion includes a hump-shaped weir.

[0016] In one embodiment, the protrusion structure is a continuous structure.

[0017] In one embodiment, the array substrate further includes:

[0018] The dam is located in the non-display area;

[0019] Optionally, the array substrate further includes a planarization layer and / or a pixel definition layer, and the dam is disposed in the same layer as the planarization layer and / or the pixel definition layer.

[0020] In one embodiment, the material of the protrusion structure includes organic and / or inorganic materials;

[0021] Optionally, the substrate includes a flexible layer, a buffer layer, and a barrier layer, and the protrusion structure is disposed in the same layer as at least one of the flexible layer, the buffer layer, and the barrier layer.

[0022] A method for fabricating an array substrate, wherein the array substrate defines a display area, a non-display area, and a boundary area, the non-display area surrounding the display area, and the boundary area located between the non-display area and the display area, the method comprising:

[0023] Provide substrate;

[0024] Multiple conductive layers and multiple performance-related layers are formed on one side of the substrate. The multiple conductive layers and the multiple performance-related layers form a pixel circuit arranged in the display area array. The performance-related layers are film layers that affect the performance of the pixel circuit.

[0025] The plurality of performance-related layers include a first related layer, which is located at least in the display area and the boundary area, and in the display area, the structure of the first related layer on the substrate side is uneven; before forming at least one first related layer, the process includes:

[0026] A first protruding layer is formed in the boundary area;

[0027] And / or,

[0028] The plurality of performance-related layers include a second related layer located in the display area, wherein the structure of the second related layer on the substrate side of the display area is uneven; prior to forming at least one second related layer, the following is included:

[0029] A second protruding layer is formed in the boundary area.

[0030] A display panel, comprising:

[0031] The array substrate described above or the array substrate prepared according to the array substrate preparation method described above;

[0032] A light-emitting functional layer is located on the array substrate.

[0033] A display device includes a display panel as described above.

[0034] In the aforementioned array substrate and its fabrication method, display panel, and display device, by providing a protruding structure (a first protruding layer and / or a second protruding layer) at the interface, and ensuring that the protruding structure is formed before the first and / or second related layers (performance-related layers formed on the basis of the uneven structure of the display area), it is beneficial to ensure that the edge region and the central region of the display area are in a more consistent airflow environment during the film formation process of the first and / or second related layers. Therefore, the film quality and thickness of the first and / or second related layers in the edge region and the central region of the display area are more consistent, thereby improving the performance consistency of the pixel circuits in the edge region and the central region of the display area, and ultimately improving the display uniformity of the edge region and the central region of the display area. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a partial cross-sectional structure of an array substrate in related technologies;

[0037] Figure 2 This is a planar schematic diagram of the array substrate in one embodiment of this application;

[0038] Figure 3 For along Figure 2 A schematic diagram of the local cross-sectional structure of the array substrate formed after the cross-section line AA' is cut;

[0039] Figure 4 This is a partial cross-sectional structural diagram of the array substrate in another embodiment of this application;

[0040] Figure 5 This is a planar schematic diagram of the array substrate in another embodiment of this application;

[0041] Figure 6 This is a partial cross-sectional structural diagram of the array substrate in another embodiment of this application.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100-Substrate, 110-Flexible layer, 120-Buffer layer, 130-Barrier layer, 200-Conductive layer, 300a-First related layer, 300b-Second related layer, 310-Active layer, 311-Source region, 312-Drain region, 313-Channel region, 320-Gate insulating layer, 330-Capacitor insulating layer, 400-Bump structure, 410-First bump layer, 420-Second bump layer, 401-Bump, 10-Pixel circuit, A1-Display area, A2-Boundary area, A3-Non-display area. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0046] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0047] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0048] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0049] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form has a distinctly different meaning in the context.

[0050] When a phrase such as “at least one of…” follows a list of elements, it modifies the entire list of elements, not individual elements within that list. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. As used in the application documents, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0051] As mentioned in the background section, in related technologies in the industry, the outermost virtual pixels of the display area A1 are eliminated to further reduce the bezel size. However, this design causes an uneven visual effect between the edge and central areas of the display area A1. The inventors have discovered that the reason for this problem is:

[0052] The pixel brightness and color of the pixel panel are affected by the performance of the pixel circuit 10 of each sub-pixel, such as the performance of the thin-film transistors (TFTs) in the pixel circuit 10. The performance of the pixel circuit 10 is affected by the quality and thickness of its performance-related layers (such as the active layer 310, the gate insulating layer 320, and the capacitor insulating layer 330). However, please refer to... Figure 1 Before forming performance-related layers (such as gate insulating layer 320, capacitor insulating layer 330, etc.), the previously formed structure is flat in the boundary region A2 between the display area A1 and the non-display area A3, while the display area A1 is uneven, resulting in a gap in the boundary region A2, which easily leads to a funnel effect. At this time, during the formation of the performance-related layers, the airflow velocity in the boundary region A2 is high, and the gas accelerates through the boundary region A2 and flows towards the display area A1. This results in different airflow environments at the edge and center of the display area A1, leading to poor uniformity in the film quality and thickness of the performance-related layers between the edge and center of the display area A1, and consequently, differences in the circuit characteristics between the peripheral pixel circuit 10 and the central region. Therefore, the problem of uneven visual effects between the edge and central regions of the display area A1 occurs.

[0053] Based on this, this application provides an array substrate that improves the visual unevenness between the edge and central regions, a method for fabricating the same, a display panel, and a display device.

[0054] In one embodiment, a display panel is provided, including an array substrate and a light-emitting functional layer. The light-emitting functional layer is located on the array substrate.

[0055] The light-emitting functional layer may include multiple light-emitting units of various colors, such as red light-emitting units, green light-emitting units, and blue light-emitting units. The material of the light-emitting units may include multiple layers of organic materials.

[0056] The array substrate is used to drive the individual light-emitting units in the light-emitting functional layer.

[0057] In addition, the display panel may also include an encapsulation layer and a cover plate. The encapsulation layer can cover the light-emitting functional layer, thereby preventing water, oxygen, and other substances from intruding into the individual light-emitting units in the light-emitting functional layer. Specifically, the encapsulation layer may include alternating inorganic and organic layers. The cover plate can be located on a layer of the encapsulation layer away from the light-emitting functional layer, and it can be bonded by optical adhesive or the like.

[0058] In one embodiment, see Figure 2 The array substrate is defined with a display area A1, a non-display area A3, and a boundary area A2.

[0059] Each light-emitting unit of the light-emitting functional layer is located within the display area A1, thereby emitting light for display within the display area A1. The non-display area A3 surrounds the display area A1. The non-display area A3 can be used to form traces connecting the various light-emitting units within the display area A1. The boundary area A2 is located between the non-display area A3 and the display area A1.

[0060] Please see Figure 3 The array substrate includes a substrate 100, multiple conductive layers 200, and multiple performance-related layers. The array substrate also includes a protrusion structure 400.

[0061] The substrate 100 can be a flexible substrate or a rigid substrate.

[0062] Multiple conductive layers 200 and multiple performance-related layers are located on one side of the substrate 100. It is understood that "multiple" in this document means two or more.

[0063] The conductive layer 200 may be, but is not limited to, a metal layer. The same conductive layer 200 may include multiple spaced conductive structures (such as conductive lines). Different conductive layers 200 may be placed in different locations as needed. Different performance-related layers may also be placed in different locations as needed.

[0064] Multiple conductive layers 200 and multiple performance-related layers are formed in the pixel circuit 10 arranged in an array in the display area A1. The pixel circuit 10 can be configured one-to-one with a light-emitting unit. Each pixel circuit 10 can form a sub-pixel with its corresponding light-emitting unit.

[0065] The performance-dependent layer is a film layer that affects the performance of the pixel circuit 10. The pixel circuit 10 may include thin-film transistors (TFTs) and storage capacitors, etc. The performance-dependent layer may include the active layer 310 and gate insulating layer 320 of the thin-film transistor (TFT), etc. The performance-dependent layer may also include the capacitor insulating layer 330 of the storage capacitor, etc.

[0066] The raised structure 400 is located in the boundary area A2 and surrounds the display area A1.

[0067] For example, please refer to Figure 3The system includes multiple performance-related layers, including a first related layer 300a. The first related layer 300a is located at least in the display area A1 and the boundary area A2. Exemplarily, the first related layer 300a may extend from the display area A1 to the boundary area A2. Further, the first related layer 300a may also extend from the display area A1, through the boundary area A2, to the non-display area A3. Of course, the first related layer 300a located in the display area A1 and the first related layer 300a located in the boundary area A2 may be spaced apart and not continuous. This is not a limitation.

[0068] In display area A1, the structure on the side of the first correlation layer 300a near the substrate 100 is uneven. That is, during the fabrication of the array substrate, the preceding structure formed before the formation of the first correlation layer 300a is uneven in display area A1. Exemplarily, the first correlation layer 300a may include a gate insulating layer 320 and / or a capacitor insulating layer 330.

[0069] Meanwhile, the protrusion structure 400 located in the boundary region A2 includes a first protrusion layer 410. The first protrusion layer 410 is located on the side of at least one first related layer 300a near the back side of the array substrate. That is, during the fabrication of the array substrate, the first protrusion layer 410 is formed in the boundary region A2 before the formation of the first related layer 300a. Here, it can be understood that the side of the array substrate with the light-emitting functional layer is its front side, and the side away from the light-emitting functional layer is its back side. The first protrusion layer 410 can be disposed adjacent to the first related layer 300a or spaced apart from the first related layer 300a.

[0070] For example, the first protruding layer 410 may be disposed on the originally flat structural surface of the junction area A2.

[0071] Due to the presence of the first protrusion layer 410, the boundary region A2 and the display region A1 have similar environments before the formation of the first correlation layer 300a. Therefore, during the deposition of the first correlation layer 300a, the airflow velocities in the boundary region A2 and the display region A1 can be similar, thereby mitigating the gas velocity difference between the edge and central regions of the display region A1. This results in a more uniform deposition of the first correlation film across all regions of the display region A1, with higher consistency in film quality and thickness, thus improving the performance consistency of the pixel circuits 10 between the edge and central regions of the display region A1. Therefore, this effectively improves the display uniformity between the edge and central regions of the display region A1.

[0072] As another example, please refer to Figure 4 Multiple performance-related layers include a second related layer 300b. The second related layer 300b is located in the display area A1.

[0073] For example, the second related layer 300b may be located only in the display area A1. And the second related layer 300b may include a plurality of graphical structures located at intervals within the display area A1.

[0074] The process of forming the second correlation layer 300b may include first depositing a second correlation material layer over the entire surface. Then, the second correlation material layer is patterned and etched using a photolithography process to form the second correlation layer 300b located in the display area A1.

[0075] In display area A1, the structure on the side of the second related layer 300b near the substrate 100 is uneven. That is, during the fabrication of the array substrate, before the formation of the second related layer 300b, the preceding structure formed in display area A1 is uneven. For example, as... Figure 4 As shown, the thin-film transistor of the pixel circuit 10 can be a bottom-gate transistor. In this case, the second related layer 300b of the thin-film transistor can include the active layer 310 of the thin-film transistor. The formation process of the second related layer 300b can be as follows: First, a semiconductor material layer (second related material layer) is formed. The material of the semiconductor material layer can be, but is not limited to, a-Si. Then, the semiconductor material layer is patterned to form multiple spaced semiconductor patterns. Then, source and drain doping is performed on both sides of the semiconductor patterns to form source region 311 and drain region 312. The semiconductor pattern between source region 311 and drain region 312 can form a channel region 313. Source region 311, drain region 312, and channel region 313 together form active region 311, and multiple active regions 311 form active layer 310.

[0076] Meanwhile, the protruding structure 400 located in the boundary area A2 includes a second protruding layer 420.

[0077] The second protrusion layer 420 is located on the side of at least one second related layer 300b near the back surface of the array substrate; and / or, the second protrusion layer 420 and at least one second related layer 300b are located on the same film surface. That is, during the fabrication of the array substrate, the second protrusion layer 420 is formed in the junction region A2 before the formation of the second related layer 300b. It is understood that when the second protrusion layer 420 is formed in a process adjacent to the process of the second related layer 300b, the second protrusion layer 420 can be located on the same film surface as the second related layer 300b. When the second protrusion layer 420 is formed in a process not adjacent to the process of the second related layer 300b, the second protrusion layer 420 is located on the side of the second related layer 300b near the back surface of the array substrate.

[0078] For example, the second protruding layer 420 may be disposed on the originally flat structural surface of the junction area A2.

[0079] Due to the provision of the second raised layer 420, the boundary area A2 and the display area A1 have similar environments before the formation of the second related layer 300b.

[0080] During the formation of the second correlation layer 300b, when forming the second correlation material layer, the airflow velocity in the boundary region A2 and the display region A1 can be similar due to the setting of the second protrusion layer 420. This improves the difference in gas flow velocity between the edge and central regions of the display region A1, resulting in a more uniform film formation of the second correlation material layer in the display region A1. Therefore, after patterning the second correlation material layer to obtain the second correlation layer 300b, the consistency of film quality and thickness of the second correlation layer 300b between the edge and central regions of the display region A1 is higher. Thus, the performance consistency of the pixel circuits 10 between the edge and central regions of the display region A1 can be improved, effectively enhancing the display uniformity between the edge and central regions of the display region A1.

[0081] In this embodiment, by providing a protruding structure 400 (first protruding layer 410 and / or second protruding layer 420) in the boundary region A2, and making the protruding structure 400 a structure formed before the first related layer 300a and / or the second related layer 300b (performance-related layers formed on the basis of the uneven structure of the display region A1), it is beneficial to ensure that the edge region and the central region of the display region A1 are in a more consistent airflow environment during the film formation process of the first related layer 300a and / or the second related layer 300b. Therefore, the film quality and thickness of the first related layer 300a and / or the second related layer 300b in the edge region and the central region of the display region A1 are more consistent, thereby improving the performance consistency of the pixel circuit 10 in the edge region and the central region of the display region A1, and thus improving the display uniformity of the edge region and the central region of the display region A1.

[0082] In one embodiment, the maximum height of the first related layer 300a located in the boundary area A2 is the same as the maximum height of the first related layer 300a located in the display area A1.

[0083] During the fabrication of the array substrate, the height of the first related layer 300a located in the boundary region A2 can be adjusted by adjusting the height of the first protrusion layer 410, thereby making the maximum height of the first related layer 300a located in the boundary region A2 the same as the maximum height of the first related layer 300a located in the display region A1.

[0084] At this time, during the film formation process of the first related layer 300a, the gas flow rate and other airflow environment of the junction area A2 and the display area A1 can be more consistent, which is more conducive to improving the display uniformity of the edge area and the central area of ​​the display area A1.

[0085] It is understandable that "high degree of similarity" here does not necessarily mean absolute similarity; it can mean similarity within the allowable range of process error.

[0086] In one embodiment, see Figure 5 The protrusion structure 400 (first protrusion layer 410 and / or second protrusion layer 420) includes a plurality of protrusions 401 spaced apart.

[0087] At this time, the connection traces between the pixel circuit 10 and the pixel signal traces in the non-display area A3 can be set between adjacent protrusions 401 without having to climb over the protrusions 401, thereby reducing the risk of trace breakage when climbing over the protrusions.

[0088] As an example, the shape of the protrusion 401 includes a hump-shaped weir, which allows the first protrusion layer 410 and / or the second protrusion layer 420 to better regulate airflow during the preparation of the corresponding performance-related layers.

[0089] At this time, during the fabrication of the first raised layer 410 and / or the second raised layer 420, a raised material layer can be formed first. Then, based on a semi-transparent photomask, photolithography is performed on the raised material layer, so that the etched state of the raised material layer at different locations is different, thereby forming a hump-shaped protrusion 401. For example, some of the raised material layer can be left unetched, another part of the raised material layer can be etched, and the remaining part of the raised material layer can be completely etched away, thereby forming a plurality of hump-shaped, spaced protrusions 401 in the junction region A2.

[0090] Of course, the shape and fabrication method of the protrusion 401 are not limited to this. For example, during the fabrication of the first protrusion layer 410 and / or the second protrusion layer 420, a protrusion material layer can be formed first. Then, based on a conventional photomask, the protrusion material layer is photolithographically patterned to form a plurality of spaced protrusions 401 in the junction region A2. In this case, the fabrication cost of the first protrusion layer 410 and / or the second protrusion layer 420, which includes a plurality of spaced protrusions 401, can be effectively reduced.

[0091] In one embodiment, see Figure 2 The raised structure 400 (first raised layer 410 and / or second raised layer 420) is a continuous structure.

[0092] For example, the first raised layer 410 and / or the second raised layer 420 are closed rings. In this case, the first raised layer 410 and / or the second raised layer 420 can provide a beneficial effect of slowing down the airflow velocity at any position around the display area A1, thereby helping to better improve the film uniformity of the related performance related layer in the edge region and the central region of the display area A1.

[0093] For example, the shape of the first raised layer 410 and / or the second raised layer 420 may be the same as the shape of the display area A1, thereby uniformly alleviating the airflow velocity at the edges of different locations of the display area A1.

[0094] Simultaneously, during the fabrication of the first raised layer 410 and / or the second raised layer 420, a raised material layer can also be formed first. Then, based on a conventional photomask, photolithography is performed on the raised material layer to form the first raised layer 410 and / or the second raised layer 420 with a continuous structure. In this case, the photomask cost is lower, which helps to reduce the process cost. At the same time, the continuous structure of the first raised layer 410 and / or the second raised layer 420 can also reduce the precision requirements of the photolithography process.

[0095] It is understood that, in some embodiments, please refer to Figure 3 The performance-related layer may include multiple first protrusion layers 410. The multiple first protrusion layers 410 may be configured in the same or different ways. In some embodiments, the performance-related layer may include multiple second protrusion layers 420. The multiple second protrusion layers 420 may be configured in the same or different ways. In some embodiments, please refer to... Figure 4 The performance-related layer may simultaneously include a first protrusion layer 410 and a second protrusion layer 420. In this case, the first protrusion layer 410 and the second protrusion layer 420 may be configured in the same way or differently. Furthermore, in some embodiments, the first protrusion layer 410 and the second protrusion layer 420 may be the same protrusion structure 400. That is, the same protrusion structure 400 may be the first protrusion layer 410 for the first related layer 300a and the second protrusion layer 420 for the second related layer 300b. For example, please refer to... Figure 4 The raised structure 400 located below is a first raised layer 410 for the gate insulating layer 320 (first related layer 300a) and a second raised layer 420 for the active layer 310 (second related layer 300b).

[0096] In one embodiment, the array substrate further includes a dam. The dam is located in the non-display area A3. The protrusion structure 400 is located in the boundary area A2 between the display area A1 and the non-display area A3. Therefore, the protrusion structure 400 is located between the display area A1 and the dam.

[0097] In the display panel manufacturing process, after forming a light-emitting functional layer on the array substrate, an encapsulation layer can be formed on the light-emitting functional layer. Specifically, a first inorganic encapsulation layer can be formed first. Then, an organic encapsulation layer is formed on the first inorganic encapsulation layer. To form the organic encapsulation layer, a liquid organic encapsulation material can be coated first. A dam can act as a flow barrier during the leveling process of the liquid organic encapsulation material. Subsequently, the liquid organic encapsulation material solidifies, thereby forming the organic encapsulation layer. Then, a second inorganic encapsulation layer is formed on the organic encapsulation layer.

[0098] The array substrate also includes a planarization layer and / or a pixel definition layer.

[0099] For example, when forming the array substrate, pixel circuits 10 may first be formed on substrate 100. Then, wiring layers, etc., may be formed on pixel circuits 10. A planarization layer may cover the wiring layer, thereby providing a flat surface for the formation of subsequent structures. The material of the planarization layer may include, but is not limited to, organic materials.

[0100] For example, the pixel circuit 10 may have multiple routing layers. After each routing layer is formed, a planarization layer may be formed, so that the array substrate includes multiple planarization layers.

[0101] After forming the planarization layer of the last wiring layer, multiple spaced first electrodes can be formed on this planarization layer. The first electrodes can be, for example, anodes. Then, a pixel definition material layer is formed covering the first electrodes. Subsequently, the pixel definition material layer is patterned and etched to form the pixel definition layer. The material of the pixel definition layer can include organic or inorganic materials. The pixel definition layer has pixel openings corresponding one-to-one with each of the first electrodes. The pixel openings expose the corresponding first electrodes. Then, light-emitting units of different colors can be formed within different pixel openings.

[0102] As an example, the dam can be disposed on the same layer as the planarization layer. Specifically, when the array substrate has multiple planarization layers, the dam can be disposed on the same layer as at least one planarization layer.

[0103] At this point, during the planarization layer formation process, a planarization material layer can be formed first. Then, the planarization material layer is etched to form planarization layers and dams spaced apart. The dams are located in the non-display area A3.

[0104] As another example, the dam can be set on the same layer as the pixel definition layer. In this case, while etching the pixel definition material layer to form a pixel definition layer with pixel openings, the dam can be formed in the non-display area A3.

[0105] Of course, the dam can also be divided into multiple sub-layers. Some sub-layers can be set on the same layer as the planarization layer, and some sub-layers can be set on the same layer as the pixel definition layer.

[0106] In one embodiment, the material of the protrusion structure 400 (first protrusion layer 410 and / or second protrusion layer 420) includes organic and / or inorganic materials.

[0107] As an example, substrate 100 may be a flexible substrate, which may include a flexible layer 110, a buffer layer 120 and a barrier layer 130.

[0108] The flexible layer 110 can be used for support. The material of the flexible layer 110 may include polyimide (PI) and the like.

[0109] The buffer layer 120 is located on the flexible layer 110 and can be used to improve the surface flatness of the flexible substrate, enhance the adhesion of subsequent thin film layers, and alleviate the stress between the flexible layer 110 and the device layer. The material of the buffer layer 120 may include silicon dioxide or silicon nitride, etc. The buffer layer 120 can be a multilayer structure. Of course, the buffer layer 120 can also be a single-layer structure, depending on the actual needs.

[0110] The barrier layer 130 is located on the buffer layer 120 and can be used to prevent external moisture and oxygen from penetrating into the light-emitting functional layer, thus avoiding the failure of the light-emitting device. The material of the barrier layer 130 may include silicon nitride or aluminum oxide, etc.

[0111] The protruding structure 400 (first protruding layer 410 and / or second protruding layer 420) is disposed in the same layer as at least one of the flexible layer 110, buffer layer 120, and barrier layer 130. For example, please refer to Figure 6 The protrusion structure 400 (first protrusion layer 410 and / or second protrusion layer 420) is disposed in the same layer as the barrier layer 130. In this case, the protrusion structure 400 can be disposed within the substrate 100, so as not to affect the subsequent device structure or film layer processing.

[0112] For example, when the protrusion structure 400 and the flexible layer 110 are disposed in the same layer, a flexible material layer with a relatively thick thickness can be formed first. Then, the flexible material layer is etched to form the flexible layer 110 protruding in the junction region A2. The protruding portion of the flexible layer 110 forms the protrusion structure 400 (the first protrusion layer 410 and / or the second protrusion layer 420).

[0113] When the protrusion structure 400 and the buffer layer 120 are disposed in the same layer, a buffer material layer with a relatively thick thickness can be formed first. Then, the buffer material layer is etched to form the buffer layer 120 protruding in the junction region A2. The protruding portion of the buffer layer 120 forms the protrusion structure 400 (first protrusion layer 410 and / or second protrusion layer 420).

[0114] Please see Figure 6 When the protrusion structure 400 and the barrier layer 130 are disposed in the same layer, a barrier material layer with a relatively thick thickness can be formed first. Then, the barrier material layer is etched to form the barrier layer 130 protruding in the junction region A2. The protruding portion of the barrier layer 130 forms the protrusion structure 400 (first protrusion layer 410 and / or second protrusion layer 420).

[0115] In one embodiment, a method for fabricating an array substrate is also provided. The array substrate defines a display area A1, a non-display area A3, and a boundary area A2. The non-display area A3 surrounds the display area A1. The boundary area A2 is located between the non-display area A3 and the display area A1.

[0116] The method for fabricating the array substrate includes the following steps:

[0117] Step S10: Provide substrate 100;

[0118] In step S20, a plurality of conductive layers 200 and a plurality of performance-related layers are formed on one side of the substrate 100. The plurality of conductive layers 200 and the plurality of performance-related layers are formed in the pixel circuit 10 arranged in the display area A1 array. The performance-related layers are film layers that affect the performance of the pixel circuit 10.

[0119] In step S10, the substrate 100 can be a flexible substrate or a rigid substrate. For example, the substrate 100 is a flexible substrate and includes a flexible layer 110, a buffer layer 120 and a barrier layer 130.

[0120] In step S20, the conductive layer 200 may be, but is not limited to, a metal layer. The same conductive layer 200 may include multiple spaced conductive structures (such as conductive lines). Different conductive layers 200 may be positioned at different locations as needed. Different performance-related layers may also be positioned at different locations as needed.

[0121] Multiple conductive layers 200 and multiple performance-related layers are formed in the pixel circuit 10 arranged in an array in the display area A1. The pixel circuit 10 may include thin-film transistors (TFTs) and storage capacitors, etc. The performance-related layers may include the active layer 310 and gate insulating layer 320 of the thin-film transistors (TFTs), etc. The performance-related layers may also include the capacitor insulating layer 330 of the storage capacitors, etc.

[0122] In one embodiment, the plurality of performance-related layers includes a first related layer 300a. The first related layer 300a is located at least in the display area A1 and the boundary area A2. Exemplarily, the first related layer 300a may extend from the display area A1 to the boundary area A2. Further, the first related layer 300a may also extend from the display area A1, through the boundary area A2, to the non-display area A3. Of course, the first related layer 300a located in the display area A1 and the first related layer 300a located in the boundary area A2 may also be spaced apart and not continuous. This is not a limitation.

[0123] In display area A1, the structure on the side of the first related layer 300a near the substrate 100 is uneven. Specifically, the preceding structure formed before the formation of the first related layer 300a is uneven in display area A1. Exemplarily, the first related layer 300a may include a gate insulating layer 320 and / or a capacitor insulating layer 330.

[0124] At this point, before forming at least one first related layer 300a, the following is included:

[0125] Step S21: A first protruding layer 410 is formed in the boundary area A2.

[0126] As an example, the first raised layer 410 can be a continuous structure. In this case, a raised material layer can be formed first. Then, based on a conventional photomask, the raised material layer is photolithographically ...

[0127] As an example, the first raised layer 410 may also be an intermittent structure. Specifically, the first raised layer 410 may include a plurality of spaced-apart raised portions 401.

[0128] For example, the shape of the protrusion 401 includes a hump-shaped dam. During the fabrication of the first protrusion layer 410, a protrusion material layer may be formed first. Then, based on a semi-transparent photomask, the protrusion material layer is photolithographically etched to form a plurality of spaced protrusions 401 in a hump-shaped dam pattern in the junction region A2.

[0129] In this embodiment, before forming at least one first correlation layer 300a, a first protrusion layer 410 is formed in the boundary region A2, so that the boundary region A2 and the display region A1 have similar environments. Therefore, during the film formation process of at least one first correlation layer 300a, the airflow velocity in the boundary region A2 and the display region A1 can be similar, thereby improving the difference in gas flow velocity between the edge region and the central region of the display region A1. This results in a more uniform and consistent formation of the first correlation film layer in all regions of the display region A1, with higher consistency in film quality and thickness, thereby improving the performance consistency of the pixel circuits 10 in the edge region and the central region of the display region A1. Therefore, the display uniformity between the edge region and the central region of the display region A1 can be effectively improved.

[0130] In one embodiment, the plurality of performance-related layers includes a second related layer 300b. The second related layer 300b is located in the display area A1.

[0131] For example, the second related layer 300b may be located only in the display area A1. And the second related layer 300b may include a plurality of graphical structures located at intervals within the display area A1.

[0132] The process of forming the second correlation layer 300b may include first depositing a second correlation material layer over the entire surface. Then, the second correlation material layer is patterned and etched using a photolithography process to form the second correlation layer 300b located in the display area A1.

[0133] In display area A1, the structure on the side of the second correlation layer 300b closest to the substrate 100 is uneven. That is, during the fabrication of the array substrate, the preceding structure formed before the formation of the second correlation layer 300b is uneven in display area A1. Exemplarily, as shown in the figure, the thin-film transistor of the pixel circuit 10 can be a bottom-gate transistor. In this case, the second correlation layer 300b of the thin-film transistor can include the active layer 310 of the thin-film transistor.

[0134] At this point, before forming at least one second related layer 300b, the process includes:

[0135] Step S22: A second protrusion layer 420 is formed in the boundary area A2.

[0136] The second protrusion layer 420 can be formed in a process adjacent to the process of the second associated layer 300b, or it can be formed in a process that is not adjacent to the process of the second associated layer 300b.

[0137] The second protruding layer 420 can be a continuous structure or a discontinuous structure. The preparation method of the second protruding layer 420 is preferably similar to the preparation method of the first protruding layer 410 in the aforementioned embodiments, and will not be described in detail here.

[0138] In this embodiment, before forming at least one second correlation layer 300b, a second protrusion layer 420 is formed in the boundary region A2, thereby making the boundary region A2 and the display region A1 have similar environments. During the fabrication of at least one second correlation layer 300b, when forming the second correlation material layer, the airflow velocity in the boundary region A2 and the display region A1 can be similar due to the provision of the second protrusion layer 420. This improves the difference in gas flow velocity between the edge and central regions of the display region A1, resulting in a more uniform film formation of the second correlation material layer in the display region A1. Therefore, after patterning the second correlation material layer to obtain the second correlation layer 300b, the consistency of film quality and thickness of the second correlation layer 300b between the edge and central regions of the display region A1 is higher. Therefore, the performance consistency of the pixel circuits 10 between the edge and central regions of the display region A1 can be improved, thereby effectively improving the display uniformity between the edge and central regions of the display region A1.

[0139] In some embodiments, the first protruding layer 410 and the second protruding layer 420 can be the same protruding structure. That is, the same protruding structure, for the first related layer 300a, can be the first protruding layer 410, and for the second related layer 300b, can be the second protruding layer 420.

[0140] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel in the above embodiments.

[0141] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0142] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate defines a display area, a non-display area, and a boundary area. The non-display area surrounds the display area, and the boundary area is located between the non-display area and the display area. The array substrate includes: Substrate; Multiple conductive layers and multiple performance-related layers are located on one side of the substrate, and the multiple conductive layers and the multiple performance-related layers form a pixel circuit arranged in the display area array. The performance-related layers are film layers that affect the performance of the pixel circuit. A raised structure is located in the boundary area and surrounds the display area; The plurality of performance-related layers include a first related layer, which is located at least in the display area and the boundary area, and in the display area, the structure of the first related layer near the substrate is uneven; the protrusion structure includes a first protrusion layer, which is located on the side of at least one of the first related layers near the back surface of the array substrate. And / or, The plurality of performance-related layers include a second related layer located in the display area, and in the display area, the structure of the second related layer on the substrate side is uneven; the protrusion structure includes a second protrusion layer located on the side of at least one second related layer near the back of the array substrate, and / or, the second protrusion layer and at least one second related layer are located on the same film surface.

2. The array substrate according to claim 1, characterized in that, The first associated layer includes a gate insulating layer and / or a capacitor insulating layer; and / or, the second associated layer includes an active layer.

3. The array substrate according to claim 1, characterized in that, The maximum height of the first related layer located in the boundary area is the same as the maximum height of the first related layer located in the display area.

4. The array substrate according to claim 1, characterized in that, The protrusion structure includes a plurality of protrusions spaced apart; Optionally, the shape of the protrusion includes a camel hump-shaped weir.

5. The array substrate according to claim 1, characterized in that, The protruding structure is a continuous structure.

6. The array substrate according to claim 1, characterized in that, The array substrate further includes: The dam is located in the non-display area; Optionally, the array substrate further includes a planarization layer and / or a pixel definition layer, and the dam is disposed in the same layer as the planarization layer and / or the pixel definition layer.

7. The array substrate according to claim 1, characterized in that, The material of the protruding structure includes organic materials and / or inorganic materials; Optionally, the substrate includes a flexible layer, a buffer layer, and a barrier layer, and the protrusion structure is disposed in the same layer as at least one of the flexible layer, the buffer layer, and the barrier layer.

8. A method for fabricating an array substrate, characterized in that, The array substrate is defined with a display area, a non-display area, and a boundary area, wherein the non-display area surrounds the display area, and the boundary area is located between the non-display area and the display area; the method includes: Provide substrate; Multiple conductive layers and multiple performance-related layers are formed on one side of the substrate. The multiple conductive layers and the multiple performance-related layers form a pixel circuit arranged in the display area array. The performance-related layers are film layers that affect the performance of the pixel circuit. The plurality of performance-related layers include a first related layer, which is located at least in the display area and the boundary area, and in the display area, the structure of the first related layer on the substrate side is uneven; before forming at least one first related layer, the process includes: A first protruding layer is formed in the boundary area; And / or, The plurality of performance-related layers include a second related layer located in the display area, wherein the structure of the second related layer on the substrate side of the display area is uneven; prior to forming at least one second related layer, the following is included: A second protruding layer is formed in the boundary area.

9. A display panel, characterized in that, include: The array substrate according to any one of claims 1-7 or the array substrate prepared by the method of preparing the array substrate according to claim 8; A light-emitting functional layer is located on the array substrate.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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