ESD / EOS protection device

Abstract

An ESD / EOS protection device is provided. The ESD / EOS protection device includes a fin structure formed of semiconductor material and located above a semiconductor substrate; a first source / drain region within the fin structure; a second source / drain region within the fin structure; a gate structure above the fin structure and located between the first and second source / drain regions; a first dummy gate structure above the fin structure; a first doped region within the fin structure and located between the first and second source / drain regions; and a first doped layer below the first dummy gate structure and extending from the second source / drain region to the first doped region. The lower surface of the first doped layer is higher than the lower surface of the first doped region.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to ESD / EOS protection devices. Background Technology

[0002] Electrostatic discharge (ESD) events and electrical over stress (EOS) events are common causes of damage or malfunction in electronic equipment. An ESD event is a transient discharge between objects at different potentials. ESD events can involve voltages ranging from hundreds to thousands of volts. EOS events can be transient events lasting only milliseconds or continuous under sustained conditions. EOS events may occur at lower voltages, typically less than 100 volts. Standard methods for preventing ESD events are not very effective at preventing EOS events. The industry typically uses ESD / EOS protection devices to prevent damage to electronic equipment from both ESD and EOS events. FinFET structures can be used to form ESD / EOS protection devices. However, the protection capabilities of existing FinFET-based ESD / EOS protection devices remain insufficient. Summary of the Invention

[0003] This invention provides an ESD / EOS protection device that has good protection capabilities against both ESD and EOS events.

[0004] According to some embodiments of the present invention, an ESD / EOS protection device is provided. The ESD / EOS protection device includes a fin structure formed of a semiconductor material and located above a semiconductor substrate; a first source / drain region in the fin structure; a second source / drain region in the fin structure; a gate structure above the fin structure and located between the first source / drain region and the second source / drain region; a first dummy gate structure above the fin structure; a first doped region in the fin structure and located between the first source / drain region and the second source / drain region; and a first doped layer below the first dummy gate structure and extending from the second source / drain region to the first doped region. The lower surface of the first doped layer is higher than the lower surface of the first doped region.

[0005] According to some embodiments of the present invention, an ESD / EOS protection device is provided. The ESD / EOS protection device includes a fin structure formed of a semiconductor material on a semiconductor substrate, a first source / drain region in the fin structure, a second source / drain region in the fin structure, a gate structure on the fin structure and between the first source / drain region and the second source / drain region, a first dummy gate structure on the fin structure, a first doped region in the fin structure and between the first source / drain region and the second source / drain region, a first doped layer below the first dummy gate structure and extending from the second source / drain region to the first doped region, a second dummy gate structure on the fin structure, a second doped region in the fin structure, and a second doped layer below the second dummy gate structure and extending from the first doped region to the second doped region. The first doped layer and the second doped layer are separated from each other.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a circuit diagram illustrating an ESD / EOS protection device and its internal circuitry according to some embodiments of the present invention;

[0008] Figure 2 This is a schematic cross-sectional view illustrating a transistor in an ESD / EOS protection device according to some embodiments of the present invention;

[0009] Figure 3 This is a schematic perspective view illustrating a transistor in an ESD / EOS protection device according to some embodiments of the present invention; and

[0010] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C The current-voltage (IV) characteristic curves measured by the TLP test are shown.

[0011] [Symbol Explanation]

[0012] 10: ESD / EOS protection device

[0013] 20: Internal Circuitry

[0014] 30: Transistor

[0015] 100: Detection circuit

[0016] 101: Resistor

[0017] 102: Capacitor

[0018] 110: Control Circuit

[0019] 111: PMOS transistor

[0020] 112: NMOS transistor

[0021] 120: Transistor

[0022] 300: Semiconductor substrate

[0023] 300U: Top surface

[0024] 310: Fin-like structure

[0025] 311: First source / drain region

[0026] 312, 313: Doped regions

[0027] 314: Second source / drain region

[0028] 315, 319: Outer doped layer

[0029] 316: LDD Components

[0030] 317, 318: Doped layers

[0031] 321: Gate structure

[0032] 322, 323: Dummy gate structure

[0033] 322L, 323L: Length

[0034] 331, 332, 333, 334, 335: Contact plugs

[0035] 341: Isolation element

[0036] 342: Well Area

[0037] 343: Deep Well Area

[0038] 351, 353, 354, 355: Conductive films

[0039] 361: Spacing structure

[0040] 3211: Gate dielectric layer

[0041] 3212: Gate material layer

[0042] DCG: Distance

[0043] N1, N3: Nodes

[0044] X, Y, Z: Direction Detailed Implementation

[0045] The accompanying drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale with the actual product. In the following manufacturing methods, one or more additional operations may be present between the operations, and the order of the operations may vary. Therefore, the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of the invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0046] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "over," "above," "higher than," "top," "lower," "below," "below," "below," "below," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to those shown in the drawings. Structures may be flipped or rotated at various angles, and the spatial terms used herein may be interpreted accordingly. The singular forms "a" and "the" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The word "and / or" used in the specification and claims includes any and all combinations of one or more listed items.

[0047] Furthermore, the term "electrically connected" in the specification and appended claims can mean that current flows between multiple elements or that multiple elements are operationally related. Operational relatedness can be, for example, one element driving another element, but current may not flow directly between the two elements. The term "adjacent" in the specification and appended claims means "adjacent and in contact." The term "dummy gate structure" in the specification and appended claims means that the current between the source and drain of the transistor is not controlled by this gate structure.

[0048] Please refer to Figure 1 . Figure 1This is a circuit diagram illustrating an ESD / EOS protection device 10 and internal circuitry 20 according to some embodiments of the present invention. The ESD / EOS protection device 10 is electrically connected to the internal circuitry 20 to protect the internal circuitry 20 by discharging the charge accumulated during an electrostatic discharge event. The internal circuitry 20 may include one or more active elements and / or one or more passive elements. Active elements include, but are not limited to, transistors and diodes. Transistors include, but are not limited to, planar field-effect transistors, fin field-effect transistors (FinFETs), nanowire field-effect transistors, nanosheet field-effect transistors, complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, and high-frequency transistors. Passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0049] ESD / EOS protection device 10 includes a detection circuit 100, a control circuit 110, and a transistor 120. The detection circuit 100 is electrically connected between voltage VDD and voltage VSS. In one embodiment, voltage VDD is any voltage suitable for operating the internal circuit 20. In another embodiment, voltage VSS is ground voltage. The detection circuit 100 may include a resistor 101 and a capacitor 102. A first terminal of resistor 101 is electrically connected to voltage VDD. A second terminal of resistor 101 is electrically connected to node N1. A first terminal of capacitor 102 is electrically connected to node N1. A second terminal of capacitor 102 is electrically connected to voltage VSS. Resistor 101 and capacitor 102 may form a resistor-capacitor (RC) circuit. In one embodiment, the detection circuit 100 may include any number of resistors 101 and any number of capacitors 102. The control circuit 110 is electrically connected between voltage VDD and voltage VSS. Control circuit 110 may include a P-type metal-oxide-semiconductor (PMOS) transistor 111 and an N-type metal-oxide-semiconductor (NMOS) transistor 112. The source of PMOS transistor 111 is electrically connected to voltage VDD. The gate of PMOS transistor 111 is electrically connected to node N1. The drain of PMOS transistor 111 is electrically connected to node N3. The source of NMOS transistor 112 is electrically connected to voltage VSS. The gate of NMOS transistor 112 is electrically connected to node N1. The drain of NMOS transistor 112 is electrically connected to node N3. Control circuit 110 may be an inverter. In one embodiment, a slowly rising voltage at node N1 can be inverted by control circuit 110 to cause a rapid voltage rise at node N3. In another embodiment, a rapidly rising voltage at node N1 can be inverted by control circuit 110 to cause a slow voltage rise at node N3. In one embodiment, PMOS transistor 111 and NMOS transistor 112 are configured to generate an inverted output signal in response to an input signal. Transistor 120 is electrically connected between voltages VDD and VSS. Transistor 120 may be a clamping transistor. Transistor 120 may be or may include an NMOS transistor. The source of transistor 120 is electrically connected to voltage VSS. The gate of transistor 120 is electrically connected to node N3. The drain of transistor 120 is electrically connected to voltage VDD.

[0050] In one embodiment, during an ESD or EOS event, the voltage at node N1 between resistor 101 and capacitor 102 is pulled down to voltage VSS. After being inverted by control circuit 110, the voltage at node N3 is pulled up to a high voltage, and transistor 120 is turned on to release the charge accumulated during the electrostatic discharge event. In another embodiment, during normal operation without an ESD or EOS event, voltage VDD is electrically connected to detection circuit 100, and the voltage at node N1 is high. After being inverted by control circuit 110, the voltage at node N3 is low, thereby turning off transistor 120, and voltage VDD can be supplied to internal circuit 20 for operation.

[0051] Please refer to Figure 2 and Figure 3 . Figure 2 This is a schematic cross-sectional view illustrating a transistor 30 according to some embodiments of the present invention. Figure 3 This is a schematic perspective view illustrating a transistor 30 according to some embodiments of the present invention. Figure 2 and Figure 3 The transistor 30 can be Figure 1 Transistor 120. Figure 2 and Figure 3 The X, Y, and Z directions are perpendicular to each other.

[0052] Transistor 30 includes a semiconductor substrate 300, a fin structure 310, a first source / drain region 311, a second source / drain region 314, a gate structure 321, a dummy gate structure 323, a doped region 313, and a doped layer 318. The semiconductor substrate 300 may be a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator (SOI) substrate, or other suitable semiconductor material. The fin structure 310 may be disposed above the semiconductor substrate 300 in the Z direction. The fin structure 310 may protrude upwards from the upper surface 300U of the semiconductor substrate 300. The fin structure 310 may extend in the X direction. The fin structure 310 may be formed of a semiconductor material, such as silicon, epitaxial silicon, silicon-germanium, silicon carbide, etc. In one embodiment, the fin structure 310 may contain a first-type dopant or a second-type dopant. The conductivity type of the first-type dopant is different from that of the second-type dopant. A gate structure 321 may be disposed above the semiconductor substrate 300 in the Z direction. The gate structure 321 may be disposed above the fin structure 310. The gate structure 321 may extend in the Y direction. The gate structure 321 may cover the upper surface of the fin structure 310 and its opposing sidewalls. The gate structure 321 is located between a first source / drain region 311 and a second source / drain region 314. The gate structure 321 may include a gate dielectric layer 3211 and a gate material layer 3212 disposed on the gate dielectric layer 3211. In one embodiment, the gate material layer 3212 may include a high dielectric constant dielectric layer, a work function metal layer, and a conductive layer. In one embodiment, the gate material layer 3212 may include polysilicon. The first source / drain region 311 and the second source / drain region 314 are disposed in the fin structure 310. The first source / drain region 311 and the second source / drain region 314 may be disposed in the fin structure 310 and the semiconductor substrate 300 below the fin structure 310. The first source / drain region 311 and the second source / drain region 314 may be disposed on opposite sides of the gate structure 321 in the X direction. In this embodiment, the first source / drain region 311 may serve as the source of the transistor 30, and the second source / drain region 314 may serve as the drain of the transistor 30, but the present invention is not limited thereto. The first source / drain region 311 and the second source / drain region 314 may contain a first type dopant or a second type dopant.

[0053] A dummy gate structure 323 may be disposed above the semiconductor substrate 300 in the Z direction. The dummy gate structure 323 may be disposed above the fin structure 310. The dummy gate structure 323 may extend in the Y direction. The dummy gate structure 323 may cover the upper surface of the fin structure 310 and its opposing sidewalls. The dummy gate structure 323 may be disposed between the gate structure 321 and the second source / drain region 314 in the X direction. In one embodiment, the dummy gate structure 323 may include a dummy gate dielectric layer and a dummy gate material layer disposed on the dummy gate dielectric layer. The dummy gate material layer may include a high dielectric constant dielectric layer, a work function metal layer, and a conductive layer. In one embodiment, the dummy gate material layer may include polysilicon. In one embodiment, the dummy gate structure 323 and the gate structure 321 may have the same structure and material. A doped region 313 is disposed in the fin structure 310. A doped region 313 may be disposed in the fin structure 310 and the semiconductor substrate 300 below the fin structure 310. The doped region 313 may be disposed between the first source / drain region 311 and the second source / drain region 314. The doped region 313 may be disposed on one side of the dummy gate structure 323 and between the dummy gate structure 323 and the gate structure 321. The doped region 313 and the second source / drain region 314 may be disposed on opposite sides of the dummy gate structure 323 in the X direction. The doped region 313 may contain a first-type dopant or a second-type dopant. A doped layer 318 is disposed in the fin structure 310. The doped layer 318 may be disposed above the semiconductor substrate 300 in the Z direction. The doped layer 318 may be completely disposed in the fin structure 310 without extending into the semiconductor substrate 300. The doped layer 318 may be disposed below the dummy gate structure 323 in the Z direction. The doped layer 318 may be adjacent to the second source / drain region 314 and the doped region 313. The doped layer 318 extends from the second source / drain region 314 to the doped region 313. The doped layer 318 may contain a type I dopant or a type II dopant. The lower surface of the doped layer 318 may be higher than the lower surface of the doped region 313 in the Z direction.

[0054] Transistor 30 may include one or more dummy gate structures, one or more doped layers, and one or more doped regions. The number of doped layers and doped regions may depend on the number of dummy gate structures. In one embodiment, when transistor 30 includes only one dummy gate structure (e.g., dummy gate structure 323) disposed between gate structure 321 and second source / drain region 314, transistor 30 may include a doped layer (e.g., doped layer 318) below the dummy gate structure and a doped region (e.g., doped region 313) between the dummy gate structure and gate structure 321; in this case, doped region 313 may extend from one side of gate structure 321 to doped layer 318. In one embodiment, when the transistor 30 includes two dummy gate structures (e.g., dummy gate structure 323 and dummy gate structure 322) disposed between the gate structure 321 and the second source / drain region 314, the transistor 30 may include two doped layers (e.g., doped layer 318 and doped layer 317) below the dummy gate structures, and two doped regions (e.g., doped region 313 and doped region 312) between the dummy gate structures and the gate structure 321, such as... Figure 2As shown. A dummy gate structure 322 can be disposed above the semiconductor substrate 300 in the Z direction. The dummy gate structure 322 can be disposed above the fin structure 310. The dummy gate structure 322 can extend in the Y direction. The dummy gate structure 322 can cover the upper surface of the fin structure 310 and its opposing sidewalls. The dummy gate structure 322 can be disposed between the gate structure 321 and the dummy gate structure 323 in the X direction. It can have the same structure and material as the gate structure 321. A doped region 312 is disposed in the fin structure 310. The doped region 312 can be disposed in the fin structure 310 and the semiconductor substrate 300 below the fin structure 310. The doped region 312 can be disposed on one side of the dummy gate structure 322 and between the dummy gate structure 322 and the gate structure 321. The doped region 312 and the doped region 313 can be disposed on opposite sides of the dummy gate structure 322 in the X direction. The doped region 312 can contain a first-type dopant or a second-type dopant. A doped layer 317 is disposed within the fin structure 310. The doped layer 317 may be disposed above the semiconductor substrate 300 in the Z direction. The doped layer 317 may be completely disposed within the fin structure 310 without extending into the semiconductor substrate 300. The doped layer 317 may be disposed below the dummy gate structure 322 in the Z direction. The doped layer 317 may be adjacent to doped regions 312 and 313. The doped layer 317 extends from doped region 312 to doped region 313. The doped layer 317 may contain a first-type dopant or a second-type dopant. The lower surface of the doped layer 317 may be higher than the lower surface of doped region 312 in the Z direction. Doped region 313 may separate doped layer 317 from doped layer 318. Doped layers 317 and 318 may be disposed on opposite sides of doped region 313. Doped regions 312 and 313 and the second source / drain region 314 may be separated from each other.

[0055] In one embodiment, when the transistor 30 includes three or more dummy gate structures disposed between the gate structure 321 and the second source / drain region 314, the configuration of the dummy gate structures, doped layers and doped regions in the transistor 30 can be deduced by analogy from the foregoing.

[0056] Transistor 30 may include isolation elements 341, well regions 342, and deep well regions 343. The structure, location, and material of the isolation elements are described below using two isolation elements 341 as an example, but the invention is not limited thereto; transistor 30 may include fewer or more than two isolation elements. The two isolation elements 341 may be disposed in the semiconductor substrate 300 and on opposite sides of the fin structure 310. The two isolation elements 341 may be disposed on opposite sides of the gate structure 321. One of the two isolation elements 341 may be disposed on the side of the second source / drain region 314 opposite to the first source / drain region 311, and the other of the two isolation elements 341 may be disposed on the side of the first source / drain region 311 opposite to the second source / drain region 314. The upper surface of the isolation element 341 may be substantially flush with the lower surface of the fin structure 310. The isolation element 341 may contain an insulating material such as silicon oxide. Well region 342 is located in the semiconductor substrate 300. A fin structure 310 may be disposed in well region 342. Well region 342 may surround fin structure 310. Well region 342 may surround first source / drain region 311, second source / drain region 314, doped region 312, doped region 313, doped layer 317, and doped layer 318. Isolation element 341 may be disposed in well region 342. Well region 342 may contain a first type dopant or a second type dopant. Deep well region 343 is in semiconductor substrate 300. Well region 342 may be disposed in deep well region 343. Deep well region 343 may surround well region 342. Deep well region 343 may contain a first type dopant or a second type dopant.

[0057] The transistor structure 30 may include multiple LDD (low-doped drain) elements 316. The multiple LDD elements 316 are separated from each other. The LDD elements 316 are disposed within the fin structure 310. The LDD elements 316 may be disposed above the semiconductor substrate 300 in the Z direction. The LDD elements 316 may be completely disposed within the fin structure 310 without extending into the semiconductor substrate 300. The LDD elements 316 may be disposed below the gate structure 321 in the Z direction. The LDD elements 316 may contain a first-type dopant or a second-type dopant. The lower surface of the LDD elements 316 may be higher in the Z direction than the lower surface of the first source / drain region 311, the lower surface of the doped region 312, the lower surface of the doped region 313, and the lower surface of the second source / drain region 314.

[0058] In an embodiment where transistor 30 includes only one dummy gate structure (e.g., dummy gate structure 323), one of the plurality of LDD elements 316 may be disposed on the side of the first source / drain region 311 facing the doped region 313 and adjacent to the first source / drain region 311, and another of the plurality of LDD elements 316 may be disposed on the side of the doped region 313 facing the first source / drain region 311 and adjacent to the doped region 313. In an embodiment where transistor 30 includes two dummy gate structures (e.g., dummy gate structure 323 and dummy gate structure 322), one of the plurality of LDD elements 316 may be disposed on the side of the first source / drain region 311 facing the doped region 312 and adjacent to the first source / drain region 311, and another of the plurality of LDD elements 316 may be disposed on the side of the doped region 312 facing the first source / drain region 311 and adjacent to the doped region 312.

[0059] Transistor 30 may include a spacer structure 361. The spacer structure 361 may be disposed on the sidewalls of gate structure 321, dummy gate structure 322, and dummy gate structure 323. The spacer structure 361 may comprise a single-layer structure (not shown) or a multi-layer structure (e.g., Figure 2 (As shown). The multilayer structure of the spacer structure 361 can be formed of different materials. The spacer structure 361 may contain an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0060] Transistor 30 may include contacts 331, 332, 333, 334, and 335, and conductive films 351, 353, 354, and 355. Conductive film 351 is disposed between contact 331 and a first source / drain region 311. Contact 331 is electrically connected to the first source / drain region 311 via conductive film 351. Conductive film 353 is disposed between contact 333 and a doped region 312. Contact 333 is electrically connected to the doped region 312 via conductive film 353. Conductive film 354 is disposed between contact 334 and a doped region 313. Contact 334 is electrically connected to the doped region 313 via conductive film 354. Conductive film 355 is disposed between contact 335 and a second source / drain region 314. Contact 335 is electrically connected to the second source / drain region 314 via conductive film 355. Contact plug 332 is disposed on and electrically connected to gate structure 321. Contact plugs 331, 332, 333, 334, and 335 may contain conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), or cobalt tungsten phosphide (CoWP). Conductive films 351, 353, 354, and 355 may contain metal silicides, such as titanium silicide (TiSi).

[0061] Transistor 30 may include outer doped layers 315 and 319. Outer doped layers 315 and 319 are disposed within fin structure 310. Outer doped layers 315 and 319 may be disposed above semiconductor substrate 300 in the Z direction. Outer doped layers 315 and 319 may be completely disposed within fin structure 310 without extending into semiconductor substrate 300. Outer doped layer 315 may be adjacent to the side of first source / drain region 311 opposite to gate structure 321. Outer doped layer 319 may be adjacent to the side of second source / drain region 314 opposite to gate structure 321. Outer doped layers 315 and 319 may contain either a first-type dopant or a second-type dopant. The lower surfaces of outer doped layers 315 and 319 may be higher than the lower surfaces of the first source / drain region 311 and the second source / drain region 314 in the Z direction.

[0062] In one embodiment, the gate structure 321, the dummy gate structure 322, and the dummy gate structure 323 may be formed simultaneously or in the same process step. In one embodiment, the LDD element 316, the doped layer 317, the doped layer 318, the outer doped layer 315, and the outer doped layer 319 may be formed simultaneously or in the same process step. In one embodiment, the LDD element 316, the doped layer 317, the doped layer 318, the outer doped layer 315, and the outer doped layer 319 may have the same or substantially the same height in the Z direction, and the height may be the distance from the upper surface to the lower surface of these elements in the Z direction. In one embodiment, the first source / drain region 311, the second source / drain region 314, the doped region 312, and the doped region 313 may be formed simultaneously or in the same process step. In one embodiment, the first source / drain region 311, the second source / drain region 314, the doped region 312, and the doped region 313 may have the same or substantially the same height in the Z direction, and the height may be the distance in the Z direction from the upper surface of these elements to the lower surface of these elements.

[0063] LDD element 316, doped layer 317, doped layer 318, outer doped layer 315, and outer doped layer 319 may contain dopants of the same conductivity type. First source / drain region 311, second source / drain region 314, doped region 312, and doped region 313 may contain dopants of the same conductivity type. Well region 342 and first source / drain region 311 may contain dopants of different conductivity types. In one embodiment, the first type dopant is an N-type dopant, and the second type dopant is a P-type dopant; LDD element 316, doped layer 317, doped layer 318, outer doped layer 315, and outer doped layer 319 contain the first type dopant and have a first doping concentration; the first source / drain region 311, the second source / drain region 314, the doped region 312, and the doped region 313 contain the first type dopant and have a second doping concentration, wherein the first doping concentration is less than the second doping concentration; well region 342 contains the second type dopant; and deep well region 343 contains the first type dopant. In one embodiment, the dopant can be implanted into the target element using doping technology or other suitable techniques. Doping techniques include, but are not limited to, high-temperature diffusion doping technology and ion implantation doping technology.

[0064] The dummy gate structure 322 may have a length 322L in the X direction. The dummy gate structure 323 may have a length 323L in the X direction. The lengths 322L and 323L may be less than or equal to 50 nanometers (nm), for example, less than or equal to 40 nm or less than or equal to 36 nm. When the length of the dummy gate structure in the X direction is greater than 50 nm, the doped layer below the dummy gate structure cannot extend continuously below the dummy gate structure. The doped layer below the dummy gate structure may be divided into two or more separate parts. The discontinuously extending doped layer cannot serve as a carrier channel, thus failing to improve the protection capability of the ESD / EOS protection device. The lengths 322L of the dummy gate structure 322 and 323L of the dummy gate structure 323 may be the same or different from each other.

[0065] The distance between the gate structure 321 and the contact plug 335 in the X direction can be expressed as distance DCG. Distance DCG can be the distance (in the X direction) between the sidewall of the gate structure 321 facing the second source / drain region 314 and the sidewall of the contact plug 335 facing the gate structure 321.

[0066] In one embodiment, the transistor includes two dummy gate structures disposed between the gate structure and the second source / drain region (as the drain region), each dummy gate structure having a length of 20 nm in the X direction, the gate structure having a length of 135 nm in the X direction, and a distance of 700 nm from the DCG. In another embodiment, the transistor includes three dummy gate structures disposed between the gate structure and the second source / drain region (as the drain region), each dummy gate structure having a length of 36 nm in the X direction, the gate structure having a length of 135 nm in the X direction, and a distance of 700 nm from the DCG.

[0067] The electrical performance of some embodiments of the ESD / EOS protection devices of the present invention and comparative examples of the ESD / EOS protection devices was evaluated using the human body model (HBM) test, transmission line pulse (TLP) test, and the IEC 61000-4-5 surge test as defined by the International Electrotechnical Commission (IEC). Relevant parameters are listed in Table 1 below, and the current-voltage (IV) characteristic curves measured by the TLP test are listed in Table 1. Figures 4A to 5B .exist Figures 4A to 5B In the diagram, solid square, solid circle, and solid triangle data points and the curves they form correspond to the Y-axis (TLP current) and the lower X-axis (TLP voltage), while hollow square, hollow circle, and hollow triangle data points and the curves they form correspond to the Y-axis (TLP current) and the upper X-axis (leakage current). HBM testing simulates discharge caused by a charged human body touching or approaching the device; test results are listed in the HBM column of Table 1 below. TLP testing generates adjustable, fast-rise-time pulse currents, applying a pulse current under different conditions to the device each time to obtain an IV point, continuously applying pulse currents under different conditions until the leakage current exceeds the specified value. IEC 61000-4-5 surge testing simulates surge voltage and current generated during lightning strikes or switching processes to evaluate the device's immunity to interference; test results are listed in the EOS column of Table 1 below. Examples 1 to 6 have... Figure 2 The structures shown are different, but the number of dummy gate structures, and / or the length of each dummy gate structure in the X direction, and / or the distance DCG in the X direction may vary in these embodiments. Embodiments 1 to 3 correspond to Figure 4A Examples 4 to 6 correspond to Figure 4B Comparative Examples 1 to 6 have similar characteristics Figure 2The structures shown are different, but they do not include a doped layer beneath the dummy gate structures, and the number of dummy gate structures, and / or the length of each dummy gate structure in the X direction, and / or the distance DCG in the X direction may vary in these comparative examples. Comparative Examples 1 to 3 correspond to Figure 5A Comparative Examples 4 to 6 correspond to Figure 5B In Examples 1 to 6 and Comparative Examples 1 to 6, m and n are integers or non-integers greater than zero. All m values ​​are the same, and all n values ​​are the same. Therefore, the distance DCG in Example 2 can be understood as 1.71 times the distance DCG in Example 1, and the length of the dummy gate structure in Examples 1 to 3 can be understood as 0.15 times the length of the dummy gate structure in Comparative Examples 4 to 6.

[0068] [Table 1]

[0069]

[0070]

[0071] Depend on Figures 4A to 5B As shown in Table 1, compared to Comparative Examples 1 to 6, Examples 1 to 6 have lower on-resistance (Ron) and higher secondary breakdown current (I). t2 This indicates that setting a dummy gate structure and its underlying doped layer in the transistor can improve the protection against ESD and EOS events. Furthermore, as shown in Table 1, increasing the distance from the DCG can improve the protection against EOS events.

[0072] Please refer to Figures 6A to 6C . Figure 6A The current-voltage (IV) characteristic curves of Examples 1, 4, Comparative Example 1, and Comparative Example 4, measured by TLP, are displayed in the same graph. Figures 6A to 6C In the diagram, the solid square, solid circle, solid triangle, and solid cross (×) data points and the curves they form correspond to the Y-axis (TLP current) and the lower X-axis (TLP voltage), while the hollow square, hollow circle, hollow triangle, and hollow cross (×) data points and the curves they form correspond to the Y-axis (TLP current) and the upper X-axis (leakage current). Figure 6B The current-voltage (IV) characteristic curves of Examples 2, 5, Comparative Example 2 and Comparative Example 5, measured by TLP, are displayed in the same graph. Figure 6C The current-voltage (IV) characteristic curves of Examples 3, 6, Comparative Example 3, and Comparative Example 6, measured by TLP, are displayed in the same graph. Figures 6A to 6CAs shown in Table 1, under the same distance from DCG, increasing the number of dummy gate structures can increase the voltage that can be withstood under HBM testing, which means that increasing the number of dummy gate structures can improve the protection capability against ESD events.

[0073] This invention provides an ESD / EOS protection device comprising at least one dummy gate structure disposed between a gate structure and a source / drain region, and at least one doped layer below the dummy gate structure. The doped layer extending continuously below the dummy gate structure can serve as a carrier channel, increasing the transistor's driving current and reducing on-resistance, thereby enhancing the ESD / EOS protection device's ability to protect against ESD and EOS events. Furthermore, the configuration of this invention can be integrated into existing fin-type field-effect transistor fabrication processes without the need for additional photomasks, offering advantages such as simplified fabrication and reduced costs.

[0074] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An ESD / EOS protection device, comprising: Fin-shaped structures, formed of semiconductor material and located above a semiconductor substrate; The first source / drain region is located in this fin structure; The second source / drain region is located in this fin structure; A gate structure is located above the fin structure and between the first source / drain region and the second source / drain region; The first dummy gate structure is located above the fin structure; The first doped region is located in the fin structure and between the first source / drain region and the second source / drain region; as well as A first doped layer is located below the first dummy gate structure and extends from the second source / drain region to the first doped region, wherein the lower surface of the first doped layer is higher than the lower surface of the first doped region.

2. The ESD / EOS protection device as claimed in claim 1, wherein the first doped layer is above the semiconductor substrate.

3. The ESD / EOS protection device as claimed in claim 1, wherein the first doped layer contains a first type of dopant and has a first doping concentration, the second source / drain region contains the first type of dopant and has a second doping concentration, and the first doping concentration is less than the second doping concentration.

4. The ESD / EOS protection device of claim 1 further includes an isolation element in the semiconductor substrate and on the side of the second source / drain region opposite to the first source / drain region.

5. The ESD / EOS protection device of claim 4 further includes a well region in the semiconductor substrate, wherein the isolation element is located in the well region.

6. The ESD / EOS protection device as claimed in claim 5, wherein the second source / drain region, the first source / drain region and the first doped region each contain a first type of dopant, and the well region contains a second type of dopant different from the first type of dopant.

7. The ESD / EOS protection device as claimed in claim 5, wherein the well region surrounds the first source / drain region, the second source / drain region, the first doped region, and the first doped layer.

8. The ESD / EOS protection device of claim 1, wherein the fin structure extends along a first direction, the first dummy gate structure extends along a second direction perpendicular to the first direction, and the length of the dummy gate structure along the first direction is less than 50 nm.

9. The ESD / EOS protection device of claim 8, wherein the length of the dummy gate structure along the first direction is less than 40 nm.

10. The ESD / EOS protection device as claimed in claim 1, further comprising: The second dummy gate structure is located above the fin structure; The second doped region is located within the fin structure; A second doped layer is located below the second dummy gate structure and extends from the first doped region to the second doped region. The first doped layer and the second doped layer are separate from each other.

11. The ESD / EOS protection device of claim 10, wherein the first doped layer and the second doped layer are located on opposite sides of the first doped region.

12. The ESD / EOS protection device of claim 10 further includes a well region in the semiconductor substrate, the well region surrounding the first doped layer, the first doped region, the second doped layer, and the second doped region.

13. The ESD / EOS protection device of claim 10, wherein the fin structure extends along a first direction, the first dummy gate structure extends along a second direction perpendicular to the first direction, and the length of the first dummy gate structure along the first direction and the length of the second dummy gate structure along the first direction are less than 50 nm.

14. The ESD / EOS protection device of claim 10 further comprises a plurality of LDD elements, the LDD elements being located on one side of the first source / drain region and on one side of the second doped region, the LDD elements being separated from each other.

15. An ESD / EOS protection device, comprising: Fin-like structures are formed of semiconductor material and are located on a semiconductor substrate; The first source / drain region is located in this fin structure; The second source / drain region is located in this fin structure; A gate structure is located on the fin structure and between the first source / drain region and the second source / drain region; A first dummy gate structure is present on the fin-shaped structure; The first doped region is located in the fin structure and between the first source / drain region and the second source / drain region; A first doped layer is located below the first dummy gate structure and extends from the second source / drain region to the first doped region; A second dummy gate structure is present on the fin-shaped structure; The second doped region is located within the fin structure; as well as A second doped layer is located below the second dummy gate structure and extends from the first doped region to the second doped region. The first doped layer and the second doped layer are separate from each other.

16. The ESD / EOS protection device of claim 15 further comprises a plurality of LDD elements, the LDD elements being respectively located on one side of the first source / drain region and on one side of the second doped region, the LDD elements being separated from each other, the side of the first source / drain region facing the side of the second doped region.

17. The ESD / EOS protection device of claim 16, wherein the first doped layer contains a first type dopant and has a first doping concentration, the second doped layer contains the first type dopant and has the first doping concentration, and the LDD elements respectively contain the first type dopant and have the first doping concentration.

18. The ESD / EOS protection device of claim 17, wherein the second source / drain region contains the first type dopant and has a second doping concentration, the first doping concentration being less than the second doping concentration.

19. The ESD / EOS protection device of claim 15, wherein the fin structure extends along a first direction, the first dummy gate structure extends along a second direction perpendicular to the first direction, and the length of the first dummy gate structure along the first direction is less than 50 nm.

20. The ESD / EOS protection device of claim 19, wherein the length of the first dummy gate structure along the first direction and the length of the second dummy gate structure along the first direction are less than 40 nm.

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