Photovoltaic cells and photovoltaic modules

Abstract

This application relates to a photovoltaic cell and a photovoltaic module, and pertains to the field of photovoltaic technology. The photovoltaic cell includes a silicon substrate and a doped conductive structure. The silicon substrate includes a first surface and a second surface disposed opposite to each other. Emitters are disposed at intervals within the first surface. The second surface includes a first recessed portion recessed into the silicon substrate and a main portion adjacent to the first recessed portion. The first recessed portion is adjacent to the edge of the silicon substrate, and the depth of the first recessed portion is 1 micrometer to 8 micrometers. The doped conductive structure includes a first portion and a second portion connected together. The first portion is disposed on the first recessed portion, and the second portion is disposed on the main portion. At least one of the first portion and the second portion includes a doped amorphous dielectric layer and a doped polycrystalline dielectric layer, with the doped amorphous dielectric layer located between the silicon substrate and the doped polycrystalline dielectric layer. The first portion disposed on the first recessed portion has relatively low stress concentration and relatively high passivation reliability, thus resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a photovoltaic cell and a photovoltaic module. Background Technology

[0002] Photovoltaic cells absorb energy from sunlight to generate photogenerated carriers (free electrons and holes). When connected to an external circuit, the photovoltaic cell outputs current to that circuit. In related technologies, the photoelectric conversion efficiency of photovoltaic cells needs further improvement. Summary of the Invention

[0003] This application provides a photovoltaic cell and a photovoltaic module, which improve the photoelectric conversion efficiency of the photovoltaic cell and the output power of the photovoltaic module.

[0004] This application provides a photovoltaic cell, which includes a silicon substrate and a doped conductive structure. The silicon substrate includes a first surface and a second surface disposed opposite to the first surface. Emitters are disposed in the first surface at intervals. The second surface includes a first recessed portion recessed into the silicon substrate and a main portion adjacent to the first recessed portion. The depth of the first recessed portion is 1 micrometer to 8 micrometers. The doped conductive structure includes a first portion and a second portion connected to each other. The first portion is disposed on the first recessed portion and the second portion is disposed on the main portion. At least one of the first portion and the second portion includes a doped amorphous dielectric layer and a doped polycrystalline dielectric layer. The doped amorphous dielectric layer is located between the silicon substrate and the doped polycrystalline dielectric layer. The silicon substrate includes a first edge and a second edge. The extension direction of the first edge intersects the extension direction of the second edge. The first recessed portion includes a third portion and a fourth portion. The third portion is adjacent to the first edge and the fourth portion is adjacent to the second edge.

[0005] Optionally, the silicon substrate includes a first edge and a second edge, the extension direction of the first edge intersects the extension direction of the second edge, and the first recess includes a third part and a fourth part, the third part being adjacent to the first edge and the fourth part being adjacent to the second edge.

[0006] Optionally, the third part includes a first bottom wall and a first side wall, the first edge is connected to the first bottom wall, the first bottom wall is connected to the first side wall, and the first side wall is connected to the main part; the fourth part includes a second bottom wall and a second side wall, the second edge is connected to the second bottom wall, the second bottom wall is connected to the second side wall, the second side wall is connected to the main part, and the first side wall and the second side wall are connected by a chamfered side wall.

[0007] Optionally, the silicon substrate further includes a third edge, the first edge and the third edge are connected by a second edge, the first edge and the third edge are disposed opposite to each other, and the first recess further includes a fifth part, the fifth part is adjacent to the third edge.

[0008] Optionally, the silicon substrate further includes a fourth edge, the first edge and the third edge are connected through the fourth edge, the second edge and the fourth edge are disposed opposite each other, and the first recess further includes a sixth part, the sixth part being adjacent to the fourth edge.

[0009] Optionally, the length of either the third or fifth part is greater than the length of either the fourth or sixth part, and the width of either the third or fifth part is less than the width of either the fourth or sixth part.

[0010] Optionally, the silicon substrate further includes a fourth edge, and the second surface further includes a second recessed portion recessed into the silicon substrate and adjacent to the main portion. The first edge and the third edge are connected through the fourth edge, the fourth edge is disposed opposite to the second edge, the second recessed portion is adjacent to the fourth edge, and the doped conductive structure is located outside the second recessed portion.

[0011] Optionally, the first part is spaced apart from the edge of the photovoltaic cell, and the distance between the first part and the edge of the photovoltaic cell is 0.5 mm to 1.5 mm.

[0012] Optionally, the width of the first recess in the direction parallel to the first surface is 5 mm to 35 mm.

[0013] Optionally, the doped amorphous dielectric layer includes doped silicon oxide, and the doped polycrystalline dielectric layer includes doped polycrystalline silicon.

[0014] This application provides a photovoltaic module, which includes a battery string, and the battery string includes at least two connected photovoltaic cells. The photovoltaic cells are those provided in this application as described above.

[0015] In this application, compared to the passivation layer disposed on the uneven coated structure, the stress concentration of the first part disposed on the first recess is relatively small. The risk of structural damage such as cracking or film bursting is relatively low, and the passivation effect of the first part is relatively reliable. Therefore, the minority carrier lifetime in the region near the first part within the silicon substrate is relatively long, resulting in a relatively large hole current in the edge region of the silicon substrate, thus leading to a relatively high photoelectric conversion efficiency of the photovoltaic cell. Because of the relatively high photoelectric conversion efficiency of the photovoltaic cell, the output power of the photovoltaic module is relatively high.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the three-dimensional structure of a silicon substrate in some embodiments; Figure 2 This is a cross-sectional view of a silicon substrate in some embodiments; Figure 3 This is a partial cross-sectional view of the silicon substrate and doped conductive structure in some embodiments. Figure 4 This is a partial cross-sectional view of a silicon substrate, a doped amorphous dielectric layer, and a doped polycrystalline dielectric layer in some embodiments; Figure 5 This is another partial cross-sectional view of the silicon substrate and doped conductive structure in some embodiments; Figure 6 for Figure 1 A top view of the silicon substrate in the image; Figure 7 This is a schematic diagram of the silicon substrate in some other embodiments; Figure 8 This is a partial structural diagram of a silicon substrate in some other embodiments; Figure 9 This is a schematic diagram of the silicon substrate in some other embodiments; Figure 10 This is a partial structural diagram of a silicon substrate in some other embodiments; Figure 11 This is a partial cross-sectional view of the photovoltaic cell provided in this application in some embodiments.

[0019] Explanation of reference numerals in the attached drawings: 10-Photovoltaic cell, 1-Silicon substrate, 1a-First surface, 1b-Second surface, 11-Base region, 12-Emitter, 13-First recess, 131-Third part, 1311-First bottom wall, 1312-First side wall, 132-Fourth part, 1321-Second bottom wall, 1322-Second side wall, 133-Fifth part, 134-Sixth part, 135-Chamfered side wall, 14-Edge, 141-First edge, 142-Second edge, 1 43-Third edge, 144-Fourth edge, 15-Second recess, 151-Seventh part, 152-Eighth part, 153-Ninth part, 17-Main part, 2-Doped conductive structure, 2a-Doped amorphous dielectric layer, 2b-Doped polycrystalline dielectric layer, 21-First part, 22-Second part, 3-First passivation layer, 4-Second passivation layer, 41-Thirteenth part, 42-Fourteenth part, 5-First gate electrode, 6-Second gate electrode, 61-Fifteenth part, 62-Sixteenth part. Detailed Implementation

[0020] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments described in this application. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without inventive effort are within the scope of protection of this application.

[0022] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. The term “and / or” as used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone.

[0023] It should be understood that the feature prefixes in this article, such as ordinal numbers like "first", "second", "third", "fourth", "fifth" and "sixth", are used to avoid confusion between different features and do not necessarily limit the features in terms of quantity.

[0024] It should be understood that, for clarity, the proportions of layers, films, regions, and other structures in the accompanying figures may not be proportions of the actual structures.

[0025] It should be understood that when it is mentioned that feature a (e.g., layer, membrane, region) is "set on" or "located on" feature b (e.g., layer, membrane, region, substrate, wall, surface), feature a may be directly set on or located on feature b, or there may be other features c between feature a and feature b. Conversely, when it is mentioned that feature a is "directly located on" or "directly set on" feature b, it means that there are no other features between feature a and feature b.

[0026] It should be understood that the meaning of electrical connection can include: after two structures with conductive properties are physically connected, under the action of an electric field, one of the two physically connected structures with conductive properties can conduct electricity to the other. The physical connection used for conduction can be a direct connection or an indirect connection through other conductive media.

[0027] It should be understood that in the accompanying drawings, every two of the first direction X, the second direction Y, and the third direction Z are perpendicular to each other; the fourth direction U is the reverse of the first direction X; the fifth direction V is the reverse of the second direction Y; and the sixth direction W is the reverse of the third direction Z. The first direction X is parallel to the thickness direction of the photovoltaic cell.

[0028] This application provides some embodiments of photovoltaic cells, relating to the field of photovoltaic technology. Please refer to... Figures 1 to 3 As shown, the photovoltaic cell includes a silicon substrate 1, which includes a first surface 1a and a second surface 1b disposed opposite to each other. The first surface 1a is used to be directly or primarily irradiated by sunlight, and is therefore considered the light-facing surface of the silicon substrate 1. When sunlight irradiates the first surface 1a, the silicon substrate 1 absorbs the energy of the sunlight to generate electron-hole pairs.

[0029] In some embodiments, please refer to Figure 3 As shown, the silicon substrate 1 includes a base region 11 and an emitter 12. The base region 11 may be doped with at least one N-type element (a group 5 element of the periodic table), such as phosphorus, arsenic, antimony, etc. The emitter 12 may be doped with at least one P-type element (a group 3 element of the periodic table), such as boron, aluminum, gallium, etc. Therefore, a PN junction exists between the base region 11 and the emitter 12. Under the influence of the built-in electric field of the PN junction, electron-hole pairs separate, with holes moving into the emitter 12 and free electrons moving into the base region 11.

[0030] In some embodiments, the emitters 12 are spaced apart within the first surface 1a. From another perspective, the emitters 12 are local regions extending a certain depth from the first surface 1a into the silicon substrate 1, and there is a spacing between at least two emitters 12.

[0031] In some embodiments, please refer to Figures 3 to 4 As shown, the photovoltaic cell also includes a doped conductive structure 2, located on the side of the base region 11 away from the emitter 12. The doped conductive structure 2 includes a doped amorphous dielectric layer 2a and a doped polycrystalline dielectric layer 2b. The doped amorphous dielectric layer 2a is located between the silicon substrate 1 and the doped polycrystalline dielectric layer 2b. The doped amorphous dielectric layer 2a acts as a dangling bond on the surface of the saturated base region 11 to reduce the number of recombination centers; that is, the doped amorphous dielectric layer 2a acts as a chemical passivation layer. Both the doped amorphous dielectric layer 2a and the doped polycrystalline dielectric layer 2b are doped with at least one N-type element. The activation doping concentration of the N-type element in the doped polycrystalline dielectric layer 2b is greater than that in the base region 11. A high / low junction (N / N) exists between the base region 11 and the doped polycrystalline dielectric layer 2b. + Under the influence of the built-in electric field of the high-low junction, free electrons in the base region 11 move through the doped amorphous dielectric layer 2a to the doped polycrystalline dielectric layer 2b, while holes in the base region 11 move away from the interface between the base region 11 and the doped amorphous dielectric layer 2a. Thus, the doped polycrystalline dielectric layer 2b acts as a field passivation layer. Therefore, the doped conductive structure 2 increases the lifetime of holes as minority carriers, thereby improving the photoelectric conversion efficiency of the photovoltaic cell.

[0032] In some embodiments, the photovoltaic cell further includes a first grid electrode and a second grid electrode. The first grid electrode is electrically connected to the emitter 12, and the second grid electrode is electrically connected to the doped polycrystalline dielectric layer 2b. When the first grid electrode and the second grid electrode are electrically connected to an external circuit, the photovoltaic cell outputs current to the outside. The first grid electrode is considered the positive electrode, and the second grid electrode is considered the negative electrode.

[0033] In some embodiments, please refer to Figures 2 to 3 As shown, the second surface 1b includes a first recess 13 and a main portion 17 adjacent to the first recess 13. The main portion 17 is considered the main part of the second surface 1b. The first recess 13 is recessed into the silicon substrate 1 relative to the main portion 17, and the first recess 13 is adjacent to the edge 14 of the silicon substrate 1. The depth S of the first recess is from 1 micrometer (μm) to 8 micrometers (μm). For the silicon substrate 1, the first recess 13 is a structure formed after etching the uneven winding structure near the edge 14 during the fabrication of photovoltaic cells. Compared with the passivation layer provided on the uneven winding structure, the stress concentration of the passivation layer provided on the first recess 13 is relatively small, and the risk of structural damage such as cracking and film bursting of the passivation layer provided on the first recess 13 is relatively small.

[0034] In some embodiments, please refer to Figure 3As shown, the doped conductive structure 2 includes a first part 21 and a second part 22. The first part 21 is disposed on the first recess 13, and the second part 22 is disposed on the main part 17. Both the first part 21 and the second part 22 may include a doped amorphous dielectric layer 2a and a doped polycrystalline dielectric layer 2b. From another perspective, both the first part 21 and the second part 22 are layer structures with passivation effects. As can be seen from the above, the stress concentration of the first part 21 disposed on the first recess 13 is relatively small, the risk of structural damage such as cracking or film bursting of the first part 21 is relatively low, and the reliability of the passivation effect of the first part 21 is relatively high. Therefore, the minority carrier lifetime in the region near the first part 21 within the silicon substrate 1 is relatively large, resulting in a relatively large hole current in the region near the edge 14 of the silicon substrate 1, thus leading to a relatively high photoelectric conversion efficiency of the photovoltaic cell.

[0035] In some embodiments, other passivating layer structures (not shown in the figure) may also be provided on the first recess 13, such as at least one of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The stress concentration of the passivation layer provided on the first recess 13 is relatively small, and the possibility of structural damage problems such as cracking and thin film is relatively small. Therefore, the photoelectric conversion efficiency of the photovoltaic cell is relatively large.

[0036] In some embodiments, the first part 21 is connected to the second grid electrode, which can be understood from another perspective as the second grid electrode being disposed on the first recess 13. Compared to the second grid electrode disposed on the uneven coated structure, the stress concentration of the second grid electrode disposed on the first recess 13 is relatively small, and the possibility of grid breakage is relatively small, thus the photoelectric conversion efficiency of the photovoltaic cell is relatively large.

[0037] In some embodiments, please refer to Figure 3 As shown, the depth S of the first recess 13 is from 1 μm to 8 μm, wherein the depth S of the first recess 13 can specifically be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm. Furthermore, the depth S is the dimension in the first direction X.

[0038] In some embodiments, please refer to Figure 3 As shown, the depth S of the first recess 13 can also be 2μm to 4μm, wherein the depth S of the first recess 13 can specifically be 2μm, 2.5μm, 3μm, 3.5μm or 4μm.

[0039] In some embodiments, please refer to Figure 3 As shown, the depth S of the first recess 13 can also be 5μm to 7μm, wherein the depth S of the first recess 13 can specifically be 5μm, 5.5μm, 6μm, 6.5μm or 7μm.

[0040] In some embodiments, please refer to Figure 4 As shown, the doped amorphous dielectric layer 2a may include doped silicon oxide, in which at least one N-type element is doped.

[0041] In some embodiments, the thickness of the doped amorphous dielectric layer 2a can be from 1 nm to 2 nm. The doped amorphous dielectric layer 2a has a quantum tunneling effect, and free electrons in the base region 11 can pass through the doped amorphous dielectric layer 2a and move into the doped polycrystalline dielectric layer 2b.

[0042] In some embodiments, please refer to Figure 4 As shown, the doped amorphous dielectric layer 2a may also include doped silicon nitride, in which at least one N-type element is doped.

[0043] In some embodiments, please refer to Figure 4 As shown, the doped amorphous dielectric layer 2a may also include doped alumina, in which at least one N-type element is doped.

[0044] In some embodiments, please refer to Figure 4 As shown, the doped polycrystalline dielectric layer 2b may include doped polycrystalline silicon, in which at least one N-type element is doped.

[0045] In some embodiments, please refer to Figure 4 As shown, the doped polycrystalline dielectric layer 2b may include polycrystalline silicon germanium, which is doped with at least one N-type element.

[0046] In some embodiments, please refer to Figure 4 As shown, the doped polycrystalline dielectric layer 2b may include polycrystalline silicon carbide, which is doped with at least one N-type element.

[0047] In some embodiments (not shown in the figures), one of the first part and the second part may include a stacked doped amorphous dielectric layer and a doped polycrystalline dielectric layer, while the other part may include a stacked amorphous dielectric layer and a doped polycrystalline dielectric layer, wherein the doped amorphous dielectric layer is located between the silicon substrate and the doped polycrystalline dielectric layer, and the amorphous dielectric layer is located between the silicon substrate and the doped polycrystalline dielectric layer. The amorphous dielectric layer may include silicon oxide, aluminum oxide, or silicon nitride.

[0048] In some embodiments, please refer to Figure 3 As shown, the width K of the first recess 13 can be from 5 mm to 35 mm to ensure that there are no or almost no uneven plating structures around the silicon substrate 1. The width K is a dimension in a direction parallel to the main portion 17 or the first surface 1a.

[0049] In some embodiments, when the width K of the first recess 13 is 5mm to 35mm, the width K can specifically be 5mm, 10mm, 15mm, 20mm, 25mm, 30mm or 35mm.

[0050] In some embodiments, please refer to Figure 3 As shown, the width K of the first recess 13 can also be 10mm to 20mm. Specifically, the width K can be 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm or 20mm.

[0051] In some embodiments, please refer to Figure 3 As shown, the width K of the first recess 13 can also be 20mm to 30mm. Specifically, the width K can be 20mm, 21mm, 22mm, 23mm, 24mm, 25mm, 26mm, 27mm, 28mm, 29mm or 30mm.

[0052] In some embodiments, please refer to Figure 5 As shown, although a first part 21 is provided on the first recess 13 adjacent to the edge 14, there is a gap G between the first part 21 and the edge 14, wherein the gap G is 0.5mm to 1.5mm, so as to isolate the first part 21 from the edge 14, reduce the leakage current in the area near the edge 14, and thus make the photoelectric conversion efficiency of the photovoltaic cell relatively large.

[0053] In some embodiments, please refer to Figure 5 As shown, when the interval distance G is between 0.5mm and 1.5mm, the interval distance G can specifically be 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm or 1.5mm.

[0054] In some embodiments, please refer to Figure 5 As shown, the interval distance G can also be 0.5mm to 1mm. Specifically, the interval distance G can be 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm or 1mm.

[0055] In some embodiments, please refer to Figure 5 As shown, the interval distance G can also be 1mm to 1.5mm. Specifically, the interval distance G can be 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm or 1.5mm.

[0056] In some embodiments, Figure 3The structure shown can be the structure viewed from the first cross-sectional plane of the photovoltaic cell. The first cross-sectional plane is a virtual reference plane that is parallel to the first direction X and the second direction Y and perpendicular to the third direction Z.

[0057] In some embodiments, Figure 5 The structure shown can be a structure viewed from the second cross-sectional plane of a photovoltaic cell. The second cross-sectional plane is also a virtual reference plane. The second cross-sectional plane is parallel to the first direction X and the second direction Y and perpendicular to the third direction Z. The first cross-sectional plane and the second cross-sectional plane are parallel and there is a gap between the first cross-sectional plane and the second cross-sectional plane.

[0058] In some embodiments, the first gate electrode may include a first main gate electrode and a first sub-gate electrode, with the same first main gate electrode and multiple first sub-gate electrodes connected together. Figure 3 Each emitter 12 shown is connected to the corresponding first main gate electrode. Figure 5 The emitter 12 shown is connected to the first sub-gate electrode.

[0059] In some embodiments, the second gate electrode may include a second main gate electrode and a second sub-gate electrode, with the same second main gate electrode and multiple second sub-gate electrodes connected together. Figure 3 The first part 21 and the second part 22 shown are each connected to the corresponding second main gate electrode. Figure 5 The first part 21 and the second part 22 shown are connected to the same second sub-gate electrode.

[0060] In some embodiments, please refer to Figure 6 As shown, the silicon substrate 1 includes a first edge 141, a second edge 142, a third edge 143, and a fourth edge 144. The extension direction of the first edge 141 (e.g., the second direction Y) intersects the extension direction of the second edge 142 (e.g., the third direction Z). The extension direction of the second edge 142 intersects the extension direction of the third edge 143 (e.g., the second direction Y). The extension direction of the third edge 143 intersects the extension direction of the fourth edge 144 (e.g., the third direction Z). The fourth edge 144 intersects the first edge 141. The first edge 141 and the third edge 143 are disposed opposite to each other, and the second edge 142 and the fourth edge 144 are disposed opposite to each other. The first edge 141 is connected to the second edge 142, the second edge 142 is connected to the third edge 143, the third edge 143 is connected to the fourth edge 144, and the fourth edge 144 is connected to the first edge 141. From another perspective, one end of the first edge 141 is connected to one end of the third edge 143 through the second edge 142, and the other end of the first edge 141 is connected to the other end of the third edge 143 through the fourth edge 144. The second edge 142 and the fourth edge 144 are located between the first edge 141 and the third edge 143.

[0061] In some embodiments, the first edge 141 and the second edge 142 may be connected by a first chamfered edge.

[0062] In some embodiments, the second edge 142 and the third edge 143 may be connected by a second conductive edge.

[0063] In some embodiments, the third edge 143 and the fourth edge 144 may be connected by a third chamfered edge.

[0064] In some embodiments, the fourth edge 144 and the first edge 141 can be connected by a fourth chamfered edge.

[0065] In some embodiments, when the photovoltaic cell is a single, continuous cell, please refer to... Figure 6 As shown, a first recess 13 can be formed around the silicon substrate 1. The first recess 13 includes a third part 131, a fourth part 132, a fifth part 133, and a sixth part 134. The third part 131 is adjacent to the first edge 141, the fourth part 132 is adjacent to the second edge 142, the fifth part 133 is adjacent to the third edge 143, and the sixth part 134 is adjacent to the fourth edge 144. For the entire cell, the silicon substrate 1 has little or no uneven coating structure around its perimeter, thus resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell. The specific technical effects have been described above and will not be repeated here.

[0066] In some embodiments, Figure 6 The third part 131, the fourth part 132, the fifth part 133 and the sixth part 134 shown can all be equipped with the first part 21.

[0067] In some embodiments, please refer to Figure 6 As shown, when the silicon substrate 1 is a rectangular or approximately rectangular sheet, the length of either the first edge 141 or the third edge 143 is greater than the length of either the second edge 142 or the fourth edge 144. During the fabrication of the photovoltaic cell, the width of the wrap-around structure near the relatively shorter edge is relatively large. After removing the wrap-around structure to form the first recess 13, the length of either the third portion 131 or the fifth portion 133 is greater than the length of either the fourth portion 132 or the sixth portion 134, and the width of either the third portion 131 or the fifth portion 133 is less than the width of either the fourth portion 132 or the sixth portion 134, to ensure that there are no or almost no uneven wrap-around structures around the silicon substrate 1.

[0068] In some embodiments, when the photovoltaic cell is a segmented cell, for example, four segments are formed by cutting a whole cell along a cross-cut line, please refer to... Figure 7As shown, the silicon substrate 1 includes a first edge 141 and a second edge 142. The extending direction of the first edge 141 intersects the extending direction of the second edge 142. The first recess 13 includes a third part 131 and a fourth part 132. The third part 131 is adjacent to the first edge 141, and the fourth part 132 is adjacent to the second edge 142. For sectional solar cells, the silicon substrate 1 has little or no uneven coating structure around its perimeter, thus resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cells.

[0069] In some embodiments, Figure 7 Both the third part 131 and the fourth part 132 shown can be equipped with the first part 21.

[0070] In some embodiments, please refer to Figure 7 As shown, the third edge 143 and the fourth edge 144 serve as the cutting edges of the silicon substrate 1 of the sectional cell.

[0071] In some embodiments, please refer to Figure 8 As shown, the third part 131 includes a first bottom wall 1311 and a first side wall 1312. The first edge 141 is connected to the first bottom wall 1311, the first bottom wall 1311 is connected to the first side wall 1312, and the first side wall 1312 is connected to the main part 17. The fourth part 132 includes a second bottom wall 1321 and a second side wall 1322. The second edge 142 is connected to the second bottom wall 1321, the second bottom wall 1321 is connected to the second side wall 1322, and the second side wall 1322 is connected to the main part 17. The first side wall 1312 and the second side wall 1322 are connected by a chamfered side wall 135. The stress concentration of the chamfered side wall 135 is relatively small, the possibility of structural damage problems such as microcracks in the chamfered side wall 135 is relatively small, and the number of composite centers in the vicinity of the chamfered side wall 135 is relatively small.

[0072] In some embodiments, please refer to Figure 8 As shown, a first part 21 is provided on both the first bottom wall 1311 and the second bottom wall 1321.

[0073] In some embodiments, the chamfered sidewall can be a right-angled chamfered sidewall, which has the advantage of relatively low stress concentration. The right-angled chamfered sidewall can be referred to as a C-chamfer or a beveled chamfer.

[0074] In some embodiments, the chamfered sidewall can be a rounded corner sidewall, which has the advantage of less stress concentration. The rounded corner sidewall can be referred to as an R-chamfer or a fillet.

[0075] In some embodiments, whether it is a whole battery or a segmented battery, if the first recess 13 comprises two parts and the extending directions of the two parts intersect, the sidewalls of the two parts can be connected by chamfered sidewalls.

[0076] In some embodiments, when the photovoltaic cell is a two-piece cell, for example, it is formed by cutting a whole cell along a cutting line to create two separate cells. Please refer to... Figure 9 As shown, the first recessed portion 13 includes a third portion 131, a fourth portion 132, and a fifth portion 133. The third portion 131 is adjacent to the first edge 141, the fourth portion 132 is adjacent to the second edge 142, and the fifth portion 133 is adjacent to the third edge 143. For sectional solar cells, the silicon substrate 1 has little or no uneven coating structure around its perimeter, thus resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell.

[0077] In some embodiments, Figure 9 The third part 131, the fourth part 132 and the fifth part 133 shown can all be equipped with the first part 21.

[0078] In some embodiments, Figure 9 The silicon substrate 1 shown can also be a structure formed by cutting into three or four pieces.

[0079] In some embodiments, please refer to Figure 9 As shown, the second surface 1b may further include a second recess 15, which is adjacent to the main portion 17. The second recess 15 is recessed into the silicon substrate 1 relative to the main portion 17. The second recess 15 is adjacent to a fourth edge 144, which serves as a cutting edge. A doped conductive structure 2 is located outside the second recess 15. The second recess 15 isolates the fourth edge 144 and the doped conductive structure 2, so that the leakage current in the region near the fourth edge 144 is relatively small, and therefore the photoelectric conversion efficiency of the photovoltaic cell is relatively large.

[0080] In some embodiments, the width of the second recess 15 is smaller than the width of the first recess 13, and the widths of the first recess 13 and the second recess 15 are both dimensions in a direction parallel to the main portion 17 or the first surface 1a.

[0081] In some embodiments, please refer to Figure 9 As shown, the width of the second recess 15 in the third direction Z is less than the width of the third part 131 in the second direction Y, the width of the second recess 15 in the third direction Z is less than the width of the fourth part 132 in the third direction Z, and the width of the second recess 15 in the third direction Z is less than the width of the fifth part 133 in the second direction Y.

[0082] In some embodiments, the width of the second recess 15 can be in the range of 50 μm to 500 μm. Specifically, the width of the second recess 15 can be 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm.

[0083] In some embodiments, the width of the second recess 15 may also be 100μm to 200μm. Specifically, the width of the second recess 15 may be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, or 200μm.

[0084] In some embodiments, the width of the second recess 15 may also be 200 μm to 300 μm. Specifically, the width of the second recess 15 may be 200 μm, 210 μm, 220 μm, 230 μm, 240 μm, 250 μm, 260 μm, 270 μm, 280 μm, 290 μm, or 300 μm.

[0085] In some embodiments, please refer to Figures 9 to 10 As shown, the second recessed portion 15 may include a seventh portion 151, an eighth portion 152, and a ninth portion 153. The seventh portion 151 is connected to the third portion 131 and is recessed into the silicon substrate 1 relative to the third portion 131. The eighth portion 152 is recessed into the silicon substrate 1 relative to the main portion 17. The ninth portion 153 is connected to the fifth portion 133 and is recessed into the silicon substrate 1 relative to the fifth portion 133. The seventh portion 151 can isolate the fourth edge 144 from the first portion 21 disposed on the third portion 131. The eighth portion 152 can isolate the fourth edge 144 from the second portion 22 disposed on the main portion 17. The ninth portion 153 can isolate the fourth edge 144 from the first portion 21 disposed on the fifth portion 133, so that the leakage current in the region near the fourth edge 144 is relatively small, and therefore the photoelectric conversion efficiency of the photovoltaic cell is relatively large.

[0086] In some embodiments, the cross-sectional structure of the photovoltaic cell 10 can be as follows: Figure 11 As shown, a first passivation layer 3 is provided on the first surface 1a, a thirteenth part 41 of a second passivation layer 4 is provided on the first recess 13, and a fourteenth part 42 of the second passivation layer 4 is provided on the main part 17. The first passivation layer 3 may include at least one of an aluminum oxide layer and a silicon nitride layer, and the second passivation layer 4 may include at least one of an aluminum oxide layer and a silicon nitride layer.

[0087] In some embodiments, please refer to Figure 11As shown, the emitter 12 is connected to the first gate electrode 5, the first part 21 is connected to the fifteenth part 61 of the second gate electrode 6, and the second part 22 is connected to the sixteenth part 62 of the second gate electrode 6.

[0088] In some embodiments, Figure 11 The photovoltaic cell 10 shown can be a tunnel oxide passivated contact (TOPCon) photovoltaic cell.

[0089] In some embodiments, the silicon substrate 1 may include a plurality of pyramidal or conical structures with micron-sized dimensions on the first surface 1a. Alternatively, the first surface 1a may be understood as having a textured surface. Therefore, the first surface 1a has an anti-reflective effect.

[0090] In some embodiments, the silicon substrate 1 may include a plurality of micron-sized pyramidal or conical structures on the second surface 1b; conversely, the second surface 1b may be understood as having a textured surface. Therefore, the second surface 1b has an anti-reflective effect.

[0091] In some embodiments, the silicon substrate 1 may include a plurality of pyramidal or conical structures with micron-sized dimensions in the first recess 13. Alternatively, the first recess 13 may be understood as having a textured surface. Therefore, the first recess 13 has an anti-reflective effect.

[0092] In some embodiments, when pyramids exist in both the first recess 13 and the main portion 17, the depth S of the first recess 13 is measured from the bottom of the pyramid in the first recess 13 to the bottom of the pyramid in the main portion 17, wherein the depth S is a dimension parallel to the first direction X.

[0093] In some embodiments, the height of the pyramid can be from 1.5 micrometers to 5 micrometers.

[0094] This application provides some embodiments of photovoltaic modules, which include a battery string comprising at least two electrically connected photovoltaic cells, wherein the photovoltaic cells can be those described in the above embodiments. Because photovoltaic cells have relatively high photoelectric conversion efficiency, the output power of the photovoltaic module is relatively high.

[0095] In some embodiments, the photovoltaic module further includes an encapsulating film that encapsulates the cell string.

[0096] In some embodiments, the photovoltaic module further includes a first cover plate and a second cover plate, with the cell string and encapsulating film located between the first cover plate and the second cover plate. The first cover plate is located on the light-facing side of the cell string and has high light transmittance.

[0097] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application, or the scope of this application should be defined by the appended claims.

Claims

1. A photovoltaic cell, characterized in that, The photovoltaic cell includes: A silicon substrate includes a first surface and a second surface disposed opposite to the first surface. Emitters are disposed in the first surface at intervals. The second surface includes a first recessed portion recessed into the silicon substrate and a main portion adjacent to the first recessed portion. The depth of the first recessed portion is 1 micrometer to 8 micrometers. A doped conductive structure includes a first part and a second part connected to each other. The first part is disposed on the first recessed part, and the second part is disposed on the main part. At least one of the first part and the second part includes a doped amorphous dielectric layer and a doped polycrystalline dielectric layer. The doped amorphous dielectric layer is located between the silicon substrate and the doped polycrystalline dielectric layer. The silicon substrate includes a first edge and a second edge, the extension direction of the first edge intersects the extension direction of the second edge, and the first recess includes a third part and a fourth part, the third part being adjacent to the first edge and the fourth part being adjacent to the second edge.

2. The photovoltaic cell according to claim 1, characterized in that, The third part includes a first bottom wall and a first side wall. The first edge is connected to the first bottom wall, the first bottom wall is connected to the first side wall, and the first side wall is connected to the main part. The fourth part includes a second bottom wall and a second side wall. The second edge is connected to the second bottom wall, the second bottom wall is connected to the second side wall, and the second side wall is connected to the main part. The first side wall and the second side wall are connected by a chamfered side wall.

3. The photovoltaic cell according to claim 1, characterized in that, The silicon substrate further includes a third edge, the first edge and the third edge are connected by a second edge, the first edge and the third edge are disposed opposite to each other, and the first recess further includes a fifth part, the fifth part being adjacent to the third edge.

4. The photovoltaic cell according to claim 3, characterized in that, The silicon substrate further includes a fourth edge, the first edge and the third edge are connected through the fourth edge, the second edge is disposed opposite to the fourth edge, and the first recess further includes a sixth part, the sixth part being adjacent to the fourth edge.

5. The photovoltaic cell according to claim 4, characterized in that, The length of either the third part or the fifth part is greater than the length of either the fourth part or the sixth part, and the width of either the third part or the fifth part is less than the width of either the fourth part or the sixth part.

6. The photovoltaic cell according to claim 3, characterized in that, The silicon substrate further includes a fourth edge, and the second surface further includes a second recessed portion that is recessed into the silicon substrate and adjacent to the main portion. The first edge and the third edge are connected through the fourth edge. The fourth edge is disposed opposite to the second edge. The second recessed portion is adjacent to the fourth edge. The doped conductive structure is located outside the second recessed portion.

7. The photovoltaic cell according to claim 6, characterized in that, The silicon substrate includes a first edge and a third edge disposed opposite to each other, and the second surface includes two first recesses, one of which is adjacent to the first edge and the other of which is adjacent to the third edge.

8. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The width of the first recess in the direction parallel to the first surface is 5 mm to 35 mm.

9. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The doped amorphous dielectric layer includes doped silicon oxide, and the doped polycrystalline dielectric layer includes doped polycrystalline silicon.

10. A photovoltaic module, characterized in that, The photovoltaic module includes a battery string, the battery string including at least two connected photovoltaic cells, the photovoltaic cells being the photovoltaic cells according to any one of claims 1 to 9.

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