Back contact heterojunction solar cell and method of manufacturing the same

Abstract

This invention discloses a back-contact heterojunction solar cell and its fabrication method. The back-contact heterojunction solar cell may include: a crystalline silicon substrate, with alternating first and second conductive regions on the back side; an n-type carrier collection layer disposed in the first conductive region, the n-type carrier collection layer including electrode contact regions and non-electrode contact regions; a p-type carrier collection layer disposed in the second conductive region; a metal silicide transition layer disposed at least outside the electrode contact regions of the n-type carrier collection layer, and the metal silicide transition layer is not disposed outside the p-type carrier collection layer; and a transparent conductive film layer disposed in the first conductive region, the transparent conductive film layer being located outside the metal silicide transition layer and in contact with the metal silicide transition layer, which can effectively reduce the contact resistance of the back-contact heterojunction solar cell.

Description

Technical Field

[0001] This invention relates to a back-contact heterojunction solar cell and its fabrication method. Background Technology

[0002] A back-contact heterojunction solar cell (HBC) is a high-efficiency crystalline silicon solar cell that combines heterojunction technology with a back-contact structure. For example, the back side of an n-type crystalline silicon substrate includes n-type and p-type functional regions. A tunneling passivation layer and an n-type doped polycrystalline silicon layer are disposed in the n-type functional region, while an intrinsic amorphous silicon film and a p-type doped silicon-containing film are disposed in the p-type functional region. Transparent conductive films are disposed on the outer sides of the n-type doped polycrystalline silicon layer in the n-type functional region and the p-type doped silicon-containing film in the p-type functional region, respectively. However, there is an energy level difference between the n-type doped polycrystalline silicon layer and the p-type doped silicon-containing film. A transparent conductive film with the same work function cannot be simultaneously matched to both the n-type doped polycrystalline silicon layer and the p-type doped silicon-containing film. This results in a high contact resistance for HBCs using the same transparent conductive film in both the n-type and p-type functional regions. Therefore, the structure of existing HBCs still needs improvement. Summary of the Invention

[0003] In view of this, the present invention provides a back-contact heterojunction solar cell and a method for fabricating the same. The back-contact heterojunction solar cell uses a metal silicide transition layer disposed at least outside the electrode contact region of the n-type carrier collection layer as a bridge between the n-type carrier collection layer and the transparent conductive film layer. The metal silicide transition layer can form a low potential barrier and a low interfacial contact resistance with the n-type carrier collection layer. Furthermore, the work function of the metal silicide transition layer matches the work function of the transparent conductive film layer, which can effectively reduce the electron injection barrier and the interfacial contact resistance, thereby reducing the contact resistance of the back-contact heterojunction solar cell.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a back-contact heterojunction solar cell, comprising: A crystalline silicon substrate, the back side of which includes alternating first and second conductive regions; An n-type carrier collection layer is disposed in the first conductive region, and the n-type carrier collection layer includes an electrode contact region and a non-electrode contact region; A p-type carrier collection layer is disposed in the second conductive region; A metal silicide transition layer is provided at least outside the electrode contact region of the n-type carrier collection layer, and the metal silicide transition layer is not provided outside the p-type carrier collection layer. A transparent conductive film layer is disposed in the first conductive region, located outside the metal silicide transition layer, and in contact with the metal silicide transition layer.

[0005] Secondly, embodiments of the present invention provide a method for fabricating a back-contact heterojunction solar cell, comprising: Step S1: Provide a crystalline silicon substrate, wherein the back side of the crystalline silicon substrate includes alternating first and second conductive regions; Step S2: An n-type carrier collection layer is formed in the first conductive region and a p-type carrier collection layer is formed in the second conductive region, wherein the n-type carrier collection layer includes an electrode contact region and a non-electrode contact region; a metal silicide transition layer is formed at least in the electrode contact region, and the metal silicide transition layer is not formed on the outside of the p-type carrier collection layer. Step S3: A transparent conductive film layer is formed in the first conductive region. The transparent conductive film layer is located outside the metal silicide transition layer and is in contact with the metal silicide transition layer.

[0006] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: The back-contact heterojunction solar cell provided in this embodiment of the invention is a novel back-contact heterojunction solar cell structure. It features a metal silicide transition layer disposed on the outer side of the n-type carrier collection layer in the first conductive region, at least corresponding to the electrode contact region. This metal silicide transition layer forms a low potential barrier and a low interfacial contact resistance with the n-type carrier collection layer. Simultaneously, the work function of the metal silicide transition layer matches the work function of the transparent conductive film layer, effectively reducing the electron injection barrier and interfacial contact resistance between the metal silicide transition layer and the transparent conductive film layer. Therefore, the metal silicide transition layer acts as a bridge between the n-type carrier collection layer and the transparent conductive film layer, effectively reducing the electron injection barrier and interfacial contact resistance in the first conductive region, thereby reducing the contact resistance of the back-contact heterojunction solar cell, facilitating electron carrier transport, and improving the photoelectric conversion efficiency and fill factor of the back-contact heterojunction solar cell. Attached Figure Description

[0007] Figure 1 This is a partial cross-sectional structural diagram of the first type of back-contact heterojunction solar cell provided in this embodiment of the invention; Figure 2 This is a partial cross-sectional structural diagram of the second type of back-contact heterojunction solar cell provided in this embodiment of the invention; Figure 3 This is a partial cross-sectional structural diagram of the third type of back-contact heterojunction solar cell provided in this embodiment of the invention; Figure 4This is a partial cross-sectional structural diagram of the fourth type of back-contact heterojunction solar cell provided in this embodiment of the invention; Figure 5 This is a schematic diagram of the main process of a method for fabricating a back-contact heterojunction solar cell according to an embodiment of the present invention; Figure 6 This is a schematic cross-sectional view of the partial structural changes corresponding to steps S21 to S26 according to an embodiment of the present invention; Figure 7 This is a schematic cross-sectional view of partial structural changes of the first structure corresponding to steps S26 to S28 according to an embodiment of the present invention. Figure 8 This is a schematic cross-sectional view of the partial structural changes of the second structure corresponding to steps S26 to S28 according to an embodiment of the present invention. Figure 9 This is a schematic cross-sectional view of the partial structural changes of the third structure corresponding to steps S26 to S28 according to an embodiment of the present invention.

[0008] The attached figures are labeled as follows: 10-Crystal silicon substrate; 11-First conductive region; 12-Second conductive region; 13-Electrically isolated region; 20-n-type carrier collection layer; 21-Electrode contact region; 22-Non-electrode contact region; 23-First tunneling passivation layer; 24-n-type doped polycrystalline silicon layer; 24'-Initial n-type doped polycrystalline silicon layer; 24''-Intermediate n-type doped polycrystalline silicon layer; 30-p-type carrier collection layer; 31-Second intrinsic amorphous silicon layer; 32-p-type doped silicon-containing film layer; 40-Metal silicide transition layer; 50-Transparent conductive film layer; 60-Metal transition layer; 71-First electrode; 72-Second electrode; 81-Mask layer; 82-Silicon oxide layer; 90-Passivation antireflection layer; 91-Front-side passivation layer; 92-Antireflection layer. Detailed Implementation

[0009] The back-contact heterojunction solar cell involved in the embodiments of the present invention refers to a crystalline silicon solar cell obtained by combining a tunneling passivation contact structure with heterojunction technology.

[0010] Existing back-contact heterojunction solar cells have an n-type conductive region and a p-type conductive region on the back side. The n-type conductive region typically separates and collects electron carriers through a phosphorus-doped polycrystalline silicon layer, while the p-type conductive region typically separates and collects hole carriers through a boron-doped silicon-containing film. Transmission of these carriers occurs through a combination of transparent conductive films and metal electrodes located in the n-type and p-type conductive regions. Currently, the transparent conductive film is typically a doped oxide layer such as indium tin oxide (ITO) or tin oxide (TITO), with a work function generally between 4.5 eV and 4.8 eV. The work function of this transparent conductive film differs significantly from that of the phosphorus-doped polycrystalline silicon layer in the n-type conductive region (approximately 4.1 eV) (a difference of about 0.4 eV to 0.7 eV). This results in a relatively high electron injection barrier in the n-type conductive region, which is detrimental to the collection and transmission of electron carriers. In addition, structural mismatch and distortion exist at the interface between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer, causing interface defects and making it easy for interfacial carrier recombination to occur, which also leads to low carrier transport efficiency.

[0011] Furthermore, in the existing fabrication process of back-contact heterojunction solar cells, a doped oxide layer is generally formed directly on the surface of the phosphorus-doped polycrystalline silicon layer and the boron-doped silicon-containing film layer by magnetron sputtering. During the formation of the doped oxide layer by magnetron sputtering, oxygen is generally used as the process gas, which will form an oxide layer on the surface of the phosphorus-doped polycrystalline silicon layer and the boron-doped silicon-containing film layer. The presence of this oxide layer will lead to an increase in the contact resistance between the phosphorus-doped polycrystalline silicon layer and the transparent conductive film layer, as well as the contact resistance between the boron-doped silicon-containing film layer and the transparent conductive film layer.

[0012] To address the aforementioned problems with existing back-contact heterojunction solar cells and their fabrication processes, this invention provides a novel back-contact heterojunction solar cell structure and a novel fabrication method for this novel structure. The novel back-contact heterojunction solar cell structure and the novel fabrication method provided by this invention involve adding a metal silicide transition layer 40 at least in the electrode contact region 21 of the n-type carrier collection layer 20. This metal silicide transition layer 40 acts as a bridge between the n-type carrier collection layer 20 and the transparent conductive film layer 50. On one hand, the work function of the metal silicide transition layer 40 is located between the work function of the n-type carrier collection layer 20 and the work function of the transparent conductive film layer 50, thereby reducing the interfacial potential barrier between the various film layers in the first conductive region, and thus reducing... Lowering the electron injection barrier in the first conductive region is beneficial for electron carrier transport in the first conductive region. On the other hand, the silicon atoms in the metal silicide transition layer 40 can ensure structural matching between the metal silicide transition layer 40 and the n-type carrier collection layer 20, reduce lattice distortion on the surface of the n-type carrier collection layer 20, thereby reducing interfacial carrier recombination in the n-type carrier collection layer 20. Therefore, by introducing the metal silicide transition layer 40 at least between the electrode contact region 21 of the n-type carrier collection layer 20 and the transparent conductive film layer 50, the carrier collection and transport efficiency of the first conductive region 11 can be effectively improved. Furthermore, since the work function of the metal silicide transition layer 40 differs significantly from that of the p-type carrier collection layer 30, introducing the metal silicide transition layer 40 between the p-type carrier collection layer 30 and the transparent conductive film layer 50 would actually increase the hole injection barrier of the second conductive region 12, which would be detrimental to the hole carrier transport in the second conductive region 12. Therefore, in the back contact heterojunction solar cell provided in this embodiment of the invention, the metal silicide transition layer 40 is not disposed on the outside of the p-type carrier collection layer 30.

[0013] It should be noted that the terms "first," "second," "third," and "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0014] In the embodiments of the present invention, the back side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 that faces away from sunlight during the operation of the solar cell. The front side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 that faces sunlight during the operation of the solar cell.

[0015] Unless otherwise specified, the term "from inside to outside" in the embodiments of this invention generally refers to the direction along the thickness of the back-contact heterojunction solar cell, with the crystalline silicon substrate 10 as the reference, from the position closest to the crystalline silicon substrate 10 to the position furthest away from the crystalline silicon substrate 10. Correspondingly, the inner and outer sides of a film layer are also referenced to the crystalline silicon substrate 10. The side of the film layer closest to the crystalline silicon substrate 10 is the inner side of the film layer, and the side of the film layer furthest from the crystalline silicon substrate 10 is the outer side of the film layer.

[0016] Unless otherwise contradictory, the doping concentration of a film layer in the embodiments of the present invention generally refers to the average number of activated doped atoms contained in a unit volume of the film layer.

[0017] The work function of a film layer involved in the embodiments of the present invention generally refers to the minimum energy required to move an electron at the Fermi level from inside the film layer to outside the film layer under the conditions of absolute zero, thermal equilibrium, and no external field inside the film layer, and the unit is eV.

[0018] In this embodiment of the invention, the valence band top of the p-type carrier collection layer 30 refers to the highest energy extreme point that electrons in the valence band of the p-type carrier collection layer 30 can reach, which is the upper boundary between the valence band and the band gap of the p-type carrier collection layer 30.

[0019] The conductivity types involved in the embodiments of this invention are generally divided into n-type conductivity types and p-type conductivity types, where n-type and p-type are two opposite conductivity types. Specifically, n-type conductivity films are generally doped with n-type dopant atoms (such as phosphorus atoms, arsenic atoms, antimony atoms, or bismuth atoms), while p-type conductivity films are generally doped with p-type dopant atoms (such as boron atoms, gallium atoms, aluminum atoms, or indium atoms).

[0020] Unless otherwise specified, in embodiments of the present invention, the electrode contact area of ​​a film generally refers to the region corresponding to the electrode in the thickness direction, while the non-electrode contact area generally refers to other regions of the film outside the electrode contact area, which do not correspond to the electrode in the thickness direction. It is understood that the electrode contact area and its corresponding electrode can be in direct or indirect contact.

[0021] Unless otherwise contradictory, in the embodiments of the present invention, another film layer disposed on a film layer generally refers to the other film layer being formed on the basis of the first film layer, and the other film layer is generally located on the side of the first film layer away from the crystalline silicon substrate 10. The other film layer disposed on a film layer does not specifically mean that the other film layer is located above the first film layer.

[0022] It is understood that a structure or membrane layer involved in the embodiments of the present invention includes one or more components or membrane layers. In addition to the components or membrane layers included in the structure or membrane layer disclosed in the embodiments of the present invention, the structure or membrane layer may also include other components or membrane layers.

[0023] Specifically, such as Figures 1 to 4 As shown, the back-contact heterojunction solar cell provided in this embodiment of the invention may include: a crystalline silicon substrate 10, an n-type carrier collection layer 20, a p-type carrier collection layer 30, a metal silicide transition layer 40, and a transparent conductive film layer 50.

[0024] More specifically, the back side of the crystalline silicon substrate 10 includes alternating first conductive regions 11 and second conductive regions 12; an n-type carrier collection layer 20 is disposed in the first conductive region 11, the n-type carrier collection layer 20 includes an electrode contact region 21 and a non-electrode contact region 22; a p-type carrier collection layer 30 is disposed in the second conductive region 12; a metal silicide transition layer 40 is disposed at least outside the electrode contact region 21 of the n-type carrier collection layer 20, and the metal silicide transition layer 40 is not disposed outside the p-type carrier collection layer 30; a transparent conductive film layer 50 is disposed in the first conductive region 11, located outside the metal silicide transition layer 40, and in contact with the metal silicide transition layer 40.

[0025] The silicon substrate 10 can be an n-type silicon substrate doped with n-type dopant atoms or a p-type silicon substrate doped with p-type dopant atoms. Preferably, the silicon substrate 10 is an n-type silicon substrate, which has fewer defects and can reduce carrier recombination.

[0026] It should be noted that in the back-contact solar cell provided in this embodiment of the invention, the first conductive region 11 is improved by the cooperation of an n-type carrier collection layer 20, a metal silicide transition layer 40 disposed at least outside the electrode contact region 21 of the n-type carrier collection layer 20, and a transparent conductive film layer 50 disposed in the first conductive region 11 and located outside the metal silicide transition layer 40. That is, the back-contact solar cell provided in this embodiment of the invention improves the first conductive region 11 by the metal silicide transition layer 40, the placement of the metal silicide transition layer 40 (located between the n-type carrier collection layer 20 and the transparent conductive film layer 50), and the cooperation of the metal silicide transition layer 40 with the n-type carrier collection layer 20 and the transparent conductive film layer 50.

[0027] The back-contact solar cell provided in this embodiment of the invention has a metal silicide transition layer 40 disposed on the outer side of the n-type carrier collection layer 20 in the first conductive region 11, at least corresponding to the electrode contact region 21. The metal silicide transition layer 40 forms a low potential barrier and a low interface contact resistance with the n-type carrier collection layer 20. At the same time, the work function of the metal silicide transition layer 40 matches the work function of the transparent conductive film layer 50, which can effectively reduce the electron injection barrier and interface contact resistance between the metal silicide transition layer 40 and the transparent conductive film layer 50. Therefore, the metal silicide transition layer 40 acts as a bridge between the n-type carrier collection layer 20 and the transparent conductive film layer 50, which can effectively reduce the electron injection barrier and interface contact resistance of the first conductive region 11, thereby reducing the contact resistance of the back-contact heterojunction solar cell, which is beneficial to electron carrier transport and improves the photoelectric conversion efficiency and fill factor of the back-contact heterojunction solar cell.

[0028] More specifically, the metal silicide transition layer 40 serves as a bridge between the n-type carrier collection layer 20 and the transparent conductive film layer 50. On one hand, its work function lies between the n-type carrier collection layer 20 and the transparent conductive film layer 50, resulting in a lower interfacial potential barrier between both the n-type carrier collection layer 20 and the metal silicide transition layer 40, and also a lower interfacial potential barrier between the metal silicide transition layer 40 and the transparent conductive film layer 50. This allows more electron carriers to cross the lower interfacial potential barrier, thereby reducing the electron injection barrier of the first conductive region 11, reducing energy loss during electron carrier migration, and lowering the electron current carrying capacity. Electrons accumulate and recombine at the interface of the n-type carrier collection layer 20, thereby effectively improving the collection and transport efficiency of electron carriers in the first conductive region 11. On the other hand, the silicon atoms in the metal silicide transition layer 40 are well matched with the interface structure of the n-type carrier collection layer 20. The metal atoms in the metal silicide transition layer 40 can combine with the atoms (such as oxygen atoms) in the transparent conductive film layer 50. At the same time, the metal atoms in the metal silicide transition layer 40 have strong conductivity, and they can form a low barrier ohmic contact with the n-type carrier collection layer 20 and the transparent conductive film layer 50, thereby effectively reducing the interface contact resistance.

[0029] In addition, the metal atoms in the metal silicide transition layer 40 can combine with the atoms (such as oxygen atoms) in the transparent conductive film layer 50 to reduce the interfacial stress, thereby effectively reducing the risk of cracking and peeling of the transparent conductive film layer 50.

[0030] In a preferred embodiment, the silicon atoms in the metal silicide transition layer 40 originate from the n-type carrier collection layer 20, thereby ensuring that the metal silicide transition layer 40 and the n-type carrier collection layer 20 are bonded by chemical bonds, which can effectively prevent the metal silicide transition layer 40 from cracking and falling off.

[0031] It is worth noting that the valence band peak of the p-type carrier collection layer 30 is approximately 5.0 eV, which is higher than the work function of the transparent conductive film layer 50 (4.5 eV~4.8 eV). However, the work function of the metal silicide transition layer 40 is lower than that of the transparent conductive film layer 50. That is, the difference between the work function of the metal silicide transition layer 40 and the valence band peak of the p-type carrier collection layer 30 is greater than the difference between the work function of the transparent conductive film layer 50 and the valence band peak of the p-type carrier collection layer 30. If a metal silicide transition layer 40 is provided between the p-type carrier collection layer 30 and the transparent conductive film layer 50, it will increase the hole injection barrier of the second conductive region 12, hindering hole injection in the second conductive region 12 and impeding hole carrier transport in the second conductive region 12. Therefore, the back contact heterojunction solar cell provided in this embodiment of the invention does not provide a metal silicide transition layer 40 on the outside of the p-type carrier collection layer 30. More specifically, "the metal silicide transition layer 40 is not provided on the outside of the p-type carrier collection layer 30" specifically means that a metal silicide transition layer 40 that contacts the outer interface of the p-type carrier collection layer 30 is not provided.

[0032] Furthermore, in embodiments of the present invention, such as Figures 1 to 4 As shown, the transparent conductive film layer 50 is also disposed on the outside of the p-type carrier collection layer 30. The transparent conductive film layer 50 disposed on the outside of the p-type carrier collection layer 30 is disconnected from the transparent conductive film layer 50 disposed on the outside of the metal silicide transition layer 40 between the first conductive region 11 and the second conductive region 12, so as to ensure the hole carrier transport in the second conductive region 12.

[0033] The transparent conductive film layer 50 is selected from at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium indium zinc oxide (GIZO), and has a thickness of 20 nm to 100 nm. For example, the thickness of the transparent conductive film layer 50 can be 20 nm, 30 nm, 50 nm, 70 nm, 80 nm, or 100 nm.

[0034] Furthermore, in embodiments of the present invention, such as Figure 2 As shown, the metal silicide transition layer 40 may also be disposed outside the non-electrode contact region 22 of the n-type carrier collection layer 20 to further improve the electron carrier transport efficiency of the first conductive region 11.

[0035] Furthermore, in embodiments of the present invention, such as Figure 3 and Figure 4As shown, the back-contact heterojunction solar cell may further include a metal transition layer 60, which is disposed between the p-type carrier collection layer 30 and the transparent conductive film layer 50, and is in contact with both the p-type carrier collection layer 30 and the transparent conductive film layer 50. On one hand, the work function of the metal transition layer 60 is essentially the same as the valence band top of the p-type carrier collection layer 30, so that the interface potential barrier between the p-type carrier collection layer 30 and the transparent conductive film layer 50 is essentially unaffected. On the other hand, the metal transition layer 60 has strong conductivity, which is beneficial for hole carrier transport. Therefore, the placement of the metal transition layer 60 will not increase the hole injection barrier of the second conductive region 12, and the strong conductivity of the metal transition layer 60 improves the hole carrier transport efficiency of the second conductive region 12.

[0036] Furthermore, the metal transition layer 60 located between the p-type carrier collection layer 30 and the transparent conductive film layer 50 in the second conductive region 12 avoids the need for a mask during the deposition of the metal silicide transition layer 40 in the first conductive region 11, thereby preventing laser damage caused by laser etching masks. Additionally, it avoids complex selective deposition processes, simplifying the deposition process of the metal silicide transition layer 40 and minimizing damage to each film layer.

[0037] Furthermore, the metal transition layer 60 may also be disposed on the outside of the non-electrode contact region 22 of the n-type carrier collection layer 20 and between the transparent conductive film layer 50, and in contact with the non-electrode contact region 22 and the transparent conductive film layer 50. By using the highly conductive metal transition layer 60 as a bridge between the non-electrode contact region 22 and the transparent conductive film layer 50 of the n-type carrier collection layer 20, the contact resistance between the non-electrode contact region 22 and the transparent conductive film layer 50 can be effectively reduced.

[0038] As can be seen from the above, the embodiments of the present invention provide various main structures for back-contact solar cells. For example... Figures 1 to 4 As shown, the common structure of various main structures may include: a crystalline silicon substrate 10, the back side of which includes alternating first conductive regions 11 and second conductive regions 12; an n-type carrier collection layer 20 disposed in the first conductive region 11, the n-type carrier collection layer 20 including an electrode contact region 21 and a non-electrode contact region 22; a p-type carrier collection layer 30 disposed in the second conductive region 12; a metal silicide transition layer 40; and a transparent conductive film layer 50 disposed in the first conductive region 11 and the second conductive region 12, the transparent conductive film layer 50 disposed in the first conductive region 11 and the transparent conductive film layer 50 disposed in the second conductive region 12 being disconnected between the first conductive region 11 and the second conductive region 12.

[0039] The structural differences between the various main structures are as follows: The first type of main structure: such as Figure 1 As shown, the metal silicide transition layer 40 is disposed outside the electrode contact region 21 of the n-type carrier collection layer 20, and the metal silicide transition layer 40 is not disposed outside the p-type carrier collection layer 30. The metal silicide transition layer 40 is in contact with the electrode contact region 21 of the n-type carrier collection layer 20. In addition, the transparent conductive film layer 50 located in the first conductive region 11 is disposed outside the metal silicide transition layer 40 and is in contact with the non-electrode contact region 22 of the metal silicide transition layer 40 and the n-type carrier collection layer 20; the transparent conductive film layer 50 located in the second conductive region 12 is disposed outside the p-type carrier collection layer 30 and is in contact with the p-type carrier collection layer 30.

[0040] The second type of main structure: such as Figure 2 As shown, the metal silicide transition layer 40 is disposed outside the electrode contact region 21 and the non-electrode contact region 22 of the n-type carrier collection layer 20, and the metal silicide transition layer 40 is not disposed outside the p-type carrier collection layer 30. The metal silicide transition layer 40 is in contact with the electrode contact region 21 and the non-electrode contact region 22 of the n-type carrier collection layer 20. In addition, the transparent conductive film layer 50 located in the first conductive region 11 is disposed outside the metal silicide transition layer 40 and is in contact with the metal silicide transition layer 40; the transparent conductive film layer 50 located in the second conductive region 12 is disposed outside the p-type carrier collection layer 30 and is in contact with the p-type carrier collection layer 30.

[0041] The third type of main structure: Based on the first type of main structure, it adds a metal transition layer 60. Specifically, as shown in... Figure 3 As shown, the metal transition layer 60 is disposed outside and in contact with the p-type carrier collection layer 30, and the metal silicide transition layer 40 is disposed outside the electrode contact region 21 of the n-type carrier collection layer 20. The metal silicide transition layer 40 is not disposed outside the p-type carrier collection layer 30, but is in contact with the electrode contact region 21 of the n-type carrier collection layer 20. Furthermore, the transparent conductive film layer 50 located in the first conductive region 11 is disposed outside the metal silicide transition layer 40 and is in contact with the non-electrode contact region 22 of both the metal silicide transition layer 40 and the n-type carrier collection layer 20; the transparent conductive film layer 50 located in the second conductive region 12 is disposed outside and in contact with the metal transition layer 60.

[0042] The fourth type of main structure: Based on the second type of main structure, a metal transition layer 60 is added. Specifically, as shown... Figure 4As shown, the metal transition layer 60 is disposed outside and in contact with the p-type carrier collection layer 30. The metal silicide transition layer 40 is disposed outside the electrode contact region 21 and the non-electrode contact region 22 of the n-type carrier collection layer 20, but is not disposed outside the p-type carrier collection layer 30; instead, the metal silicide transition layer 40 is in contact with both the electrode contact region 21 and the non-electrode contact region 22 of the n-type carrier collection layer 20. Furthermore, the transparent conductive film layer 50 located in the first conductive region 11 is disposed outside and in contact with the metal silicide transition layer 40; the transparent conductive film layer 50 located in the second conductive region 12 is disposed outside and in contact with the metal transition layer 60.

[0043] The fifth main structure (not shown in the figure): Based on the first main structure, a metal transition layer 60 is added. Specifically, the metal transition layer 60 is disposed between the outside of the non-electrode contact region 22 of the n-type carrier collection layer 20 and the transparent conductive film layer 50, and the metal transition layer 60 is in contact with the non-electrode contact region 22 of the n-type carrier collection layer 20 and the transparent conductive film layer 50, while the p-type carrier collection layer 30 of the second conductive region 12 is in contact with the transparent conductive film layer 50.

[0044] The sixth main structure (not shown in the figure): Based on the first main structure, a metal transition layer 60 is added. Specifically, the metal transition layer 60 is disposed outside and in contact with the p-type carrier collection layer 30. Simultaneously, the metal transition layer 60 is also disposed outside the non-electrode contact region 22 of the n-type carrier collection layer 20 and between it and the transparent conductive film layer 50. The metal silicide transition layer 40 is disposed outside the electrode contact region 21 of the n-type carrier collection layer 20, and is in contact with the electrode contact region 21 of the n-type carrier collection layer 20. Furthermore, the transparent conductive film layer 50 located in the first conductive region 11 is disposed outside the metal silicide transition layer 40 in the electrode contact region 21 and the metal transition layer 60 in the non-electrode contact region 22, and is in contact with both the metal silicide transition layer 40 and the metal transition layer 60; the transparent conductive film layer 50 located in the second conductive region 12 is disposed outside and in contact with the metal transition layer 60.

[0045] The above six main structures, by setting a metal silicide transition layer 40 in the first conductive region 11, can reduce or even avoid the contact between oxygen introduced during the subsequent setting of the transparent conductive film layer 50 and the n-type carrier collection layer 20 of the first conductive region 11, thereby avoiding the introduction of silicon oxide between the n-type carrier collection layer 20 and the metal silicide transition layer 40 in the first conductive region 11, and effectively reducing the contact resistance of the first conductive region 11.

[0046] Furthermore, the third, fourth, and sixth main structures described above, by providing a metal transition layer 60 in the second conductive region 12, can prevent oxygen introduced during the subsequent provision of the transparent conductive film layer 50 from contacting the p-type carrier collection layer 30 of the second conductive region 12, thereby preventing the formation of silicon oxide on the surface of the p-type carrier collection layer 30 of the second conductive region 12 and effectively reducing the contact resistance of the second conductive region 12.

[0047] For any of the aforementioned main structures, the work function of the metal silicide transition layer 40 is generally controlled between 4.3 eV and 4.6 eV. For example, the work function of the metal silicide transition layer 40 can be 4.3 eV, 4.4 eV, 4.5 eV, or 4.6 eV, etc. By controlling the work function of the metal silicide transition layer 40, it can be ensured that the work function of the metal silicide transition layer 40 can be matched with that of the transparent conductive film layer 50 and the n-type carrier collection layer 20 simultaneously.

[0048] In this embodiment of the invention, the metal silicide transition layer 40 and the n-type carrier collection layer 20 form an ohmic contact with an electron injection potential barrier (i.e., electron injection barrier) of less than 0.2 eV, so as to ensure that the first conductive region 11 has a strong ability to collect and transport electron carriers.

[0049] The interfacial contact resistance between the metal silicide transition layer 40 and the n-type carrier collection layer 20 is less than 10 Ω. -4 Ω·cm². This specific contact resistance refers to the interfacial contact resistance per unit effective area when the metal silicide transition layer 40 and the n-type carrier collection layer 20 form an interface. This specific contact resistance is controlled to be less than 10 Ω·cm². -4 With a resistance of Ω·cm², the interfacial contact resistance between the metal silicide transition layer 40 and the n-type carrier collection layer 20 can be effectively reduced.

[0050] In this embodiment of the invention, the metal silicide transition layer 40 includes ASi. x Where A represents one or more of Ni, Ti, Co, and Sn. x This indicates the number of Si atoms that are bonded to one A atom, 0.5 ≤ x A work function ≤2 ensures that the work function of the metal silicide transition layer 40 is simultaneously matched to both the n-type carrier collection layer 20 and the transparent conductive film layer 50. Furthermore, by selecting one or more of Ni, Ti, Co, and Sn, the work function of the metal silicide transition layer 40 can be maintained within the aforementioned range of 4.3 eV to 4.6 eV, while simultaneously ensuring its conductivity, which helps to improve its ability to transport electron carriers.

[0051] In a preferred embodiment, the metal silicide transition layer 40 comprises NiSix , 0.5≤ x ≤2. The NiSi x The work function is 4.4 eV to 4.5 eV, which is a good match for both the work function of the transparent conductive film layer 50 and the work function of the n-type carrier collection layer 20. Furthermore, the nickel atoms exhibit better structural compatibility with both the n-type carrier collection layer 20 and the transparent conductive film layer 50. This reduces the electron injection barrier between the n-type carrier collection layer 20 and the transparent conductive film layer 50 from the existing difference of 0.4 eV to 0.7 eV to below 0.2 eV, and also reduces the existing interfacial contact resistance between the n-type carrier collection layer 20 and the transparent conductive film layer 50 from 10... - ³Ω·cm²~10 - ²Ω·cm² decreased to 10 -4 With a resistance of Ω·cm² or less, a low-barrier ohmic contact can be formed between the metal silicide transition layer 40, the n-type carrier collection layer 20, and the transparent conductive film layer 50, thereby effectively reducing the interfacial contact resistance. In a more preferred embodiment, the metal silicide transition layer 40 is made of NiSi. x Composition. NiSi x With a dense crystal lattice, few interstitial defects, and the presence of In, Sn, and other metal atoms in the transparent conductive film, as well as Ag, Cu, and other metal atoms in the electrodes, in NiSi x The extremely low solubility and diffusion coefficient of NiSi make it difficult for these molecules to diffuse. x The metal silicide transition layer 40 can prevent metal atoms in the transparent conductive film layer and the metal atoms in the electrode from migrating and diffusing to the n-type carrier collection layer 20 and the crystalline silicon substrate 10, thereby ensuring the structural stability of the n-type carrier collection layer 20 and the crystalline silicon substrate 10, improving the lifetime of the first conductive region 11, and thus effectively improving the lifetime of the back contact heterojunction solar cell. Additionally, NiSi... x It has high stability and can prevent nickel atoms from diffusing into the n-type carrier collection layer 20, thereby avoiding the formation of deep energy level defects in the n-type carrier collection layer 20, so as to ensure the structural stability and reliability of the n-type carrier collection layer 20.

[0052] Besides the choice of metal material in the metal silicide transition layer 40 affecting the compatibility between the metal silicide transition layer 40 and the n-type carrier collection layer 20 and the transparent conductive film layer 50, the thickness of the metal silicide transition layer 40 also affects its compatibility with these layers. In this embodiment of the invention, the thickness of the metal silicide transition layer 40 is 2 nm to 15 nm. By controlling the thickness of the metal silicide transition layer 40, the uniformity of its distribution between the n-type carrier collection layer 20 and the transparent conductive film layer 50 can be ensured, reducing or even avoiding contact between the transparent conductive film layer 50 and the n-type carrier collection layer 20. Simultaneously, the thickness of the metal silicide transition layer 40 allows electron carriers to pass through it rapidly. Furthermore, the thickness of the metal silicide transition layer 40 ensures the surface flatness of the metal silicide transition layer 40, thereby guaranteeing the flatness and uniformity of the transparent conductive film layer 50 formed based on the metal silicide transition layer 40. For example, the thickness of the metal silicide transition layer 40 can be 2nm, 4nm, 5nm, 8nm, 10nm, 12nm, or 15nm, etc.

[0053] For any of the third to sixth main body structures mentioned above, the thickness of the metal transition layer 60 is 1 nm to 10 nm. By controlling the thickness of the metal transition layer 60, it is possible to ensure that the metal transition layer 60 is uniformly distributed on the p-type carrier collection layer 30 of the second conductive region 12, and to ensure the uniformity of the thickness of the transparent conductive film layer 50 formed on the basis of the metal transition layer 60. In addition, the thickness of the metal transition layer 60 is related to the thickness of the metal silicide transition layer 40 of the first conductive region 11. By controlling the thickness of the metal transition layer 60, the thickness of the metal silicide transition layer 40 can be controlled.

[0054] In this embodiment of the invention, the work function of the metal transition layer 60 is 4.9 eV to 5.2 eV. For example, the work function of the metal transition layer 60 can be 4.9 eV, 5.0 eV, 5.1 eV, or 5.2 eV. By controlling the work function of the metal transition layer 60, it can be ensured that the work function of the metal transition layer 60 is simultaneously matched with the p-type carrier collection layer 30 and the transparent conductive film layer 50, so as to reduce the hole injection barrier of the second conductive region 12 and improve the hole carrier transport efficiency of the second conductive region 12.

[0055] More specifically, the metal transition layer 60 and the p-type carrier collection layer 30 form an ohmic contact with a hole injection potential barrier of less than 0.2 eV to ensure hole carrier transport.

[0056] The interfacial contact resistance between the metal transition layer 60 and the p-type carrier collection layer 30 is less than 10 Ω. -4Ω·cm², to effectively reduce the contact resistance between the metal transition layer 60 and the p-type carrier collection layer 30.

[0057] In this embodiment of the invention, the metal transition layer 60 may include one or more elemental metals selected from Ni, Ti, Co, and Sn. This ensures that the work function of the metal transition layer 60 matches both the p-type carrier collection layer 30 and the transparent conductive film layer 50, and effectively reduces the interfacial contact resistance. Preferably, the metal atoms contained in the metal transition layer 60 are identical to those contained in the metal silicide transition layer 40, allowing the metal silicide transition layer 40 to be formed on the basis of the metal transition layer 60. This effectively simplifies the fabrication process of the metal silicide transition layer 40 and avoids the use of masks and laser etching of masks during the formation of the metal silicide transition layer 40, thereby reducing damage to each film layer.

[0058] In a preferred embodiment, the metal transition layer 60 is composed of one or more elemental metals selected from Ni, Ti, Co, and Sn, to further improve the work function matching between the metal transition layer 60 and the p-type carrier collection layer 30 and the transparent conductive film layer 50, and to ensure a low interfacial contact resistance. In a more preferred embodiment, the metal transition layer 60 is composed of elemental Ni. Furthermore, the solubility and diffusion coefficient of metal atoms such as In and Sn in the transparent conductive film layer, and metal atoms such as Ag and Cu in the electrode, are extremely low in the metal transition layer 60 composed of elemental Ni. This allows the metal transition layer 60 composed of elemental Ni to prevent the migration and diffusion of metal atoms from the transparent conductive film layer and the electrode to the p-type carrier collection layer 30 and the crystalline silicon substrate 10, thereby ensuring the structural stability of the p-type carrier collection layer 30 and the crystalline silicon substrate 10, improving the lifetime of the second conductive region 12, and thus effectively improving the lifetime of the back-contact heterojunction solar cell.

[0059] As can be seen from the above, the preferred structure of the back-contact solar cell of the present invention is to simultaneously provide a metal transition layer 60 and a metal silicide transition layer 40, so as to simultaneously improve the electron carrier transport efficiency of the first conductive region 11 and the hole carrier transport efficiency of the second conductive region, and ensure the structural stability of the first conductive region 11 and the second conductive region 12, thereby more effectively reducing the contact resistance of the back-contact heterojunction solar cell and improving the service life of the back-contact heterojunction solar cell.

[0060] In the embodiments of the present invention, based on the structure of the back contact heterojunction solar cell provided in any of the above embodiments, there can be various combinations of the n-type carrier collection layer 20 and the p-type carrier collection layer 30.

[0061] Specifically, the first combination structure of the n-type carrier collection layer 20 and the p-type carrier collection layer 30 is as follows: Figures 1 to 4As shown, the n-type carrier collection layer 20 includes a first tunneling passivation layer 23 and an n-type doped polycrystalline silicon layer 24 stacked from the inside to the outside; the p-type carrier collection layer 30 includes a second intrinsic amorphous silicon layer 31 and a p-type doped silicon-containing film layer 32 stacked from the inside to the outside.

[0062] The first tunneling passivation layer 23 is generally a silicon oxide layer, and its thickness is generally 0.5 nm to 2 nm. For example, the thickness of the first tunneling passivation layer 23 can be 0.5 nm, 0.8 nm, 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm, etc., to passivate the surface of the crystalline silicon substrate 10 of the first conductive region 11 while ensuring that electron carriers can tunnel through the first tunneling passivation layer 23. The thickness of the n-type doped polycrystalline silicon layer 24 is 100 nm to 150 nm, and the doping concentration of the n-type doped polycrystalline silicon layer 24 is 1 × 10⁻⁶. 20 atoms / cm 3 ~2×10 21 atoms / cm 3 For example, the thickness of the n-type doped polysilicon layer 24 can be 100 nm, 120 nm, 130 nm, or 150 nm, and the doping concentration of the n-type doped polysilicon layer 24 can be 1 × 10⁻⁶. 20 atoms / cm 3 3×10 20 atoms / cm 3 5×10 20 atoms / cm 3 9×10 20 atoms / cm 3 1×10 21 atoms / cm 3 Or 2×10 21 atoms / cm 3 The thickness of the n-type doped polysilicon layer 24 is matched with that of the metal silicide transition layer 40, which effectively ensures that the passivation effect of the n-type doped polysilicon layer 24 does not decrease significantly. Furthermore, during the fabrication of the metal silicide transition layer 40, the n-type doped polysilicon layer 24 prevents metal atoms or dopants from advancing into the first tunneling passivation layer 23 and the silicon substrate 10, thus avoiding damage to their surfaces. Moreover, by controlling the doping concentration and thickness of the n-type doped polysilicon layer 24, the advancement of dopants into the first tunneling passivation layer 23 and the silicon substrate 10 can be further prevented during the fabrication process of the metal silicide transition layer 40.

[0063] The thickness of the second intrinsic amorphous silicon layer 31 is 6 nm to 13 nm to ensure passivation of the surface of the crystalline silicon substrate 10 and to ensure the transport of hole carriers in the second conductive region 12, while also reducing parasitic absorption in the second conductive region 12. For example, the thickness of the second intrinsic amorphous silicon layer 31 can be 6 nm, 8 nm, 10 nm, or 13 nm.

[0064] Alternatively, the first tunneling passivation layer 23 and the n-type doped polysilicon layer 24 stacked from the inside to the outside in the first combined structure can be replaced with an n-type doped diffusion layer formed by directly diffusing n-type doped atoms on the surface of the crystalline silicon substrate 10 in the first conductive region 11.

[0065] A second combination structure of n-type carrier collection layer 20 and p-type carrier collection layer 30: n-type carrier collection layer 20 includes a first intrinsic amorphous silicon layer and an n-type doped silicon-containing film layer stacked from the inside to the outside; p-type carrier collection layer 30 includes a second intrinsic amorphous silicon layer 31 and a p-type doped silicon-containing film layer 32 stacked from the inside to the outside.

[0066] The thickness of the first intrinsic amorphous silicon layer is 6 nm to 20 nm. The thickness of the n-type doped silicon film is 90 nm to 130 nm, and the doping concentration of the n-type doped silicon film is 1 × 10⁻⁶. 20 atoms / cm 3 ~2×10 21 atoms / cm 3 For example, the thickness of the first intrinsic amorphous silicon layer can be 6nm, 8nm, 10nm, 13nm, 15nm, 18nm, or 20nm, etc., and the thickness of the n-type doped silicon film can be 90nm, 100nm, 110nm, 120nm, or 130nm, etc., and the doping concentration of the n-type doped silicon film can be 1×10⁻⁶. 20 atoms / cm 3 3×10 20 atoms / cm 3 5×10 20 atoms / cm 3 9×10 20 atoms / cm 3 1×10 21 atoms / cm 3 Or 2×10 21 atoms / cm 3By controlling the thickness of the first intrinsic amorphous silicon layer, passivation can be ensured while maintaining electron carrier transport in the first conductive region 11. Furthermore, by controlling the thickness of the n-type doped silicon film, on the one hand, the n-type doped silicon film can be made dense enough to prevent metal atoms from migrating inwards to the first intrinsic amorphous silicon layer; on the other hand, the passivation effect and electron carrier transport capability of the n-type doped silicon film can be guaranteed. In addition, by controlling the doping concentration and thickness of the n-type doped silicon film, the propagation of doped atoms into the first intrinsic amorphous silicon layer and the crystalline silicon substrate 10 can be further prevented during the fabrication of the metal silicide transition layer 40, thus avoiding the formation of recombination centers between the doped atoms and the crystalline silicon substrate 10.

[0067] In this context, the n-type doped silicon-containing film typically contains crystalline silicon particles with a particle size generally less than 100 nm, meaning the silicon particles are typically microcrystalline or nanocrystalline. The presence of crystalline silicon particles in the n-type doped silicon-containing film effectively improves its conductivity and further reduces its contact resistance with the metal silicide transition layer 40, which is beneficial for electron carrier transport.

[0068] A third combination structure of n-type carrier collection layer 20 and p-type carrier collection layer 30: The n-type carrier collection layer 20 includes a first intrinsic amorphous silicon layer and an n-type doped silicon-containing film layer stacked from the inside out; the p-type carrier collection layer 30 includes a second tunneling passivation layer and a p-type doped polycrystalline silicon layer stacked from the inside out. This third combination structure is generally used in conjunction with a p-type crystalline silicon substrate.

[0069] The second tunneling passivation layer is a silicon oxide layer, which passivates the surface of the crystalline silicon substrate 10 of the second conductive region 12. Its thickness is generally 0.5nm to 2nm. For example, the thickness of the second tunneling passivation layer can be 0.5nm, 0.8nm, 1nm, 1.3nm, 1.5nm, 1.8nm or 2nm, etc., to ensure that hole carriers can tunnel through the second tunneling passivation layer.

[0070] Alternatively, the second tunneling passivation layer and the p-type doped polysilicon layer stacked from the inside to the outside in the third combination structure can be replaced with a p-type doped diffusion layer formed by directly diffusing p-type doped atoms on the surface of the crystalline silicon substrate 10 in the second conductive region 12.

[0071] In one embodiment, in the first and second combined structures of the n-type carrier collection layer 20 and the p-type carrier collection layer 30, the p-type doped silicon-containing film layer 32 can be a p-type doped amorphous silicon layer, or it can include nanoscale crystalline silicon particles and amorphous silicon. The valence band top of this p-type doped silicon-containing film layer 32 is matched with the work function of the metal transition layer 60, effectively reducing the interface barrier and contact resistance. Furthermore, the thickness of the p-type doped silicon-containing film layer 32 is 20 nm to 30 nm. For example, the thickness of the p-type doped silicon-containing film layer 32 can be 20 nm, 25 nm, 28 nm, or 30 nm. By matching the thickness of the p-type doped silicon-containing film layer 32 with the metal transition layer 60, metal atoms in the metal transition layer 60 can be prevented from entering the second intrinsic amorphous silicon layer 31 and the crystalline silicon substrate 10, avoiding the formation of recombination centers between the metal and the crystalline silicon substrate 10, thereby effectively improving the hole carrier collection capability of the second conductive region 12.

[0072] In an optional embodiment, the p-type doped silicon-containing film layer 32 has a textured structure to improve the light-trapping properties of the second conductive region 12, thereby improving the light utilization efficiency of the back-contact solar cell.

[0073] In a preferred embodiment, for cases where the p-type doped silicon-containing film 32 may include nanoscale crystalline silicon particles and amorphous silicon, the tip of the textured structure of the p-type doped silicon-containing film 32 is crystalline silicon, while the bottom and body are amorphous silicon. This can enable good electrical contact between the tip of the textured p-type doped silicon-containing film 32 and the transparent conductive film 50, thereby reducing the contact resistance of the second conductive region 12.

[0074] In addition, in the second and third combined structures of the above-mentioned n-type carrier collection layer 20 and p-type carrier collection layer 30, the n-type doped silicon-containing film layer can be an n-type doped amorphous silicon layer, and the n-type doped silicon-containing film layer can also include nanoscale crystalline silicon particles and amorphous silicon.

[0075] Furthermore, the first conductive region 11 and the second conductive region 12 of the back-contact solar cell provided in this embodiment of the invention can be either a finger-cross structure or a strip structure, which can meet the needs of different photovoltaic modules.

[0076] The width of the first conductive region 11 and the second conductive region 12 is generally 100μm to 500μm. For example, the width of the first conductive region 11 and the second conductive region 12 can be 100μm, 120μm, 150μm, 180μm, 200μm, 250μm, 300μm, 400μm, 450μm or 500μm, etc. By controlling the width of the first conductive region 11 and the second conductive region 12, the collection and transport efficiency of electron carriers and hole carriers can be effectively balanced while ensuring the realization of the process.

[0077] Furthermore, such as Figures 1 to 4 As shown, any of the above-described back-contact heterojunction solar cells may further include: an electrically isolated region 13, disposed between adjacent first conductive regions 11 and second conductive regions 12; an n-type carrier collection layer 20 and a p-type carrier collection layer 30 extending to the electrically isolated region 13, wherein the p-type carrier collection layer 30 and the n-type carrier collection layer 20 are stacked and electrically isolated in the electrically isolated region 13. Specifically, for the first and second combined structures of the n-type carrier collection layer 20 and the p-type carrier collection layer 30, the p-type carrier collection layer 30 is stacked outside the n-type carrier collection layer 20 in the electrically isolated region 13; for the third combined structure of the n-type carrier collection layer 20 and the p-type carrier collection layer 30, the n-type carrier collection layer 20 is stacked outside the p-type carrier collection layer 30.

[0078] The width of the electrical isolation region 13 can be 50μm to 200μm to ensure process operability. Specifically, the width of the electrical isolation region 13 can be 50μm, 70μm, 90μm, 100μm, 120μm, 150μm, 180μm, or 200μm, etc. It is worth noting that the width of the electrical isolation region 13 is generally smaller than the width of the first conductive region 11 and the second conductive region 12.

[0079] Furthermore, such as Figures 1 to 4 As shown, the aforementioned back-contact heterojunction solar cell may further include: a first electrode 71 and a second electrode 72, wherein the first electrode 71 is disposed on the outside of the transparent conductive film layer 50 of the electrode contact region 21; and the second electrode 72 is disposed on the outside of the transparent conductive film layer 50 of the second conductive region 12.

[0080] Furthermore, such as Figures 1 to 4 As shown, the back-contact heterojunction solar cell may further include a passivation antireflection layer 90 disposed on the front side of the crystalline silicon substrate 10. Specifically, the passivation antireflection layer 90 may include a front passivation layer 91 and an antireflection layer 92 stacked from the inside to the outside.

[0081] Furthermore, embodiments of the present invention provide a method for fabricating a back-contact heterojunction solar cell. Specifically, as shown in the following example... Figure 5 As shown, the preparation method may include: Step S1: Provide a crystalline silicon substrate 10, the back side of which includes alternating first conductive regions 11 and second conductive regions 12.

[0082] The silicon substrate 10 can be an n-type silicon substrate or a p-type silicon substrate.

[0083] The first conductive region 11 and the second conductive region 12 are defined and divided to allow for precise control over the formation of the n-type carrier collection layer 20 and the p-type carrier collection layer 30 in subsequent processes. Understandably, there is no difference between the first conductive region 11 and the second conductive region 12 before the formation of the n-type carrier collection layer 20 and the p-type carrier collection layer 30.

[0084] Step S2: An n-type carrier collection layer 20 is formed in the first conductive region 11, and a p-type carrier collection layer 30 is formed in the second conductive region 12. The n-type carrier collection layer 20 includes an electrode contact region 21 and a non-electrode contact region 22. A metal silicide transition layer 40 is formed at least in the electrode contact region 21, and the metal silicide transition layer 40 is not formed on the outside of the p-type carrier collection layer 30.

[0085] Step S3: A transparent conductive film layer 50 is formed in the first conductive region 11. The transparent conductive film layer 50 is located outside the metal silicide transition layer 40 and is in contact with the metal silicide transition layer 40.

[0086] The above-described preparation method can be used to prepare the back-contact heterojunction solar cell provided in any of the above embodiments. By forming a metal silicide transition layer 40 at least in the electrode contact region 21 of the n-type carrier collection layer 20 and not forming the metal silicide transition layer 40 outside the p-type carrier collection layer 30, the n-type carrier collection layer 20, the metal silicide transition layer 40 formed at least outside the electrode contact region 21 of the n-type carrier collection layer 20, and the transparent conductive film layer 50 formed in the first conductive region 11 and located outside the metal silicide transition layer 40 can be combined to improve the carrier transport efficiency of the first conductive region 11 and effectively improve the photoelectric conversion efficiency and fill factor of the prepared back-contact heterojunction solar cell.

[0087] The preparation method provided in this embodiment of the invention mainly involves improvements to step S2 described above.

[0088] Specifically, the specific implementation of step S2 may include the following steps S21 to S28: Step S21: A first tunneling passivation layer 23, an initial n-type doped polysilicon layer 24', and a mask layer 81 are sequentially stacked on the back side of the crystalline silicon substrate 10.

[0089] Specifically, in step S21, a silicon oxide layer serving as the first tunneling passivation layer 23 is first formed on the back side of the crystalline silicon substrate 10 using a furnace tube oxidation method. Then, using silane as a reaction precursor, an intrinsic polycrystalline silicon layer or an intrinsic amorphous silicon layer is deposited by low-temperature plasma chemical vapor deposition. In a diffusion furnace, n-type dopant atoms (such as phosphorus atoms, arsenic atoms, etc.) are diffused onto the intrinsic polycrystalline silicon layer or intrinsic amorphous silicon layer to form an initial n-type doped polycrystalline silicon layer 24'. It should be noted that since the diffusion temperature is generally between 800℃ and 900℃, during the diffusion of n-type dopant atoms into the intrinsic amorphous silicon layer, the amorphous silicon is converted into polycrystalline silicon. Therefore, even if n-type dopant atoms are diffused into the intrinsic amorphous silicon layer, the result is still an initial n-type doped polycrystalline silicon layer 24'.

[0090] Understandably, during the process of forming the initial n-type doped polysilicon layer 24', a doped silicon glass layer will also be formed on the outside of the initial n-type doped polysilicon layer 24', so the mask layer 81 is actually formed on the outside of the doped silicon glass layer.

[0091] Furthermore, a silicon nitride layer serving as mask layer 81 is deposited using plasma-enhanced chemical vapor deposition under a reaction precursor of silane and ammonia. More specifically, the deposited mask layer 81 has a refractive index of 2.1 and a thickness of 30 nm to 50 nm, for example, the thickness of mask layer 81 can be 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. It should be noted that the refractive index of the required mask layer 81 can be obtained by controlling the flow ratio of silane and ammonia. By controlling the refractive index and thickness of the mask layer 81, it can be ensured that during the laser etching process in step S22, the laser can pass through the mask layer 81 and be absorbed by the doped silicon glass layer and the initial n-type doped polysilicon layer 24' inside the mask layer 81, resulting in thermal expansion. Through the thermal expansion of the doped silicon glass layer and the initial n-type doped polysilicon layer 24', the mask layer 81 is broken through, thereby removing the mask layer 81. At the same time, a silicon oxide layer 82 is formed on the outside of the initial n-type doped polysilicon layer 24' corresponding to the second conductive region 12.

[0092] In addition, during the processing of step S21, a first wrap-around coating corresponding to the first tunneling passivation layer 23, a second wrap-around coating corresponding to the initial n-type doped polysilicon layer 24', and a third wrap-around coating corresponding to the doped silicon glass layer are formed on the front side of the crystalline silicon substrate 10.

[0093] Step S22: Laser etching removes the mask layer 81 corresponding to the second conductive region 12, and forms a silicon oxide layer 82 on the outside of the initial n-type doped polysilicon layer 24' corresponding to the second conductive region 12.

[0094] Step S23: The silicon oxide layer 82 is removed by cleaning with HF solution, and the initial n-type doped polysilicon layer 24', the first tunneling passivation layer 23 and part of the crystalline silicon substrate 10 corresponding to the second conductive region 12 are removed by cleaning with alkaline solution.

[0095] The HF solution used in this step has a mass fraction of 1% to 5%. The cleaning time is 30s to 200s, and the alkaline solution has a mass fraction of 0.5% to 2%, with a cleaning time of 3min to 15min. For example, the mass fraction of the HF solution can be 1%, 2%, 3%, or 5%, and the cleaning time can be 30s, 50s, 60s, 90s, 120s, 150s, or 200s, etc. The mass fraction of the alkaline solution can be 0.5%, 0.8%, 1%, 1.2%, 1.5%, or 2%, etc., and the cleaning time can be 3min, 5min, 8min, 10min, 12min, or 15min, etc. By controlling the mass fraction of the HF solution and the cleaning time, this step ensures that the silicon oxide layer 82 of the second conductive region 12 and the doped silicon glass layer corresponding to the second conductive region 12 are removed, and that the mask layer 81 of the electrically isolated region 13 and the first conductive region 11 are well preserved.

[0096] It should be noted that in this step, the HF solution can simultaneously clean and remove the doped silicon glass layer corresponding to the second conductive region 12 and the third surrounding plating layer formed on the front side of the crystalline silicon substrate 10. The alkaline solution (such as KOH or NaOH solution) can simultaneously clean and remove the second surrounding plating layer, the first surrounding plating layer, and part of the crystalline silicon substrate 10 formed on the front side of the crystalline silicon substrate 10. Additionally, this step can also use a solution containing a texturing solvent and a strong alkali (KOH or NaOH) to texturize the front side of the second conductive region 12 and the crystalline silicon substrate 10. Whether using alkaline solution cleaning or texturing, the remaining mask layer 81, with its refractive index of 2.1 and thickness, ensures high density, effectively blocking OH groups. - The initial n-type doped polysilicon layer 24' penetrates into the first conductive region 11, avoiding damage to the initial n-type doped polysilicon layer 24' in step S24.

[0097] Furthermore, before or after step S24, the method may further include forming a passivation antireflection layer 90 on the front side of the crystalline silicon substrate 10.

[0098] Step S24: Clean with HF solution to remove the remaining mask layer 81.

[0099] The HF solution used in this step has a mass fraction of 5% to 10%, and the cleaning time is 50 to 400 seconds. For example, the mass fraction of the HF solution can be 5%, 6%, 8%, or 10%, and the cleaning time can be 50, 90, 120, 150, 180, 240, 270, or 300 seconds, etc. By controlling the mass fraction of the HF solution and the cleaning time, it can be ensured that the remaining mask layer 81 can be completely removed. In addition, this step of cleaning with the HF solution can also remove residual impurities in the second conductive region 12.

[0100] Understandably, step S24 can also simultaneously remove the remaining doped silicon glass layer.

[0101] Furthermore, regarding the formation of the passivation antireflection layer 90 on the front side of the silicon substrate 10 before step S24, step S24 can also simultaneously clean the surrounding plating layer corresponding to the passivation antireflection layer 90 deposited on the outer side of the mask layer 81 and the second conductive region 12 using HF solution. Alternatively, the formation of the passivation antireflection layer 90 on the front side of the silicon substrate 10 can also be done after step S24. If the formation of the passivation antireflection layer 90 on the front side of the silicon substrate 10 is done after step S24, then before step S25, it is necessary to further clean the surrounding plating layer corresponding to the passivation antireflection layer 90 using HF solution.

[0102] Step S25: A second intrinsic amorphous silicon layer 31 and a p-type doped silicon-containing film layer 32 are sequentially stacked on the outside of the second conductive region 12 and the remaining initial n-type doped polycrystalline silicon layer 24'.

[0103] Step S26: Laser etching removes the p-type doped silicon film layer 32 and the second intrinsic amorphous silicon layer 31 corresponding to the first conductive region 11, and activates some doped atoms in the initial n-type doped polysilicon layer 24' to form an intermediate n-type doped polysilicon layer 24''.

[0104] During the laser processing in step S26, some doped atoms in the initial n-type doped polysilicon layer 24' can be further activated, so that the doping concentration of the intermediate n-type doped polysilicon layer 24'' is higher than that of the initial n-type doped polysilicon layer 24', thereby enhancing the passivation effect of the first conductive region 11.

[0105] Step S27: Form a metal transition layer 60 at least in the electrode contact area 21.

[0106] The metal transition layer 60 is generally composed of a metallic element. More specifically, the metallic element may be one or more of Ni, Ti, Co, and Sn, and preferably, the metallic element is Ni.

[0107] Step S28: Irradiate at least the metal transition layer 60 corresponding to the electrode contact region 21 with a laser to form an ASi layer. xThe metal silicide transition layer 40 further activates the doped atoms in the intermediate n-type doped polysilicon layer 24'' to form an n-type doped polysilicon layer 24, where A represents one or more of Ni, Ti, Co, and Sn. x This indicates the number of Si atoms that are bonded to one A atom, 0.5 ≤ x ≤2.

[0108] By using a metal transition layer 60 in conjunction with a laser, it is possible to form an alloy including ASi. x While activating the doped atoms in the metal silicide transition layer 40 and the intermediate n-type doped polysilicon layer 24'', the damage of the laser to the intermediate n-type doped polysilicon layer 24'' can be effectively reduced.

[0109] Understandably, in step S28, the energy provided by the laser causes the elemental metal in the metal transition layer 60 to react with the silicon atoms on the surface of the intermediate n-type doped polycrystalline silicon layer 24'' to form ASi. x .

[0110] The main structural changes corresponding to steps S21 to S28 above are as follows: Figure 6 As shown.

[0111] Optionally, the second conductive region 12 has a pyramidal textured structure. After step 26 and before step 27, the process further includes step S26': laser treatment of the tip region of the p-type doped silicon-containing film 32 corresponding to the second conductive region 12, converting the tip region of the p-type doped silicon-containing film 32 from amorphous silicon to crystalline silicon. Specifically, the laser treatment conditions in step S26' may include a laser power of 5W to 10W. For example, the laser power can be 5W, 6W, 8W, or 10W, etc. Because the tip of the pyramidal textured structure has strong light absorption and the laser energy is easily focused, only a lower energy is needed to crystallize the tip. Furthermore, by controlling the laser power and focusing depth, the energy can be precisely reached to the tip crystallization threshold, reducing damage to the p-type doped silicon-containing film 32 caused by the laser.

[0112] More specifically, step S27 may include forming a metal transition layer 60 on the outer side of the n-type carrier collection layer 20 and the outer side of the p-type carrier collection layer 30. In an optional embodiment, step S28 involves laser irradiation of the metal transition layer 60 corresponding to the electrode contact region 21 of the first conductive region 11 to form a metal silicide transition layer 40 corresponding to the electrode contact region 21 of the first conductive region 11. In a preferred embodiment, step S28 involves laser irradiation of the metal transition layer 60 corresponding to the first conductive region 11 to form a metal silicide transition layer 40 corresponding to the first conductive region 11. Understandably, in the case of laser irradiation of the electrode contact region 21 corresponding to the first conductive region 11 in step S28, step S28 activates the doped atoms of the electrode contact region 21 in the intermediate n-type doped polysilicon layer 24'', while the doping concentration of the non-electrode contact region 22 in the intermediate n-type doped polysilicon layer 24'' remains unaffected. This reduces the contact resistance of the electrode contact region 21 while maintaining a low doping concentration in the non-electrode contact region 22, thereby reducing the parasitic absorption of the finally formed n-type doped polysilicon layer 24.

[0113] By combining steps S27 and S28, a metal transition layer 60 is formed on the outer side of the n-type carrier collection layer 20 and the outer side of the p-type carrier collection layer 30. The electrode contact area 21 or the entire first conductive region 11 is irradiated with a laser to transform the metal transition layer 60 corresponding to the electrode contact area 21 of the first conductive region 11 into a metal silicide transition layer 40, or the metal transition layer 60 corresponding to the first conductive region 11 into a metal silicide transition layer 40. Therefore, in the process of forming the metal silicide transition layer 40 for the first conductive region 11, the use of a mask layer and the removal of the mask layer by laser etching can be avoided, thereby avoiding film damage during the formation of the metal silicide transition layer 40.

[0114] In an optional embodiment, step S27 uses magnetron sputtering to form a metal transition layer 60. The control parameters of the magnetron sputtering include: magnetron sputtering power of 1kW to 3kW and working gas pressure of 0.5Pa to 1.0Pa. For example, the magnetron sputtering power can be 1kW, 1.5kW, 2kW, 2.5kW or 3kW, and the working gas pressure can be 0.5Pa, 0.8Pa or 1.0Pa, etc., to ensure the thickness of the formed metal transition layer 60.

[0115] Optionally, the laser conditions for irradiating the metal transition layer 60 in step S28 include: a laser wavelength of 532 nm or 1064 nm, and a laser power density of 1 × 10⁻⁶. 4 W / cm² ~ 1×10 5The laser power density is W / cm², the scanning speed is 300mm / s~1000mm / s, and the spot diameter is 10μm~50μm. For example, the laser power density for irradiating the metal transition layer 60 in step S28 can be 1×10⁻⁶. 4 W / cm², 3×10 4 W / cm², 5×10 4 W / cm², 8×10 4 W / cm² or 1×10 5 The laser energy can be controlled by the laser's power (W / cm²), scanning speed (300mm / s, 500mm / s, 800mm / s, or 1000mm / s), and spot diameter (10μm, 20μm, 30μm, 40μm, or 50μm). By controlling these laser conditions, on the one hand, the metal atoms in the metal transition layer 60 can react in situ with the silicon atoms in the intermediate n-type doped polysilicon layer 24'' to form a metal silicide transition layer 40. On the other hand, the laser energy can further activate the dopant atoms in the intermediate n-type doped polysilicon layer 24'' to form an n-type doped polysilicon layer 24. Simultaneously, it can prevent excessive laser energy from damaging the formed n-type doped polysilicon layer 24, thus ensuring that the n-type doped polysilicon layer 24 has good passivation performance.

[0116] In this process, steps S27 and S28 work together to form a metal silicide transition layer 40 in the electrode contact region 21 of the first conductive region 11, resulting in the following structural changes: Figure 7 As shown. Steps S27 and S28 work together to form a metal silicide transition layer 40 in the electrode contact region 21 and non-electrode contact region 22 of the first conductive region 11. The corresponding structural changes are as follows: Figure 8 As shown. Steps S27 and S28 work together to form a metal silicide transition layer 40 in the electrode contact region 21 and non-electrode contact region 22 of the first conductive region 11, and to form a metal transition layer 60 in the second conductive region 12. The corresponding structural changes are as follows: Figure 9 As shown. In addition, steps S27 and S28 can be combined to form a metal silicide transition layer 40 in the electrode contact region 21 of the first conductive region 11, and a metal transition layer 60 can be formed in the second conductive region 12 and the non-electrode contact region 22 of the first conductive region 11.

[0117] Further, step S3 also includes: simultaneously forming a transparent conductive film layer 50 in the second conductive region 12. Specifically, a transparent conductive film layer 50 is simultaneously formed in the first conductive region 11, the second conductive region 12, and the electrically isolated region 13, and a portion of the transparent conductive film layer 50 and a portion of the metal transition layer 60 in the electrically isolated region 13 are removed by laser etching to ensure electrical isolation between the metal silicide transition layer 40 of the first conductive region 11 and the metal transition layer 60 of the second conductive region 12.

[0118] Compared to existing technologies that use complex photolithography masks or selective deposition processes, the fabrication method provided in this embodiment of the invention, through the combination of steps S27 and S28, can avoid the use of a mask. Furthermore, the laser energy required for step S28 is far lower than that required for laser etching of the mask, thus avoiding laser damage to the film layer in step S28 and ensuring the formation of ASi. x The metal silicide transition layer 40.

[0119] Furthermore, in this embodiment of the invention, a metal transition layer 60 is formed in the first conductive region 11 and the second conductive region 12 in step S27, and a metal silicide transition layer 40 is formed in the first conductive region 11 in step S28. This allows oxygen to be used as the process gas in the subsequent step S3 to form the transparent conductive film layer 50. In this process, oxygen can be prevented from contacting the n-type carrier collection layer 20 and the p-type carrier collection layer 30, thereby preventing the formation of a silicon oxide layer on the surface of the n-type carrier collection layer 20 and the p-type carrier collection layer 30 that would lead to increased contact resistance. Therefore, in this embodiment of the invention, by combining steps S27, S28 and S3, the contact resistance of the formed back contact solar cell can be effectively reduced.

[0120] Furthermore, the above preparation method may also include: forming a first electrode 71 and a second electrode 72 in the first conductive region 11 and the second conductive region 12, respectively.

[0121] The technical solutions provided by the embodiments of the present invention will be described in detail below with specific examples and comparative examples.

[0122] Example: Step A: Select a single-crystal n-type silicon wafer with a bulk resistivity of 4.2 Ω·cm and a size of 182×182 mm.

[0123] Step B: Removal of the damaged layer on the silicon wafer surface. The silicon wafer is isotropically etched using a 25% sodium hydroxide alkaline solution, resulting in a weight reduction of more than 1.2 grams.

[0124] Step C: Form a tunneling silicon oxide layer on the entire surface of the silicon wafer. Using furnace tube oxidation, a silicon oxide layer with a thickness of 1.4 nm is prepared as the first tunneling passivation layer at an oxidation temperature of 590℃ and an oxidation time of 20 min.

[0125] Step D: Using low-pressure plasma chemical vapor deposition, at a deposition temperature of 610℃ and a deposition time of 36min, an intrinsic polycrystalline silicon layer with a thickness of 130nm is deposited on the surface of the first tunneling passivation layer of the silicon wafer.

[0126] Step E: Phosphorus doping is performed on the intrinsic polycrystalline silicon layer to prepare an n-type polycrystalline silicon layer. Using a furnace tube diffusion method, phosphorus diffusion is performed on the intrinsic polycrystalline silicon layer at a diffusion temperature of 890℃ and a diffusion time of 45 min to form a phosphorus-doped polycrystalline silicon layer and a phosphorus-doped silicon glass layer located outside the phosphorus-doped polycrystalline silicon layer.

[0127] Step F: Deposit a silicon nitride mask layer. A silicon nitride mask layer with a refractive index of 2.1 and a thickness of 30 nm is deposited using a tubular plasma-enhanced chemical vapor deposition system at a temperature of 50°C and a power of 20 kW.

[0128] Step G: Use a laser with a wavelength of 532 nm to etch the nitride mask layer corresponding to the second conductive region, and form a silicon oxide layer on the outside of the phosphorus-doped silicon glass layer.

[0129] Step H: Clean with 3% HF solution for 120 seconds to remove the silicon oxide layer and phosphorus-doped silicon glass layer formed in the second conductive region 12.

[0130] Step I: Cleaning and KOH texturing. A 1.5% (w / w) potassium hydroxide solution is used to remove the phosphorus-doped polysilicon layer and tunneling silicon oxide layer from the second conductive region 12, and the second conductive region 12 of the silicon wafer is then texturized. Next, an HF acid solution is used to clean the texturized silicon surface, simultaneously removing any remaining silicon nitride mask layer.

[0131] Step J: Complete the passivation of the front side of the silicon wafer: Using atomic vapor deposition, deposit an aluminum oxide layer with a thickness of 4nm as the front passivation layer on the front side of the silicon wafer; then deposit a silicon nitride layer with a thickness of 75nm as the anti-reflection layer on the surface of the aluminum oxide layer.

[0132] Step K, Wet cleaning: First, clean the wrap-around coating corresponding to the aluminum oxide layer and the wrap-around coating corresponding to the anti-reflective layer with a 5% HF solution. Then, clean with RCA (potassium hydroxide, hydrogen peroxide and hydrochloric acid) solution to remove organic contaminants, particulate impurities and metal ions, and remove the natural oxide layer on the back side with HF solution.

[0133] Step L: An intrinsic amorphous silicon layer with a thickness of 8 nm and a boron-doped silicon-containing film layer with a thickness of 20 nm are sequentially stacked on the outside of the second conductive region 12 and the remaining phosphorus-doped polycrystalline silicon layer.

[0134] Step M: Use a 532nm laser to remove the intrinsic amorphous silicon layer and boron-doped silicon film layer in the first conductive region, and clean the surface of the etched area with HF solution.

[0135] Step N: Using a solid-state laser with a wavelength of 532nm and a laser power of 7W, selectively irradiate the pyramid tip region of the second conductive region 12 to transform the tip of the boron-doped silicon film layer into nanocrystalline silicon.

[0136] Step O: In a magnetron sputtering apparatus, a 3 nm thick ultrathin nickel layer is deposited on the surface of the boron-doped silicon film layer and the remaining phosphorus-doped polycrystalline silicon layer in the second conductive region 12 by DC magnetron sputtering. The sputtering target is a 99.99% pure nickel target, the sputtering power is 2 kW, the working pressure is 0.6 Pa, the gas is pure argon, and the substrate temperature is 100 °C.

[0137] Step P: Use a fiber laser with a wavelength of 1064nm and a laser power density of 1×10⁻⁶. 5 The laser beam has a power density of W / cm², a spot diameter of 25 μm, and a scanning speed of 300 mm / s, selectively irradiating the first conductive region 11. The laser irradiation raises the temperature of the first conductive region 11 to 450°C and maintains it for about 0.3 seconds, promoting the reaction between nickel and n-type polycrystalline silicon to form nickel silicide, thereby forming a nickel silicide transition layer on the surface of the phosphorus-doped polycrystalline silicon layer.

[0138] Step Q: In the magnetron sputtering equipment, switch to a ceramic target with a mass ratio of In₂O₃:SnO₂ = 90:10, and perform radio frequency magnetron sputtering to deposit a 50 nm thick indium tin oxide layer as a transparent conductive film on the surface of the ultrathin nickel layer and the nickel silicide transition layer. The sputtering power is 6 kW, the working gas pressure is 0.5 Pa, the argon flow rate is 600 sccm, the oxygen flow rate is 10 sccm, and the substrate temperature is 100°C.

[0139] Step R: Use a laser with a wavelength of 325nm to etch the transparent conductive film layer at the interface between the first conductive region and the second conductive region, and remove the ultrathin nickel layer at the interface.

[0140] Step S: Conductive silver paste is applied to the first and second conductive regions respectively, and after drying and sintering, a back-contact heterojunction solar cell is obtained.

[0141] Comparative Example

[0142] The difference between this comparative example and the embodiment is that steps N to P are omitted, and a transparent conductive film with a thickness of 50 nm is directly deposited on the surface of the boron-doped silicon film layer and the surface of the phosphorus-doped polycrystalline silicon layer through step Q.

[0143] The photoelectric conversion efficiency and fill factor of the back-contact heterojunction solar cells prepared in the examples and comparative examples were detected using the IV detection method, and the contact resistance was detected using the linear transmission line model (TLM) method. In order to more intuitively show the difference between the detection results of the examples and the comparative examples, the detection results were normalized. The detection results of the back-contact heterojunction solar cells of the comparative examples were used as the benchmark, that is, the photoelectric conversion efficiency, fill factor and contact resistance of the detection results of the comparative examples were all taken as 100%. The photoelectric conversion efficiency, fill factor and contact resistance of the back-contact heterojunction solar cells of the examples after normalization were obtained using the following calculation formula (1).

[0144]

[0145] in, This represents the normalized value of any index (photovoltaic conversion efficiency, fill factor, or contact resistance) in the test results of the back-contact heterojunction solar cell of the embodiment. The term represents any one of the indicators (photovoltaic conversion efficiency, fill factor, or contact resistance) in the test results of the back-contact heterojunction solar cell of the embodiment. This represents any one of the test results (photovoltaic conversion efficiency, fill factor, or contact resistance) for a comparative example of a back-contact heterojunction solar cell. Understandably, For the photoelectric conversion efficiency of the embodiment, then The photoelectric conversion efficiency is for comparison. For the fill factor of the example, then The fill factor is for the comparison. For the contact resistance of the embodiment, then The contact resistance is shown as a comparative example. The normalized test results are shown in Table 1 below.

[0146] Table 1

[0147] As can be seen from Table 1, compared with the comparative example (existing technology), the back contact heterojunction solar cell prepared in the embodiment has a 2% increase in photoelectric conversion efficiency, a 2% increase in fill factor, and a 14% decrease in contact resistance. This indicates that the back contact heterojunction solar cell provided by the embodiment of the present invention can effectively improve photoelectric conversion efficiency and fill factor, and effectively reduce contact resistance.

[0148] The above steps are provided only to help understand the method, structure, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A back-contact heterojunction solar cell, characterized in that, include: The crystalline silicon substrate (10) has an alternating arrangement of a first conductive region (11) and a second conductive region (12) on its back side. An n-type carrier collection layer (20) is disposed in the first conductive region (11). The n-type carrier collection layer (20) includes an electrode contact region (21) and a non-electrode contact region (22). p-type carrier collection layer (30) is disposed in the second conductive region (12); A metal silicide transition layer (40) is provided at least outside the electrode contact region (21) of the n-type carrier collection layer (20), and the metal silicide transition layer (40) is not provided outside the p-type carrier collection layer (30). A transparent conductive film layer (50) is disposed in the first conductive region (11) and located outside the metal silicide transition layer (40), and is in contact with the metal silicide transition layer (40).

2. The back-contact heterojunction solar cell according to claim 1, characterized in that, The transparent conductive film layer (50) is also disposed on the outside of the p-type carrier collection layer (30). The transparent conductive film layer (50) disposed on the outside of the p-type carrier collection layer (30) and the transparent conductive film layer (50) disposed on the outside of the metal silicide transition layer (40) are disconnected between the first conductive region (11) and the second conductive region (12). Optionally, the back-contact heterojunction solar cell further includes a metal transition layer (60). The metal transition layer (60) is disposed between the p-type carrier collection layer (30) and the transparent conductive film layer (50), and is in contact with the p-type carrier collection layer (30) and the transparent conductive film layer (50); Optionally, the metal transition layer (60) is also disposed between the outside of the non-electrode contact area (22) of the n-type carrier collection layer (20) and the transparent conductive film layer (50), and is in contact with the non-electrode contact area (22) of the n-type carrier collection layer (20) and the transparent conductive film layer (50); Optionally, the back-contact heterojunction solar cell further includes: a first electrode (71) and a second electrode (72). The first electrode (71) is disposed on the outside of the transparent conductive film layer (50) of the electrode contact area (21); The second electrode (72) is disposed on the outside of the transparent conductive film layer (50) of the second conductive region (12).

3. The back-contact heterojunction solar cell according to claim 1, characterized in that, The metal silicide transition layer (40) is also disposed outside the non-electrode contact region (22) of the n-type carrier collection layer (20); And / or, The metal silicide transition layer (40) includes ASi x Where A represents one or more of Ni, Ti, Co, and Sn, and 0.5 ≤ x ≤2; Optionally, the metal silicide transition layer (40) comprises NiSi. x 0.5≤ x ≤2; Optionally, the metal silicide transition layer (40) is made of NiSi. x constitute.

4. The back-contact heterojunction solar cell according to claim 1 or 3, characterized in that, The thickness of the metal silicide transition layer (40) is 2nm~15nm; And / or, The work function of the metal silicide transition layer (40) is 4.3 eV to 4.6 eV; And / or, The metal silicide transition layer (40) and the n-type carrier collection layer (20) form an ohmic contact with an electron injection potential barrier of less than 0.2 eV; And / or, The interfacial contact resistance between the metal silicide transition layer (40) and the n-type carrier collection layer (20) is less than 10 Ω. -4 Ω·cm².

5. The back-contact heterojunction solar cell according to claim 2, characterized in that, The thickness of the metal transition layer (60) is 1 nm to 10 nm; And / or, The metal transition layer (60) includes one or more elemental metals selected from Ni, Ti, Co and Sn; Optionally, the metal transition layer (60) is composed of one or more elemental metals selected from Ni, Ti, Co and Sn; Optionally, the metal transition layer (60) is composed of elemental Ni; And / or, The work function of the metal transition layer (60) is 4.9 eV to 5.2 eV; And / or, The metal transition layer (60) and the p-type carrier collection layer (30) form an ohmic contact with a hole injection potential barrier of less than 0.2 eV; And / or, The interfacial contact resistance between the metal transition layer (60) and the p-type carrier collection layer (30) is less than 10 Ω. -4 Ω·cm².

6. The back-contact heterojunction solar cell according to any one of claims 1 to 5, characterized in that, The n-type carrier collection layer (20) includes a first tunneling passivation layer (23) and an n-type doped polycrystalline silicon layer (24) stacked from the inside to the outside; the p-type carrier collection layer (30) includes a second intrinsic amorphous silicon layer (31) and a p-type doped silicon-containing film layer (32) stacked from the inside to the outside. or, The n-type carrier collection layer (20) includes a first intrinsic amorphous silicon layer and an n-type doped silicon-containing film layer stacked from the inside to the outside; the p-type carrier collection layer (30) includes a second intrinsic amorphous silicon layer (31) and a p-type doped silicon-containing film layer (32) stacked from the inside to the outside, or the p-type carrier collection layer (30) includes a second tunneling passivation layer and a p-type doped polycrystalline silicon layer stacked from the inside to the outside; Optionally, the p-type doped silicon-containing film (32) is a p-type doped amorphous silicon layer or the p-type doped silicon-containing film (32) includes nanoscale crystalline silicon particles and amorphous silicon; Optionally, the p-type doped silicon-containing film layer (32) has a textured structure. Optionally, the top of the textured structure of the p-type doped silicon-containing film layer (32) is crystalline silicon, and the bottom and body are amorphous silicon. And / or, The first conductive region (11) and the second conductive region (12) are either intersecting structures or strip structures.

7. The back-contact heterojunction solar cell according to any one of claims 1 to 5, characterized in that, The widths of the first conductive region (11) and the second conductive region (12) are 100μm~500μm; And / or, The back-contact heterojunction solar cell further includes: an electrical isolation region (13). The electrical isolation region (13) is disposed between the adjacent first conductive region (11) and second conductive region (12); The n-type carrier collection layer (20) and the p-type carrier collection layer (30) extend to the electrically isolated region (13), and in the electrically isolated region (13), the p-type carrier collection layer (30) is stacked and electrically isolated from the n-type carrier collection layer (20); Optionally, the width of the electrical isolation region (13) is 50μm~200μm; And / or, The back-contact heterojunction solar cell further includes a passivation antireflection layer (90) disposed on the front side of the crystalline silicon substrate (10).

8. A method for fabricating a back-contact heterojunction solar cell, characterized in that, include: Step S1: Provide a crystalline silicon substrate (10), the back side of which includes alternating first conductive regions (11) and second conductive regions (12). Step S2: An n-type carrier collection layer (20) is formed in the first conductive region (11), and a p-type carrier collection layer (30) is formed in the second conductive region (12), wherein the n-type carrier collection layer (20) includes an electrode contact region (21) and a non-electrode contact region (22); at least a metal silicide transition layer (40) is formed in the electrode contact region (21), and the metal silicide transition layer (40) is not formed on the outside of the p-type carrier collection layer (30); Step S3: A transparent conductive film layer (50) is formed in the first conductive region (11). The transparent conductive film layer (50) is located outside the metal silicide transition layer (40) and is in contact with the metal silicide transition layer (40).

9. The preparation method according to claim 8, characterized in that, Step S2 includes: Step S21: A first tunneling passivation layer (23), an initial n-type doped polycrystalline silicon layer (24'), and a mask layer (81) are sequentially stacked on the back side of the crystalline silicon substrate (10); Optionally, the mask layer (81) is a silicon nitride layer with a refractive index of 2.1 and a thickness of 30nm~50nm. Step S22: Use laser etching to remove the mask layer (81) corresponding to the second conductive region (12), and form a silicon oxide layer (82) on the outside of the initial n-type doped polysilicon layer (24') corresponding to the second conductive region (12). Step S23: The silicon oxide layer (82) is removed by cleaning with HF solution, and the initial n-type doped polysilicon layer (24'), the first tunneling passivation layer (23) and part of the crystalline silicon substrate (10) corresponding to the second conductive region (12) are removed by cleaning with alkaline solution. Step S24: Use HF solution to clean and remove the remaining mask layer (81). Step S25: A second intrinsic amorphous silicon layer (31) and a p-type doped silicon-containing film layer (32) are sequentially stacked on the outside of the second conductive region (12) and the remaining initial n-type doped polycrystalline silicon layer (24'). Step S26: Use laser etching to remove the p-type doped silicon film layer (32) and the second intrinsic amorphous silicon layer (31) corresponding to the first conductive region (11), and activate some doped atoms in the initial n-type doped polycrystalline silicon layer (24') to form an intermediate n-type doped polycrystalline silicon layer (24''). Step S27: Form a metal transition layer (60) at least in the electrode contact area (21); Step S28: Irradiate at least the metal transition layer (60) corresponding to the electrode contact region (21) with a laser to form an ASi layer. x The metal silicide transition layer (40) is further activated to activate the doped atoms in the intermediate n-type doped polysilicon layer (24'') to form an n-type doped polysilicon layer (24), where A represents one or more of Ni, Ti, Co and Sn, and 0.5 ≤ x ≤2; Optionally, the second conductive region (12) is a pyramidal textured structure. After step S26 and before step S27, the method further includes: step S26', using laser processing to treat the apex region of the p-type doped silicon-containing film layer (32) corresponding to the second conductive region (12), so that the apex region of the p-type doped silicon-containing film layer (32) is converted from amorphous silicon to crystalline silicon.

10. The preparation method according to claim 9, characterized in that, Step S27 includes: forming a metal transition layer (60) on the outside of the n-type carrier collection layer (20) and the outside of the p-type carrier collection layer (30); Optionally, step S28 includes: irradiating the metal transition layer (60) corresponding to the first conductive region (11) with a laser to form a metal silicide transition layer (40) corresponding to the first conductive region (11). Optionally, step S27 uses magnetron sputtering to form a metal transition layer (60), wherein the control parameters of magnetron sputtering include: magnetron sputtering power of 1kW~3kW and working gas pressure of 0.5Pa~1.0Pa; Optionally, the laser conditions for irradiating the metal transition layer (60) in step S28 include: a laser wavelength of 532 nm or 1064 nm, and a laser power density of 10. 4 ~10 5 W / cm², scanning speed of 300 mm / s ~ 1000 mm / s, spot diameter of 10 μm ~ 50 μm; Optionally, step S3 further includes: simultaneously forming a transparent conductive film layer (50) in the second conductive region (12).

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