Single photon avalanche diode and pixel array with stepped optical aperture

Abstract

This invention discloses a CMOS single-photon avalanche diode and pixel array with stepped optical apertures, belonging to the field of semiconductor optoelectronic devices. To achieve decoupling of photoelectric control without requiring special processes such as microlenses, the single-photon avalanche diode of this invention comprises two, three, or more metal layers on one side of the photosensitive absorption region formed on the substrate, with openings formed between the same metal layers; along the accumulation direction of the metal layers, the area of ​​the openings in different metal layers gradually increases or increases in a stepped manner; and only interlayer dielectrics are present between different metal layers. This invention can decouple photoelectric control, achieving enhanced photon counting and detection by controlling the optical propagation and absorption stages, avoiding a simultaneous increase in DCR when improving the PDP.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more specifically to a single-photon avalanche diode and pixel array with a stepped optical aperture. Background Technology

[0002] A single-photon avalanche diode (SPAD) is a photodetector operating in Geiger mode, a special operating mode of APDs. It can detect a single photon and is a core device for weak light and single-photon detection. While ordinary APDs operate at a voltage below their breakdown voltage, SPADs apply a reverse bias (overbias) higher than their breakdown voltage, hence the term Geiger mode.

[0003] The photon detection probability (PDP) of a SPAD depends on the absorption of incident light in the semiconductor, the transport and collection of photogenerated carriers, and the probability of carrier-triggered avalanche. A front-illuminated CMOS SPAD has multiple back-end metal and dielectric layers above it, which alter the light field reaching the silicon photosensitive region through reflection, diffraction, and interference.

[0004] Existing technologies for improving optical coupling include enlarging single-layer openings, microlenses / light pipes, back-illumination processes, and modifying the junction region of front-end devices, but all of these have significant drawbacks.

[0005] (1) Microlenses and independent light tubes: Although they can improve the fill factor or focusing efficiency, they increase the cost of additional materials, processes, alignment and packaging.

[0006] (2) Modify the front-end device structure and back-illumination process: Although the spectral response and quantum efficiency can be changed, the breakdown voltage, dark count rate (DCR), junction capacitance and other electrical parameters will be changed simultaneously, and the optical effect and electrical effect cannot be decoupled.

[0007] In addition, although there are some multi-layer metal aperture schemes in the existing technology, which have the same or common narrowing of the openings in each layer, most of them are used to reduce the light intensity of the light-passing aperture, suppress stray light, reduce crosstalk, and improve the dynamic range, but none of them are used to improve the light absorption of the active area and the PDP.

[0008] Prior Art 1: US20200168748A1, Single Photon Avalanche Diode And Array Of SinglePhoton Avalanche Diodes, 2020.05.28

[0009] Prior art 2: WO2020083606A1, Optical Sensor Device And Method For Manufacturing AnOptical Sensor Device, 2020.4.29

[0010] Existing technology 3: C. Lee, B. Johnson, T. Jung, and A. Molnar, A 72 × 60 angle-sensitive SPAD imaging array for lens-less FLIM. Sensors, vol. 16, no. 9, Art. no. 1422, Sep. 2016

[0011] Existing technology 4: CN109148637B, Single-photon avalanche diode detector with stepped grating structure and its fabrication method, 2020.10.02

[0012] Prior Art 5: CN104900748B, A vertically incident avalanche photodiode with unequal photoelectric aperture, 2015.09.09

[0013] Existing technology 1 employs a bimetallic stacked structure to construct a miniaturized effective aperture, solving the problem of insufficient optical control precision in traditional SPADs and achieving a higher linear dynamic range and stronger resistance to off-axis light interference. Existing technology 2 solves the optical crosstalk problem by setting a via (VIA) structure surrounding the photosensitive region in the metal layer, achieving optical path isolation and improved signal purity. Existing technology 3 discloses an angle-sensitive SPAD comprising: a SPAD that provides precise photon arrival time through time-resolved operation to avoid stimulation-induced saturation; and a diffraction grating integrated on top of the SPAD for extracting the angle information of the incident light. This structural combination enables micron-level precision three-dimensional spatial mapping of fluorescence sources with different lifetimes. Existing technology 4 sets a five-level stepped grating structure within the metal isolation dielectric region, forming transmission windows through different refractive indices and utilizing the optical diffraction effect to enhance the photon generation rate in the avalanche region. This structure is compatible with standard CMOS processes, achieving a SPAD detector with high integration, low power consumption, and strong anti-interference capabilities. Existing technology 5 solves the problem that traditional APDs, which have difficulty balancing light input efficiency and performance due to the consistency of optical and electrical apertures, by designing unequal photoelectric aperture structures in vertical avalanche photodiodes, and achieves a synergistic improvement in high sensitivity and wide bandwidth.

[0014] In SPADs, the front-end FEOL determines the electrical characteristics (avalanche junction, doping, junction depth, guard ring), while the back-end BEOL metallic dielectric optical structure is responsible for optical field modulation. If improvements to optical performance necessitate modifications to the front-end device, it means that optical and electrical characteristics are deeply intertwined and cannot be decoupled. If the optical structure cannot be decoupled from the SPAD's front-end electrical structure, optimizing the photon detection response will simultaneously alter electrical properties such as the avalanche junction, doping, and junction depth. This makes it difficult to distinguish whether the performance improvement originates from optical modulation or changes in electrical parameters. It can also lead to a degradation of noise indicators such as dark count rate, a shift in the operating point such as breakdown voltage, increased tape-out iteration costs, and hinders comparative verification of multiple optical schemes on a unified electrical substrate.

[0015] In summary, existing technologies that improve optical coupling by modifying only the back-end BEOL require special processes, which are difficult and costly; while modifying the front-end FEOL results in the inability to control and decouple photoelectric coupling.

[0016] How to achieve decoupling of photoelectric control without requiring special processes (microlenses, light tubes, etc.) is an important technical challenge in this field. Summary of the Invention

[0017] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows:

[0018] A single-photon avalanche diode: one side of the photosensitive absorption region formed on the substrate includes two, three or more metal layers, and an opening is formed between the same metal layer; along the accumulation direction of the metal layers, the area of ​​the openings of different metal layers gradually increases or increases in a stepwise manner; and the different metal layers contain only an interlayer dielectric.

[0019] Preferably, the stepwise increase specifically refers to:

[0020] - The area of ​​the openings corresponding to different metal layers increases monotonically; or,

[0021] - The area of ​​the openings corresponding to different metal layers increases overall, but the area of ​​the openings corresponding to some adjacent metal layers is equal.

[0022] Preferably, the multilayer metal layers include a layer that does not contain any metal layers;

[0023] The layer without a metal layer contains:

[0024] - A medium with the same composition as the interlayer medium; or / and

[0025] - Components other than the interlayer medium that have the same composition.

[0026] Preferably, the center of the opening corresponding to the metal layer:

[0027] - Coaxial; or,

[0028] - At least partially different axes.

[0029] Preferably, the centers of the openings corresponding to the metal layer are at least partially off-axis and offset in one direction.

[0030] Preferably, the shape of the opening is one of the following: circular, elliptical, square, rectangular, polygonal, annular, or irregular.

[0031] Preferably, the angle between the line connecting the edge of the metal layer near the opening and the normal to the substrate is greater than 0° and less than or equal to 60°.

[0032] Preferably, the area where the opening is located:

[0033] - Contains interlayer medium; or

[0034] - Hollowed-out design.

[0035] Preferably, the single-photon avalanche diode is manufactured using one of the following processes:

[0036] Standard CMOS process, CIS process, BCD process, compound semiconductor process, and custom non-standard process.

[0037] A pixel array, wherein at least a portion of the pixels in the pixel array comprises a single-photon avalanche diode as described in any of the preceding claims.

[0038] Preferably, at least some pixels in the pixel array each have several metal layers that use different aperture sequences.

[0039] Preferably, the same sequence of apertures is used in the metal layers of each pixel in the pixel array.

[0040] The technical solution of this invention has one or more of the following beneficial technical effects:

[0041] 1. Achieving relative decoupling between the optical structure and the front-end electrical structure, meaning that optical coupling performance and PDP can be improved simply by modifying the BEOL, without needing to change the FEOL. In one example, the four sets of verification samples of this invention all adopted completely identical SPAD FEOL electrical structures, approximately 10μm photosensitive regions, and uniform electrical operating conditions. Only the geometry of the rear-end optical opening composed of the M3~M6 metal layers and dielectric layers was used as the experimental variable. Thus, the performance differences between the samples can directly characterize the modulation effect brought about by the rear-end optical structure.

[0042] 2. Improved photon detection response and effective enhancement of PDP. In one example, under test conditions of 25°C, 500nm vertical incidence, 0.6V overbias, and monochromator collimated spot, the PDP of the stepped aperture sample can achieve a relative improvement of 50%~55% compared to the 0° control group. Combined with 10nm step spectral scanning results, it can be confirmed that this multilayer back-end metal stepped optical aperture can effectively modulate and enhance the optical detection response of CMOS SPAD.

[0043] 3. The dark count rate (DCR) does not increase proportionally with the photodiode density (PDP). Typically, the DCR increases synchronously with the PDP. However, in this invention, since the device body structure, doping distribution, avalanche junction depth, and other electrical-related core parameters of each sample group can remain unchanged (this invention allows modifications to only occur in the BEOL to improve the PDP), the electrical noise characteristics such as the dark count are not affected by changes in the optical structure, further verifying the optical-electrical structure decoupling effect of this invention. The change in PDP performance originates entirely from the modulation of the incident light propagation behavior by the back-end metal dielectric stack, thereby altering the light absorption level within the active photosensitive silicon region.

[0044] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of SPAD in the prior art;

[0046] Figure 2 This is another structural diagram of SPAD in the prior art;

[0047] Figure 3 This is a schematic diagram of the SPAD structure in the first embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the SPAD structure in the second embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the SPAD structure in the third embodiment of the present invention;

[0050] Figure 6 This is the absorption diagram of the 500nm wavelength photosensitive absorption region of the example structure obtained from simulation;

[0051] Figure 7 This is a photon detection probability map obtained by testing with a collimated light source at an actual room temperature of 25 degrees Celsius.

[0052] Figure 8 This is a flowchart of the SPAD back-end stepped optical aperture design method;

[0053] Figure 9 This is a flowchart of the combined electrical and electromagnetic simulation.

[0054] Figure 10 This is a schematic diagram of the structure of the metal layer in several alternative embodiments of the present invention;

[0055] Figure 11 This is a schematic diagram of the opening region in one type of embodiment of the present invention;

[0056] Figure 12 This is a photograph of the actual object corresponding to one embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0058] In the description of this invention, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this invention is merely a description of the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural.

[0059] In the description of this invention, unless otherwise stated, "a plurality of" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0060] Furthermore, to facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0061] In the embodiments of the present invention, the words "exemplarily," "for example," etc., are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "exemplarily" or "for example" in the embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the words "exemplarily," "for example," etc., is intended to present the relevant concepts in a specific manner for ease of understanding.

[0062] This invention relates to some English abbreviations and full names, and their Chinese translations:

[0063] SPAD: Single-Photon Avalanche Diode

[0064] APD: Avalanche PhotoDiodes

[0065] PDP: Photon Detection Probability

[0066] DCR: Dark Count Rate

[0067] DRC: Design Rule Check

[0068] FEOL: Front-End-Of-Line, the front-end process (wafer front-end process, the part of semiconductor device manufacturing such as active regions, wells, and junctions).

[0069] BEOL: Back-End-Of-Line, referring to back-end processes (back-end metal interconnects and dielectric layer processes).

[0070] GDS: Graphic Data System (an integrated circuit layout tape-out file format).

[0071] CMOS: Complementary Metal-Oxide-Semiconductor

[0072] VIA: Via hole, through hole

[0073] PDK: Process Design Kit

[0074] COMSOL: COMSOL Multiphysics, a multiphysics simulation software.

[0075] PML: Perfectly Matched Layer

[0076] STI: Shallow Trench Isolation

[0077] LVS: Layout Versus Schematic, Layout Principles Figure 1 Adaptability test

[0078] Terminology Explanation:

[0079] Metal Layer: In SPADs, the metal layer primarily serves electrical functions such as wiring and electrode interconnection. Metal materials are opaque to visible light; only the optical openings created by removing metal patterns allow incident light to propagate downwards to the silicon photosensitive region. The interfaces between multiple metal layers and their dielectric layers introduce reflection, diffraction, and interference optical effects. The concept of a metal layer in this invention does not extend to the dielectric layer that encapsulates it.

[0080] Edge line: A line connecting the edges of the metal layers closest to the opening on the whole. For example, a point on the top of the metal layer closest to the opening can be chosen as the point for constructing the line. In actual physical manufacturing, there are many non-ideal factors, so reasonable errors are allowed for the edge line here. For embodiments applying the present invention, if the areas of the openings corresponding to some adjacent metal layers are equal, the overall line is determined by the two metal layers on the top and bottom sides.

[0081] Bottom limiting opening: The opening formed by the bottom metal layer for optical modulation, which is an innovative design of this invention.

[0082] Along the accumulation direction of the metal layer: the direction in which multiple metal layers are formed on the substrate, which is opposite to the incident direction of light and in the same direction as the direction that is simultaneously away from the photosensitive absorption region and the substrate.

[0083] Optoelectronic decoupling: This refers to the decoupling of optoelectronic control, which in this invention means modifying / adjusting only the BEOL without adaptively and synchronously modifying / adjusting the FEOL. In other words, this invention only adjusts the optical absorption portion while maintaining the electrical characteristics unchanged.

[0084] PDP represents the probability that a device will successfully output a pulse when an incident photon is emitted, while DCR represents the count of erroneous pulses emitted by the device under no illumination conditions. This count originates from noise such as thermal excitation and tunneling. The higher the DCR, the greater the noise, which is a negative indicator.

[0085] Bottom / Bottom / Top / Top: For ease of description, this invention conventionally refers to the side closer to the substrate as the "bottom side" or "bottom," and the side that approaches the incident light earlier as the "top side" or "top." Along the direction of incident light, the light rays travel from the top to the bottom.

[0086] Figure 1This is a schematic diagram of the structure of a SPAD in the prior art. A SPAD consists of two main parts: FEOL and BEOL.

[0087] FEOL can be constructed using a P-type substrate, with a deep N-well, a layer of N-wells, P-wells, N-wells, P-wells, and another layer of P+ regions, STIs, N+ regions, STIs, P+ regions, STIs, N+ regions, STIs, and P+ regions built sequentially along the opposite direction of the incident light. The last two layers are centered on the P+ region and N-well (which constitute the photosensitive absorption region), with the other regions arranged symmetrically around the central area. FEOL can also be constructed using any other arrangement.

[0088] In one embodiment, the SPAD in this invention can also be adopted. Figure 1 The FEOL shown is irrelevant and will not be discussed further below.

[0089] In some existing technologies, BEOL may also involve multiple metal layers. Figure 1 The example shows metal layer 1 (denoted as M1, hereinafter the same), metal layer 2 (M2), metal layer 3 (M3), metal layer 4 (M4), metal layer 5 (M5), and metal layer 6 (M6). Metal layers with the same designation are located in the same layer, and the layer may also include an interlayer medium.

[0090] A metal layer M1 can also be placed between M2 and FEOL. M1 can be discrete and discontinuous. M1 can be located anywhere reasonable below M2. Electrical connections between FEOL and M1, and between M1 and M2, can be established using through-holes (VIA).

[0091] Figure 2 This is another schematic diagram of a SPAD structure in the prior art. In the prior art, even if multiple metal layers are included, and an opening is formed between the same metal layer to receive incident light, the edge line of the metal layer near the opening and the normal line perpendicular to the substrate overlap, or in other words, the angle between them is 0°.

[0092] M6, located on the same floor, has an opening 6 between it and another opening 5. This continues until M2, also on the same floor, has an opening 2 between it and another opening. However, the areas (diameters, distances, etc.) between these openings are equal.

[0093] The present invention discloses a single-photon avalanche diode:

[0094] - The photosensitive absorption region formed on the substrate includes two, three or more metal layers on one side, and an opening is formed between the same metal layers;

[0095] - Along the accumulation direction of the metal layers, the area of ​​the openings in different metal layers gradually increases or increases in a stepwise manner; and,

[0096] - The different metal layers contain only an interlayer medium.

[0097] In one embodiment, the top of the SPAD disclosed in this invention also includes a passivation layer.

[0098] In one embodiment, the interlayer medium of the present invention may be, but is not limited to, silicon oxide, silicon nitride, etc.

[0099] In this invention, when using standard CMOS technology, aluminum, aluminum-copper alloy, copper, and tungsten are commonly used as metal layers, and the top layer can be made of thick aluminum metal.

[0100] This invention utilizes the opening geometry of metal layers with different heights to intentionally employ reflection, diffraction, and interference to modulate the light absorption inside silicon without altering the silicon device, thereby increasing the photon detection probability of the PDP and achieving control over the incident light field without modifying the internal SPAD avalanche junction device of silicon.

[0101] One of the advantages of this invention is that it can be implemented entirely on standard process platforms (such as standard CMOS processes), without requiring any customization of the foundry's basic manufacturing processes, and is compatible with the standard foundry service models of mainstream foundries. Specifically, all FEOL device structures and process parameters of the SPAD, including avalanche junction, doping distribution, junction depth, well structure, and isolation structure, directly adopt the standard design of the target process node, without modifying any foundry-fixed process parameters such as doping concentration, implantation conditions, and epitaxial thickness, and without needing to apply for process customization permissions. All optical performance control is achieved by modifying the opening geometry (size, shape, center position, interlayer combination) of the back-end metal interconnect layer, which is a pure layout-level design change, completely limited to the PDK process design rules and DRC checks provided by the foundry. Therefore, several other details of this SPAD will be described in detail later.

[0102] Figure 3 This is a schematic diagram of the SPAD structure in the first embodiment of the present invention. In this embodiment, the angle β between the normal of the substrate and the line connecting the edge of the metal layer near the opening side is 10° (10-degree tilted optical opening).

[0103] In this embodiment, for several layers (not necessarily all layers) in the BEOL, the metal layers (M2~M6) contained therein only contain interlayer dielectric. In other words, apart from the interlayer dielectric, there are no other components, such as VIA, between the metal layers (not extending to the opening area).

[0104] In this embodiment, M1 does not participate in the construction of the stepped optical opening, therefore the limitation of only including interlayer medium does not include the layer containing M1.

[0105] In this embodiment, starting from the bottom metal layer 2 and moving up to the top metal layer 6, the edge near the opening gradually moves away from the opening. This results in a gradual increase in the diameter and distance of the openings (M6-M6, M5-M5, etc.), leading to a gradual increase in the opening area. In this embodiment, the opening area increases in a step-like manner. That is, the openings 2 between M2, 3 between M3, ..., and 6 between M6 increase discretely each time, similar to the change in the height of a staircase. In other words, in this embodiment, the opening area of ​​the metal layers increases monotonically in a step-like manner from bottom to top.

[0106] Furthermore, in some embodiments of the present invention, metal layer 1 (M1) is allowed to be the first metal layer for CMOS back-end interconnection, adjacent to the FEOL silicon device, and locally led out and short-distance interconnected with electrodes such as SPAD avalanche junctions and guard rings through contact holes. As an electrode for electrical interconnection devices, M1 is typically not optically modulated. M1 directly contacts the doped regions of the SPAD anode, cathode, guard ring, etc., on the silicon substrate through contact holes, and is located directly above the avalanche junction silicon surface, serving as the first conductive layer connecting the silicon device to the upper metal network. The presence or design of M1 is generally a conventional design in the art, and the present invention will not elaborate on or limit it further.

[0107] In this embodiment of the invention, the bottom limiting opening is determined by M2, which is the only one closest to the photosensitive absorption region and is used for optical modulation, rather than M1. Electrical connections can be established between M1 and FEOL, and between M1 and M2, via VIA.

[0108] Figure 4 This is a schematic diagram of the SPAD structure in the second embodiment of the present invention. In this embodiment, the angle β' between the normal of the substrate and the line connecting the edge of the metal layer near the opening side is 15° (15-degree tilted optical opening).

[0109] Compared with the first embodiment, the only difference between the two is the size of the included angle.

[0110] Figure 5 This is a schematic diagram of the SPAD structure in the third embodiment of the present invention. In this embodiment, the angle β'' between the normal of the substrate and the line connecting the edge of the metal layer near the opening side is 20° (20-degree tilted optical opening).

[0111] Compared with the first and second embodiments, the only difference among the three is the size of the included angle. For example, the included angle can also be other values, such as 30°, 40°, 45°, 50°, or 60°. Considering factors such as manufacturing process, the included angle in this invention is greater than 0° and less than or equal to 60°.

[0112] In a simulation example, the three embodiments of the present invention described above are compared. Figure 2 The existing technology represented (control group) was analyzed. All four schemes:

[0113] - Front-illuminated standard CMOS SPAD with a 180nm design;

[0114] - Uses the same avalanche knot, protective ring, contact structure, and approximately 10 μm active photosensitive region;

[0115] - No VIA within the optical channel;

[0116] - The outer metal components complete the necessary electrical connections and meet DRC requirements;

[0117] - The absolute height, thickness, and process tolerances of each selected metal interconnect layer and dielectric layer shall comply with the requirements of the process PDK.

[0118] To obtain information about the photosensitive absorption region, the inventors built a COMSOL simulation model based on the aforementioned process stack-up information. Multiphysics simulations were conducted using the frequency domain electromagnetic waves (Frequency Domain) and semiconductor physics interface of COMSOL 6.2 software. The simulation model fully reproduces the structure of the silicon substrate, interlayer dielectric, selected back-end conductive metal layer, and top passivation layer. The metal material can be characterized using an ideal perfect conductor model or the Johnson complex permittivity model. The simulation excitation was set to 500nm perpendicularly normal incident plane light, and the computational domain boundary combination employed a PML perfectly matched layer and scattering boundary conditions. Local mesh refinement was performed at the metal opening edges, dielectric film interfaces, and the silicon active photosensitive region to ensure computational accuracy in critical areas.

[0119] The core evaluation metrics extracted by the simulation include the absorption power, normalized absorptivity, and photogenerated carrier generation distribution within the active silicon volume. It can also output field information such as electric field distribution, Poynting energy flow, and absorption density.

[0120] Figure 6 The image shows the absorption diagram of the 500nm wavelength photosensitive absorption region of the example structure obtained from simulation. Part (a) corresponds to the vertical opening in the prior art, part (b) corresponds to the 10-degree tilted optical opening, part (c) corresponds to the 15-degree tilted optical opening, and part (d) corresponds to the 20-degree tilted optical opening. Figure 6 The bottom represents the normalized silicon absorption density.

[0121] Simulation results show that, compared with the 0° control sample, the light absorption distribution inside the active silicon of the stepped opening structure under 500nm incident conditions is significantly different. The simulation results of the absorption characteristics of this silicon region can reasonably explain and verify the trend of photon detection probability (PDP) changes obtained by actual chip measurement.

[0122] In addition, the inventors conducted a comparative test experiment on the PDP. In the experiment, four groups of samples were placed on a unified testing platform for comparative testing. The testing environment was set at 25℃, and the device operating conditions were selected as 0.6V over-bias and passive quenching mode. A calibrated light source was used for the test, and the count rate under illumination and dark conditions was collected respectively. Then, following a predetermined testing procedure, the incident light power was converted into the photon flux acting on the effective area of ​​the device. During the test, necessary data corrections were made for influencing factors such as dead time, after-pulse effect, ambient background light, and light spot coverage deviation. In this test, the effective light-receiving area of ​​the SPAD was defined as the area of ​​the active photosensitive region of the device. Commercial phototubes were used to calibrate the light power at different wavelengths, and the incident photon count was further calculated.

[0123] Figure 7 This is a photon detection probability diagram obtained using a collimated light source at an actual room temperature of 25 degrees Celsius. The experimental conditions were set with a breakdown voltage of 10.67V and an overbias voltage of 0.6V. The diagram reveals significant differences between this invention and existing technologies regarding the photon detector (PDP) in the 460nm–660nm wavelength range, particularly in the 480nm–580nm wavelength range.

[0124] Actual measurements show that, under vertical incidence conditions, the ratio of photon detection probability (PDP) of the stepped-opening sample to the 0° control group is approximately 1.53-1.55.

[0125] Figure 8 This is a flowchart of a stepped optical aperture design method for the back end of a SPAD, especially for standard CMOS processes. To optimize the optical field modulation effect of the multi-layer metal aperture at the back end without altering the front-end electrical structure of the SPAD, this invention also discloses a systematic design process that fixes the front-end device substrate and optimizes the back-end optical geometry through simulation. The complete process consists of six stages:

[0126] Phase 1: Acquire and lock all basic parameters of the target CMOS process, including the FEOL SPAD device structure, active photosensitive area size, height and thickness of each metal layer at the back end, optical parameters of the interlayer dielectric, passivation layer parameters, and layout design rules, as fixed constraints for subsequent optical design to ensure decoupling of the optical structure from the front-end electrical structure.

[0127] Phase 2: Define the optical operating conditions for the target application scenario, including the target wavelength / band, incident angle range, polarization state, and spot range; at the same time, clarify the design objectives, namely, to maximize, minimize, or shape specific waveforms of the optical response.

[0128] Phase 3: Parametric generation of candidate aperture sequence: Select metal layers for optical control from the available back-end conductive layers. Parametrically model the size, shape, center offset, layer selection combination, and VIA ban area of ​​each layer aperture to generate multiple sets of candidate aperture schemes that meet the minimum line width, line spacing, metal density, and wiring rules.

[0129] Phase 4: Conduct electromagnetic simulations for each candidate structure to calculate core optical quantities such as absorption power, normalized absorptivity, and photogenerated carrier generation distribution within the active silicon volume; if it is necessary to directly predict the photon detection probability (PDP), carrier transport / collection probability and avalanche triggering probability models can be further superimposed, and the model inputs, boundary conditions, and parameter sources can be clearly defined.

[0130] Phase 5: Using the active silicon absorption or PDP under target wavelength, angle, and polarization conditions as the objective function, and simultaneously applying engineering constraints such as DRC design rules, metal density, interconnect wiring, and pixel fill factor, the candidate aperture sequence is screened or iteratively optimized to obtain the optimal aperture combination.

[0131] Phase 6: Output the final GDS or mask layout, complete DRC / LVS checks and optical structure verification; and use a control sample with the same FEOL for fabrication, and verify the actual effect of the design through PDP, DCR, spectral response and angular response tests.

[0132] Figure 9 This is a flowchart of the electrical and electromagnetic co-simulation process. The electrical-electromagnetic co-simulation adopts a dual-branch parallel verification and final joint output architecture. The process can be summarized as follows:

[0133] 1. Electrical verification branch: Conduct semiconductor simulation of the front-end junction region to simulate the carrier avalanche triggering process and verify that the electrical properties of the four groups of samples are consistent due to the completely identical front-end FEOL structure, thus eliminating the interference of electrical differences on the comparison of optical performance.

[0134] 2. Optical and electromagnetic branches: Complete electromagnetic simulation of the front and rear ends of the four sets of structures was carried out to calculate the optical absorption probability and determine the differences in the active silicon absorption trend of different stepped opening structures.

[0135] 3. Joint Calculation Output: Based on consistent electrical characteristics and combined with differentiated optical absorption results, the final trend of photon detection probability (PDP) variation is jointly calculated.

[0136] The purpose of this simulation is to separate the two major sources of contribution of PDP, and to verify from a mechanistic perspective that the improvement of PDP in the present invention comes entirely from the control of the back-end optical structure, rather than the change of the front-end electrical properties. At the same time, it can predict the change trend of PDP with different aperture designs before fabrication.

[0137] Finally, the simulation results of this invention corroborate the experimental trends. Modeling and simulation were conducted using the COMSOL multiphysics simulation tool. The results show that, under 500nm incident conditions, the light absorption distribution in the active silicon region differs significantly from the 0° control sample, verifying the modulation effect of the multilayer back-end metal staircase opening on light field propagation from a simulation perspective.

[0138] Figure 10 This is a schematic diagram of the structure of the metal layers in several alternative embodiments of the present invention. Part (a) of the figure shows that the area of ​​the openings corresponding to different metal layers increases overall, but the area of ​​the openings corresponding to some adjacent metal layers (specifically M5 and M6) is equal. Therefore, the overall structure presents a stepped, non-monotonic increase (because the areas of the openings corresponding to M5 and M6 are equal).

[0139] (b) illustrates the case where the opening area gradually increases. In this type of embodiment, the edge of the metal layer near the opening is not parallel to the normal of the substrate, but rather forms a certain angle, in which case the opening area shows a continuous changing trend.

[0140] (c) implies the existence of a skip layer in the metal layer; the layer between M4 and M6 is a metal-free layer. However, this does not affect the overall structure of the invention: the area of ​​the openings corresponding to M4, M6, and M7 continuously increases: in a stepped, monotonically increasing manner. This metal-free layer contains: a medium with the same composition as the interlayer medium; and / or components other than the medium with the same composition as the interlayer medium. If the metal-free layer only contains a medium with the same composition as the interlayer medium, then this metal-free layer can also be called a dielectric layer. Alternatively, the metal-free layer may also contain other components.

[0141] Figure 11 This is a schematic diagram of the opening region in one type of embodiment of the present invention. Figure 11 The opening area is rectangular. However, the present invention is not limited to this; the opening shape of the present invention can also be circular, elliptical, square, rectangular, polygonal, annular, or irregular.

[0142] Furthermore, the perpendicular line to the center of opening 4 is Z4, the perpendicular line to the center of opening 5 is Z5, and the perpendicular line to the center of opening 6 is Z6. In one embodiment, Z4, Z5, and Z6 may be collinear. In another embodiment, Z4, Z5, and Z6 may be at least partially non-collinear.

[0143] In other words, the center of the opening corresponding to the metal layer is either coaxial or at least partially non-coaxial.

[0144] like Figure 11 As shown, the center of the opening corresponding to the metal layer in this invention can also be offset in one direction.

[0145] Furthermore, the area where the opening is located in this invention includes an interlayer medium or is hollowed out.

[0146] Furthermore, single-photon avalanche diodes are manufactured using one of the following processes: standard (general) CMOS process, CIS process, BCD process, compound semiconductor process, where the latter can be III and V group (SiC, GaN, etc.) compound semiconductor process, or II and VI group compound semiconductor process, as well as custom non-standard processes.

[0147] Furthermore, the optical channel in this invention does not contain a VIA.

[0148] Furthermore, multiple pixels in a pixel array can share the same type of FEOL.

[0149] Furthermore, the pixel array uses different, layer-by-layer aperture sequences (in the example, a sequence consisting of aperture sizes from M2 to M6) to form complementary spectral, angular, polarization, or multi-level optical coupling responses.

[0150] Furthermore, the bottom limiting opening matches (is equal to) the active photosensitive area.

[0151] Figure 12 This is a photograph of a corresponding embodiment of the present invention. The photograph shows five metal layers, with the area of ​​the openings increasing monotonically in a stepped manner.

[0152] It's worth noting that various non-ideal factors exist in chip manufacturing. Even if the metal layer is designed with a stepped shape (the edge of the metal layer near the opening is parallel to the substrate normal), the actual manufacturing process may result in something like this. Figure 12 Similarly, the edge of the metal layer near the opening is slightly skewed (reverse skew). This should be considered a manufacturing error, and this embodiment should still be considered part of the present invention. Figure 3 Examples of the disclosed stepped form.

[0153] This invention utilizes BEOL multilayer metal to create a stepped outward-expanding optical opening, and modulates the light field using diffraction interference to enhance the light absorption of the photosensitive silicon region, thereby improving the PDP without altering the front-end devices and maintaining the same electrical performance.

[0154] While keeping the SPAD front-end avalanche junction structure and the bottom direct light transmission range basically unchanged, multiple standard CMOS back-end planar conductive layers / metal layers at different heights are used to form stepped optical openings of various styles, so as to control the effective absorption and photon detection probability of the active silicon region under the target wavelength and incident conditions.

[0155] It should be noted that the methods described in this paper describe possible implementations, and that operations and steps can be rearranged or otherwise modified, and that other implementations are possible. Furthermore, aspects from two or more methods can be combined.

[0156] The specification set forth in conjunction with the accompanying drawings describes exemplary configurations and does not represent all examples that can be implemented or are within the scope of the claims. As used herein, the term "example" means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other examples." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be implemented without these specific details. In some instances, known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0157] The description herein is provided to enable those skilled in the art to implement or use the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

[0158] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of the present invention.

[0159] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A single-photon avalanche diode, characterized in that: The photosensitive absorption region formed on the substrate includes two, three or more metal layers on one side, and an opening is formed between the same metal layers; Along the accumulation direction of the metal layers, the area of ​​the openings in different metal layers gradually increases or increases in a stepwise manner; and, The different metal layers contain only an interlayer medium.

2. The single-photon avalanche diode according to claim 1, characterized in that: The aforementioned step-by-step increase specifically refers to: - The area of ​​the openings corresponding to different metal layers increases monotonically; or, - The area of ​​the openings corresponding to different metal layers increases overall, but the area of ​​the openings corresponding to some adjacent metal layers is equal.

3. The single-photon avalanche diode according to claim 1, characterized in that: The multilayer metal layer includes a layer that does not contain any metal layers; The layer without a metal layer contains: - A medium with the same composition as the interlayer medium; or / and - Components other than the interlayer medium that have the same composition.

4. The single-photon avalanche diode according to claim 1, characterized in that: The center of the opening corresponding to the metal layer: - Coaxial; or, - At least partially different axes.

5. The single-photon avalanche diode according to claim 4, characterized in that: If the centers of the openings corresponding to the metal layer are at least partially off-axis, and Offset in one direction.

6. The single-photon avalanche diode according to claim 1, characterized in that: The opening can be one of the following shapes: circular, elliptical, square, rectangular, polygonal, annular, or irregular.

7. The single-photon avalanche diode according to claim 1, characterized in that: The angle between the line connecting the edge of the metal layer near the opening and the normal to the substrate is greater than 0° and less than or equal to 60°.

8. The single-photon avalanche diode according to claim 1, characterized in that: The area where the opening is located: - Contains interlayer medium; or - Hollowed-out design.

9. The single-photon avalanche diode according to claim 1, characterized in that: The single-photon avalanche diode is manufactured using one of the following processes: Standard CMOS process, CIS process, BCD process, compound semiconductor process, and custom non-standard process.

10. A pixel array, characterized in that: At least a portion of the pixels in the pixel array comprise a single-photon avalanche diode as described in any one of claims 1-9; and In the pixel array, each pixel's respective metal layers use the same sequence of aperture sizes; or... In the pixel array, at least some pixels each have several metal layers that use different aperture sequences.

Images