Image sensor and method of operating an image sensor

Abstract

This disclosure relates to image sensors and methods of operating image sensors. An example image sensor includes: a first subpixel group including a first plurality of photodiodes arranged in multiple rows and columns and sharing a first floating diffusion node; a second subpixel group adjacent to the first subpixel group and including a second plurality of photodiodes arranged in multiple rows and columns and sharing a second floating diffusion node separate from the first floating diffusion node; a color filter, at least a portion of which is disposed on the first and second subpixel groups; and a first lens, at least a first portion of which is superimposed on the first and second subpixel groups in a plane.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0048450, filed with the Korean Intellectual Property Office on April 14, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to image sensors and methods for operating image sensors. Background Technology

[0003] The demand for mobile devices such as smartphones, tablet PCs, digital cameras, and e-readers is growing rapidly, and most mobile devices are equipped with at least one image sensor to capture images. Vehicles are also equipped with image sensors to obtain various information necessary for driving, etc.

[0004] With the recent trend towards increasing image resolution and miniaturizing image sensors, image sensors are increasingly employing shared pixel array structures, in which multiple photodiodes are electrically connected to the same floating diffuser. While shared pixel arrays facilitate pixel binning techniques in low-light environments, the structural characteristics of image sensors with shared floating diffusers limit the performance of some operations (e.g., limiting operating speed).

[0005] One of these limitations is the limited performance of the autofocus (AF) function in bright light. Summary of the Invention

[0006] This disclosure relates to an image sensor, a method for operating an image sensor that can easily perform AF operation in bright environments where overflow occurs while improving resolution, a method for operating an image sensor that can easily perform AF operation over a wide dynamic range while improving resolution, and a method for operating an image sensor that can facilitate AF operation in bright environments while minimizing light loss.

[0007] In some embodiments, an image sensor includes: a first subpixel group including a first plurality of photodiodes arranged in multiple rows and columns and sharing a first floating diffusion node; a second subpixel group adjacent to the first subpixel group and including a second plurality of photodiodes arranged in multiple rows and columns and sharing a second floating diffusion node separate from the first floating diffusion node; a color filter, at least a portion of which is disposed on the first subpixel group and the second subpixel group; and a first lens, at least a first portion of which is superimposed on the first subpixel group and the second subpixel group in a plane.

[0008] In some embodiments, an image sensor includes: a first photodiode configured to receive light through a first lens to generate photocharge and electrically connected to a first floating diffusion node via a first transfer transistor; a second photodiode configured to receive light through a second lens to generate photocharge and electrically connected to the first floating diffusion node via a second transfer transistor; a first driving transistor configured to generate a first pixel signal in response to a voltage of the first floating diffusion node; a third photodiode configured to receive light through the first lens to generate photocharge and electrically connected to a second floating diffusion node separated from the first floating diffusion node via a third transfer transistor; a fourth photodiode configured to receive light through the third lens to generate photocharge and electrically connected to the second floating diffusion node via a fourth transfer transistor; a second driving transistor configured to generate a second pixel signal in response to a voltage of the second floating diffusion node; a color filter, at least a portion of which is disposed on the first to fourth photodiodes; and a readout circuit configured to receive the first pixel signal through a first column line and receive the second pixel signal through a second column line separated from the first column line, to generate image data based on the first and second pixel signals.

[0009] In some embodiments, a method of operating an image sensor includes: resetting a first subpixel group and a second subpixel group, the first subpixel group sharing a first floating diffusion node and configured to output a pixel signal for a first color, the second subpixel group sharing a second floating diffusion node separate from the first floating diffusion node and configured to output a pixel signal for the first color, wherein at least a portion of the first subpixel group and at least a portion of the second subpixel group are superimposed on a plane with a first lens; receiving a first reset level signal from the first floating diffusion node and a second reset level signal from the second floating diffusion node together; receiving the first pixel signal from the first floating diffusion node and the second pixel signal from the second floating diffusion node together in a first conversion gain mode; changing the first conversion gain mode to a second conversion gain mode for the first subpixel group and the second subpixel group; receiving a third pixel signal from the first floating diffusion node and a fourth pixel signal from the second floating diffusion node together in the second conversion gain mode; and generating phase data based on the third pixel signal and the fourth pixel signal. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an example of an image sensor.

[0011] Figure 2 This is a plan view showing an example of a pixel array.

[0012] Figure 3 and Figure 4 yes Figure 2 An example magnified view of the first pixel group of the pixel array.

[0013] Figure 5 yes Figure 3 An example cross-sectional view taken along line I-I' of the first pixel group.

[0014] Figure 6 yes Figure 3 An example cross-sectional view taken along line J-J' of the first pixel group.

[0015] Figure 7 This is an example circuit diagram for a pixel group.

[0016] Figure 8 This is a timing diagram illustrating an example of AF operation for a group of pixels.

[0017] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a diagram used to explain the AF operation of pixel groups.

[0018] Figure 17 This is a plan view showing an example of a pixel array.

[0019] Figure 18 yes Figure 17 An example magnified view of the first pixel group of the pixel array.

[0020] Figure 19 This is an example circuit diagram for a pixel group.

[0021] Figure 20 This is a timing diagram illustrating an example of AF operation for a group of pixels.

[0022] Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 This is a diagram used to explain the AF operation of pixel groups.

[0023] Figure 27 This is a plan view showing an example of a group of pixels.

[0024] Figure 28 This is a plan view showing an example of a group of pixels.

[0025] Figure 29 This is a plan view showing an example of a group of pixels.

[0026] Figure 30 This is a plan view showing an example of a group of pixels.

[0027] Figure 31 This is a flowchart illustrating an example of a method for operating an image sensor.

[0028] Figure 32 This is a block diagram illustrating an example of a computer device.

[0029] Figure 33 This is a block diagram showing an example of a vehicle. Detailed Implementation

[0030] In the following, several embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein.

[0031] For clarity of this disclosure, parts not related to the description have been omitted, and throughout the specification, equivalent or similar reference numerals are assigned to equivalent or similar components.

[0032] Furthermore, throughout the specification, when a component is referred to as "including" an assembly, it is noted that, unless otherwise expressly stated, it does not exclude the presence of other components but may also include additional components.

[0033] Furthermore, even if a specific quantity is explicitly stated in a claim, the specific quantity set forth in a claim should not be construed as a limitation on a specific quantity in a claim where such a statement does not exist. For example, subsequent dependent claims may include the phrases "at least one (species)" and "one or more (species)" to aid understanding. However, the use of such interpretation should not be construed as being limited by the vague article "one (species)" described for the purpose of illustrative purposes.

[0034] Furthermore, when using conventions such as "at least one of A, B, or C," those skilled in the art will readily understand that such phrases (i.e., "a system (architecture) including at least one of A, B, or C") include, but are not limited to, only A, only B, only C, A and B, A and C, B and C, and / or A, B, and C together). Alternatively, words and / or phrases having two or more separate alternative terms in the detailed description, claims, or drawings should be considered capable of including one or any one or both terms. For example, the phrase "A or B" should be understood to include the possibility of "A," or "B," or "A and B."

[0035] The terms “module,” “unit,” “part,” etc., used in this document are intended to refer to a component that performs at least one function or operation, and such a component may be implemented as hardware or software, or as a combination of hardware and software.

[0036] Figure 1 This is a block diagram illustrating an example of an image sensor.

[0037] Reference Figure 1 The image sensor 100 can be mounted on an electronic device with image or light sensing capabilities. For example, the image sensor 100 can be mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, tablet PCs (personal computers), PDAs (personal digital assistants), PMPs (portable multimedia players), navigation devices, etc. Furthermore, the image sensor 100 can be mounted on electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring devices, etc.

[0038] The image sensor 100 may include a pixel array 110, a row driver 120, a readout circuit 130, a ramp signal generator 140, a timing controller 150, and an image signal processor 160.

[0039] In some embodiments, the pixel array 110 may include a plurality of unit pixels 112. Each unit pixel 112 may include a plurality of photodiodes, and the plurality of photodiodes may be connected to a plurality of transmission transistors and electrically connected to a driving transistor, etc. The plurality of photodiodes may receive light to generate photocharge and provide the photocharge to a floating diffusion node (or floating diffusion region) through the plurality of transmission transistors, and generate a pixel signal in response to the potential (or “potential”) of the photocharge accumulated in the floating diffusion node. In some embodiments, each unit pixel 112 may include a plurality of photodiodes arranged adjacent to each other in a plurality of rows and columns. For example, each unit pixel 112 may include photodiodes arranged adjacent to each other in a 4×2 array or in a 2×2 array.

[0040] Furthermore, the pixel array 110 may include multiple pixel groups as a collection of multiple unit pixels 112. In some embodiments, each pixel group may include unit pixels 112 arranged adjacent to each other and receiving light filtered by a color filter of the same color. In some embodiments, a group of pixels may include photodiodes arranged adjacent to each other in a 4×4 array.

[0041] In some embodiments, multiple photodiodes may be arranged in a Tetra Quad Bayer pattern. In other embodiments, multiple photodiodes may be arranged in an RGGB pattern having pixel groups arranged in a 4×4 array as the basic unit.

[0042] In some embodiments, a pixel group may include at least two photodiodes sharing the same microlens. The image sensor 100 can generate phase data and image data through the arrangement of the shared lenses. In this disclosure, the shared lens may be referred to as an AF lens.

[0043] In some embodiments, each of the plurality of unit pixels 112 may include a shared pixel structure in which a plurality of photodiodes share a single floating diffusion node. In some embodiments, a pixel group may use or correspond to at least two shared floating diffusion nodes, and the photodiodes within the pixel group may be electrically connected to one of the at least two shared floating diffusion nodes via a pixel drive signal (e.g., in response to a pixel drive signal).

[0044] In some implementations, the sharing relationships between multiple photodiodes and microlenses within a pixel group, and between multiple photodiodes and floating diffusion nodes, can be misaligned (inconsistent). Specifically, at least two photodiodes sharing the same microlens within a pixel group can be electrically connected to different shared floating diffusion nodes.

[0045] In some implementations, unit pixel 112 may operate in a multi-exposure mode performing multiple exposures, or in a single-exposure mode performing a single exposure during the integration period. For example, unit pixel 112 may operate in a multi-exposure mode in which photocharge is generated by a photodiode in response to a single exposure operation during the integration period, and then additional photocharge is generated by a photodiode in response to an exposure operation during a readout period following the integration period. As another example, unit pixel 112 may operate in a single-exposure mode in which photocharge is generated by a photodiode after a single exposure operation during the integration period.

[0046] The charge generated by the photodiode in each unit pixel 112 can accumulate in the floating diffusion node, and the charge accumulated in the floating diffusion node can be converted into voltage. The ratio of the charge accumulated in the floating diffusion node to voltage is then referred to as the conversion gain. The conversion gain can vary depending on the capacitance of the floating diffusion node.

[0047] Specifically, as the capacitance of the floating diffusion node increases, the conversion gain can decrease, and as the capacitance of the floating diffusion node decreases, the conversion gain can increase. In some embodiments, each of the plurality of unit pixels 112 can operate in multiple conversion gain modes.

[0048] In some implementations, each of the plurality of unit pixels 112 may operate in a three-conversion gain mode. The three-conversion gain mode may include a high conversion gain mode, a medium conversion gain mode, and a low conversion gain mode. For example, "operating in a three-conversion gain mode" may mean operating while continuously changing from a high conversion gain mode to a medium conversion gain mode and from a medium conversion gain mode to a low conversion gain mode, and may also include operating while continuously changing from a low conversion gain mode to a medium conversion gain mode and from a medium conversion gain mode to a high conversion gain mode.

[0049] In some implementations, each of the plurality of unit pixels 112 may operate in a dual conversion gain mode. The dual conversion gain mode may include a high conversion gain mode and a low conversion gain mode. For example, "operating in a dual conversion gain mode" may mean operating while continuously changing from a high conversion gain mode to a low conversion gain mode, and may include operating while continuously changing from a low conversion gain mode to a high conversion gain mode.

[0050] The rate at which charge is converted into voltage is highest in high conversion gain mode and lowest in low conversion gain mode. Therefore, in low conversion gain mode, more pixel signal generation operations suitable for bright environments can be performed compared to medium and high conversion gain modes. Similarly, in medium conversion gain mode, more pixel signal generation operations suitable for bright environments can be performed compared to high conversion gain mode.

[0051] The pixel array 110 can receive pixel drive signals, including reset signals, transmission signals, conversion gain enable signals, and selection signals, from the row driver 120 via multiple row lines RLn. The pixel array 110 operates according to the received pixel drive signals, and each of the plurality of unit pixels 112 can convert the optical signal into a pixel signal as an analog signal.

[0052] The row driver 120 can select any row of the pixel array 110 under the control of the timing controller 150. The row driver 120 can generate a selection signal to select one of multiple rows. In addition, the row driver 120 can activate reset signals and transmission signals for the photodiodes corresponding to the selected rows in a setting sequence.

[0053] The pixel signal generated by each unit pixel 112 can be provided to the readout circuit 130 via multiple column lines CLm. In this case, the pixel signal generated by each unit pixel 112 may include image information and phase information.

[0054] The readout circuit 130 may include a correlated dual sampler (CDS) 131, an analog-to-digital converter (ADC) 132, a phase data generator 133, and an image data generator 134.

[0055] The correlated double sampler 131 may include multiple comparators, each of which compares a pixel signal received from the pixel array 110 via multiple column lines CLm with a ramp signal RAMP received from the ramp signal generator 140. Specifically, the correlated double sampler 131 compares the received pixel signal with the ramp signal RAMP and outputs the comparison result to the analog-to-digital converter 132.

[0056] The correlated dual sampler 131 can receive a reset level signal and a pixel signal generated from the photodiode of the selected row. Here, the reset level signal can be an analog signal corresponding to the reference voltage of the floating diffusion node, and the pixel signal can be an analog signal corresponding to the signal voltage of the floating diffusion node.

[0057] The analog-to-digital converter 132 can convert the comparison result of the correlated double sampler 131 into a digital signal and output it. In some embodiments, the readout circuit 130 includes an output buffer, and the digital signal of each column cell provided by the analog-to-digital converter 132 can be latched and output through the output buffer.

[0058] In some embodiments, the phase data generator 133 may receive digital signals corresponding to at least two photodiodes included in a plurality of pixel groups. More specifically, the phase data generator 133 may receive digital signals corresponding to at least two photodiodes sharing a microlens among the photodiodes included in a plurality of pixel groups.

[0059] For example, the phase data generator 133 can receive digital signals corresponding to the left-hand photodiode of at least two photodiodes sharing a microlens, and extract first phase information by merging them. Furthermore, the phase data generator 133 can receive digital signals corresponding to the right-hand photodiode of at least two photodiodes sharing a microlens, and extract second phase information by merging them.

[0060] Phase data generator 133 can generate phase data PDTA using first phase information and second phase information. For example, phase data generator 133 can generate phase data PDTA by comparing the first phase information with the second phase information.

[0061] The readout circuit 130 can receive pixel signals generated by different shared floating diffusion nodes within a pixel group and generate phase data PDTA based on the pixel signals. In high-light environments where overflow occurs, the image sensor 100 can simultaneously receive multiple pixel signals for a shared lens from different shared floating diffusion nodes through the sharing relationship of microlenses and floating diffusion nodes within a pixel group.

[0062] In some implementations, the image data generator 134 may generate image data IDTA based on digital signals received from a plurality of pixels included in the pixel array 110. Specifically, the image data generator 134 may receive digital signals corresponding to at least two photodiodes sharing a microlens among photodiodes included in a plurality of pixel groups, and generate image data IDTA based on the digital signals.

[0063] More specifically, the image data generator 134 can generate image data IDTA by synthesizing digital signals based on pixel signals of multiple unit pixels 112.

[0064] For example, the image data generator 134 may receive a first digital signal corresponding to a photodiode located on the left side of a pixel group and a second digital signal corresponding to a photodiode located on the right side of the same pixel group. Here, each of the first and second digital signals may include image information and phase information. The image data generator 134 can generate image data IDTA by synthesizing the first and second digital signals. In this case, the phase information of the first and second digital signals can cancel each other out.

[0065] exist Figure 1 In this embodiment, the correlated dual sampler 131 and the analog-to-digital converter 132 are shown as being implemented by integration into the readout circuit 130, but this is not a limitation, and according to the embodiment, the correlated dual sampler 131 and the analog-to-digital converter 132 may be implemented in a construction (configuration) separate from the readout circuit 130.

[0066] The ramp signal generator 140 generates a ramp signal RAMP and sends it to the readout circuit 130. The ramp signal generator 140 may include a current source, a resistor, a capacitor, etc. The ramp signal generator 140 can generate multiple ramp signals with a slope decreasing or increasing as determined by the current magnitude of the variable current source or the resistance value of the variable resistor by controlling the ramp voltage applied to the ramp resistor through controlling the current magnitude of the variable current source or the resistance value of the variable resistor.

[0067] The timing controller 150 can control at least some of the pixel array 110, the line driver 120, the readout circuit 130, and the ramp signal generator 140. More specifically, the timing controller 150 can provide control signals (such as clock signals, timing control signals, etc.) for operation of the pixel array 110, the line driver 120, the readout circuit 130, and the ramp signal generator 140.

[0068] The timing controller 150 may include logic control circuitry, phase-locked loop (PLL) circuitry, timing control circuitry, and communication interface circuitry.

[0069] The timing controller 150 can control the timing of the elements within the pixel array 110 during a reset period, an integration period, and a readout period. The reset period can be the period during which the charge accumulated in the floating diffusion nodes within the pixel array 110 is reset. The integration period can be the period during which the photodiode is exposed to light and photocharge is generated. The readout period can be the period during which a pixel signal based on the photocharge generated from the photodiode is sent to the readout circuit 130.

[0070] The image signal processor 160 can perform image signal processing on the image data ITA and phase data PDTA received from the readout circuit 130.

[0071] The image signal processor 160 can use the phase data PDTA received from the readout circuit 130 to perform AF operation to measure the focus on the object. Furthermore, the image signal processor 160 can use the image data IDTA received from the readout circuit 130 to generate an image of the object.

[0072] Figure 2 This is a plan view showing an example of a pixel array. Figure 3 and Figure 4 yes Figure 2 An example magnified view of the first pixel group of the pixel array.

[0073] Reference Figures 2 to 4 The pixel array 110 may include a first pixel group PG1a to a fourth pixel group PG4a. Each of the first pixel groups PG1a to the fourth pixel group PG4a may include a photodiode region arranged in a 4×4 array in a first direction D1 and a second direction D2. The first pixel group PG1a and the second pixel group PG2a may be arranged in the second direction D2, and the third pixel group PG3a and the fourth pixel group PG4a may be arranged in the second direction D2. Furthermore, the first pixel group PG1a and the third pixel group PG3a may be arranged in the first direction D1, and the second pixel group PG2a and the fourth pixel group PG4a may be arranged in the first direction D1.

[0074] The first pixel group PG1a to the fourth pixel group PG4a can be distinguished and electrically isolated by the device isolation pattern 310. Furthermore, the photodiode regions within the first pixel group PG1a to the fourth pixel group PG4a can be separated and electrically isolated by the device isolation pattern 310. In this disclosure, the photodiode region can be a region where photodiodes are arranged, and multiple photodiodes can be electrically separated by the device isolation pattern 310.

[0075] For ease of explanation in this disclosure, each pixel group is shown as including a photodiode region arranged in a 4×4 array, but is not limited thereto, and a pixel group may include multiple photodiodes arranged in various combinations (e.g., in an n×m array, where m and n are arbitrary positive integers).

[0076] Each of the first pixel group PG1a to the fourth pixel group PG4a can receive filtered light of the same color. In some embodiments, the first pixel group PG1a to the fourth pixel group PG4a can be arranged in an RGGB pattern with pixel groups as the basic unit (cell), and the multiple photodiodes within the first pixel group PG1a to the fourth pixel group PG4a can be arranged in a four-in-one Bayer pattern. (See also...) Figure 2 As an example, the pixels of the first pixel group PG1a can receive red light R filtered by the first color filter CF1, the pixels of the fourth pixel group PG4a can receive blue light B filtered by the second color filter CF2, and the pixels of the second pixel group PG2a and the third pixel group PG3a can receive green light G filtered by the third color filter CF3.

[0077] Although not shown, the pixel array 110 may also include pixel groups arranged in the first direction D1 or the second direction D2, in addition to the first pixel group PG1a to the fourth pixel group PG4a.

[0078] Microlens MLa (a) and microlens MLB (b) can be arranged on pixel array 110 with different pixel groups. (Refer to...) Figure 2 As an example, the a-th microlens MLA and the B-th microlens MLb can be arranged on the first pixel group PG1a that receives red light R and the fourth pixel group PG4a that receives blue light B, and the a-th microlens MLA can be arranged on the second pixel group PG2a and the third pixel group PG3a that receive green light G.

[0079] The a-th microlens MLA corresponds to a photodiode, and at least a portion of the a-th microlens MLA is superimposed on a photodiode relative to the third-directed D3 plane (on a plane), and incident light can be focused onto a photodiode. The image sensor 100 can generate light through the photodiode corresponding to the a-th microlens MLA. Figure 1The image data IDT is generated. A photodiode corresponding to the a-th microlens MLA can be used for image generation. The b-th microlens MLA corresponds to a photodiode arranged in a 2×2 array, and at least a portion of the b-th microlens MLA can be planarly (on a plane) superimposed on the photodiode, focusing incident light onto the photodiode. In some embodiments, the photodiodes arranged in a 2×2 array in the first pixel group PG1a and the fourth pixel group PG4a can share the b-th microlens MLA, and the image sensor 100 can generate image data using the photodiodes sharing the b-th microlens MLA. Figure 1 Image data ITA and phase data PDTA. The photodiode sharing the b-th microlens MLb can be used for various purposes (including image generation and phase detection).

[0080] The image sensor 100 can receive green light G, which is responsible for the brightness information of the user's eye, without light loss through the arrangement of microlenses MLa and MLb as described above, and receive red light R and blue light B, which are responsible for color information, through a multi-purpose photodiode for phase difference detection and image generation, thereby enabling high-resolution image quality and accurate AF performance to be achieved simultaneously.

[0081] In the accompanying drawings, microlenses MLa, MLb and device isolation pattern 310 are shown aligned and arranged, but this is not the only case, and the degree of alignment between microlenses MLa, MLb and device isolation pattern 310 may vary depending on the position of the corresponding photodiode.

[0082] Each of the first pixel group PG1a to the fourth pixel group PG4a may include two sub-pixel groups arranged horizontally, and multiple photodiodes within each sub-pixel group may share a floating diffusion node, a reset transistor, a conversion gain transistor, a MIM (Metal-Insulator-Metal) capacitor, and a driving transistor. The image sensor 100 can be miniaturized and provide high-resolution images through the shared structure of each sub-pixel group. Each sub-pixel group may correspond to... Figure 1 The unit is 112 pixels.

[0083] The first pixel group PG1a may include sub-pixel groups PGs11 (1_1) and PGs12 (1_2) arranged adjacently in the second direction D2, and the second pixel group PG2a may include sub-pixel groups PGs21 (2_1) and PGs22 (2_2) arranged adjacently in the second direction D2. Similarly, the third pixel group PG3a may include sub-pixel groups PGs31 (3_1) and PGs32 (3_2) arranged adjacently in the second direction D2, and the fourth pixel group PG4a may include sub-pixel groups PGs41 (4_1) and PGs42 (4_2) arranged adjacently in the second direction D2.

[0084] For ease of explanation, the subpixel groups described below will focus on subpixel group 1_1 PGs11 and subpixel group 1_2 PGs12. The descriptions of subpixel group 1_1 PGs11 and subpixel group 1_2 PGs12 below can be applied to other subpixel groups within pixel array 110.

[0085] Sub-pixel group PGs11 (1_1) and sub-pixel group PGs12 (1_2) can be separated by a pixel group separation region 310s extending in the first direction D1. The pixel group separation region 310s is part of the device isolation pattern 310, and sub-pixel group PGs11 (1_1) and sub-pixel group PGs12 (1_2) can be separated by the pixel group separation region 310s in the second direction D2.

[0086] Sub-pixel group PGs11 may include first photodiode regions PR1 to eighth photodiode regions PR8 arranged in a 4×2 array along the first direction D1 and the second direction D2, and sub-pixel group PGs12 may include ninth photodiode regions PR9 to sixteenth photodiode regions PR16 arranged in a 4×2 array along the first direction D1 and the second direction D2. Photodiodes may be arranged in each of the first photodiode regions PR1 to sixteenth photodiode regions PR16.

[0087] The first photodiode region PR1 to the eighth photodiode region PR8 share a first floating diffusion node FD1, and the photodiodes in the first photodiode region PR1 to the eighth photodiode region PR8 are electrically connected to the first floating diffusion node FD1. The ninth photodiode region PR9 to the sixteenth photodiode region PR16 share a second floating diffusion node FD2, and the photodiodes in the ninth photodiode region PR9 to the sixteenth photodiode region PR16 are electrically connected to the second floating diffusion node FD2. The first floating diffusion node FD1 and the second floating diffusion node FD2 are electrically isolated from each other.

[0088] The first floating diffusion node FD1 may include a first polysilicon local interconnect PLI1. The first polysilicon local interconnect PLI1 may include a first a contact region PLI1a, a first b contact region PLI1b, and a first connection region PLI1c. At least a portion of the first a contact region PLI1a may be planarly (on a plane) superimposed with the first photodiode regions PR1 to the fourth photodiode regions PR4, and at least a portion of the first b contact region PLI1b may be planarly (on a plane) superimposed with the fifth photodiode regions PR5 to the eighth photodiode regions PR8. The first connection region PLI1c connects the first a contact region PLI1a and the first b contact region PLI1b, extends along the first direction D1, and may be planarly (on a plane) superimposed with at least a portion of the device isolation pattern 310.

[0089] The first polysilicon local interconnect PLI1 includes a conductive pattern, wherein the conductive pattern may include at least one of doped polysilicon, metal, metal silicide, metal nitride, and metal-containing film. For example, the first polysilicon local interconnect PLI1 may be made of polysilicon doped with N-type impurities (such as phosphorus (P) or arsenic (As)).

[0090] The second floating diffusion node FD2 may include a second polysilicon local interconnect PLI2. The second polysilicon local interconnect PLI2 may include a second_a contact region PLI2a, ​​a second_b contact region PLI2b, and a second connection region PLI2c. At least a portion of the second_a contact region PLI2a may be planarly (on a plane) superimposed on the ninth photodiode region PR9 to the twelfth photodiode region PR12, and at least a portion of the second_b contact region PLI2b may be planarly (on a plane) superimposed on the thirteenth photodiode region PR13 to the sixteenth photodiode region PR16. The second connection region PLI2c connects the second_a contact region PLI2a and the second_b contact region PLI2b, extends along the first direction D1, and may be planarly (on a plane) superimposed on at least a portion of the device isolation pattern 310.

[0091] The second polysilicon local interconnect PLI2 includes a conductive pattern, wherein the conductive pattern may include at least one of doped polysilicon, metal, metal silicide, metal nitride, and metal-containing film. For example, the second polysilicon local interconnect PLI2 may be made of polysilicon doped with N-type impurities (such as phosphorus (P) or arsenic (As)).

[0092] Furthermore, the pixel group separation region 310s can be arranged between the first polysilicon local interconnect PLI1 and the second polysilicon local interconnect PLI2.

[0093] Although not shown, the insulating spacer may be positioned to extend along the sidewall of each of the first polysilicon local interconnect PLI1 and the second polysilicon local interconnect PLI2.

[0094] The a-th microlens MLA can be located on the first photodiode region PR1, the second photodiode region PR2, the third photodiode region PR3, the fifth photodiode region PR5, the seventh photodiode region PR7, and the eighth photodiode region PR8 within the 1_1 sub-pixel group PGs11. Each of the first photodiode region PR1, the second photodiode region PR2, the third photodiode region PR3, the fifth photodiode region PR5, the seventh photodiode region PR7, and the eighth photodiode region PR8 corresponds to the a-th microlens MLA, receives red light R filtered by the first color filter CF1, and can output a pixel signal of red light R.

[0095] The a-th microlens MLA can be respectively arranged on the ninth photodiode region PR9, the tenth photodiode region PR10, the twelfth photodiode region PR12, the fourteenth photodiode region PR14, the fifteenth photodiode region PR15, and the sixteenth photodiode region PR16 in the 1-2 sub-pixel group PGs12. Each of the ninth photodiode region PR9, the tenth photodiode region PR10, the twelfth photodiode region PR12, the fourteenth photodiode region PR14, the fifteenth photodiode region PR15, and the sixteenth photodiode region PR16 corresponds to the a-th microlens MLA, receives the red light R filtered by the first color filter CF1, and can output the pixel signal of the red light R.

[0096] Figure 1 The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the a-th microlens MLa, and generate... Figure 1 Image data IDTA.

[0097] The b-th microlens MLb can be arranged across sub-pixel groups PGs11 and PGs12, and can be arranged on the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13. The fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 can share the b-th microlens MLb, and each of the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 can receive red light R filtered by the first color filter CF1 and output a pixel signal of red light R.

[0098] Figure 1 The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the b-th microlens MLb, and generate Figure 1 The image data ITA or phase data PDTA is obtained. The readout circuit 130 receives pixel signals corresponding to the photodiodes in the fourth photodiode region PR4 and the sixth photodiode region PR6 (located on the left) of the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 to extract first phase information, and receives pixel signals corresponding to the photodiodes in the eleventh photodiode region PR11 and the thirteenth photodiode region PR13 (located on the right) to extract second phase information. The readout circuit 130 generates phase data PDTA by comparing the first phase information with the second phase information. The readout circuit 130 can receive pixel signals from the photodiodes in the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 substantially simultaneously through the separation structure of the first floating diffusion node FD1 and the second floating diffusion node FD2.

[0099] also, Figure 1 The readout circuit 130 can generate image data IDTA based on the pixel signals of the photodiodes in the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13.

[0100] Each of the first MIM capacitors MIM1 and MIM2 is shared by a 1_1 sub-pixel group PGs11 and may be planarly (on a plane) superimposed on at least a portion of the 1_1 sub-pixel group PGs11. For example, the first MIM capacitors MIM1 and MIM2 may be planarly (on a plane) at least partially separated from each other. For example, the first MIM capacitors MIM1 and MIM2 may be planarly (on a plane) not superimposed on each other. Similarly, each of the third MIM capacitors MIM3 and MIM4 is shared by a 1_2 sub-pixel group PGs12 and may be planarly (on a plane) superimposed on at least a portion of the 1_2 sub-pixel group PGs12. For example, the third MIM capacitors MIM3 and MIM4 may be planarly (on a plane) at least partially separated from each other. For example, the third MIM capacitors MIM3 and MIM4 may be planarly (on a plane) not superimposed on each other. In some embodiments, the first MIM capacitor MIM1, the second MIM capacitor MIM2, the third MIM capacitor MIM3, and the fourth MIM capacitor MIM4 may be planar (on a plane) separated from each other or not stacked. See reference. Figure 4 As an example, the first MIM capacitor MIM1 may be planarly (on a plane) superimposed on at least a portion of the first photodiode region PR1 to the fourth photodiode region PR4, and the second MIM capacitor MIM2 may be planarly (on a plane) superimposed on at least a portion of the third photodiode region PR3 to the eighth photodiode region PR8. The third MIM capacitor MIM3 may be planarly (on a plane) superimposed on at least a portion of the ninth photodiode region PR9 to the twelfth photodiode region PR12, and the fourth MIM capacitor MIM4 may be planarly (on a plane) superimposed on at least a portion of the eleventh photodiode region PR11 to the sixteenth photodiode region PR16.

[0101] Each of the first MIM capacitors MIM1 to the fourth MIM capacitors MIM4 may include at least two metal films stacked planarly to each other in the 1_1 sub-pixel group PGs11 and an insulating film disposed between the at least two metal films. The metal films may include, but are not limited to, tungsten (W), aluminum (Al), copper (Cu), or combinations thereof.

[0102] The first MIM capacitors MIM1 to the fourth MIM capacitors MIM4, and the microlenses MLa and MLb can be arranged to face each other based on sub-pixel group PGs11 (1_1) and sub-pixel group PGs12 (1_2). For example, if the first MIM capacitors MIM1 and the second MIM capacitors MIM2 are arranged on the front surface of sub-pixel group PGs11 (1_1), then the microlenses MLa and MLb can be arranged on the rear surface of sub-pixel group PGs11 (1_1).

[0103] Although not shown, one electrode of each of the first MIM capacitor MIM1 and the second MIM capacitor MIM2 can be electrically connected to the first floating diffusion node FD1 based on a conversion gain enable signal. The charge storage capacity (full well capacity) and conversion gain mode of the 1_1 sub-pixel group PGs11 can be changed according to the electrical connection between the first floating diffusion node FD1 and the first MIM capacitor MIM1 and the second MIM capacitor MIM2.

[0104] Similarly, one electrode of each of the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4 can be electrically connected to the second floating diffusion node FD2 based on the conversion gain enable signal. Depending on the electrical connection between the second floating diffusion node FD2 and the third MIM capacitors MIM3 and MIM capacitors MIM4, the charge storage capacity and conversion gain mode of the 1_2 sub-pixel group PGs12 can be changed.

[0105] Each of the first MIM capacitors MIM1 to MIM4 can be a lateral overflow integration capacitor (LOFIC). If the first MIM capacitors MIM1 to MIM4 are LOFICs, the overflow charge from the photoelectric charge transferred from the first photodiode region PR1 to the eighth photodiode region PR8 to the first floating diffusion node FD1 can be stored in at least one of the first MIM capacitors MIM1 and MIM2, and the overflow charge from the photoelectric charge transferred from the ninth photodiode region PR9 to the sixteenth photodiode region PR16 to the second floating diffusion node FD2 can be stored in at least one of the third MIM capacitors MIM3 and MIM4. That is, a large amount of overflow charge is not discarded and can be integrated into the first MIM capacitors MIM1 to MIM4.

[0106] The areas of the metal films in the first MIM capacitor MIM1 and the second MIM capacitor MIM2 can be different from each other, and the charge storage capacities of the first MIM capacitor MIM1 and the second MIM capacitor MIM2 can also be different from each other. Similarly, the areas of the metal films in the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4 can be different from each other, and the charge storage capacities of the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4 can also be different from each other. By utilizing the differences in charge storage capacities between the first MIM capacitor MIM1 and the second MIM capacitor MIM2, and between the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4, the image sensor can effectively adjust the conversion gain according to the lighting environment.

[0107] Figure 5 yes Figure 3 An example cross-sectional view taken along line I-I' of the first pixel group. Figure 6 yes Figure 3 An example cross-sectional view taken along line J-J' of the first pixel group. Specifically, Figure 5 and Figure 6 It is shown Figure 1 and Figure 2 A cross-sectional view of a portion of the pixel array 110.

[0108] Reference Figures 2 to 6 The image sensor may include a semiconductor substrate 320, a wiring layer 330, a color filter grid 350, a surface insulating layer 360, color filters CF1 to CF3, and microlenses MLa and MLb.

[0109] Semiconductor substrate 320 may be a semiconductor substrate. For example, semiconductor substrate 320 may be bulk silicon or silicon-on-insulator (SOI). Semiconductor substrate 320 may be a silicon substrate, or may include semiconductor materials comprising other materials (e.g., silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide). Optionally, semiconductor substrate 320 may have an epitaxial layer formed on a substrate.

[0110] The semiconductor substrate 320 may include a first surface SF1 and a second surface SF2 opposite to each other. In some embodiments, the first surface SF1 may be referred to as the front side of the semiconductor substrate 320, and the second surface SF2 may be referred to as the back side of the semiconductor substrate 320. In some embodiments, the second surface SF2 of the semiconductor substrate 320 may be a light-receiving surface on which light is incident and on which a plurality of photodiodes are exposed. That is, the image sensor may be a back-illuminated (BSI) image sensor.

[0111] Multiple pixel groups PG1a to PG4a can be arranged on a semiconductor substrate 320. The semiconductor substrate 320 includes photodiodes arranged in each photodiode region and device isolation patterns 310 separating the photodiodes, and a transmission transistor corresponding to each photodiode can be arranged on a first surface SF1 of the semiconductor substrate 320. In addition, microlenses MLa and MLB, and color filters CF1 to CF3 can be arranged on the multiple pixel groups PG1a to PG4a.

[0112] A photodiode generates a photocharge proportional to the amount of light incident upon it from the outside. For example, a photodiode can be a photosensitive device made of organic or inorganic materials (such as inorganic photodiodes, organic photodiodes, perovskite photodiodes, phototransistors, photogates, or pinned photodiodes). A photodiode can be formed by doping impurities into a semiconductor substrate 320. For example, if the semiconductor substrate 320 is doped with P-type impurities, the photodiode can be doped with N-type impurities. That is, the types of impurities doped into the semiconductor substrate 320 and the types of impurities doped into the photodiode can be different from each other.

[0113] by Figure 5 and Figure 6 As an example, the first photodiode PD1 in the first photodiode region PR1 and the third photodiode PD3 in the third photodiode region PR3 can be separated by device isolation pattern 310, and the fourth photodiode PD4 in the fourth photodiode region PR4 and the thirteenth photodiode PD13 in the thirteenth photodiode region PR13 can be separated by device isolation pattern 310. Furthermore, the first transmission transistor TX1, the third transmission transistor TX3, the fourth transmission transistor TX4, and the thirteenth transmission transistor TX13 can be arranged on the first surface SF1 of the semiconductor substrate 320. The first color filter CF1 can be arranged on the first photodiode region PR1, the third photodiode region PR3, the fourth photodiode region PR4, and the thirteenth photodiode region PR13 of the first pixel group PG1a. Additionally, the a-th microlens MLA can be disposed on each of the first photodiode region PR1 and the third photodiode region PR3, and the b-th microlens MLB can be disposed on each of the fourth photodiode region PR4 and the thirteenth photodiode region PR13.

[0114] The transmission transistor corresponding to each photodiode can be implemented using a vertical transmission gate (VTG) structure and can be arranged adjacent to a polysilicon local interconnect shared within the sub-pixel group. The contact region of the polysilicon local interconnect contacts the impurity regions corresponding to the source / drain of the same transmission transistor, and the polysilicon local interconnect and the impurity regions in the semiconductor substrate 320 that contact the polysilicon local interconnect can form a shared floating diffusion node. Figure 5 and Figure 6 As an example, the first _a contact region PLI1a contacts the impurity regions SD1, SD3, and SD4 of the first transmission transistor TX1, the third transmission transistor TX3, and the fourth transmission transistor TX4, and the first polysilicon local interconnect PLI1 and the impurity regions in the semiconductor substrate 320 that contact the first polysilicon local interconnect PLI1 can form a first floating diffusion node FD1. Furthermore, the second _b contact region PLI2b of the second polysilicon local interconnect PLI2 contacts the impurity region SD13 of the thirteenth transmission transistor TX13, and the second polysilicon local interconnect PLI2 and the impurity regions in the semiconductor substrate 320 that contact the second polysilicon local interconnect PLI2 can form a second floating diffusion node FD2.

[0115] By utilizing the contact structure between the polysilicon local interconnects and the impurity regions of the transmission transistor, the image sensor 100 can form a shared floating diffusion node without requiring multiple contacts, and reduces the parasitic capacitance of the floating diffusion node formed between multiple contacts. Through the improved parasitic capacitance structure of the shared floating diffusion node, the image sensor 100 can operate with high sensitivity in a high conversion gain mode.

[0116] Although not shown, at least some of the various transistors (e.g., transfer transistors, reset transistors, drive transistors, conversion gain transistors, and selection transistors) used to operate the pixels within the pixel group may be disposed on the first surface SF1.

[0117] Device isolation pattern 310 is arranged in a grid shape within semiconductor substrate 320, and multiple photodiode regions can be divided and electrically isolated according to the grid shape. From a planar view, the multiple photodiode regions can be arranged in a two-dimensional grid shape along a first direction D1 and a second direction D2. Device isolation pattern 310 can be formed by filling insulating material into deep trenches formed by patterning semiconductor substrate 320.

[0118] At least a portion of the device isolation pattern 310 may be planarly (on a plane) superimposed on and in contact with the polysilicon local interconnects PLI1 and PLI2.

[0119] In some embodiments, the device isolation pattern 310 may include an insulating spacer film 311 and a conductive fill pattern 312. The insulating spacer film 311 may extend along the side of a trench in the semiconductor substrate 320. The conductive fill pattern 312 may be formed on the insulating spacer film 311 to fill a portion of the trench in the semiconductor substrate 320. In some embodiments, the insulating spacer film 311 may have a structure in which the width increases as the insulating spacer film 311 approaches the first surface SF1.

[0120] In the accompanying drawings, the insulating spacer film 311 is depicted as a single material layer; however, according to an embodiment, an insulating material layer different from the insulating spacer film 311 may be arranged between the first surface SF1 and the conductive filling pattern 312. This insulating material layer may be arranged according to a shallow trench structure formed on the insulating spacer film 311 and the conductive filling pattern 312.

[0121] A surface insulating layer 360 may be stacked on the second surface SF2 of the semiconductor substrate 320. Color filter grid 350, substrate 353, color filters CF1 to CF3, and microlenses MLa and MLb may be arranged in the region defined by the surface insulating layer 360.

[0122] Color filters CF1 to CF3 may be formed on the surface insulating layer 360. Color filters CF1 to CF3 may be arranged corresponding to a pixel group. For example, each of color filters CF1 to CF3 may be at least partially disposed on a sub-pixel group included in the corresponding pixel group. From a planar viewpoint, color filters CF1 to CF3 may be arranged in two dimensions. Color filters CF1 to CF3 may include a first color filter CF1 as a red color filter, a second color filter CF2 as a blue color filter, and a third color filter CF3 as a green color filter.

[0123] Microlenses MLa and MLb can be formed on color filters. Microlens MLa is arranged to correspond to a photodiode and can be positioned on first color filters CF1 to third color filters CF3. In some embodiments, the photodiode corresponding to microlens MLa can be used for image generation purposes. Microlens MLb is arranged to correspond to multiple photodiode regions arranged in a 2×2 array and can be positioned on first color filters CF1 and second color filters CF2. Furthermore, one of the microlenses MLb can be positioned across different groups of neighboring sub-pixels. (See reference...) Figure 6 As an example, the b-th microlens MLb can be arranged across the fourth photodiode region PR4 of sub-pixel group 1_1 PGs11 and the thirteenth photodiode region PR13 of sub-pixel group 1_2 PGs12. Multiple photodiodes corresponding to the b-th microlens MLb can be used for image generation and phase detection purposes.

[0124] Microlenses MLa and MLb have a convex shape and may have a predetermined radius of curvature. Microlenses MLa and MLb may include, but are not limited to, light-transmitting resins.

[0125] The color filter grid 350 can be arranged in a grid shape between color filters CF1 to CF3, and can define the area in which color filters CF1 to CF3 are arranged in a grid shape. Therefore, at least a portion of the color filter grid 350 can be planarly (on a plane) superimposed on the device isolation pattern 310.

[0126] A color filter grid 350 may be formed on a surface insulating layer 360. The color filter grid 350 may include, for example, a metallic pattern 351 and a low-refractive-index pattern 352. The metallic pattern 351 and the low-refractive-index pattern 352 may be sequentially stacked on the surface insulating layer 360.

[0127] A liner 353 may be formed on the surface insulating layer 360 and the color filter grid 350. The liner 353 may extend along the surfaces of the surface insulating layer 360 and the color filter grid 350. The liner 353 may include, for example, but not limited to, aluminum oxide.

[0128] The wiring layer 330 may include an interlayer insulating film 331, multiple wirings 341, multiple contacts 342, and MIM capacitors. Electronic components within the pixel array 110 can be electrically connected to each other via the wiring layer 330.

[0129] Multiple wirings 341 are arranged in multiple layers within an interlayer insulating film 331, and multiple contacts 342 extend in a third direction D3 within the interlayer insulating film 331 to electrically connect the multiple wirings 341, MIM capacitors, transistors, etc. (Refer to...) Figure 5 As an example, some of the multiple contacts 342 may be electrically connected between the gate of the first transmission transistor TX1 and the multiple wirings 341, and some of the multiple contacts 342 may be electrically connected between the multiple wirings 341 and the first MIM capacitor MIM1.

[0130] The interlayer insulating film 331 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The multiple wirings 341 and the multiple contacts 342 include conductive materials and may include, for example, but not limited to, at least one of copper (Cu), aluminum (Al), tungsten (W), gold (Au), silver (Ag), and alloys thereof.

[0131] The MIM capacitor may include at least two metal films stacked planarly on a third-direction D3 and a portion of an interlayer insulating film 331 disposed between the at least two metal films. At least a portion of the MIM capacitor may be planarly (on a plane) stacked with a plurality of pixels.

[0132] by Figure 5 and Figure 6 Taking the first MIM capacitor MIM1 and the fourth MIM capacitor MIM4 as examples, the first MIM capacitor MIM1 may include a first metal film 343 and a second metal film 344 stacked planarly on a third direction D3, and a portion of an interlayer insulating film 331 disposed between the first metal film 343 and the second metal film 344. The first MIM capacitor MIM1 may be planarly (on a plane) stacked with a first photodiode region PR1, a third photodiode region PR3, and a fourth photodiode region PR4. The fourth MIM capacitor MIM4 may include a third metal film 345 and a fourth metal film 346 stacked planarly on a third direction D3, and a portion of an interlayer insulating film 331 disposed between the third metal film 345 and the fourth metal film 346. The fourth MIM capacitor MIM4 may be planarly (on a plane) stacked with a thirteenth photodiode region PR13.

[0133] The metal film of the MIM capacitor may include, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), or combinations thereof. In some embodiments, the material of the metal film of the MIM capacitor may be different from the material of the plurality of contacts 342 and the plurality of wirings 341.

[0134] Although not shown, wiring layer 330 may also include a bonding metal disposed on top, with a portion of the bonding metal exposed by interlayer insulating film 331, and the bonding metal may be bonded to bonding metal of another layered structure to form a bonding structure. In some embodiments, the bonding structure may be formed by Cu-Cu bonding, but is not limited thereto.

[0135] Figure 7 This is an example circuit diagram for a pixel group. Specifically, Figure 7 The circuit diagram shows Figures 2 to 6 The connection relationship between elements within the first pixel group PG1a. Figure 7 The first pixel group PG1a corresponds to Figures 2 to 6 The first pixel group PG1a, Figure 7 Each of the first photodiode PD1 to the sixteenth photodiode PD16 corresponds to Figures 2 to 6 The first photodiode region PR1 to the sixteenth photodiode region PR16, and Figure 7 The first MIM capacitor MIM1 to the fourth MIM capacitor MIM4 can respectively correspond to Figures 2 to 6 The first MIM capacitor MIM1 to the fourth MIM capacitor MIM4.

[0136] Reference Figures 2 to 7The first pixel group PG1a may include a first photodiode PD1 to a sixteenth photodiode PD16, wherein the first photodiode PD1 to the eighth photodiode PD8 share a first intermediate conversion gain transistor MCX1, a first low conversion gain transistor LCX1, a first reset transistor RX1, a first MIM capacitor MIM1, a second MIM capacitor MIM2, a first drive transistor DX1, and a first selection transistor SEL1, and the ninth photodiode PD9 to the sixteenth photodiode PD16 share a second intermediate conversion gain transistor MCX2, a second low conversion gain transistor LCX2, a second reset transistor RX2, a third MIM capacitor MIM3, a fourth MIM capacitor MIM4, a second drive transistor DX2, and a second selection transistor SEL2.

[0137] The first photodiode PD1 to the eighth photodiode PD8 share the first floating diffusion node FD1 and are electrically connected to the first floating diffusion node FD1. The ninth photodiode PD9 to the sixteenth photodiode PD16 share the second floating diffusion node FD2 and are electrically connected to the second floating diffusion node FD2. The first floating diffusion node FD1 and the second floating diffusion node FD2 can be separated from each other.

[0138] Each of the first photodiodes PD1 to PD8 can be electrically connected to the first floating diffusion node FD1 via each of the first transmission transistors TX1 to TX8. Each of the first transmission transistors TX1 to TX8 can provide photocharge generated from each of the first photodiodes PD1 to PD8 to the first floating diffusion node FD1 based on each of the first transmission signal TG1 to the eighth transmission signal TG8.

[0139] Each of the ninth photodiodes PD9 to the sixteenth photodiodes PD16 can be electrically connected to the second floating diffusion node FD2 via each of the ninth to sixteenth transmission transistors TX9 to TX16. Each of the ninth to sixteenth transmission transistors TX9 to TX16 can provide photocharge generated from each of the ninth to sixteenth photodiodes PD9 to PD16 to the second floating diffusion node FD2 based on each of the ninth to sixteenth transmission signals TG9 to TG16. In some embodiments, the first transmission signal TG1 to the sixteenth transmission signal TG16 can be obtained from... Figure 1 The row drive 120 is provided.

[0140] The first medium-conversion-gain transistor MCX1, the first low-conversion-gain transistor LCX1, and the first reset transistor RX1 can be connected in series with the first floating diffusion node FD1 and the power supply voltage V. DDBetween the power cords.

[0141] The first intermediate-conversion-gain transistor MCX1 may include a control terminal for receiving a first intermediate-conversion-gain enable signal MCG1, a first terminal electrically connected to one electrode of a first MIM capacitor MIM1, and a second terminal electrically connected to a first floating diffusion node FD1. In some embodiments, the first intermediate-conversion-gain transistor MCX1 may be an N-type metal-oxide-semiconductor (NMOS) transistor. In this disclosure, the first terminal may be referred to as the drain terminal, and the second terminal may be referred to as the source terminal.

[0142] The first low-switching-gain transistor LCX1 may include a control terminal for receiving a first low-switching-gain enable signal LCG1, a first terminal electrically connected to one electrode of the second MIM capacitor MIM2, and a second terminal electrically connected to one electrode of the first MIM capacitor MIM1. In some embodiments, the first low-switching-gain transistor LCX1 may be an NMOS transistor.

[0143] The first reset transistor RX1 may include a control terminal for receiving a first reset signal RG1 and is electrically connected to a power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to one electrode of the second MIM capacitor MIM2. In some embodiments, the first reset transistor RX1 may be an NMOS transistor.

[0144] The first MIM capacitor MIM1 may include one electrode electrically connected to a first terminal of the first intermediate conversion gain transistor MCX1 and a second terminal of the first low conversion gain transistor LCX1, and another electrode grounded. The second MIM capacitor MIM2 may include one electrode electrically connected to a first terminal of the first low conversion gain transistor LCX1 and a second terminal of the first reset transistor RX1, and another electrode grounded.

[0145] The second medium-conversion-gain transistor MCX2, the second low-conversion-gain transistor LCX2, and the second reset transistor RX2 can be connected in series with the second floating diffusion node FD2 and the power supply voltage V. DD Between the power cords.

[0146] The second intermediate conversion gain transistor MCX2 may include a control terminal for receiving the first intermediate conversion gain enable signal MCG1, a first terminal electrically connected to one electrode of the third MIM capacitor MIM3, and a second terminal electrically connected to the second floating diffusion node FD2. In some embodiments, the second intermediate conversion gain transistor MCX2 may be an NMOS transistor.

[0147] The second low-conversion-gain transistor LCX2 may include a control terminal for receiving a first low-conversion-gain enable signal LCG1, a first terminal electrically connected to one electrode of a fourth MIM capacitor MIM4, and a second terminal electrically connected to one electrode of a third MIM capacitor MIM3. In some embodiments, the second low-conversion-gain transistor LCX2 may be an NMOS transistor.

[0148] The second reset transistor RX2 may include a control terminal for receiving the first reset signal RG1 and an electrical connection to a power supply voltage V. DD The first terminal of the power supply line and the second terminal are electrically connected to one electrode of the fourth MIM capacitor MIM4. In some embodiments, the second reset transistor RX2 may be an NMOS transistor.

[0149] The third MIM capacitor MIM3 may include one electrode electrically connected to a first terminal of the second intermediate conversion gain transistor MCX2 and a second terminal of the second low conversion gain transistor LCX2, and another electrode grounded. The fourth MIM capacitor MIM4 may include one electrode electrically connected to a first terminal of the second low conversion gain transistor LCX2 and a second terminal of the second reset transistor RX2, and another electrode grounded.

[0150] In some implementations, the conversion gain mode of the first pixel group PG1a can be controlled by controlling the operation of the first intermediate conversion gain transistor MCX1, the first low conversion gain transistor LCX1, the second intermediate conversion gain transistor MCX2, and the second low conversion gain transistor LCX2.

[0151] In some embodiments, in response to the conduction of the first intermediate conversion gain transistor MCX1, the first low conversion gain transistor LCX1, and the first reset transistor RX1, the charge stored in the first floating diffusion node FD1 and the first MIM capacitor MIM1 and the second MIM capacitor MIM2 can be reset. In some embodiments, in response to the conduction of the second intermediate conversion gain transistor MCX2, the second low conversion gain transistor LCX2, and the second reset transistor RX2, the charge stored in the second floating diffusion node FD2 and the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4 can be reset.

[0152] The first driving transistor DX1 may include a control terminal electrically connected to the first floating diffusion node FD1, and an electrical connection to the power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to the first terminal of the first select transistor SEL1. In some embodiments, the first drive transistor DX1 may be an NMOS transistor.

[0153] The first selection transistor SEL1 may include a control terminal for receiving a first selection signal SG1, a first terminal electrically connected to a second terminal of a first driving transistor DX1, and a second terminal electrically connected to the i-th column line CLI. In some embodiments, the first selection transistor SEL1 may be an NMOS transistor.

[0154] The first driving transistor DX1 can amplify the photocharge according to the potential of the photocharge accumulated in the first floating diffusion node FD1 and send the pixel signal to the first selection transistor SEL1. The first selection transistor SEL1 can output the pixel signal to the i-th column line CLi electrically connected to the first photodiode PD1 to the eighth photodiode PD8 in response to the first selection signal SG1.

[0155] The second driving transistor DX2 may include a control terminal electrically connected to the second floating diffusion node FD2, and an electrical connection to the power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to the first terminal of the second selection transistor SEL2. In some embodiments, the second drive transistor DX2 may be an NMOS transistor.

[0156] The second selection transistor SEL2 may include a control terminal for receiving the first selection signal SG1, a first terminal electrically connected to the second terminal of the second driving transistor DX2, and a second terminal electrically connected to the j-th column line CLj. In some embodiments, the second selection transistor SEL2 may be an NMOS transistor.

[0157] The second driving transistor DX2 can amplify the photocharge according to the potential of the photocharge accumulated in the second floating diffusion node FD2 and send the pixel signal to the second selection transistor SEL2. The second selection transistor SEL2 can output the pixel signal to the j-th column line CLj electrically connected to the ninth photodiode PD9 to the sixteenth photodiode PD16 in response to the first selection signal SG1.

[0158] In some implementations, the first intermediate conversion gain enable signal MCG1, the first low conversion gain enable signal LCG1, the first reset signal RG1, and the first selection signal SG1 can be obtained from... Figure 1 The row drive 120 is provided.

[0159] Figure 8 This is a timing diagram illustrating an example of AF operation for a group of pixels. Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16This is a diagram used to explain an example of AF operation for pixel groups. Specifically, Figures 9 to 16 Each shows in terms of structure Figure 7 The potentials of the photodiode, floating diffusion node, and MIM capacitor in the AF operation of the first pixel group PG1a.

[0160] Reference Figure 3 , Figure 7 and Figure 8 During the reset period between time t0 and time t5, the power supply voltage V DD This can be supplied to the photodiode, floating diffusion node, and MIM capacitor sharing the b-th microlens MLb. During the reset period, the charge present in the photodiode, floating diffusion node, and MIM capacitor can leak out to the supply voltage V. DD The power cord was reset.

[0161] At time t0, the first intermediate conversion gain enable signal MCG1, the first low conversion gain enable signal LCG1, the first reset signal RG1, the first selection signal SG1, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can be at logic low level L. The first intermediate conversion gain transistor MCX1, the first low conversion gain transistor LCX1, the first reset transistor RX1, the first selection transistor SEL1, the second intermediate conversion gain transistor MCX2, the second low conversion gain transistor LCX2, the second reset transistor RX2, the second selection transistor SEL2, the fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned off.

[0162] At time t1, the first intermediate conversion gain enable signal MCG1, the first low conversion gain enable signal LCG1, and the first reset signal RG1 can transition from logic low level L to logic high level H. The first intermediate conversion gain transistor MCX1, the first low conversion gain transistor LCX1, the first reset transistor RX1, the second intermediate conversion gain transistor MCX2, the second low conversion gain transistor LCX2, and the second reset transistor RX2 can be turned on. Through the turn-on operation described above, the power supply voltage V... DD It can be provided to the first floating diffusion node FD1 and the second floating diffusion node FD2.

[0163] At time t2, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic low level L to logic high level H. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can then conduct. Through this conduction operation as described above, the power supply voltage V...DD It can be provided to the fourth photodiode PD4, the sixth photodiode PD6, the eleventh photodiode PD11, and the thirteenth photodiode PD13.

[0164] At time t3, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic high level H to logic low level L. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned off.

[0165] At time t4, the first intermediate conversion gain enable signal MCG1, the first low conversion gain enable signal LCG1, and the first reset signal RG1 can change from logic high level H to logic low level L. The first intermediate conversion gain transistor MCX1, the first low conversion gain transistor LCX1, the first reset transistor RX1, the second intermediate conversion gain transistor MCX2, the second low conversion gain transistor LCX2, and the second reset transistor RX2 can be turned off.

[0166] Figure 9 The potential at time t5 is shown. Additional reference is also provided. Figure 9 The charge accumulated in the fourth photodiode PD4, the sixth photodiode PD6, the eleventh photodiode PD11, and the thirteenth photodiode PD13 within the first pixel group PG1a can be drained to the power line and reset. Furthermore, the charge stored in the first floating diffusion node FD1, the second floating diffusion node FD2, and the first MIM capacitors MIM1 to MIM4 can be drained to the power line and reset.

[0167] During the integration period from time t5 to time t6, the fourth photodiode PD4, the sixth photodiode PD6, the eleventh photodiode PD11, and the thirteenth photodiode PD13 are exposed to light and undergo photoelectric conversion to generate photocharge. The photocharge generated by photoelectric conversion preferentially accumulates in the photodiodes (PD4, PD6, PD11, PD13). In a high-light environment, the charge accumulated in the photodiodes (PD4, PD6, PD11, PD13) from time t5 onwards can exceed the gate barrier of the cut-off transmission transistors (TX4, TX6, TX11, TX13) and overflow. The overflowing charge can be transferred to the first floating diffusion node FD1 and the second floating diffusion node FD2, as well as the first MIM capacitors MIM1 to the fourth MIM capacitors MIM4, and accumulate in the first floating diffusion node FD1 and the second floating diffusion node FD2, as well as the first MIM capacitors MIM1 to the fourth MIM capacitors MIM4. Specifically, the overflow charge can represent the charge accumulated when a certain amount or more of charge is charged into the photodiodes (PD4, PD6, PD11, PD13) while the transmission transistors (TX4, TX6, TX11, TX13) are turned off, by moving to the first floating diffusion node FD1 and the second floating diffusion node FD2, as well as the first MIM capacitors MIM1 to the fourth MIM capacitors MIM4.

[0168] During the integration period, the first intermediate conversion gain enable signal MCG1 is at logic low level L, and the first intermediate conversion gain transistor MCX1 and the second intermediate conversion gain transistor MCX2 are turned off, so that the first floating diffusion node FD1 can be electrically isolated from the first MIM capacitor MIM1 and the second MIM capacitor MIM2, and the second floating diffusion node FD2 can be electrically isolated from the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4. The first pixel group PG1a can operate in high conversion gain mode.

[0169] During the readout period from time t6 to time t22, the pixel signal generated in the first pixel group PG1a is sent to Figure 1 The readout circuit 130. During the readout period, the first reset level signal RLS1, the first pixel signal PSIG1, the second pixel signal PSIG2, the third pixel signal PSIG3, and the second reset level signal RLS2 can be sequentially sent to... Figure 1 The readout circuit 130. In some embodiments, during the readout period, a multi-exposure operation may be performed, in which multiple exposure operations are performed on multiple photodiodes within the first pixel group PG1a.

[0170] In some implementations, during the readout period, the first pixel group PG1a can operate in a three-conversion-gain mode, the first reset level signal RLS1 can be a reset level signal in a high conversion-gain mode, the first pixel signal PSIG1 can be a pixel signal in a high conversion-gain mode, the second pixel signal PSIG2 can be a pixel signal in a medium conversion-gain mode, the third pixel signal PSIG3 can be a pixel signal in a low conversion-gain mode, and the second reset level signal RLS2 can be a reset level signal in a low conversion-gain mode.

[0171] At time t6, the first selection signal SG1 transitions from logic low L to logic high H. The first selection transistor SEL1 turns on, and the second terminal of the first driving transistor DX1 is electrically connected to the i-th column line CL1. The second selection transistor SEL2 turns on, and the second terminal of the second driving transistor DX2 is electrically connected to the j-th column line CLj. Thereafter, during the readout period, the first selection signal SG1 remains at logic high H.

[0172] At time t7, the first low-switching-gain enable signal LCG1 and the first reset signal RG1 can transition from logic low level L to logic high level H. The first low-switching-gain transistor LCX1, the second low-switching-gain transistor LCX2, the first reset transistor RX1, and the second reset transistor RX2 can then be turned on. The power supply voltage V... DD They are supplied to the first MIM capacitors MIM1 through the fourth MIM capacitors MIM4, and the first MIM capacitors MIM1 through the fourth MIM capacitors MIM4 are resettable.

[0173] At time t8, the first reset level signal RLS1 can be output. Figure 10 The potential at time t8 is shown. Additional reference is also provided. Figure 10 The first reset level signal RLS1 may include a 1_1 reset level signal RLS1_L and a 1_2 reset level signal RLS1_R. The 1_1 reset level signal RLS1_L and the 1_2 reset level signal RLS1_R are pixel signals generated by the charge overflowing into the first floating diffusion node FD1 and the second floating diffusion node FD2, which are separated from each other. In the first reset level signal RLS1, the 1_1 reset level signal RLS1_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the first floating diffusion node FD1 connected to the fourth photodiode PD4 and the sixth photodiode PD6 located on the left side. The 1_1 reset level signal RLS1_L can be provided through the i-th column line CLI. Figure 1The readout circuit 130. In the first reset level signal RLS1, the 1_2 reset level signal RLS1_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the second floating diffusion node FD2 connected to the eleventh photodiode PD11 and the thirteenth photodiode PD13 located on the right side. The 1_2 reset level signal RLS1_R can be provided through the j-th column line CLj to... Figure 1 The readout circuit 130.

[0174] At time t9, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic low level L to logic high level H. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned on. Through the turn-on operation described above, the threshold voltage between the fourth photodiode PD4 and the sixth photodiode PD6 and the first floating diffusion node FD1 can be reduced, and the threshold voltage between the eleventh photodiode PD11 and the thirteenth photodiode PD13 and the second floating diffusion node FD2 can be reduced. The charge accumulated in the fourth photodiode PD4 and the sixth photodiode PD6 can move to the first floating diffusion node FD1 due to the potential difference, and the charge accumulated in the eleventh photodiode PD11 and the thirteenth photodiode PD13 can move to the second floating diffusion node FD2 due to the potential difference.

[0175] At time t10, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic high level H to logic low level L. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned off.

[0176] At time t11, the first pixel signal PSIG1 can be output. Figure 11 The potential at time t11 is shown. Additional reference is also provided. Figure 11The first pixel signal PSIG1 may include a 1_1 pixel signal PSIG1_L and a 1_2 pixel signal PSIG1_R, which are pixel signals generated by accumulating charge in the first floating diffusion node FD1 and the second floating diffusion node FD2, which are separated from each other. Within the first pixel signal PSIG1, the 1_1 pixel signal PSIG1_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the first floating diffusion node FD1 connected to the fourth photodiode PD4 and the sixth photodiode PD6 located on the left side. The 1_1 pixel signal PSIG1_L may be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the first pixel signal PSIG1, the 1_2 pixel signal PSIG1_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the second floating diffusion node FD2 connected to the eleventh photodiode PD11 and the thirteenth photodiode PD13 located on the right side. The 1_2 pixel signal PSIG1_R can be provided to the j-th column line CLj. Figure 1 The readout circuit 130.

[0177] At time t12, the first intermediate conversion gain enable signal MCG1 can transition from logic low level L to logic high level H, and the first low conversion gain enable signal LCG1 can transition from logic high level H to logic low level L. The first intermediate conversion gain transistor MCX1 and the second intermediate conversion gain transistor MCX2 can be turned on, and the first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 can be turned off. The turning on of the first intermediate conversion gain transistor MCX1 and the second intermediate conversion gain transistor MCX2 allows the first floating diffusion node FD1 and the first MIM capacitor MIM1 to be electrically connected, and the second floating diffusion node FD2 and the third MIM capacitor MIM3 to be electrically connected. The first pixel group PG1a operates in intermediate conversion gain mode, and the capacitance of the first floating diffusion node FD1 and the second floating diffusion node FD2 can be increased.

[0178] At time t13, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic low level L to logic high level H. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned on.

[0179] Figure 12 The potential at time t13 is shown. Additional reference is also provided. Figure 12Through the conduction of the fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 as described above, the threshold voltage between the fourth photodiode PD4 and the sixth photodiode PD6 and the first floating diffusion node FD1 can be reduced, and the threshold voltage between the eleventh photodiode PD11 and the thirteenth photodiode PD13 and the second floating diffusion node FD2 can be reduced. The charge accumulated in the fourth photodiode PD4 and the sixth photodiode PD6 can move to the first floating diffusion node FD1 and the first MIM capacitor MIM1 due to the potential difference, and the charge accumulated in the eleventh photodiode PD11 and the thirteenth photodiode PD13 can move to the second floating diffusion node FD2 and the third MIM capacitor MIM3 due to the potential difference.

[0180] At time t14, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic high level H to logic low level L. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned off.

[0181] At time t15, the second pixel signal PSIG2 can be output. Figure 13 The potential at time t15 is shown. Additional reference is also provided. Figure 13 The second pixel signal PSIG2 may include a 2_1 pixel signal PSIG2_L and a 2_2 pixel signal PSIG2_R. The 2_1 pixel signal PSIG2_L and the 2_2 pixel signal PSIG2_R are pixel signals generated by accumulating charge in the first floating diffusion node FD1 and the second floating diffusion node FD2, which are separated from each other. Within the second pixel signal PSIG2, the 2_1 pixel signal PSIG2_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged in the first floating diffusion node FD1 and the first MIM capacitor MIM1 connected to the fourth photodiode PD4 and the sixth photodiode PD6 located on the left side. The 2_1 pixel signal PSIG2_L can be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the second pixel signal PSIG2, the 2_2 pixel signal PSIG2_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged in the second floating diffusion node FD2 connected to the eleventh photodiode PD11 and the thirteenth photodiode PD13 located on the right side, and the third MIM capacitor MIM3. The 2_2 pixel signal PSIG2_R can be provided to the j-th column line CLj. Figure 1 The readout circuit 130.

[0182] At time t16, the first low conversion gain enable signal LCG1 can transition from logic low level L to logic high level H, and the first reset signal RG1 can transition from logic high level H to logic low level L. The first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 can be turned on, and the first reset transistor RX1 and the second reset transistor RX2 can be turned off. The first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 being turned on allows the first floating diffusion node FD1 and the first MIM capacitor MIM1 and the second MIM capacitor MIM2 to be electrically connected, and the second floating diffusion node FD2 and the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4 to be electrically connected. The first pixel group PG1a operates in low conversion gain mode, and the capacitance of the first floating diffusion node FD1 and the second floating diffusion node FD2 can be increased.

[0183] At time t17, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic low level L to logic high level H. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned on.

[0184] Figure 14 The potential at time t17 is shown. Additional reference is also provided. Figure 14 Through the conduction operation of the fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 as described above, the threshold voltage between the fourth photodiode PD4 and the sixth photodiode PD6 and the first floating diffusion node FD1 can be reduced, and the threshold voltage between the eleventh photodiode PD11 and the thirteenth photodiode PD13 and the second floating diffusion node FD2 can be reduced. The charge accumulated in the fourth photodiode PD4 and the sixth photodiode PD6 can be moved to the first floating diffusion node FD1 and the first MIM capacitor MIM1 and the second MIM capacitor MIM2 due to the potential difference, and the charge accumulated in the eleventh photodiode PD11 and the thirteenth photodiode PD13 can be moved to the second floating diffusion node FD2 and the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4 due to the potential difference.

[0185] At time t18, the fourth transmission signal TG4, the sixth transmission signal TG6, the eleventh transmission signal TG11, and the thirteenth transmission signal TG13 can transition from logic high level H to logic low level L. The fourth transmission transistor TX4, the sixth transmission transistor TX6, the eleventh transmission transistor TX11, and the thirteenth transmission transistor TX13 can be turned off.

[0186] At time t19, the third pixel signal PSIG3 can be output. Figure 15 The potential at time t19 is shown. Additional reference is also provided. Figure 15 The third pixel signal PSIG3 may include a 3_1 pixel signal PSIG3_L and a 3_2 pixel signal PSIG3_R. The 3_1 pixel signal PSIG3_L and the 3_2 pixel signal PSIG3_R are pixel signals generated by accumulating charge in the first floating diffusion node FD1 and the second floating diffusion node FD2, which are separated from each other. Within the third pixel signal PSIG3, the 3_1 pixel signal PSIG3_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the first floating diffusion node FD1 and the first MIM capacitor MIM1 and the second MIM capacitor MIM2, which are connected to the fourth photodiode PD4 and the sixth photodiode PD6 located on the left side. The 3_1 pixel signal PSIG3_L can be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the third pixel signal PSIG3, the 3_2 pixel signal PSIG3_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the second floating diffusion node FD2 connected to the eleventh photodiode PD11 and the thirteenth photodiode PD13 located on the right side, as well as the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4. The 3_2 pixel signal PSIG3_R can be provided to the j-th column line CLj. Figure 1 The readout circuit 130.

[0187] At time t20, the first reset signal RG1 can transition from logic low level L to logic high level H. The first reset transistor RX1 and the second reset transistor RX2 can then be turned on. Through this turn-on operation as described above, the power supply voltage V... DD The charge can be supplied to the fourth photodiode PD4, the sixth photodiode PD6, the eleventh photodiode PD11, the thirteenth photodiode PD13, the first floating diffusion node FD1, the second floating diffusion node FD2, and the first MIM capacitors MIM1 to MIM capacitors MIM4. The charge present in the fourth photodiode PD4, the sixth photodiode PD6, the eleventh photodiode PD11, the thirteenth photodiode PD13, the first floating diffusion node FD1, the second floating diffusion node FD2, and the first MIM capacitors MIM1 to MIM capacitors MIM4 can leak out to the supplied power supply voltage V. DD The power cord was reset.

[0188] At time t21, the second reset level signal RLS2 can be output. Figure 16 The potential at time t21 is shown. Additional reference is also provided. Figure 16The second reset level signal RLS2 may include a 2_1 reset level signal RLS2_L and a 2_2 reset level signal RLS2_R. The 2_1 and 2_2 reset level signals RLS2_L are pixel signals generated by the charge remaining in each of the first and second floating diffusion nodes FD1 and FD2, which are separated from each other. In the second reset level signal RLS2, the 2_1 reset level signal RLS2_L may be a pixel signal amplified by a voltage corresponding to the amount of charge remaining in the first floating diffusion node FD1 connected to the fourth photodiode PD4 and the sixth photodiode PD6 located on the left side, as well as in the first MIM capacitor MIM1 and the second MIM capacitor MIM2. The 2_1 reset level signal RLS2_L may be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the second reset level signal RLS2, the 2_2 reset level signal RLS2_R can be a pixel signal amplified by the voltage corresponding to the amount of charge remaining in the second floating diffusion node FD2 connected to the eleventh photodiode PD11 and the thirteenth photodiode PD13 located on the right side, as well as the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4. The 2_2 reset level signal RLS2_R can be provided through the j-th column line CLj to... Figure 1 The readout circuit 130.

[0189] At time t22, the first selection signal SG1 can transition from logic high level H to logic low level L. The first selection transistor SEL1 and the second selection transistor SEL2 are turned off, and the readout period can be terminated.

[0190] The first pixel group PG1a may include at least two photodiodes connected to a separate shared floating diffusion node and sharing a b-th microlens MLB. By arranging at least two photodiodes within the first pixel group PG1a as described above, the image sensor can achieve both high-resolution image quality and accurate AF performance without the need for pixels including a metal layer that only perform phase detection operations. Furthermore, by arranging at least two photodiodes within the first pixel group PG1a as described above, the image sensor can easily perform AF operations by receiving the left and right pixel signals together, without needing to receive pixel signals in an RSS (reset-signal-signal) manner in the order of reset level signal, left pixel signal, and left-right summed pixel signal.

[0191] Figure 17 This is a plan view showing an example of a pixel array. Figure 18 yes Figure 17 An example magnified view of the first pixel group of the pixel array. Figure 17 and Figure 18The pixel array 110' and the first pixel group PG1b to the fourth pixel group PG4b can each correspond to Figure 2 and Figure 3 The pixel array 110 and the first pixel group PG1a to the fourth pixel group PG4a. For ease of explanation below, the focus will be on the pixel array 110 and the first pixel group PG1a to the fourth pixel group PG4a. Figure 2 and Figure 3 The pixel array 110 and the differences between the first pixel group PG1a to the fourth pixel group PG4a are used to describe the pixel array 110' and the first pixel group PG1b to the fourth pixel group PG4b.

[0192] Reference Figure 1 , Figure 17 ,and Figure 18 The pixel array 110' may include a first pixel group PG1b to a fourth pixel group PG4b. Each of the first pixel groups PG1b to the fourth pixel group PG4b may include four sub-pixel groups arranged in a first direction D1 and a second direction D2, and each sub-pixel group may share a floating diffusion node, a reset transistor, a conversion gain transistor, a MIM capacitor, and a drive transistor. The image sensor 100 can be miniaturized and provide high-resolution images through the shared structure of each sub-pixel group.

[0193] The first pixel group PG1b may include 1-1 sub-pixel groups PGs11' to 1-4 sub-pixel groups PGs14' arranged in a 2×2 array in the first direction D1 and the second direction D2, and the second pixel group PG2b may include 2-1 sub-pixel groups PGs21' to 2-4 sub-pixel groups PGs24' arranged in a 2×2 array in the first direction D1 and the second direction D2. Similarly, the third pixel group PG3b may include 3-1 sub-pixel groups PGs31' to 3-4 sub-pixel groups PGs34' arranged in a 2×2 array in the first direction D1 and the second direction D2, and the fourth pixel group PG4b may include 4-1 sub-pixel groups PGs41' to 4-4 sub-pixel groups PGs44' arranged in a 2×2 array in the first direction D1 and the second direction D2.

[0194] For ease of explanation, the following description of subpixel groups will focus on subpixel groups 1_1 (PGs11') to 1_4 (PGs14'). The description of subpixel groups 1_1 (PGs11') to 1_4 (PGs14') below can be applied to other subpixel groups within pixel array 110'.

[0195] Sub-pixel groups PGs11' to PGs14' can be separated by a pixel group separation region 310s extending in a first direction D1 and a second direction D2. The pixel group separation region 310s is part of the device isolation pattern 310, and the sub-pixel groups PGs11' to PGs14' can be separated by the pixel group separation region 310s in the first direction D1 and the second direction D2.

[0196] Sub-pixel group PGs11' may include first photodiode regions PR1 to fourth photodiode regions PR4 arranged in a 2×2 array on the first direction D1 and the second direction D2, and sub-pixel group PGs13' may include fifth photodiode regions PR5 to eighth photodiode regions PR8 arranged in a 2×2 array on the first direction D1 and the second direction D2. Sub-pixel group PGs12' may include ninth photodiode regions PR9 to twelfth photodiode regions PR12 arranged in a 2×2 array on the first direction D1 and the second direction D2, and sub-pixel group PGs14' may include thirteenth photodiode regions PR13 to sixteenth photodiode regions PR16 arranged in a 2×2 array on the first direction D1 and the second direction D2.

[0197] The first photodiode region PR1 to the fourth photodiode region PR4 share the first floating diffusion node FD1, and the photodiodes in the first photodiode region PR1 to the fourth photodiode region PR4 are electrically connected to the first floating diffusion node FD1. The ninth photodiode region PR9 to the twelfth photodiode region PR12 share the second floating diffusion node FD2, and the photodiodes in the ninth photodiode region PR9 to the twelfth photodiode region PR12 are electrically connected to the second floating diffusion node FD2. The fifth photodiode region PR5 to the eighth photodiode region PR8 share the third floating diffusion node FD3, and the photodiodes in the fifth photodiode region PR5 to the eighth photodiode region PR8 are electrically connected to the third floating diffusion node FD3. The thirteenth photodiode region PR13 to the sixteenth photodiode region PR16 share the fourth floating diffusion node FD4, and the photodiodes in the thirteenth photodiode region PR13 to the sixteenth photodiode region PR16 are electrically connected to the fourth floating diffusion node FD4. The first floating diffusion node FD1 to the fourth floating diffusion node FD4 are electrically isolated from each other.

[0198] The first floating diffusion node FD1 may include a first polysilicon local interconnect PLI1'. At least a portion of the first polysilicon local interconnect PLI1' may be planarly (on a plane) stacked with the first photodiode regions PR1 to the fourth photodiode regions PR4. The second floating diffusion node FD2 may include a second polysilicon local interconnect PLI2'. At least a portion of the second polysilicon local interconnect PLI2' may be planarly (on a plane) stacked with the ninth photodiode region PR9 to the twelfth photodiode region PR12. The third floating diffusion node FD3 may include a third polysilicon local interconnect PLI3'. At least a portion of the third polysilicon local interconnect PLI3' may be planarly (on a plane) stacked with the fifth photodiode region PR5 to the eighth photodiode region PR8. The fourth floating diffusion node FD4 may include a fourth polysilicon local interconnect PLI4'. At least a portion of the fourth polysilicon local interconnect PLI4' may be planarly (on a plane) stacked with the thirteenth photodiode region PR13 to the sixteenth photodiode region PR16.

[0199] The first polysilicon local interconnect PLI1' to the fourth polysilicon local interconnect PLI4' include conductive patterns, wherein the conductive patterns may include at least one of doped polysilicon, metal, metal silicide, metal nitride, and metal-containing film. For example, each of the first polysilicon local interconnect PLI1' to the fourth polysilicon local interconnect PLI4' may be made of polysilicon doped with N-type impurities (such as phosphorus (P) or arsenic (As)).

[0200] Furthermore, the pixel group separation region 310s can be arranged between the first polysilicon local interconnect PLI1' and the fourth polysilicon local interconnect PLI4'.

[0201] Although not shown, insulating spacers may be positioned along the sidewalls of each of the first polysilicon local interconnects PLI1' to the fourth polysilicon local interconnect PLI4'.

[0202] The a-th microlens MLA can be positioned on the first photodiode region PR1 and the third photodiode region PR3 of sub-pixel group PGs11'. Each of the first photodiode region PR1 and the third photodiode region PR3 can correspond to one of the a-th microlenses MLA. The a-th microlens MLA can be positioned on the tenth photodiode region PR10 and the twelfth photodiode region PR12 of sub-pixel group PGs12'. Each of the tenth photodiode region PR10 and the twelfth photodiode region PR12 can correspond to one of the a-th microlenses MLA. The a-th microlens MLA can be positioned on the fifth photodiode region PR5 and the seventh photodiode region PR7 of sub-pixel group PGs13'. Each of the fifth photodiode region PR5 and the seventh photodiode region PR7 can correspond to one of the a-th microlenses MLA. The a-th microlens MLA can be positioned on the fourteenth photodiode region PR14 and the sixteenth photodiode region PR16 of sub-pixel group PGs14'. Each of the fourteenth photodiode region PR14 and the sixteenth photodiode region PR16 can correspond to one of the a-th microlenses MLa.

[0203] The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the a-th microlens MLa and generate... Figure 1 Image data IDTA.

[0204] The b-th microlens MLb can be arranged across sub-pixel groups 1-1 (PGs11') and 1-2 (PGs12'), and can be positioned on the second photodiode region PR2, the fourth photodiode region PR4, the ninth photodiode region PR9, and the eleventh photodiode region PR11. The second photodiode region PR2, the fourth photodiode region PR4, the ninth photodiode region PR9, and the eleventh photodiode region PR11 can share the b-th microlens MLb. Furthermore, the b-th microlens MLb can be arranged across sub-pixel groups 1-3 (PGs13') and 1-4 (PGs14'), and can be positioned on the sixth photodiode region PR6, the eighth photodiode region PR8, the thirteenth photodiode region PR13, and the fifteenth photodiode region PR15. The sixth photodiode region PR6, the eighth photodiode region PR8, the thirteenth photodiode region PR13, and the fifteenth photodiode region PR15 can share the b-th microlens MLb.

[0205] The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the b-th microlens MLb and generate image data IDTA or phase data PDTA. The readout circuit 130 can receive the pixel signal corresponding to the photodiodes in the left-hand second photodiode region PR2 and the fourth photodiode region PR4, among the second photodiode region PR2, the fourth photodiode region PR4, the ninth photodiode region PR9, and the eleventh photodiode region PR11, to extract first phase information; and can receive the pixel signal corresponding to the photodiodes in the right-hand ninth photodiode region PR9 and the eleventh photodiode region PR11 to extract second phase information. Similarly, the readout circuit 130 can receive pixel signals corresponding to the photodiodes in the sixth photodiode region PR6 and the eighth photodiode region PR8 located on the left, among the sixth photodiode region PR6, the eighth photodiode region PR8, the thirteenth photodiode region PR13, and the fifteenth photodiode region PR15, to extract first phase information, and can receive pixel signals corresponding to the photodiodes in the thirteenth photodiode region PR13 and the fifteenth photodiode region PR15 located on the right to extract second phase information.

[0206] The readout circuit 130 generates phase data PDTA by comparing the first phase information with the second phase information. The readout circuit 130 can simultaneously receive pixel signals from the photodiodes in the second photodiode region PR2, the fourth photodiode region PR4, the sixth photodiode region PR6, the eighth photodiode region PR8, the ninth photodiode region PR9, the eleventh photodiode region PR11, the thirteenth photodiode region PR13, and the fifteenth photodiode region PR15 through a separation structure from the first floating diffusion node FD1 to the fourth floating diffusion node FD4.

[0207] Furthermore, the readout circuit 130 can generate image data IDTA based on the pixel signals of the photodiodes in the second photodiode region PR2, the fourth photodiode region PR4, the sixth photodiode region PR6, the eighth photodiode region PR8, the ninth photodiode region PR9, the eleventh photodiode region PR11, the thirteenth photodiode region PR13, and the fifteenth photodiode region PR15.

[0208] Figure 19 This is an example circuit diagram for a pixel group. Specifically, Figure 19 The circuit diagram shows Figure 17 and Figure 18 The connection relationship between elements within the first pixel group PG1b. Figure 19 The first pixel group PG1b can correspond to Figures 17 to 18 The first pixel group PG1b, Figure 19 The first photodiode PD1 to the sixteenth photodiode PD16 can respectively correspond to Figures 17 to 18 The first photodiode region PR1 to the sixteenth photodiode region PR16, and Figure 19 The first MIM capacitor MIM1 to the fourth MIM capacitor MIM4 can respectively correspond to Figures 2 to 6 The first MIM capacitor MIM1 to the fourth MIM capacitor MIM4.

[0209] Reference Figures 17 to 19 The first pixel group PG1b may include first photodiodes PD1 to sixteenth photodiodes PD16, wherein first photodiodes PD1 to fourth photodiodes PD4, fifth photodiodes PD5 to eighth photodiodes PD8, ninth photodiodes PD9 to twelfth photodiodes PD12 and thirteenth photodiodes PD13 to sixteenth photodiodes PD16 may respectively share first low conversion gain transistors LCX1 to fourth low conversion gain transistors LCX4, first reset transistors RX1 to fourth reset transistors RX4, first MIM capacitors MIM1 to fourth MIM capacitors MIM4, first driving transistors DX1 to fourth driving transistors DX4, and first selection transistors SEL1 to fourth selection transistors SEL4.

[0210] The first photodiodes PD1 to PD4 share the first floating diffusion node FD1 and are electrically connected to it. The ninth photodiodes PD9 to twelfth photodiodes PD12 share the second floating diffusion node FD2 and are electrically connected to it. The fifth photodiodes PD5 to PD8 share the third floating diffusion node FD3 and are electrically connected to it. The thirteenth photodiodes PD13 to sixteenth photodiodes PD16 share the fourth floating diffusion node FD4 and are electrically connected to it. The first floating diffusion node FD1 to the fourth floating diffusion node FD4 can be separated from each other.

[0211] Each of the first photodiodes PD1 to PD4 can be electrically connected to the first floating diffusion node FD1 via each of the first transmission transistors TX1 to TX4. Each of the first transmission transistors TX1 to TX4 can provide the photocharge generated from each of the first photodiodes PD1 to PD4 to the first floating diffusion node FD1 based on each of the first transmission signal TG1 to the fourth transmission signal TG4.

[0212] Each of the ninth photodiodes PD9 to twelfth photodiodes PD12 can be electrically connected to the second floating diffusion node FD2 via each of the ninth transmission transistors TX9 to twelfth transmission transistors TX12. Each of the ninth transmission transistors TX9 to twelfth transmission transistors TX12 can provide the photocharge generated from each of the ninth photodiodes PD9 to twelfth transmission transistors TG12 to the second floating diffusion node FD2 based on each of the ninth transmission signal TG9 to twelfth transmission signal TG12.

[0213] Each of the fifth photodiode PD5 to the eighth photodiode PD8 can be electrically connected to the third floating diffusion node FD3 via each of the fifth transmission transistor TX5 to the eighth transmission transistor TX8. Each of the fifth transmission transistor TX5 to the eighth transmission transistor TX8 can provide the photocharge generated from each of the fifth photodiode PD5 to the eighth photodiode PD8 to the third floating diffusion node FD3 based on each of the fifth transmission signal TG5 to the eighth transmission signal TG8.

[0214] Each of the thirteenth photodiode PD13 through the sixteenth photodiode PD16 can be electrically connected to the fourth floating diffusion node FD4 via each of the thirteenth transfer transistor TX13 through the sixteenth transfer transistor TX16. Each of the thirteenth transfer transistor TX13 through the sixteenth transfer transistor TX16 can provide the photocharge generated from each of the thirteenth photodiode PD13 through the sixteenth transfer signal TG16 to the fourth floating diffusion node FD4.

[0215] The first low-switching-gain transistor LCX1 may include a control terminal receiving a first low-switching-gain enable signal LCG1, a first terminal electrically connected to one electrode of a first MIM capacitor MIM1, and a second terminal electrically connected to a first floating diffusion node FD1. In some embodiments, the first low-switching-gain transistor LCX1 may be an NMOS transistor.

[0216] The first reset transistor RX1 may include a control terminal for receiving a first reset signal RG1 and is electrically connected to a power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to one electrode of the first MIM capacitor MIM1. In some embodiments, the first reset transistor RX1 may be an NMOS transistor.

[0217] The first MIM capacitor MIM1 may include one electrode electrically connected to a first terminal of the first low conversion gain transistor LCX1 and a second terminal of the first reset transistor RX1, and another electrode grounded.

[0218] The second low-conversion-gain transistor LCX2 may include a control terminal receiving a first low-conversion-gain enable signal LCG1, a first terminal electrically connected to one electrode of a third MIM capacitor MIM3, and a second terminal electrically connected to a second floating diffusion node FD2. In some embodiments, the second low-conversion-gain transistor LCX2 may be an NMOS transistor.

[0219] The second reset transistor RX2 may include a control terminal for receiving the first reset signal RG1 and an electrical connection to a power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to one electrode of the third MIM capacitor MIM3. In some embodiments, the second reset transistor RX2 may be an NMOS transistor.

[0220] The third MIM capacitor MIM3 may include one electrode electrically connected to the first terminal of the second low conversion gain transistor LCX2 and the second terminal of the second reset transistor RX2, and another electrode grounded.

[0221] The third low-conversion-gain transistor LCX3 may include a control terminal receiving the second low-conversion-gain enable signal LCG2, a first terminal electrically connected to one electrode of the second MIM capacitor MIM2, and a second terminal electrically connected to the third floating diffusion node FD3. In some embodiments, the third low-conversion-gain transistor LCX3 may be an NMOS transistor.

[0222] The third reset transistor RX3 may include a control terminal for receiving the second reset signal RG2, and is electrically connected to a power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to one electrode of the second MIM capacitor MIM2. In some embodiments, the third reset transistor RX3 may be an NMOS transistor.

[0223] The second MIM capacitor MIM2 may include one electrode electrically connected to the first terminal of the third low conversion gain transistor LCX3 and the second terminal of the third reset transistor RX3, and another electrode grounded.

[0224] The fourth low-switching-gain transistor LCX4 may include a control terminal receiving the second low-switching-gain enable signal LCG2, a first terminal electrically connected to one electrode of the fourth MIM capacitor MIM4, and a second terminal electrically connected to the fourth floating diffusion node FD4. In some embodiments, the fourth low-switching-gain transistor LCX4 may be an NMOS transistor.

[0225] The fourth reset transistor RX4 may include a control terminal for receiving the second reset signal RG2, and an electrical connection to the power supply voltage V.DD The first terminal of the power supply line and the second terminal are electrically connected to one electrode of the fourth MIM capacitor MIM4. In some embodiments, the fourth reset transistor RX4 may be an NMOS transistor.

[0226] The fourth MIM capacitor MIM4 may include one electrode electrically connected to the first terminal of the fourth low conversion gain transistor LCX4 and the second terminal of the fourth reset transistor RX4, and another electrode grounded.

[0227] In some implementations, the conversion gain mode of the first pixel group PG1b can be controlled by controlling the operation of the first low conversion gain transistor LCX1 to the fourth low conversion gain transistor LCX4.

[0228] In some embodiments, in response to the conduction of the first low-conversion-gain transistor LCX1 and the first reset transistor RX1, the charge stored in the first floating diffusion node FD1 and the first MIM capacitor MIM1 can be reset. In some embodiments, in response to the conduction of the second low-conversion-gain transistor LCX2 and the second reset transistor RX2, the charge stored in the second floating diffusion node FD2 and the third MIM capacitor MIM3 can be reset. In some embodiments, in response to the conduction of the third low-conversion-gain transistor LCX3 and the third reset transistor RX3, the charge stored in the third floating diffusion node FD3 and the second MIM capacitor MIM2 can be reset. In some embodiments, in response to the conduction of the fourth low-conversion-gain transistor LCX4 and the fourth reset transistor RX4, the charge stored in the fourth floating diffusion node FD4 and the fourth MIM capacitor MIM4 can be reset.

[0229] The first driving transistor DX1 may include a control terminal electrically connected to the first floating diffusion node FD1, and an electrical connection to the power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to the first terminal of the first select transistor SEL1. In some embodiments, the first drive transistor DX1 may be an NMOS transistor.

[0230] The first selection transistor SEL1 may include a control terminal for receiving a first selection signal SG1, a first terminal electrically connected to a second terminal of a first driving transistor DX1, and a second terminal electrically connected to the i-th column line CLI. In some embodiments, the first selection transistor SEL1 may be an NMOS transistor.

[0231] The first driving transistor DX1 can amplify the photocharge according to the potential of the photocharge accumulated in the first floating diffusion node FD1 and transmit the pixel signal to the first selection transistor SEL1. The first selection transistor SEL1 can output the pixel signal to the i-th column line CLi electrically connected to the first photodiode PD1 to the fourth photodiode PD4 in response to the first selection signal SG1.

[0232] The second driving transistor DX2 may include a control terminal electrically connected to the second floating diffusion node FD2, and an electrical connection to the power supply voltage V. DD The first terminal of the power supply line and the second terminal electrically connected to the first terminal of the second selection transistor SEL2. In some embodiments, the second drive transistor DX2 may be an NMOS transistor.

[0233] The second selection transistor SEL2 may include a control terminal for receiving the first selection signal SG1, a first terminal electrically connected to the second terminal of the second driving transistor DX2, and a second terminal electrically connected to the j-th column line CLj. In some embodiments, the second selection transistor SEL2 may be an NMOS transistor.

[0234] The second driving transistor DX2 can amplify the photocharge according to the potential of the photocharge accumulated in the second floating diffusion node FD2 and transmit the pixel signal to the second selection transistor SEL2. The second selection transistor SEL2 can output the pixel signal to the j-th column line CLj electrically connected to the ninth photodiode PD9 to the twelfth photodiode PD12 in response to the first selection signal SG1.

[0235] The third driving transistor DX3 may include a control terminal electrically connected to the third floating diffusion node FD3, and an electrical connection to the power supply voltage V. DD The first terminal of the power supply line and the second terminal are electrically connected to the first terminal of the third selection transistor SEL3. In some embodiments, the third drive transistor DX3 may be an NMOS transistor.

[0236] The third selection transistor SEL3 may include a control terminal for receiving the second selection signal SG2, a first terminal electrically connected to the second terminal of the third drive transistor DX3, and a second terminal electrically connected to the i-th column line CLI. In some embodiments, the third selection transistor SEL3 may be an NMOS transistor.

[0237] The third driving transistor DX3 can amplify the photocharge based on the potential of the photocharge accumulated in the third floating diffusion node FD3 and transmit the pixel signal to the third selection transistor SEL3. The third selection transistor SEL3 can output the pixel signal to the i-th column line CLi electrically connected to the fifth photodiode PD5 to the eighth photodiode PD8 in response to the second selection signal SG2.

[0238] The fourth driving transistor DX4 may include a control terminal electrically connected to the fourth floating diffusion node FD4, and an electrical connection to the supply voltage V. DD The first terminal of the power supply line and the second terminal are electrically connected to the first terminal of the fourth select transistor SEL4. In some embodiments, the fourth drive transistor DX4 may be an NMOS transistor.

[0239] The fourth selection transistor SEL4 may include a control terminal for receiving the second selection signal SG2, a first terminal electrically connected to the second terminal of the second driving transistor DX2, and a second terminal electrically connected to the j-th column line CLj. In some embodiments, the fourth selection transistor SEL4 may be an NMOS transistor.

[0240] The fourth driving transistor DX4 can amplify the photocharge based on the potential of the photocharge accumulated in the fourth floating diffusion node FD4 and transmit the pixel signal to the fourth selection transistor SEL4. The fourth selection transistor SEL4 can output the pixel signal to the j-th column line CLj electrically connected to the thirteenth photodiode PD13 to the sixteenth photodiode PD16 in response to the second selection signal SG2.

[0241] In some implementations, the first low conversion gain enable signal LCG1 and the second low conversion gain enable signal LCG2, the first reset signal RG1 and the second reset signal RG2, and the first selection signal SG1 and the second selection signal SG2 can be obtained from... Figure 1 The row drive 120 is provided.

[0242] Figure 20 This is a timing diagram illustrating an example of AF operation for a group of pixels. Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 This is a diagram used to explain an example of AF operation for pixel groups. Specifically, Figures 21 to 26 Each shows in terms of structure Figure 19 The potentials of the photodiode, floating diffusion node, and MIM capacitor in the AF operation of the first pixel group PG1b. For ease of explanation below, the main focus will be on describing... Figure 18AF operation of subpixel group PGs11' and subpixel group PGs12' of subpixel group 1_1.

[0243] Reference Figures 18 to 20 During the reset period between time point t30 and time point t35, the power supply voltage V DD This can be supplied to the photodiode, floating diffusion node, and MIM capacitor sharing the b-th microlens MLb. During the reset period, the charge present in the photodiode, floating diffusion node, and MIM capacitor can leak out to the supply voltage V. DD The power cord was reset.

[0244] At time t30, the first low conversion gain enable signal LCG1, the first reset signal RG1, the first select signal SG1, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can be at logic low level L. The first low conversion gain transistor LCX1, the first reset transistor RX1, the first select transistor SEL1, the second low conversion gain transistor LCX2, the second reset transistor RX2, the second select transistor SEL2, the second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can be turned off.

[0245] At time t31, the first low-switching-gain enable signal LCG1 and the first reset signal RG1 can transition from logic low level L to logic high level H. The first low-switching-gain transistor LCX1, the first reset transistor RX1, the second low-switching-gain transistor LCX2, and the second reset transistor RX2 can then be turned on. Through this turn-on operation as described above, the power supply voltage V... DD It can be provided to the first floating diffusion node FD1 and the second floating diffusion node FD2.

[0246] At time t32, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can transition from logic low level L to logic high level H. The second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can then conduct. Through this conduction operation as described above, the power supply voltage V... DD It can be provided to the second photodiode PD2, the fourth photodiode PD4, the ninth photodiode PD9, and the eleventh photodiode PD11.

[0247] At time t33, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can transition from logic high level H to logic low level L. The second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can be turned off.

[0248] At time t34, the first low conversion gain enable signal LCG1 and the first reset signal RG1 can transition from logic high level H to logic low level L. The first low conversion gain transistor LCX1, the first reset transistor RX1, the second low conversion gain transistor LCX2, and the second reset transistor RX2 can be turned off.

[0249] Figure 21 The potential at time t35 is shown. Additional reference is also provided. Figure 21 The charge accumulated in the second photodiode PD2, the fourth photodiode PD4, the ninth photodiode PD9, and the eleventh photodiode PD11 within the first pixel group PG1b can be drained to the power line and reset. Furthermore, the charge accumulated in the first floating diffusion node FD1, the second floating diffusion node FD2, the first MIM capacitor MIM1, and the third MIM capacitor MIM3 can be drained to the power line and reset.

[0250] During the integration period from time t35 to time t36, the second photodiode PD2, the fourth photodiode PD4, the ninth photodiode PD9, and the eleventh photodiode PD11 are exposed to light and undergo photoelectric conversion to generate photocharge. The photocharge generated by photoelectric conversion preferentially accumulates in the photodiodes (PD2, PD4, PD9, PD11). In a high-light environment, starting from time t35, the charge accumulated in the photodiodes (PD2, PD4, PD9, PD11) can exceed the gate barrier of the cut-off transmission transistors (TX2, TX4, TX9, TX11) and overflow, moving to the first floating diffusion node FD1 and the second floating diffusion node FD2, as well as the first MIM capacitor MIM1 and the third MIM capacitor MIM3, and accumulating in the first floating diffusion node FD1 and the second floating diffusion node FD2, as well as the first MIM capacitor MIM1 and the third MIM capacitor MIM3.

[0251] During the integration period, the first low conversion gain enable signal LCG1 is at logic low level L, the first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 are turned off, so that the first floating diffusion node FD1 can be electrically isolated from the first MIM capacitor MIM1, and the second floating diffusion node FD2 can be electrically isolated from the third MIM capacitor MIM3. The first pixel group PG1b can operate in high conversion gain mode.

[0252] During the readout period from time t36 to time t48, the pixel signal generated in the first pixel group PG1b is sent to Figure 1 The readout circuit 130. During the readout period, the third reset level signal RLS3, the fourth pixel signal PSIG4, the fifth pixel signal PSIG5, and the fourth reset level signal RLS4 can be sequentially sent to... Figure 1 The readout circuit 130. In some embodiments, during the readout period, a multi-exposure operation may be performed, in which multiple exposure operations are performed on the photodiodes within the first pixel group PG1b.

[0253] In some implementations, during the readout period, the first pixel group PG1b can operate in dual conversion gain mode, the third reset level signal RLS3 can be a reset level signal in high conversion gain mode, the fourth pixel signal PSIG4 can be a pixel signal in high conversion gain mode, the fifth pixel signal PSIG5 can be a pixel signal in low conversion gain mode, and the fourth reset level signal RLS4 can be a reset level signal in low conversion gain mode.

[0254] At time t36, the first selection signal SG1 transitions from logic low L to logic high H. The first selection transistor SEL1 is turned on, and the second terminal of the first driving transistor DX1 is electrically connected to the i-th column line CL1. The second selection transistor SEL2 is turned on, and the second terminal of the second driving transistor DX2 is electrically connected to the j-th column line CLj. Thereafter, during the readout period, the first selection signal SG1 remains at logic high H.

[0255] At time t37, the first reset signal RG1 can transition from logic low level L to logic high level H. The first reset transistor RX1 and the second reset transistor RX2 can then conduct. Power supply voltage V DD It is supplied to the first MIM capacitor MIM1 and the third MIM capacitor MIM3, and the first MIM capacitor MIM1 and the third MIM capacitor MIM3 can be reset.

[0256] At time t38, the third reset level signal RLS3 can be output. Figure 22 The potential at time t38 is shown. Additional reference is also provided. Figure 22The third reset level signal RLS3 may include a 3_1 reset level signal RLS3_L and a 3_2 reset level signal RLS3_R. The 3_1 and 3_2 reset level signals RLS3_L are pixel signals generated by the charge overflowing into the first and second floating diffusion nodes FD1 and FD2, which are separated from each other. Within the third reset level signal RLS3, the 3_1 reset level signal RLS3_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the first floating diffusion node FD1 connected to the second photodiode PD2 and the fourth photodiode PD4 located on the left side. The 3_1 reset level signal RLS3_L can be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the third reset level signal RLS3, the 3_2 reset level signal RLS3_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the second floating diffusion node FD2 connected to the ninth photodiode PD9 and the eleventh photodiode PD11 located on the right. The 3_2 reset level signal RLS3_R can be provided via the j-th column line CLj. Figure 1 The readout circuit 130.

[0257] At time t39, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can transition from logic low level L to logic high level H. The second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can be turned on. Through the turn-on operation described above, the threshold voltage between the second photodiode PD2 and the fourth photodiode PD4 and the first floating diffusion node FD1 can be reduced, and the threshold voltage between the ninth photodiode PD9 and the eleventh photodiode PD11 and the second floating diffusion node FD2 can be reduced. The charge accumulated in the second photodiode PD2 and the fourth photodiode PD4 can move to the first floating diffusion node FD1 due to the potential difference, and the charge accumulated in the ninth photodiode PD9 and the eleventh photodiode PD11 can move to the second floating diffusion node FD2 due to the potential difference.

[0258] At time t40, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can transition from logic high level H to logic low level L. The second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can be turned off.

[0259] At time t41, the fourth pixel signal PSIG4 can be output. Figure 23 The potential at time t41 is shown. Additional reference is also provided. Figure 23 The fourth pixel signal PSIG4 may include a 4_1 pixel signal PSIG4_L and a 4_2 pixel signal PSIG4_R. The 4_1 pixel signal PSIG4_L and the 4_2 pixel signal PSIG4_R are pixel signals generated by accumulating charge in the first floating diffusion node FD1 and the second floating diffusion node FD2, which are separated from each other. Within the fourth pixel signal PSIG4, the 4_1 pixel signal PSIG4_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the first floating diffusion node FD1 connected to the second photodiode PD2 and the fourth photodiode PD4 located on the left side. The 4_1 pixel signal PSIG4_L can be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the fourth pixel signal PSIG4, the 4_2 pixel signal PSIG4_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged into the second floating diffusion node FD2 connected to the ninth photodiode PD9 and the eleventh photodiode PD11 located on the right. The 4_2 pixel signal PSIG4_R can be provided to the j-th column line CLj. Figure 1 The readout circuit 130.

[0260] At time t42, the first low conversion gain enable signal LCG1 can transition from logic low level L to logic high level H, and the first reset signal RG1 can transition from logic high level H to logic low level L. The first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 can be turned on. The turning on of the first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 makes the first floating diffusion node FD1 and the first MIM capacitor MIM1 electrically connected, and the second floating diffusion node FD2 and the third MIM capacitor MIM3 electrically connected. The first pixel group PG1b operates in low conversion gain mode, and the capacitance of the first floating diffusion node FD1 and the second floating diffusion node FD2 can be increased.

[0261] At time t43, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can transition from logic low level L to logic high level H. The second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can be turned on.

[0262] Figure 24 The potential at time t43 is shown. Additional reference is also provided. Figure 24Through the conduction of the second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 as described above, the threshold voltage between the second photodiode PD2 and the fourth photodiode PD4 and the first floating diffusion node FD1 can be reduced, and the threshold voltage between the ninth photodiode PD9 and the eleventh photodiode PD11 and the second floating diffusion node FD2 can be reduced. The charge accumulated in the second photodiode PD2 and the fourth photodiode PD4 can move to the first floating diffusion node FD1 and the first MIM capacitor MIM1 due to the potential difference, and the charge accumulated in the ninth photodiode PD9 and the eleventh photodiode PD11 can move to the second floating diffusion node FD2 and the third MIM capacitor MIM3 due to the potential difference.

[0263] At time t44, the second transmission signal TG2, the fourth transmission signal TG4, the ninth transmission signal TG9, and the eleventh transmission signal TG11 can transition from logic high level H to logic low level L. The second transmission transistor TX2, the fourth transmission transistor TX4, the ninth transmission transistor TX9, and the eleventh transmission transistor TX11 can be turned off.

[0264] At time t45, the fifth pixel signal PSIG5 can be output. Figure 25 The potential at time t45 is shown. Additional reference is also provided. Figure 25 The fifth pixel signal PSIG5 may include a 5_1 pixel signal PSIG5_L and a 5_2 pixel signal PSIG5_R. The 5_1 pixel signal PSIG5_L and the 5_2 pixel signal PSIG5_R are pixel signals generated by accumulating charge in the first floating diffusion node FD1 and the second floating diffusion node FD2, which are separated from each other. Within the fifth pixel signal PSIG5, the 5_1 pixel signal PSIG5_L may be a pixel signal amplified by a voltage corresponding to the amount of charge charged in the first floating diffusion node FD1 and the first MIM capacitor MIM1 connected to the second photodiode PD2 and the fourth photodiode PD4 located on the left side. The 5_1 pixel signal PSIG5_L can be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the fifth pixel signal PSIG5, the 5_2 pixel signal PSIG5_R can be a pixel signal amplified by a voltage corresponding to the amount of charge charged in the second floating diffusion node FD2 connected to the ninth photodiode PD9 and the eleventh photodiode PD11 located on the right side, and the third MIM capacitor MIM3. The 5_2 pixel signal PSIG5_R can be provided to the j-th column line CLj. Figure 1 The readout circuit 130.

[0265] At time t46, the first reset signal RG1 can transition from logic low level L to logic high level H. The first reset transistor RX1 and the second reset transistor RX2 can then conduct. Through this conduction operation as described above, the power supply voltage V... DD The charge can be supplied to the second photodiode PD2, the fourth photodiode PD4, the ninth photodiode PD9, the eleventh photodiode PD11, the first floating diffusion node FD1, the second floating diffusion node FD2, the first MIM capacitor MIM1, and the third MIM capacitor MIM3. The charge present in the second photodiode PD2, the fourth photodiode PD4, the ninth photodiode PD9, the eleventh photodiode PD11, the first floating diffusion node FD1, the second floating diffusion node FD2, the first MIM capacitor MIM1, and the third MIM capacitor MIM3 can leak out to the supplied power supply voltage V. DD The power cord was reset.

[0266] At time t47, the fourth reset level signal RLS4 can be output. Figure 26 The potential at time t47 is shown. Additional reference is also provided. Figure 26 The fourth reset level signal RLS4 may include a 4_1 reset level signal RLS4_L and a 4_2 reset level signal RLS4_R. The 4_1 and 4_2 reset level signals RLS4_L are pixel signals generated by the charge remaining in each of the first and second floating diffusion nodes FD1 and FD2, which are separated from each other. Within the fourth reset level signal RLS4, the 4_1 reset level signal RLS4_L may be a pixel signal amplified by a voltage corresponding to the amount of charge remaining in the first floating diffusion node FD1 and the first MIM capacitor MIM1 connected to the second photodiode PD2 and the fourth photodiode PD4 located on the left side. The 4_1 reset level signal RLS4_L may be provided via the i-th column line CLI. Figure 1 The readout circuit 130. In the fourth reset level signal RLS4, the 4_2 reset level signal RLS4_R can be a pixel signal amplified by the voltage corresponding to the amount of charge remaining in the second floating diffusion node FD2 connected to the ninth photodiode PD9 and the eleventh photodiode PD11 located on the right and the third MIM capacitor MIM3. The 4_2 reset level signal RLS4_R can be provided through the j-th column line CLj to... Figure 1 The readout circuit 130.

[0267] At time t48, the first selection signal SG1 can transition from logic high level H to logic low level L. The first selection transistor SEL1 and the second selection transistor SEL2 are turned off, and the readout period can be terminated.

[0268] The first pixel group PG1b may include at least two photodiodes connected to a separate shared floating diffusion node and sharing a b-th microlens MLB. By arranging at least two photodiodes within the first pixel group PG1b as described above, the image sensor can achieve both high-resolution image quality and accurate AF performance without the need for pixels including a metal layer that only perform phase detection operations. Furthermore, by arranging at least two photodiodes within the first pixel group PG1b as described above, the image sensor can easily perform AF operations by receiving left and right pixel signals together, without needing to implement the RSS method.

[0269] Figure 27 This is a plan view showing an example of a group of pixels. Figure 27 The first pixel group PG1c, the first polysilicon local interconnect PLI1, the second polysilicon local interconnect PLI2, and the device isolation pattern 310' can respectively correspond to Figure 3 The first pixel group PG1a, the first polysilicon local interconnect PLI1, the second polysilicon local interconnect PLI2, and the device isolation pattern 310. For ease of explanation below, the focus will be on the... Figure 3 The differences between the first pixel group PG1a, the first polysilicon local interconnect PLI1, the second polysilicon local interconnect PLI2, and the device isolation pattern 310 are used to describe the first pixel group PG1c, the first polysilicon local interconnect PLI1, the second polysilicon local interconnect PLI2, and the device isolation pattern 310'.

[0270] Reference Figure 27 The first photodiode region PR1 to the sixteenth photodiode region PR16 in the first pixel group PG1c can be electrically separated by the device isolation pattern 310'.

[0271] In some embodiments, the device isolation pattern 310' is arranged in a deformed grid shape within the semiconductor substrate, and multiple photodiode regions can be divided and electrically isolated according to the deformed grid shape. The device isolation pattern 310' may be disposed on a portion of the boundary between the first photodiode region PR1 to the fourth photodiode region PR4, a portion of the boundary between the fifth photodiode region PR5 to the eighth photodiode region PR8, a portion of the boundary between the ninth photodiode region PR9 to the twelfth photodiode region PR12, and a portion of the boundary between the thirteenth photodiode region PR13 to the sixteenth photodiode region PR16. The device isolation pattern 310' may be planar (on a plane) and not overlap with the first -a contact region PLI1a and the first -b contact region PLI1b of the first polysilicon local interconnect PLI1 and the second -a contact region PLI2a and the second -b contact region PLI2b of the second polysilicon local interconnect PLI2.

[0272] Figure 28 This is a plan view showing an example of a group of pixels. Figure 28 Each of the first pixel group PG1d and the device isolation pattern 310'' can correspond to Figure 3 Each of the first pixel group PG1a and the device isolation pattern 310. For ease of explanation below, the focus will be on the relationship with Figure 3 The difference between the first pixel group PG1a and the device isolation pattern 310 is used to describe the first pixel group PG1d and the device isolation pattern 310''.

[0273] Reference Figure 28 The first photodiode region PR1 to the sixteenth photodiode region PR16 in the first pixel group PG1d can be electrically separated by the device isolation pattern 310''.

[0274] In some embodiments, the device isolation pattern 310'' is arranged in a deformed grid shape within the semiconductor substrate, and multiple photodiode regions can be divided and electrically isolated according to the deformed grid shape. The device isolation pattern 310'' may be located at a portion of the boundary between photodiode regions of the same sub-pixel group sharing one of the b-th microlenses MLB.

[0275] Reference Figure 28 As an example, device isolation pattern 310'' may be disposed on a portion of the boundary between the fourth photodiode region PR4 and the sixth photodiode region PR6 below the b-th microlens MLB in sub-pixel group 1_1 PGs11. Similarly, device isolation pattern 310'' may be disposed on a portion of the boundary between the eleventh photodiode region PR11 and the thirteenth photodiode region PR13 below the b-th microlens MLB in sub-pixel group 1_2 PGs12 PGs12.

[0276] Figure 29 This is a plan view showing an example of a group of pixels. Figure 29 The first pixel group PG1e, the a-th microlens MLA, and the b-th microlens MLb' can respectively correspond to Figure 3 The first pixel group PG1a, the a-th microlens MLA, and the b-th microlens MLB. For ease of explanation below, the focus will be on the relationship with... Figure 3 The differences between the first pixel group PG1a, the a-th microlens MLA and the b-th microlens MLb are used to describe the first pixel group PG1e, the a-th microlens MLA and the b-th microlens MLb'.

[0277] The a-th microlens MLA corresponds to a photodiode and is capable of being superimposed with at least a portion of the corresponding photodiode relative to the third-direction D3 plane (on the plane) and focusing incident light onto the corresponding photodiode. An image sensor can generate [image data] using the photodiode corresponding to the a-th microlens MLA. Figure 1 The image data is IDT. The photodiode corresponding to the a-th microlens MLA can be used for image generation. The b-th microlens MLb' corresponds to a photodiode arranged in a 1×2 array, and at least a portion of the lens is planarly (on a plane) superimposed on the corresponding photodiode, allowing incident light to be focused onto the corresponding photodiode. Photodiodes arranged in a 1×2 array within the first pixel group PG1e can share the b-th microlens MLb', and the image sensor can generate image data using multiple photodiodes sharing the b-th microlens MLb'. Figure 1 Image data ITA and phase data PDTA. Multiple photodiodes sharing the b-th microlens MLb' can be used for image generation and phase detection purposes.

[0278] The a-th microlens MLA can be positioned on the first photodiode region PR1, the second photodiode region PR2, the third photodiode region PR3, the fifth photodiode region PR5, the seventh photodiode region PR7, and the eighth photodiode region PR8 within the 1_1 sub-pixel group PGs11. Each of the first photodiode region PR1, the second photodiode region PR2, the third photodiode region PR3, the fifth photodiode region PR5, the seventh photodiode region PR7, and the eighth photodiode region PR8 can correspond to one of the a-th microlenses MLA.

[0279] The a-th microlens MLA can be arranged on the ninth photodiode region PR9, the tenth photodiode region PR10, the twelfth photodiode region PR12, the fourteenth photodiode region PR14, the fifteenth photodiode region PR15, and the sixteenth photodiode region PR16 within the 1-2 sub-pixel group PGs12. Each of the ninth photodiode region PR9, the tenth photodiode region PR10, the twelfth photodiode region PR12, the fourteenth photodiode region PR14, the fifteenth photodiode region PR15, and the sixteenth photodiode region PR16 can correspond to one of the a-th microlenses MLA.

[0280] Figure 1 The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the a-th microlens MLa, and generate... Figure 1 Image data IDTA.

[0281] The b-th microlens MLb' can be arranged across sub-pixel group PGs11 (1_1) and sub-pixel group PGs12 (1_2). See reference... Figure 29 As an example, one of the b-th microlenses MLb' can be arranged on the fourth photodiode region PR4 and the eleventh photodiode region PR11. Furthermore, one of the b-th microlenses MLb' can be arranged on the sixth photodiode region PR6 and the thirteenth photodiode region PR13. The fourth photodiode region PR4 and the eleventh photodiode region PR11 can share one of the b-th microlenses MLb', and the sixth photodiode region PR6 and the thirteenth photodiode region PR13 can share one of the b-th microlenses MLb'.

[0282] Figure 1 The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the b-th microlens MLb', and generate Figure 1 The image data ITA or phase data PDTA is obtained. The readout circuit 130 receives pixel signals corresponding to the photodiodes in the fourth photodiode region PR4 and the sixth photodiode region PR6 (located on the left) of the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 to extract first phase information, and receives pixel signals corresponding to the photodiodes in the eleventh photodiode region PR11 and the thirteenth photodiode region PR13 (located on the right) to extract second phase information. The readout circuit 130 generates phase data PDTA by comparing the first phase information with the second phase information. The readout circuit 130 can substantially simultaneously receive pixel signals from the photodiodes in the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 through the separation structure of the first floating diffusion node FD1 and the second floating diffusion node FD2.

[0283] also, Figure 1 The readout circuit 130 can generate image data IDTA based on the pixel signals of the photodiodes in the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13.

[0284] Figure 30 This is a plan view showing an example of a group of pixels. Figure 30 The first pixel group PG1f, the a-th microlens MLA, and the b-th microlens MLB can respectively correspond to Figure 18 The first pixel group PG1b, the a-th microlens MLA, and the b-th microlens MLB. For ease of explanation below, the focus will be on the relationship with... Figure 18The differences between the first pixel group PG1b, the a-th microlens MLA, and the b-th microlens MLb are used to describe the first pixel group PG1f, the a-th microlens MLA, and the b-th microlens MLb.

[0285] The a-th microlens MLA can be positioned on the first photodiode region PR1, the second photodiode region PR2, and the third photodiode region PR3 of sub-pixel group PGs11'. Each of the first photodiode region PR1, the second photodiode region PR2, and the third photodiode region PR3 can correspond to one of the a-th microlenses MLA. The a-th microlens MLA can be positioned on the ninth photodiode region PR9, the tenth photodiode region PR10, and the twelfth photodiode region PR12 of sub-pixel group PGs12'. Each of the ninth photodiode region PR9, the tenth photodiode region PR10, and the twelfth photodiode region PR12 can correspond to one of the a-th microlenses MLA. The a-th microlens MLA can be positioned on the fifth photodiode region PR5, the seventh photodiode region PR7, and the eighth photodiode region PR8 of sub-pixel group PGs13'. Each of the fifth photodiode region PR5, the seventh photodiode region PR7, and the eighth photodiode region PR8 can correspond to one of the a-th microlenses MLA. The a-th microlens MLA can be positioned on the fourteenth photodiode region PR14, the fifteenth photodiode region PR15, and the sixteenth photodiode region PR16 within the 1-4 sub-pixel group PGs14'. Each of the fourteenth photodiode region PR14, the fifteenth photodiode region PR15, and the sixteenth photodiode region PR16 can correspond to one of the a-th microlenses MLA.

[0286] Figure 1 The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the a-th microlens MLa, and generate... Figure 1 Image data IDTA.

[0287] The b-th microlens MLb can be arranged across sub-pixel groups PGs11' to PGs14' (sub-pixel groups 1-1 and 1-4), and can be arranged on the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13. The fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 can share the b-th microlens MLb.

[0288] Figure 1The readout circuit 130 can receive the pixel signal of the photodiode corresponding to the b-th microlens MLb and generate image data IDTA or phase data PDTA. Figure 1 The readout circuit 130 can receive pixel signals corresponding to the photodiodes in the fourth photodiode region PR4 and the sixth photodiode region PR6 located on the left, among the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13, to extract first phase information, and can also receive pixel signals corresponding to the photodiodes in the eleventh photodiode region PR11 and the thirteenth photodiode region PR13 located on the right to extract second phase information.

[0289] Figure 1 The readout circuit 130 can generate phase data PDTA by comparing the first phase information with the second phase information. The readout circuit 130 can receive the pixel signals of the photodiodes in the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13 substantially simultaneously through the separation structure of the first floating diffusion node FD1 to the fourth floating diffusion node FD4.

[0290] Furthermore, the readout circuit 130 can generate image data IDTA based on the pixel signals of the photodiodes in the fourth photodiode region PR4, the sixth photodiode region PR6, the eleventh photodiode region PR11, and the thirteenth photodiode region PR13.

[0291] Figure 31 This is a flowchart illustrating an example of a method for operating an image sensor.

[0292] Reference Figure 31 During the reset period, the image sensor resets the pixels of the pixel group corresponding to the same color filter (S100).

[0293] In some embodiments, a pixel group having the same color filter may include multiple sub-pixel groups arranged adjacent to each other, and a sub-pixel group may include multiple photodiodes sharing a floating diffusion node. Floating diffusion nodes for different sub-pixel groups may be electrically isolated from each other. In some embodiments, a pixel group may include multiple photodiodes arranged in a 4×4 array, and a sub-pixel group may include multiple photodiodes arranged in a 2×4 array or a 2×2 array.

[0294] In some implementations, a shared lens shared across multiple photodiodes can be arranged across different sub-pixel groups within a single pixel group. With this arrangement of shared lenses, the sharing relationships between microlenses and multiple photodiodes within a pixel group and between floating diffusion nodes and multiple photodiodes can be inconsistent. In some implementations, the shared lens can be arranged on multiple photodiodes in a 2×2 array, and the multiple photodiodes receiving incident light through the shared lens can be used for image generation and phase detection purposes.

[0295] The pixel group of the pixel array receives a reset signal and a conversion gain enable signal, and the charge present in the photodiodes in the pixel group of the pixel array, as well as in the floating diffusion node and MIM capacitor electrically connected to the photodiodes, can be drained to the power line and reset.

[0296] During the integration period following the reset period, the photodiode of the image sensor can be exposed to light and undergo photoelectric conversion to generate photocharge.

[0297] The readout circuit receives multiple first reset level signals corresponding to a shared lens from the first and second floating diffusion nodes that are separate from each other (S200).

[0298] The readout circuit can receive multiple first reset level signals corresponding to a shared lens from the floating diffusion node for individual sub-pixel groups.

[0299] Reference Figure 3 and Figure 7 Taking the first pixel group PG1a as an example, during the readout period, the readout circuit can receive multiple first reset level signals from the first floating diffusion node FD1 and the second floating diffusion node FD2 for the 1_1 sub-pixel group PGs11 and the 1_2 sub-pixel group PGs12 sharing the b-th microlens MLb. In some embodiments, the multiple first reset level signals are pixel signals in high conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0300] Reference Figure 18 and Figure 19 Taking the first pixel group PG1b as an example, during the readout period, the readout circuit can receive multiple first reset level signals from the first floating diffusion node FD1 and the second floating diffusion node FD2 for the 1_1 sub-pixel group PGs11' and the 1_2 sub-pixel group PGs12' that share the b-th microlens MLb. In some embodiments, the multiple first reset level signals are pixel signals in high conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0301] During the readout period following the integration period, a multi-exposure operation can be performed, in which multiple exposures are applied to the photodiodes within the pixel group.

[0302] The readout circuit receives multiple first pixel signals corresponding to a shared lens from the first and second floating diffusion nodes that are separate from each other (S300).

[0303] The readout circuit can receive multiple first pixel signals from individual floating diffusion nodes for different sub-pixel groups corresponding to a shared lens.

[0304] Reference Figure 3 and Figure 7 Taking the first pixel group PG1a as an example, during the readout period, the readout circuit can receive multiple first pixel signals from different first floating diffusion nodes FD1 and FD2, including the fourth photodiode PD4 and the sixth photodiode PD6 of the 1_1 sub-pixel group PGs11 (sharing the b-th microlens MLB) and the eleventh photodiode PD11 and the thirteenth photodiode PD13 of the 1_2 sub-pixel group PGs12. In some embodiments, the multiple first pixel signals are pixel signals in a high conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0305] Reference Figure 18 and Figure 19 Taking the first pixel group PG1b as an example, during the readout period, the readout circuit can receive multiple first pixel signals from different first floating diffusion nodes FD1 and FD2, including the second photodiode PD2 and fourth photodiode PD4 of the 1_1 sub-pixel group PGs11' sharing the b-th microlens MLb, and the ninth photodiode PD9 and eleventh photodiode PD11 of the 1_2 sub-pixel group PGs12'. In some embodiments, the multiple first pixel signals are pixel signals in a high conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0306] Pixel group variation conversion gain mode (S400).

[0307] The pixel groups in the pixel array can receive pixel drive signals for controlling the operation of the switching gain transistor and the reset transistor, and the electrical connection between the floating diffusion node and the MIM capacitor can be controlled.

[0308] Reference Figure 3 and Figure 7Taking the first pixel group PG1a as an example, the first medium conversion gain transistor MCX1 and the second medium conversion gain transistor MCX2 are turned on, and the first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 are turned off, such that the first floating diffusion node FD1 can be electrically connected to one electrode of the first MIM capacitor MIM1, and the second floating diffusion node FD2 can be electrically connected to one electrode of the third MIM capacitor MIM3. In some embodiments, the conversion gain mode of the first pixel group PG1a can be changed from a high conversion gain mode to a medium conversion gain mode. Furthermore, the first medium conversion gain transistor MCX1 and the second medium conversion gain transistor MCX2 are turned on, the first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 are turned on, and the first reset transistor RX1 and the second reset transistor RX2 are turned off, such that the first floating diffusion node FD1 can be electrically connected to one electrode of each of the first MIM capacitor MIM1 and the second MIM capacitor MIM2, and the second floating diffusion node FD2 can be electrically connected to one electrode of each of the third MIM capacitor MIM3 and the fourth MIM capacitor MIM4. In some implementations, the conversion gain mode of the first pixel group PG1a can be changed from a conversion gain mode to a low conversion gain mode.

[0309] Reference Figure 18 and Figure 19 Taking the first pixel group PG1b as an example, the first low conversion gain transistor LCX1 and the second low conversion gain transistor LCX2 are turned on, and the first reset transistor RX1 and the second reset transistor RX2 are turned off, so that the first floating diffusion node FD1 can be electrically connected to one electrode of the first MIM capacitor MIM1, and the second floating diffusion node FD2 can be electrically connected to one electrode of the third MIM capacitor MIM3. In some embodiments, the conversion gain mode of the first pixel group PG1b can be changed from a high conversion gain mode to a low conversion gain mode.

[0310] The readout circuit receives multiple second pixel signals corresponding to a shared lens from the first and second floating diffusion nodes that are separate from each other (S500).

[0311] The readout circuit can receive multiple second pixel signals from a single floating diffusion node, corresponding to different sub-pixel groups of a single shared lens.

[0312] Reference Figure 3 and Figure 7Taking the first pixel group PG1a as an example, during the readout period, the readout circuit can receive multiple second pixel signals from different first floating diffusion nodes FD1 and second floating diffusion nodes FD2, including the fourth photodiode PD4 and the sixth photodiode PD6 of the 1_1 sub-pixel group PGs11 (sharing the b-th microlens MLB) and the eleventh photodiode PD11 and the thirteenth photodiode PD13 of the 1_2 sub-pixel group PGs12. In some embodiments, the multiple second pixel signals are pixel signals in medium conversion gain mode or low conversion gain mode, and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0313] Reference Figure 18 and Figure 19 Taking the first pixel group PG1b as an example, during the readout period, the readout circuit can receive multiple second pixel signals from different first floating diffusion nodes FD1 and second floating diffusion nodes FD2, namely the second photodiode PD2 and fourth photodiode PD4 of the 1_1 sub-pixel group PGs11' sharing the b-th microlens MLB, and the ninth photodiode PD9 and eleventh photodiode PD11 of the 1_2 sub-pixel group PGs12'. In some embodiments, the multiple second pixel signals are pixel signals in low conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0314] The readout circuit receives multiple second reset level signals (S600) corresponding to a shared lens from the first and second floating diffusion nodes that are separate from each other.

[0315] The readout circuit can receive multiple second reset level signals corresponding to a shared lens from the floating diffusion node used for individual sub-pixel groups.

[0316] Reference Figure 3 and Figure 7 Taking the first pixel group PG1a as an example, during the readout period, the readout circuit can receive multiple second reset level signals from the first floating diffusion node FD1 and the second floating diffusion node FD2 for the 1_1 sub-pixel group PGs11 and the 1_2 sub-pixel group PGs12 sharing the b-th microlens MLb. In some embodiments, the multiple second reset level signals are pixel signals in low conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0317] Reference Figure 18 and Figure 19Taking the first pixel group PG1b as an example, during the readout period, the readout circuit can receive multiple second reset level signals from the first floating diffusion node FD1 and the second floating diffusion node FD2 for the 1_1 sub-pixel group PGs11' and the 1_2 sub-pixel group PGs12' that share the b-th microlens MLb. In some embodiments, the multiple second reset level signals are pixel signals in low conversion gain mode and may include the left pixel signal of the first floating diffusion node FD1 and the right pixel signal of the second floating diffusion node FD2.

[0318] The readout circuit generates phase data from multiple first pixel signals, multiple second pixel signals, multiple first reset level signals, and multiple second reset level signals (S700).

[0319] The readout circuit can generate phase data by performing a comparison operation on multiple first pixel signals, multiple second pixel signals, multiple first reset level signals, and multiple second reset level signals.

[0320] Since each of the multiple first pixel signals, multiple second pixel signals, multiple first reset level signals, and multiple second reset level signals includes a left pixel signal and a right pixel signal, the readout circuit can easily generate phase data by receiving the left pixel signal and the right pixel signal together without receiving the pixel signal in RSS mode.

[0321] The image sensor employs a structure where the sharing relationships of microlenses and floating diffusion nodes are inconsistent within a pixel array structure sharing floating diffusion nodes. This allows the left and right pixel signals corresponding to a shared lens to be generated simultaneously from separate floating diffusion nodes. Through this shared structure, the image sensor can easily perform autofocus (AF) operations in bright environments while improving resolution. Furthermore, through the shared structure described above, the image sensor can easily perform AF operations in multiple conversion gain modes while improving resolution, thus enabling easy AF operation even over a wide dynamic range.

[0322] Figure 32 This is a block diagram illustrating an example of a computer device.

[0323] Reference Figure 32 The computing device 1000 may include a camera 1010, a controller 1020, a memory 1030, and a display 1040.

[0324] Camera 1010 may include image sensor 1011. Image sensor 1011 may be implemented as described above. Figures 1 to 31 The image sensor described herein. Camera 1010 can use image sensor 1011 to generate image signals, perform image signal processing on the image signals, and output the processed image signals to controller 1020.

[0325] Image sensor 1011 employs a structure where the sharing relationships between multiple photodiodes and microlenses, and between multiple photodiodes and floating diffusion nodes, are inconsistent in a pixel array structure sharing floating diffusion nodes. This allows the left and right pixel signals corresponding to a shared lens to be generated simultaneously from separate floating diffusion nodes. Through this shared structure, the image sensor can easily perform autofocus (AF) operations in high-light environments while improving resolution. Furthermore, through the shared structure described above, the image sensor can easily perform AF operations in multiple conversion gain modes while improving resolution, thus easily performing AF operations even over a wide dynamic range.

[0326] The controller 1020 may include a processor 1021. The processor 1021 can control the overall operation of each component of the computing device 1000. The processor 1021 may be implemented as at least one of various processors, such as a CPU (Central Processing Unit), an AP (Application Processor), and a GPU (Graphics Processing Unit). In some embodiments, the controller 1020 may be implemented as an integrated circuit or a system-on-a-chip (SoC).

[0327] The controller 1020 may further include an interface 1022, a memory controller 1023, a display controller 1024, and a bus 1025. In some embodiments, at least some of the interface 1022, memory controller 1023, display controller 1024, and bus 1025 may be located external to the controller 1020. In some embodiments, the controller 1020 may further include an image signal processor. The controller 1020 may correspond to... Figure 1 Image signal processor 160.

[0328] Interface 1022 can send the image signal received from image sensor 1011 to memory controller 1023 or display controller 1024 via bus 1025.

[0329] The memory 1030 can store various data and commands. The memory controller 1023 can control the transfer of data or commands to and from the memory 1030.

[0330] Under the control of the processor 1021, the display controller 1024 sends data to be displayed on the display 1040, and the display 1040 displays the received data. In some embodiments, the display 1040 may also include a touchscreen. The touchscreen can send user input to the controller 1020, which controls the operation of the computing device 1000. User input can be generated when the user touches the touchscreen.

[0331] Bus 1025 provides communication capabilities between components of controller 1020. Bus 1025 may include at least one type of bus depending on the communication protocol between components.

[0332] Figure 33 This is a block diagram showing an example of a vehicle.

[0333] Reference Figure 33 The vehicle 2000 may include an image sensor 2101, a user interface 2102, a LIDAR (light detection and ranging) sensor 2103, a RADAR (radio detection and ranging) sensor 2104, an NPU (neural processor) 2105, a CPU 2106, and an ECU (electronic control unit) 2107.

[0334] The ECU 2107 can receive the vehicle's steering angle and speed from the steering wheel 2108 and the engine 2109. Although not shown, the vehicle 2000 may also include a communication module, an input / output module, a safety module, a power control device, etc., and may further include various types of control devices.

[0335] Vehicle 2000 can detect objects using information about the external environment acquired by sensors (e.g., image sensor 2101, LIDAR sensor 2103, and / or RADAR sensor 2104). Sensors 2101, 2103, and 2104 can capture images of objects, measure distances to objects, and send images to processors (e.g., CPU 2106, NPU 2105, and ECU 2107). In addition to the sensors mentioned above, sensors 2101, 2103, and 2104 may also include time-of-flight (ToF) sensors, ultrasonic sensors, infrared sensors, magnetic sensors, position sensors (e.g., Global Positioning System (GPS)), accelerometers, atmospheric pressure sensors, temperature / humidity sensors, proximity sensors, and gyroscope sensors to detect objects.

[0336] Image sensor 2101 can be implemented as described above. Figures 1 to 31 The image sensor described herein. Image sensor 2101 can provide image or light sensing, and can be, for example, a complementary metal-oxide-semiconductor (CMOS) image sensor. Image sensor 2101 can acquire image or visual information about an object. For example, image sensor 2101 can be attached to the front of a vehicle to capture a driving image or measure the distance to an object located in front of the vehicle. The location where image sensor 2101 is attached is not limited to this, and image sensor 2101 can be attached to various locations to achieve the intended purpose of obtaining information about the object.

[0337] Image sensor 2101 can capture images of the environment surrounding vehicle 2000. Vehicle 2000 may include at least two image sensors to capture 360-degree images of the environment around the vehicle. In some embodiments, image sensor 2101 may be equipped with a wide-angle lens. In embodiments, four image sensors may be included in vehicle 2000 for the front, rear, left, and right sides of the vehicle, but are not limited thereto, and a single image sensor 2101 may also be used to capture the environment around the vehicle. Image sensor 2101 can continuously provide information about the environment around the vehicle to vehicle 2000 by continuously capturing images of the environment around the vehicle.

[0338] Images sensed by image sensor 2101 can be processed by CPU 2106 and / or NPU 2105. CPU 2106 can detect objects by processing the sensed images in a motion-based manner, and NPU 2105 can detect objects by processing the sensed images in a shape-based manner. Image sensor 2101 can be attached to the front of the vehicle to sense the external environment at the front of the vehicle, but is not limited thereto, and can be attached to various surfaces of the vehicle to sense the external environment.

[0339] Image sensor 2101 employs a structure where the sharing relationship between multiple photodiodes and microlenses, and the sharing relationship between multiple photodiodes and floating diffusion nodes, are inconsistent in a pixel array structure sharing floating diffusion nodes. This allows the left and right pixel signals corresponding to a shared lens to be generated simultaneously from separate floating diffusion nodes. Through this shared structure, the image sensor can easily perform autofocus (AF) operations in high-light environments while improving resolution. Furthermore, through the shared structure described above, the image sensor can easily perform AF operations in multiple conversion gain modes while improving resolution, thereby easily performing AF operations even over a wide dynamic range.

[0340] User interface 2102 may include various electronic and mechanical devices (such as the vehicle's dashboard, display showing driving information, navigation system and air conditioning system) contained in the driver's seat or passenger seat.

[0341] LIDAR sensor 2103 measures distance to an object by emitting laser pulses and receiving laser light reflected from the object. LIDAR sensor 2103 typically includes a laser, a scanner, a receiver, and a positioning system. The laser typically uses light with wavelengths from 600 to 1000 nanometers (nm), but this can vary depending on the application. The scanner quickly obtains information about the surrounding environment by scanning it, and various types of scanners using multiple mirrors are possible. The receiver receives laser pulses reflected from the target object and detects and amplifies photons from the laser pulses. The positioning system determines the position coordinates and orientation of the device equipped with the receiver to achieve a three-dimensional image. LIDAR sensor 2103 and RADAR sensor 2104 can be distinguished based on their effective measurement distance.

[0342] RADAR sensor 2104 measures the distance to an object, identifies the object, and measures the object's position and speed of movement by emitting electromagnetic waves and receiving electromagnetic waves reflected from the target object. RADAR sensor 2104 may include a transmitter and a receiver. The transmitter generates and outputs electromagnetic waves, and the receiver receives and processes the echo reflected from the target object. RADAR sensor 2104 may transmit and receive via a single antenna, but is not limited to this. The frequency band of the electromagnetic waves used in RADAR sensor 2104 is either the radio wave band or the microwave band, but may be changed depending on the purpose. In embodiments, LIDAR sensor 2103 and RADAR sensor 2104 may be attached to a vehicle to help determine the relative positional relationship between the vehicle and the object of interest. RADAR sensor 2104 may be classified as a long radar sensor and a short radar sensor.

[0343] The NPU 2105 receives input data, performs calculations using an artificial neural network, and provides output data based on the calculation results. The NPU 2105 is a processor optimized for simultaneous matrix operations, capable of processing multiple operations in real time, and can learn from accumulated data to derive optimal values. The NPU 2105 is optimized for simultaneous matrix operations and can process multiple operations in real time. The NPU 2105 can learn from accumulated data and derive local maxima in the current driving parameters.

[0344] In some implementations, the NPU 2105 may be a processor dedicated to executing deep learning algorithms. For example, the NPU 2105 may be a processor dedicated to executing deep learning algorithms. For example, the NPU 2105 may be capable of handling operations based on various networks, such as CNN (Convolutional Neural Network), R-CNN (Region Convolutional Neural Network), RPN (Region Proposal Network), RNN (Recurrent Neural Network), fully convolutional networks, LSTM (Long Short-Term Memory) networks, and classification networks. However, the NPU 2105 is not limited to this, and it is feasible to simulate various types of computational processing of human neural networks.

[0345] NPU 2105 can receive driving images from image sensor 2101 and perform shape-based object detection based on the driving images. NPU 2105 can distinguish each of multiple objects in a driving video by extracting features of multiple objects based on accumulated data and learning on its own. For example, NPU 2105 can extract objects (such as vehicles, pedestrians, traffic lights, and lanes) from a single driving video as criteria for driving decisions based on features determined by using accumulated data as learning material.

[0346] CPU 2106 controls the overall operation of vehicle 2000. CPU 2106 may include one processor core (single-core) or multiple processor cores (multi-core). CPU 2106 can process or execute programs and / or data stored in memory. For example, CPU 2106 can control the functions of NPU 2105 and ECU 2107 by executing programs stored in memory.

[0347] The CPU 2106 can obtain the steering angle and vehicle speed from the ECU 2107. The steering angle is determined by the driver's operation of the steering wheel 2108 and can be processed by the ECU 2107, which controls the operation of the steering control device, and provided to the CPU 2106. The vehicle speed can be measured based on at least one of the driver's pedal input (e.g., accelerator operation), the engine speed 2109, and the wheel speed measured by wheel sensors, and can be processed by the ECU 2107, which controls the vehicle speed, and provided to the CPU 2106.

[0348] Furthermore, the CPU 2106 can determine the relative positional relationship between the vehicle and surrounding vehicles, and based on the determined driving plan, issue commands to maintain the engine speed 2109 for constant speed driving to maintain a certain distance from surrounding vehicles. It can also issue commands to change the steering angle by adjusting the steering wheel 2108 left or right when the vehicle and surrounding vehicles are at a distance below a critical distance or when the vehicle is being approached by surrounding vehicles, in order to perform evasive maneuvers. Figure 33In this context, the steering wheel 2108 and engine 2109 are disclosed as configurations related to steering angle and vehicle speed, but are not limited thereto, and the steering angle and vehicle speed can be determined by various vehicle components.

[0349] CPU 2106 can perform motion-based object detection in driving video. The motion-based method detects the degree of movement of an object over time and determines its relative movement. Driving images can be continuously acquired for each frame via image sensor 2101. For example, each frame can be captured at a rate of 60 frames per second (fps), allowing CPU 2106 to detect movement over time between image frames acquired every 1 / 60th of a second. The motion-based method may include optical flow representing the distribution of motion vectors of the object.

[0350] In addition to the image sensor 2101, the CPU 2106 can also supplementarily utilize the distances to objects obtained from the LIDAR sensor 2103 and the RADAR sensor 2104 to stably maintain the vehicle's driving state. Furthermore, the CPU 2106 can issue commands to control the vehicle's internal and external states based on the driver's operations on the user interface 2102.

[0351] ECU 2107 can be an electronic control unit designed to control the overall or partial operation of a vehicle. ECU 2107 can control vehicle operation via a Controller Area Network (CAN) multiplexed bus based on the operation of the internal combustion engine, the operation of one or more electric motors, and vehicle parameters controlled by the driver (such as the operation of a semi-automatic transmission (SAGB) or an automatic transmission (AGB).

[0352] The ECU 2107 can electronically control the vehicle's engine, steering control actuator, transmission control system, anti-lock braking system, airbag control system, etc., and can provide the vehicle speed to the vehicle 2000 based on the engine speed or the wheel speed measured by the wheel sensors, and can provide the vehicle's steering angle to the vehicle 2000 from the steering control device.

[0353] In some implementations, ECU 2107 can control the state of steering wheel 2108 and engine 2109 based on commands issued from CPU 2106 and NPU 2105. In some implementations, ECU 2107 can accelerate or decelerate the vehicle in response to commands issued from CPU 2106 and NPU 2105, and can provide signals to engine 2109 to increase / decrease engine speed in response to acceleration / deceleration. Furthermore, ECU 2107 can perform evasive maneuvers by changing the steering wheel 2108 left or right when the distance to surrounding vehicles is below a threshold distance or when a surrounding vehicle cuts in (the cutting-in target), depending on the set driving plan.

[0354] In some implementations, CPU 2106 or ECU 2107 can identify a fault in the Light Module (RMP) and exit the autonomous driving mode of vehicle 2000. For example, CPU 2106 or ECU 2107 can detect a defect in the Light Module (RMP) while driving in autonomous driving mode based on image sensor 2101, and immediately change the autonomous driving mode to manual driving mode via the driver, thereby ensuring user safety. For example, vehicle 2000 can detect a fault in the Light Module (RMP) and discontinue driving assistance functions based on the Light Module (RMP), thereby ensuring the safety of the driver or user.

[0355] Although the ECU 2107 is depicted in the diagram as being installed separately from the CPU 2106 in the vehicle, this is not the case, and the vehicle control functions of the ECU 2107 can be executed simultaneously while being included within the CPU 2106. In this context, the CPU 2106 can be understood as having at least two processor cores (multi-core). Figure 33 In this context, ECU 2107 is described as a component separate from CPU 2106, but is not limited to this, and may exist within CPU 2106.

[0356] Although not in Figure 33 As shown, however, vehicle 2000 may also include a communication module. The communication module can send data to or receive data from the outside of vehicle 2000. For example, the communication module can communicate with external objects of vehicle 2000. In this case, the communication module can perform communication in V2X (Vehicle to Everything) mode. For example, the communication module can perform communication in V2V (Vehicle to Vehicle), V2I (Vehicle to Infrastructure), V2P (Vehicle to Pedestrian), and V2N (Vehicle to Nomadic Devices) modes. However, it is not limited to this, and the communication module can send and receive data through various known communication methods. For example, the communication module can perform communication through, for example, 3G, 4G (Long Term Evolution (LTE)), 5G, Wi-Fi, Bluetooth, BLE (Bluetooth Low Energy), Zigbee, NFC (Near Field Communication), ultrasonic communication, etc., and may include both short-range and long-range communication.

[0357] While this specification contains numerous details of specific embodiments, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather as descriptions of features specific to particular embodiments of the invention. Specific features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may involve sub-combinations or variations thereof.

[0358] Although embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of the present disclosure as defined in the appended claims also fall within the scope of the present disclosure.

Claims

1. An image sensor, comprising: The first sub-pixel group includes a first plurality of photodiodes, the first plurality of photodiodes being arranged in a first plurality of rows and a first plurality of columns, and the first plurality of photodiodes sharing a first floating diffusion node; The second sub-pixel group is adjacent to the first sub-pixel group. The second sub-pixel group includes a second plurality of photodiodes. The second plurality of photodiodes are arranged in a second plurality of rows and a second plurality of columns, and the second plurality of photodiodes share a second floating diffusion node that is separate from the first floating diffusion node. A color filter, wherein at least a portion of the color filter is disposed on a first sub-pixel group and a second sub-pixel group; and A first lens, wherein at least a first portion of the first lens is superimposed on a first sub-pixel group and a second sub-pixel group in a planar view.

2. The image sensor according to claim 1, further comprising: A first metal-insulating capacitor, wherein at least a portion of the first metal-insulating capacitor is superimposed on a first sub-pixel group in a planar view; and A second metal-insulating capacitor, wherein at least a portion of the second metal-insulating capacitor is superimposed on a second sub-pixel group in a planar view.

3. The image sensor according to claim 2, further comprising: The first conversion gain transistor is electrically connected between the first floating diffusion node and the first electrode of the first metal insulator metal capacitor. as well as A reset transistor is electrically connected between the first electrode of a first metal-insulator metal capacitor and a power line configured to provide a power supply voltage.

4. The image sensor according to claim 2, further comprising: A third metal-insulating capacitor, wherein at least a portion of the third metal-insulating capacitor is superimposed on the first sub-pixel group in the planar view, and is separated from the first metal-insulating capacitor in the planar view; and A fourth metal-insulating capacitor, wherein at least a portion of the fourth metal-insulating capacitor is superimposed on the second sub-pixel group in the planar view and is separated from the second metal-insulating capacitor in the planar view.

5. The image sensor according to claim 4, wherein: The first metal-insulator metal capacitor includes a first metal film and a second metal film stacked on top of each other in a plan view. The third metal insulator capacitor includes a third metal film and a fourth metal film stacked on top of each other in a plan view. The areas of the first metal film and the third metal film are different from each other, and The first metal-insulating capacitor and the third metal-insulating capacitor have different charge storage capacities.

6. The image sensor according to claim 1, wherein: The first plurality of photodiodes are arranged in a 4×2 array in the first to eighth photodiode regions, and The second plurality of photodiodes are arranged in a 4×2 array in the ninth to sixteenth photodiode regions.

7. The image sensor according to claim 6, further comprising: A plurality of second lenses, wherein each of the plurality of second lenses is arranged in a corresponding photodiode region within the first to sixth photodiode regions and the ninth to fourteenth photodiode regions. The seventh, eighth, fifteenth, and sixteenth photodiode regions are arranged in a 2×2 array, and In this configuration, at least a portion of the first lens is superimposed on the seventh photodiode region, the eighth photodiode region, the fifteenth photodiode region, and the sixteenth photodiode region in the planar view.

8. The image sensor according to claim 6, further comprising: A plurality of second lenses, wherein each of the plurality of second lenses is arranged in a corresponding photodiode region within the first to sixth photodiode regions and the ninth to fourteenth photodiode regions. The seventh photodiode region and the fifteenth photodiode region are arranged in a 1×2 array, and In this configuration, at least a portion of the first lens is superimposed on the seventh photodiode region and the fifteenth photodiode region in the planar view.

9. The image sensor according to claim 1, further comprising: The third sub-pixel group includes a third plurality of photodiodes, the third plurality of photodiodes being arranged in a third plurality of rows and a third plurality of columns, and the third plurality of photodiodes sharing a third floating diffusion node that is separate from the first floating diffusion node and the second floating diffusion node; as well as The fourth sub-pixel group includes a fourth plurality of photodiodes, which are arranged in a fourth plurality of rows and a fourth plurality of columns, and which share a fourth floating diffusion node that is separate from the first to the third floating diffusion nodes. The first to fourth sub-pixel groups are arranged in a 2×2 array, and The color filter is set on the first to fourth sub-pixel groups.

10. The image sensor according to claim 9, further comprising: A third lens, wherein at least a portion of the third lens is superimposed on a third sub-pixel group and a fourth sub-pixel group in a planar view.

11. The image sensor according to claim 9, wherein: At least a portion of the first lens is superimposed on the first to fourth sub-pixel groups in the planar view.

12. The image sensor according to any one of claims 1 to 11, wherein: The first plurality of photodiodes and the second plurality of photodiodes are included in the substrate, and The substrate includes a device isolation pattern configured to position the first plurality of photodiodes and the second plurality of photodiodes in a plurality of rows and a plurality of columns.

13. The image sensor according to claim 12, further comprising: The first transmission transistor is configured to provide photocharge generated from the first plurality of photodiodes to the first floating diffusion node; as well as The second transmission transistor is configured to provide photocharge generated from the second plurality of photodiodes to the second floating diffusion node. The substrate includes a first surface and a second surface opposite to the first surface, and the first transmission transistor and the second transmission transistor are on the first surface. At least a portion of the first floating diffusion node includes a conductive pattern that contacts at least a portion of the first surface.

14. The image sensor according to claim 1, wherein: The color filter is either a red filter or a blue filter.

15. An image sensor, comprising: A first photodiode is configured to receive light through a first lens to generate photocharge, and the first photodiode is electrically connected to a first floating diffusion node via a first transmission transistor. The second photodiode is configured to receive light through the second lens to generate photocharge, and the second photodiode is electrically connected to the first floating diffusion node through the second transmission transistor. The first driving transistor is configured to generate a first pixel signal based on the voltage of the first floating diffusion node; The third photodiode is configured to receive light through the first lens to generate photocharge. The third photodiode is electrically connected to the second floating diffusion node through the third transmission transistor. The second floating diffusion node is separated from the first floating diffusion node. The fourth photodiode is configured to receive light through the third lens to generate photocharge, and the fourth photodiode is electrically connected to the second floating diffusion node through the fourth transfer transistor; The second driving transistor is configured to generate a second pixel signal based on the voltage of the second floating diffusion node; A color filter, wherein at least a portion of the color filter is disposed on the first to fourth photodiodes; as well as The readout circuit is configured to receive a first pixel signal via a first column line and a second pixel signal via a second column line, so as to generate image data based on the first pixel signal and the second pixel signal, wherein the second column line is separate from the first column line.

16. The image sensor according to claim 15, further comprising: A first metal-insulating capacitor, wherein at least a portion of the first metal-insulating capacitor is stacked with a first photodiode and a second photodiode in a plan view; A second metal-insulating capacitor, wherein at least a portion of the second metal-insulating capacitor is stacked with a third photodiode and a fourth photodiode in a plan view; A first conversion gain transistor is electrically connected between the first floating diffusion node and the electrodes of a first metal-insulator capacitor; and The second conversion gain transistor is electrically connected between the second floating diffusion node and the electrode of the second metal insulator capacitor.

17. The image sensor according to claim 15, wherein: The first to fourth photodiodes are included in the substrate. The substrate includes a pixel group separation region, which is arranged to separate the first photodiode and the third photodiode. The first and third photodiodes are arranged in a 1×2 array.

18. The image sensor according to claim 17, wherein: The substrate includes a first surface and a second surface opposite to the first surface, and the first to fourth transmission transistors are on the first surface. At least a portion of the first floating diffusion node includes a first conductive pattern that contacts at least a first portion of the first surface. At least a portion of the second floating diffusion node includes a second conductive pattern that contacts at least a second portion of the first surface, and The pixel group separation region is located between the first conductive pattern and the second conductive pattern.

19. A method of operating an image sensor, comprising: The first sub-pixel group and the second sub-pixel group are reset, wherein the first sub-pixel group shares a first floating diffusion node and is configured to output a pixel signal for a first color, wherein the second sub-pixel group shares a second floating diffusion node separate from the first floating diffusion node and is configured to output a pixel signal for a first color, and wherein at least a portion of the first sub-pixel group and at least a portion of the second sub-pixel group are superimposed with a first lens in a planar view. Receives a first reset level signal from the first floating diffusion node and a second reset level signal from the second floating diffusion node; In the first conversion gain mode, a first pixel signal is received from a first floating diffusion node, and a second pixel signal is received from a second floating diffusion node; For the first sub-pixel group and the second sub-pixel group, the first conversion gain mode is changed to the second conversion gain mode; In the second conversion gain mode, a third pixel signal is received from the first floating diffusion node, and a fourth pixel signal is received from the second floating diffusion node; and Phase data is generated based on the third and fourth pixel signals.

20. The method of claim 19, wherein: The first sub-pixel group is superimposed on at least a portion of the first metal insulator metal capacitor in the planar view. The second sub-pixel group is superimposed on at least a portion of the second metal insulator metal capacitor in the planar view. The first metal-insulator capacitor and the second metal-insulator capacitor are not stacked on top of each other in the plan view, and The steps for changing the first conversion gain mode to the second conversion gain mode include: Electrically connect the electrodes of the first metal-insulator capacitor to the first floating diffusion node; and The electrodes of the second metal insulator are electrically connected to the second floating diffusion node.

Images