A method of manufacturing an image sensor and an image sensor

Abstract

This invention discloses a method for fabricating an image sensor, comprising: providing a substrate; forming a gate structure of a transistor on the substrate; forming a mask layer with trenches on the substrate; and performing ion implantation using the gate structure and the mask layer together as barriers to form the source and drain of the transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for fabricating an image sensor. Background Technology

[0002] CMOS image sensors (CIS) are widely used in image acquisition. As pixel size shrinks, the resolution requirements for photolithography increase. Simultaneously, to maintain or improve the full-well capacity, transistor transmission performance, and isolation performance of image sensor pixels, the ion implantation depth of the pixels also needs to be further increased. Therefore, higher requirements are placed on high aspect ratio masks. Currently, in ion implantation processes, the specific mask aspect ratio requirement is greater than 10 or even greater than 20. However, with current photolithography processes, as resolution increases, the focusing depth decreases, making it difficult to simultaneously achieve thick photoresist and high resolution; these requirements have exceeded the limits of traditional photoresists. Therefore, under these high aspect ratio process requirements, multilayer hard mask technology with a relatively large etching selectivity is generally used, such as dielectric materials like silicon oxide or silicon nitride. However, during subsequent mask stripping, the stripping process of thicker mask layers is time-consuming, allowing sufficient time for the stripping etchant to enter the mask trenches, damaging the ion implantation region and the functional layers of the device within the trenches.

[0003] The above and other existing technologies in the field of semiconductor processes demonstrate that it would be beneficial to develop a high aspect ratio ion implantation mask and a technology for removing the high aspect ratio mask without damaging the device functional layers in the mask trench features. Summary of the Invention

[0004] Based on the problems described above, the present invention proposes a method for fabricating an image sensor, comprising: providing a substrate; forming a gate structure of a transistor on the substrate; forming a mask layer with trenches on the substrate; and performing ion implantation using the gate structure and the mask layer together as barriers to form the source and drain of the transistor.

[0005] In some embodiments, the method further includes: backfilling the trench with a protective layer; removing the mask layer and the protective layer, the protective layer being used to protect the substrate surface at the bottom of the trench from damage during the removal of the mask layer.

[0006] In some embodiments, the mask layer further includes: a first mask layer and a second mask layer formed from bottom to top; the removal of the mask layer and the protective layer includes: removing the second mask layer and the top portion of the protective layer, and then removing the first mask layer and the remaining protective layer.

[0007] In some embodiments, removing the second mask layer and the top portion of the protective layer, and then removing the first mask layer and the remaining protective layer, includes: firstly removing the second mask layer and the top portion of the protective layer using fluorine-based gas etching, and then removing the first mask layer and the remaining protective layer using non-fluorine-based gas etching.

[0008] In some embodiments, the material of the first mask layer is a carbon-based material, the material of the second mask layer is an inorganic dielectric, and the material of the protective layer is selected from materials with high fluidity.

[0009] In some embodiments, the material of the first mask layer is selected from BARC, PR, SOC or APF, the material of the second mask layer is selected from LTO, SiARC or DARC, and the protective layer is selected from BARC, PR or SOC.

[0010] In some embodiments, the thickness of the first mask layer is 500-50000 Å, the thickness of the second mask layer is 10-1000 Å, and the thickness of the protective layer is 500-10000 Å.

[0011] In some embodiments, the mask layer further includes: photoresist, and / or an anti-reflective layer, wherein the anti-reflective layer is BARC or TARC.

[0012] In some embodiments, the trenched mask layer is obtained using photolithography and etching processes. In some embodiments, the aspect ratio of the trench is greater than 10.

[0013] In some embodiments, the transistor has more than one gate; two adjacent gates share a source or drain.

[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) On the one hand, by adopting a three-layer structure technology of mask and photoresist layer combined with etching process, and by selecting specific mask materials and thicknesses, a high aspect ratio ion implantation mask is achieved, the critical dimension (CD) of the ion implantation area is reduced, the implantation depth is greatly improved, and the full-well capacity of the image sensor pixels, transistor transmission performance and isolation performance are further improved.

[0015] (2) On the other hand, in the mask stripping process, a protective layer is introduced into the mask pattern trench to protect the substrate functional layer at the bottom of the mask trench from damage.

[0016] (3) In addition, by forming patterned mask trenches and stripping and removing mask layers in a specific sequence, and by using another mask to protect the substrate at the bottom of the trench in a mask layer stripping and removal process, the substrate functional layer at the bottom of the mask trench can be further protected from damage. Attached Figure Description

[0017] The accompanying drawings, which form part of this specification, are used to further understand the invention. The drawings illustrate embodiments of the invention and, together with the specification, serve to explain the principles of the invention.

[0018] Figure 1 This is a functional block diagram of an image sensor as an exemplary embodiment of the present invention.

[0019] Figures 2 to 8 This is a cross-sectional schematic diagram of the image sensor formation process, which is an exemplary embodiment of the present invention.

[0020] Figures 9 to 15 This is a cross-sectional schematic diagram of another image sensor formation process according to an exemplary embodiment of the present invention. Detailed Implementation

[0021] The following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0022] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the present invention.

[0023] Figure 1 This is a functional block diagram of an image sensor 100 as an exemplary embodiment of the present invention.

[0024] The image sensor 100 includes a pixel array 105, a readout circuit 110, a functional logic 115, and a control circuit 120.

[0025] The pixel array 105 includes a two-dimensional (“2D”) array of multiple image sensor pixels 125 (e.g., pixels P1, P2…Pn). As shown, each pixel is arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

[0026] After each pixel has acquired its image data or image charge, the image data is read out by readout circuit 110 and transmitted to functional logic 115. Readout circuit 110 may include amplifier circuitry, analog-to-digital converter (“ADC”), etc. Functional logic 115 may simply store or process the image data. In one embodiment, readout circuit 110 may read out one row of image data at a time along readout column line 102, or may utilize other techniques (not shown) to read out the image data, such as column / row readout, serial readout, or simultaneous parallel readout of all pixels.

[0027] Control circuitry 120 is connected to pixel array 105 to control pixel array 105. For example, control circuitry 120 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal may be a global shutter signal, enabling all pixels within pixel array 105 to simultaneously capture their respective image data during a single acquisition window. In other embodiments, the shutter signal may be a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

[0028] This invention proposes a method for fabricating an image sensor, comprising: providing a substrate; forming a gate structure of a transistor on the substrate; forming a mask layer with trenches on the substrate; and performing ion implantation using the gate structure and the mask layer together as barriers to form the source and drain of the transistor.

[0029] The embodiments of the present invention will be described below with reference to the accompanying drawings. Example

[0030] refer to Figure 2 A substrate 20 is provided; a gate structure 21 of a transistor is formed on the substrate 20.

[0031] refer to Figure 3 A first mask layer 221, a second mask layer 222, and a patterned photoresist and / or anti-reflective layer 23 are formed on the substrate 20 from bottom to top. The anti-reflective layer can be BARC or TARC.

[0032] refer to Figure 4 A mask layer (including a patterned first mask layer 221 and a second mask layer 222) with trenches 24 is formed on the substrate. The aspect ratio of the trenches 24 is greater than 10.

[0033] refer to Figure 5 Using the mask layer of gate structure 21 and trench 24 as a barrier, the source / drain of the transistor is formed in the substrate 20 by ion implantation.

[0034] refer to Figure 6The trench 24 is backfilled with a protective layer 26. The protective layer 26 is used to protect the surface of the substrate 20 at the bottom of the trench 24 from damage when the mask layer is removed.

[0035] refer to Figure 7 Remove the second mask layer 222 and the top protective layer 26.

[0036] refer to Figure 8 Remove the first mask layer 221 and the remaining protective layer 26.

[0037] Specifically, the second mask layer 222 and the top protective layer 26 are first removed by etching with a fluorine-based gas, and then the first mask layer 221 and the remaining protective layer 26 are removed by etching with a non-fluorine-based gas.

[0038] In some embodiments, the material of the first mask layer 221 is a carbon-based material, the material of the second mask layer 222 is an inorganic dielectric, and the material of the protective layer 26 is selected from a material with high fluidity.

[0039] In some embodiments, the material of the first mask layer 221 is selected from BARC, PR, SOC or APF, the material of the second mask layer 222 is selected from LTO, SiARC or DARC, and the protective layer 26 is selected from BARC, PR or SOC.

[0040] In some embodiments, the thickness of the first mask layer 221 is 500-50000 Å, the thickness of the second mask layer 222 is 10-1000 Å, and the thickness of the protective layer 26 is 500-10000 Å. Example

[0041] refer to Figure 9 A substrate 300 is provided; two adjacent gate structures 31 of transistors are formed on the substrate 300.

[0042] refer to Figure 10 A first mask layer 321, a second mask layer 322, and a patterned photoresist and / or anti-reflective layer 33 are formed on the substrate 30 from bottom to top. The anti-reflective layer can be BARC or TARC.

[0043] refer to Figure 11 A mask layer (including a patterned first mask layer 321 and a second mask layer 322) with trenches 34 is formed on the substrate. The aspect ratio of the trenches 34 is greater than 10.

[0044] refer to Figure 12 Using the mask layer of gate structure 31 and trench 34 as a barrier, the source / drain 35 of the transistor is formed in the substrate 30 by ion implantation. Two adjacent gates share a source or drain.

[0045] refer to Figure 13The trench 34 is backfilled with a protective layer 36. The protective layer 36 is used to protect the surface of the substrate 30 at the bottom of the trench 34 from damage when the mask layer is removed.

[0046] refer to Figure 14 Remove the second mask layer 322 and the top protective layer 36.

[0047] refer to Figure 15 Remove the first mask layer 321 and the remaining protective layer 36.

[0048] Specifically, the second mask layer 322 and the top protective layer 36 are first removed by etching with a fluorine-based gas, and then the first mask layer 321 and the remaining protective layer 36 are removed by etching with a non-fluorine-based gas.

[0049] In some embodiments, the material of the first mask layer 321 is a carbon-based material, the material of the second mask layer 322 is an inorganic dielectric, and the material of the protective layer 36 is selected from a material with high fluidity.

[0050] In some embodiments, the material of the first mask layer 321 is selected from BARC, PR, SOC or APF, the material of the second mask layer 322 is selected from LTO, SiARC or DARC, and the protective layer 36 is selected from BARC, PR or SOC.

[0051] In some embodiments, the thickness of the first mask layer 321 is 500-50000 Å, the thickness of the second mask layer 322 is 10-1000 Å, and the thickness of the protective layer 36 is 500-10000 Å.

[0052] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for fabricating an image sensor, characterized in that, include: Provide substrate; The substrate has a transistor gate structure formed on it; A mask layer with trenches is formed on the substrate; Using the gate structure and the mask layer together as barriers, ion implantation is performed to form the source and drain of the transistor.

2. The method according to claim 1, characterized in that, Also includes: The trench was backfilled with a protective layer; Remove the mask layer and the protective layer, the protective layer being used to protect the substrate surface at the bottom of the trench from damage during the removal of the mask layer.

3. The method according to claim 2, characterized in that, The mask layer further includes: a first mask layer and a second mask layer formed from bottom to top; The removal of the mask layer and the protective layer includes: Remove the second mask layer and the top protective layer, then remove the first mask layer and the remaining protective layer.

4. The method according to claim 3, characterized in that, The step of removing the second mask layer and the top protective layer, and then removing the first mask layer and the remaining protective layer includes: First, the second mask layer and the top protective layer are removed by etching with a fluorine-based gas. Then, the first mask layer and the remaining protective layer are removed by etching with a non-fluorine-based gas.

5. The method according to claim 4, characterized in that, The first mask layer is made of a carbon-based material, the second mask layer is made of an inorganic dielectric material, and the protective layer is made of a material with high fluidity.

6. The method according to claim 5, characterized in that, The material of the first mask layer is selected from BARC, PR, SOC or APF, the material of the second mask layer is selected from LTO, SiARC or DARC, and the protective layer is selected from BARC, PR or SOC.

7. The method according to claim 6, characterized in that, The thickness of the first mask layer is 500-50000 Å, the thickness of the second mask layer is 10-1000 Å, and the thickness of the protective layer is 500-10000 Å.

8. The method according to claim 1, characterized in that, The mask layer further includes: photoresist, and / or an anti-reflective layer, wherein the anti-reflective layer is BARC or TARC.

9. The method according to claim 8, characterized in that, The grooved mask layer is obtained by photolithography and etching processes.

10. The method according to claim 1, characterized in that, The aspect ratio of the trench is greater than 10.

11. The method according to claim 1, characterized in that, The transistor has more than 1 gate; Two adjacent gates share a source or drain.

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