Cmos image sensor

Abstract

This application discloses a CMOS image sensor, comprising: a substrate having a front side and a back side; a photodiode extending from the back side of the substrate into the substrate; a floating diffusion region extending from the front side of the substrate into the substrate; and an annular vertical transfer gate extending from the front side of the substrate into the substrate. The annular vertical transfer gate is a closed ring in a plane parallel to the front side of the substrate and at least partially surrounds a charge transfer channel connecting the photodiode and the floating diffusion region. The charge transfer channel is located in the inner region enclosed by the annular vertical transfer gate, which can solve the problem of difficulty in simultaneously achieving high charge transfer efficiency, low image trailing, and high full-well capacity in vertical transfer gates of related small-pixel CMOS image sensors.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a CMOS image sensor. Background Technology

[0002] As pixel sizes continue to shrink, Complementary Metal-Oxide-Semiconductor (CMOS) image sensors face increasingly higher demands on the photoelectric conversion and charge storage capabilities within the pixels. Currently, the 4T (Four-Transistor, 4T) active pixel structure has become the mainstream solution due to its reset efficiency and low noise characteristics. This structure typically includes a Reset Transistor (RST), a Transfer Gate (TG), a Source Follower (SF), a Row Select (RS), and a Floating Diffusion (FD) region.

[0003] The traditional planar transfer gate (PTG) used in the aforementioned 4T architecture has an inherent potential barrier along the charge transfer path, severely hindering the complete transfer of electrons from the PD to the FD. This results in low charge transfer efficiency (CTE) and significant image lag. To address these shortcomings, the industry has proposed using a vertical transfer gate (VTG) structure, which reduces the potential barrier between the PD and FD to some extent, improving charge transfer performance compared to PTG. However, while maintaining high charge transfer efficiency and low image lag, the existing VTG structure struggles to support higher PD doping concentrations to increase full-well capacity (FWC), resulting in a trade-off between charge transfer efficiency, image lag, and full-well capacity. Summary of the Invention

[0004] This application provides a CMOS image sensor that can solve the problem of difficulty in simultaneously achieving high charge transfer efficiency, low image trailing, and high full-well capacity in the vertical transfer gate of related small-pixel CMOS image sensors.

[0005] On one hand, embodiments of this application provide a CMOS image sensor, including: A substrate having opposing front and back sides; A photodiode, the photodiode extending from the back side of the substrate into the substrate; A floating diffusion region extending from the front side of the substrate into the interior of the substrate; An annular vertical transfer gate extends from the front side of the substrate into the substrate. The annular vertical transfer gate is in the form of a closed ring in a plane parallel to the front side of the substrate, and a charge transfer channel is formed in the inner region of the annular vertical transfer gate. The annular vertical transfer gate is located between the photodiode and the floating diffusion region, and at least partially surrounds the photodiode, so as to control the photogenerated charge generated by the photodiode to be transferred to the floating diffusion region through the charge transfer channel.

[0006] In some embodiments, the photodiode includes a first doped region and a second doped region, the first doped region being located within the substrate on the side near the front side, and the second doped region being located below the first doped region and near the back side of the substrate.

[0007] In some embodiments, the depth of the annular vertical transfer gate is not less than the depth of the first doped region.

[0008] In some embodiments, the projection shape of the annular vertical transfer grid in a plane parallel to the front surface of the substrate is circular or rectangular.

[0009] In some embodiments, the annular vertical transfer gate includes a dielectric layer and a conductive layer from bottom to top.

[0010] In some embodiments, an isolation structure is also formed within the substrate for isolating adjacent photodiodes.

[0011] In some embodiments, the CMOS image sensor further includes a color filter layer and a microlens, the color filter layer and the microlens being located on the back side of the substrate, wherein the color filter layer is located between the microlens and the photodiode.

[0012] In some embodiments, the filter layer and the microlens overlap the photodiode in a direction perpendicular to the back surface of the substrate.

[0013] The technical solution of this application has at least the following advantages: By introducing a ring-shaped vertical transfer gate structure, a fully encircling gate structure is formed within the enclosing region, thereby achieving excellent electrostatic control over the charge transfer channel. This significantly improves charge transfer efficiency, reduces image trailing, and maintains good full-well capacity. Furthermore, the ring-shaped vertical transfer gate has various selectable projection shapes (circular, rectangular, or other closed shapes) in a plane parallel to the front side of the substrate, allowing the device to flexibly adapt to different design requirements. In addition, by ensuring that the depth of the ring-shaped vertical transfer gate is not less than the depth of the first doped region, effective control of the charge transfer channel can be ensured, thereby improving the device's operational stability and reliability. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a circuit diagram of a 4T pixel structure in the prior art.

[0016] Figure 2 This is a top view of a CMOS image sensor provided in an exemplary embodiment of this application.

[0017] Figure 3 This is a cross-sectional schematic diagram of a CMOS image sensor provided in an exemplary embodiment of this application. Detailed Implementation

[0018] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] CMOS image sensors consist of pixel arrays composed of multiple pixels, reference Figure 2 The image shown is a top view of a portion of the pixel array of a CMOS image sensor provided in an exemplary embodiment of this application. (Reference) Figure 3 As shown, it illustrates a top view of a single photodiode / pixel of a CMOS image sensor provided in an exemplary embodiment of this application.

[0023] refer to Figure 3 As shown, this application provides a CMOS image sensor, including: The substrate 100 has a front side 100a and a back side 100b. Exemplarily, this application is a backside-illuminated (BSI) CMOS image sensor, wherein the front side 100a is the side where the semiconductor elements and interconnects of the CMOS image sensor are pre-formed, and the back side 100b is the side that receives incident light. In this embodiment, the substrate 100 can be a p-type doped silicon substrate, for example, with a doping concentration of 1×10⁻⁶. 16 cm -3 .

[0024] Multiple pixel units are formed within the substrate 100. Each pixel unit includes at least: A photodiode 110 extends from the back side 100b of the substrate into the substrate; optionally, in this embodiment, the photodiode 110 can be an N-type doped well, and the doping concentration can be selected according to the design requirements of the full-well capacity. For example, the doping concentration can be 5 × 10⁻⁶. 16 cm -3 Up to 1×10 17 cm -3 between.

[0025] The floating diffusion region 120 extends from the front side 100a of the substrate into the substrate and is close to the front side of the substrate. Exemplarily, the floating diffusion region 120 can be used to receive photogenerated charge transferred from the photodiode 110 and convert it into a voltage signal. For example, in this embodiment, the floating diffusion region 120 can be an N-type doped well with a doping concentration of 1×10⁻⁶. 16 cm -3 .

[0026] An annular vertical transfer gate 130 extends from the front side 100a of the substrate into the substrate; the annular vertical transfer gate 130 is in the form of a closed ring in a plane parallel to the front side 100a of the substrate, and a charge transfer channel is formed in the inner region of the annular vertical transfer gate 130. The annular vertical transfer gate 130 is located between the photodiode 110 and the floating diffusion region 120, and at least partially surrounds the photodiode 110, so as to control the photogenerated charge generated by the photodiode 110 to be transferred to the floating diffusion region 120 through the charge transfer channel.

[0027] As an optional embodiment of the present invention, to improve photoelectric conversion efficiency and optimize charge transfer characteristics, the photodiode may include multiple doped regions. For example, reference... Figure 3 As shown, the photodiode 110 may include a first doped region 111 and a second doped region 112. The first doped region 111 is located within the substrate near the front side 100a, and the second doped region 112 is located below the first doped region 111 and near the back side 100b of the substrate. The doping concentration of the first doped region is lower than that of the second doped region; for example, the doping concentration of the first doped region may be 5 × 10⁻⁶. 16 cm -3 The doping concentration of the second doped region can be 1×10⁻⁶. 17 cm -3 .

[0028] Optional, see reference Figure 3As shown, the projected shape of the annular vertical transfer gate 130 in a plane parallel to the front surface 100a of the substrate can be circular, rectangular, or other closed shapes. The depth of the annular vertical transfer gate 130 can penetrate the region where the charge transfer channel is located. For example, in this embodiment, the depth h1 of the annular vertical transfer gate 130 is not less than the depth h2 of the first doped region 111. By setting the annular vertical transfer gate to have multiple selectable projected shapes (circular, rectangular, or other closed shapes) in a plane parallel to the front surface of the substrate, and its depth can penetrate the region where the charge transfer channel is located, especially when the depth of the annular vertical transfer gate is not less than the depth of the first doped region, effective control of the charge transfer channel can be ensured, which helps to optimize the charge transfer process, improve the stability and reliability of the device, and enable it to work normally under various harsh conditions (such as high radiation environments, strong electromagnetic interference environments, etc.), thus broadening the application range of the device; at the same time, it provides flexibility for its application under different design requirements.

[0029] The annular vertical transfer gate 130 may include a dielectric layer and a conductive layer from bottom to top. The dielectric layer may include silicon oxide (SiO2) material. The conductive layer may include polysilicon, aluminum, or other conductive materials. The annular vertical transfer gate 130 can be manufactured by forming a deep trench within the front side 100a of the substrate and sequentially filling it with the dielectric layer and the conductive layer material.

[0030] Furthermore, an isolation structure 140 may be formed within the substrate of this application for isolating adjacent photodiodes / elements. Optionally, in this embodiment, the isolation structure may be a deep trench isolation structure (DTI). The isolation structure may be formed by filling with silicon oxide material.

[0031] Each pixel unit of this application may further include a color filter layer 150 and a microlens 160, which are located on the back surface 100b of the substrate. The color filter layer 150 is positioned between the photodiode 110 and the microlens 160. Optionally, in this embodiment, the color filter layer 150 and the microlens 160 overlap with the photodiode 110 in a direction perpendicular to the back surface 100b of the substrate.

[0032] When the CMOS image sensor is in operation, its operation process includes a reset stage, an exposure stage, and a charge transfer stage. Reset stage: First, a reset voltage (e.g., 2.0 V) is applied to the floating diffusion region 120, and an on-state voltage (e.g., 1.6 V) is applied to the annular vertical transfer gate 130 to clear any residual charge in the photodiode 110.

[0033] Exposure stage: The annular vertical transfer gate 130 is turned off (a shutdown voltage, such as -2.0 V is applied), and the photodiode 110 is illuminated (for example, using a light source with an intensity of 0.1 W / cm² and a wavelength of 600 nm). The photodiode 110 absorbs photons and generates photogenerated charge.

[0034] Charge transfer stage: After exposure, an on-state voltage (e.g., 1.6 V) is applied again to the annular vertical transfer gate 130. At this time, due to the all-around gate structure of the annular vertical transfer gate 130, strong electrostatic control is formed in the charge transfer channel region, forming a low-barrier channel between the photodiode 110 and the annular vertical transfer gate 130, so that the photogenerated charge stored in the photodiode 110 can be efficiently transferred to the floating diffusion region 120 located outside the annular vertical transfer gate through the charge transfer channel.

[0035] Compared to traditional vertical transfer gate structures, which suffer from potential barriers in highly doped photodiodes due to insufficient electrostatic control, the annular vertical transfer gate of this invention addresses the issue of potential barriers in highly doped photodiodes (e.g., 1×10⁻⁶). 17 cm -3 Under these conditions, a channel with a lower potential barrier can be formed between the photodiode and the annular vertical transfer gate, which significantly improves the electrostatic control capability of the charge transfer channel, thereby greatly improving the charge transfer efficiency, reducing the image trailing effect, and maintaining good full-well capacity (for example, according to simulation data, the effective full-well capacity can be increased by 40% under the same volume).

[0036] In summary, this invention introduces a ring-shaped vertical transfer gate structure to form a fully encircling gate structure within the enclosing region, thereby achieving excellent electrostatic control over the charge transfer channel. This significantly improves charge transfer efficiency, reduces image trailing, and maintains good full-well capacity. Furthermore, the ring-shaped vertical transfer gate has various selectable projection shapes (circular, rectangular, or other closed shapes) in a plane parallel to the front side of the substrate, allowing the device to flexibly adapt to different design requirements. In addition, by ensuring that the depth of the ring-shaped vertical transfer gate is not less than the depth of the first doped region, effective control of the charge transfer channel can be ensured, thereby improving the device's operational stability and reliability.

[0037] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A CMOS image sensor, characterized in that, include: A substrate having opposing front and back sides; A photodiode, the photodiode extending from the back side of the substrate into the substrate; A floating diffusion region extending from the front side of the substrate into the interior of the substrate; An annular vertical transfer gate extends from the front side of the substrate into the substrate. The annular vertical transfer gate is in the form of a closed ring in a plane parallel to the front side of the substrate, and a charge transfer channel is formed in the inner region of the annular vertical transfer gate. The annular vertical transfer gate is located between the photodiode and the floating diffusion region, and at least partially surrounds the photodiode, so as to control the photogenerated charge generated by the photodiode to be transferred to the floating diffusion region through the charge transfer channel.

2. The CMOS image sensor according to claim 1, characterized in that, The photodiode includes a first doped region and a second doped region. The first doped region is located on the side of the substrate closer to the front side, and the second doped region is located below the first doped region and closer to the back side of the substrate.

3. The CMOS image sensor according to claim 2, characterized in that, The depth of the annular vertical transfer gate is not less than the depth of the first doped region.

4. The CMOS image sensor according to claim 1 or 2, characterized in that, The projection shape of the annular vertical transfer grid in a plane parallel to the front surface of the substrate is circular or rectangular.

5. The CMOS image sensor according to claim 1 or 2, characterized in that, The annular vertical transfer gate comprises a dielectric layer and a conductive layer from bottom to top.

6. The CMOS image sensor according to claim 1 or 2, characterized in that, An isolation structure is also formed within the substrate to isolate adjacent photodiodes.

7. The CMOS image sensor according to claim 1 or 2, characterized in that, The CMOS image sensor further includes a color filter layer and a microlens, the color filter layer and the microlens being located on the back side of the substrate, wherein the color filter layer is located between the microlens and the photodiode.

8. The image sensor according to claim 7, characterized in that, The filter layer and the microlens overlap with the photodiode in a direction perpendicular to the back surface of the substrate.

Images