A back contact cell and a method of manufacturing the same

Abstract

This invention relates to a back contact battery and its fabrication method. The fabrication method of the back contact battery includes: providing a substrate having a first surface and a second surface opposite to each other; the first surface having alternately spaced N-type regions and P-type regions; forming an N-type doped layer in the N-type regions; forming a semiconductor stack in the P-type regions, the semiconductor stack including a P-type doped layer and a protective layer formed sequentially, the semiconductor stack being fabricated in the same chamber; removing the protective layer; and forming transparent conductive layers respectively covering the N-type doped layer and the P-type doped layer. This back contact battery, by forming a protective layer, achieves a stack formation scheme within the same chamber, saving process time and improving production efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a back contact cell and its preparation method. Background Technology

[0002] Solar photovoltaic (PV) technology, as a clean and environmentally friendly new energy source, is an important development direction for renewable energy in various countries. Existing heterojunction solar cells have a tandem structure consisting of an intrinsic amorphous silicon layer and a doped layer. To ensure the cleanliness of the intrinsic amorphous silicon layer during formation, the intrinsic amorphous silicon layer and the doped layer are deposited in separate chambers, resulting in a long process time and limited production efficiency. If the tandem structure is deposited entirely within a single chamber, the residual doped layer within the chamber will affect the passivation effect of the intrinsic silicon in the next processing step. Summary of the Invention

[0003] Therefore, it is necessary to provide a back contact battery and its preparation method to address the problem of inability to improve production efficiency.

[0004] This disclosure provides a back contact battery.

[0005] The method for preparing a back contact battery provided in this disclosure includes:

[0006] A substrate is provided, the substrate having a first surface and a second surface opposite to each other, the first surface having alternately spaced N-type regions and P-type regions;

[0007] An N-type doped layer is formed in the N-type region;

[0008] A semiconductor stack is formed in the P-type region, the semiconductor stack comprising a P-type doped layer and a protective layer formed sequentially, the semiconductor stack being fabricated in the same chamber;

[0009] Remove the protective layer;

[0010] A transparent conductive layer is formed covering the N-type doped layer and the P-type doped layer, respectively.

[0011] In one embodiment, the semiconductor stack is fabricated in the same chamber, including:

[0012] Within the cavity, an intrinsic amorphous silicon layer, a P-type doped layer, and a protective layer are deposited in the P-type region.

[0013] In one embodiment, the P-type doped layer is doped microcrystalline silicon or doped amorphous silicon.

[0014] In one embodiment, the chamber is a PECVD chamber.

[0015] In one embodiment, the N-type doped layer formed in the N-type region further includes a mask layer formed on the N-type doped layer.

[0016] In one embodiment, the intrinsic amorphous silicon layer has a thickness of less than 7 nanometers, the p-type doped layer has a thickness of less than 7 nanometers, and the protective layer has a thickness of less than 50 nanometers.

[0017] In one embodiment, the protective layer is made of silicon nitride, silicon dioxide, or intrinsic silicon.

[0018] In one embodiment, a passivation layer and an antireflection layer are sequentially formed on the second surface of the substrate before forming the semiconductor stack of the P-type region.

[0019] In one embodiment, electrodes are formed on transparent conductive layers in the N-type region and the P-type region, respectively.

[0020] This disclosure provides a back contact battery, which is prepared using the above-described preparation method.

[0021] The aforementioned back-contact battery employs a semiconductor stack including a protective layer. During the fabrication of the semiconductor stack within the same chamber, a P-type doped layer and a protective layer are formed sequentially. The protective layer is simultaneously deposited within the chamber, covering the previously formed P-type doped layer, forming a protective film. This prevents the escape of dopant sources from the P-type doped layer during subsequent processes, thus avoiding chamber contamination and ensuring the cleanliness of subsequent depositions. This also achieves a stack deposition scheme within a single device. It saves auxiliary time spent transferring between different devices during stack production, thereby shortening the stack formation process time and improving production efficiency. Attached Figure Description

[0022] Figure 1 A flowchart illustrating the fabrication process of a back contact battery according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 1 ;

[0024] Figure 3 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 2 ;

[0025] Figure 4 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 3 ;

[0026] Figure 5 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 4 ;

[0027] Figure 6 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 5 ;

[0028] Figure 7 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 6 ;

[0029] Figure 8 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 7 ;

[0030] Figure 9 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 8 ;

[0031] Figure 10 A schematic diagram of the structure of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 9 .

[0032] Explanation of reference numerals: 1. Silicon wafer; 2. Passivation layer; 3. Antireflective layer; 4. Tunneling oxide layer; 5. N-type doped layer; 6. Mask layer; 8. Semiconductor stack; 81. Intrinsic amorphous silicon layer; 82. P-type doped layer; 83. Protective layer; 9. Transparent conductive layer; 10. Isolation trench; 11. Electrode. Detailed Implementation

[0033] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0034] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0036] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0038] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0039] On the one hand, please refer to Figure 1 An embodiment of the present invention provides a method for preparing a back contact battery, comprising:

[0040] S01: A substrate is provided, the substrate having opposing first and second surfaces, wherein the first surface has alternately spaced N-type regions and P-type regions. The substrate is made of silicon wafer 1, or N-type silicon wafer 1.

[0041] S02: An N-type doped layer 5 formed in the N-type region; the N-type doped layer 5 is deposited in the N-type region and can be a phosphorus-doped layer, or an arsenic-doped or antimony-doped layer.

[0042] S03: A semiconductor stack 8 formed in the P-type region, comprising a P-type doped layer 82 and a protective layer 83 formed sequentially, wherein the semiconductor stack 8 is fabricated in the same chamber. The semiconductor stack 8 is formed in a plate-type PECVD apparatus. Since the semiconductor stack 8 includes the protective layer 83, which covers the previously deposited thin film within the chamber, it only needs to be formed in one process chamber. This simplifies the structure of the plate-type PECVD apparatus, requiring only one process chamber.

[0043] S04: Remove protective layer 83; the protective layer 83 can be removed by wet method or laser method.

[0044] S05: Form transparent conductive layers 9 covering the P-type doped layer 82 and the N-type doped layer respectively. The transparent conductive layers 9 covering the P-type doped layer 82 and the N-type doped layer 82 can be deposited in a PVD apparatus, and then isolation trenches 10 can be formed on the transparent conductive layers 9 to isolate the transparent conductive layers 9 on the P-type doped layer 82 and the transparent conductive layers 9 on the N-type region; alternatively, the transparent conductive layers 9 covering the P-type doped layer 82 and the N-type doped layer can be made of different materials. In other embodiments, the isolation trenches 10 can be deepened and formed on the P-type doped layer 82 to completely isolate the transparent conductive layers in the N-type and P-type regions, such as... Figure 10 As shown.

[0045] This scheme employs a method where the semiconductor stack 8 is fabricated within a single chamber. During the fabrication of the semiconductor stack 8 within the same chamber, a P-type doped layer 82 and a protective layer 83 are formed sequentially. The protective layer 83 is also deposited within the chamber, covering the previously formed P-type doped layer 82, forming a protective film. This prevents the P-type doped layer 82 from escaping during subsequent processes within the chamber, ensuring the cleanliness of subsequent depositions. This also achieves a scheme where the stack is deposited within a single device. This saves auxiliary time spent transferring between different devices during stack production, thereby shortening the process time for forming the stack and ultimately improving production efficiency.

[0046] Furthermore, the semiconductor stack 8 is fabricated within the same chamber, including: depositing an intrinsic amorphous silicon layer 81, a P-type doped layer 82, and a protective layer 83 in the P-type region within the same chamber. After depositing the intrinsic amorphous silicon layer 81 and the N-type doped layer within the same chamber, the protective layer 83 is deposited. The protective layer 83 covers the P-type doped layer 82 within the chamber, thereby preventing the precipitation of materials such as boron or gallium from the P-type doped layer 82 in subsequent processes. This ensures the cleanliness of the intrinsic amorphous silicon layer 81 deposited in subsequent processes. The P-type doped layer 82 can be doped microcrystalline silicon or doped amorphous silicon.

[0047] In this embodiment, the intrinsic silicon thickness is less than 7 nanometers, the doped layer thickness is less than 7 nanometers, and the protective layer 83 thickness is less than 50 nanometers. For example, the intrinsic silicon thickness can be 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, or any value within the range of any two of the above values; the doped layer thickness can be 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, or any value within the range of any two of the above values; and the protective layer 83 thickness can be 1 nanometer, 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, or any value within the range of any two of the above values. In other embodiments, the thicknesses of the intrinsic amorphous silicon layer, the doped layer, and the protective layer can also be set to other thicknesses as needed.

[0048] Furthermore, the protective layer 83 is made of silicon nitride. Silicon nitride can withstand temperatures up to 1700 degrees Celsius, while its decomposition temperature is approximately 1900 degrees Celsius. Due to its extremely high thermal and chemical stability, after depositing the silicon nitride-covered p-type doped layer 82 within the chamber, the stability of silicon nitride prevents it from decomposing during subsequent processes, thus ensuring the cleanliness of the chamber. In other embodiments, the protective layer 83 can also be made of silicon dioxide or intrinsic silicon.

[0049] In one embodiment, the protective layer 83 is removed before the transparent conductive layer 9 is formed. Since the protective layer 83 primarily serves to cover the N-type doped layer within the deposition chamber, it is essentially a sacrificial layer. Because the sacrificial layer is removed entirely, a wet process can be used for removal.

[0050] In one embodiment, the N-type doped layer formed in the N-type region further includes a mask layer 6 formed on the N-type doped layer 5. The N-type doped layer 5 can be formed by LPCVD, where a tunneling oxide layer 4 is deposited on a silicon wafer, followed by silicon deposition and then phosphorus diffusion to convert the deposited silicon into N-type doped silicon. During phosphorus diffusion, a phosphorus phosphorus precipitate (PSG) is simultaneously formed on the surface of the deposited silicon, and the PSG serves as the mask layer 6. Alternatively, a PECVD method can be used, where a tunneling oxide layer 4 is deposited on a silicon wafer, followed by the deposition of doped silicon as the N-type doped layer 5, and then silicon nitride is deposited as the mask layer 6.

[0051] In one embodiment, a passivation layer 2 and an antireflection layer 3 are sequentially formed on the second surface of the substrate before forming the semiconductor stack 8 of the P-type region. The antireflection layer is provided to reduce sunlight reflection and improve the utilization rate of sunlight. Since the semiconductor stack 8 includes an intrinsic amorphous silicon layer 81 made of amorphous silicon, which is formed at a low temperature, while the passivation layer 2 and the antireflection layer 3 are formed at higher temperatures than the semiconductor stack 8, if the semiconductor stack 8 were formed after the passivation layer 2 and the antireflection layer 3, the high temperature during the formation of the antireflection layer 2 and the silicon nitride layer 3 would damage the material of the semiconductor stack 8. Therefore, the antireflection layer 2 and the silicon nitride layer 3 are formed before the semiconductor stack 8. The passivation layer 2 is made of aluminum oxide, and the antireflection layer 3 is made of silicon nitride or silicon oxide.

[0052] In one embodiment, electrodes 11 are formed on the transparent conductive layers 9 in the N-type and P-type regions, respectively. The electrode 11 can be made of silver, copper, silver-copper alloy, or aluminum, and can be formed by printing and sintering silver paste, silver-copper mixed paste, or aluminum paste.

[0053] The present invention also provides an embodiment to illustrate the method for manufacturing a back-contact solar cell provided in the embodiment of the present invention.

[0054] The first step is to clean and texturize silicon wafer 1. For example, silicon wafer 1 is cleaned in a tank cleaning machine, and then texturized.

[0055] The second step involves depositing a passivation layer 2 and an antireflection layer 3 on the second side of silicon wafer 1. The passivation layer 2 is made of aluminum oxide and can be deposited in an ALD (Alternating Current Deposition) device. The antireflection layer 3 is made of silicon nitride or silicon oxide and can be deposited in a PECVD (Pure Chemical Vapor Deposition) device.

[0056] The third step is to form a tunneling oxide layer 4 on the first side of the silicon wafer 1. This tunneling oxide layer 4 can be formed in an LPCVD device, and the material of the tunneling oxide layer 4 can be silicon dioxide.

[0057] Step 4: Deposit an N-type doped layer 5 and a mask layer 6 on the tunneling oxide layer 4. The N-type doped layer 5 can be phosphorus-doped polycrystalline silicon. This step can be performed in a PECVD equipment. After forming the N-type doped layer 5, the mask layer 6 is formed. The mask layer 6 can be made of silicon nitride. Alternatively, silicon can be deposited first in LPCVD, followed by phosphorus diffusion to form the N-type polycrystalline silicon 5. The PSG produced during the formation of the N-type polycrystalline silicon 5 serves as the mask layer.

[0058] Step 5: Remove the non-N-region portion of the N-type polysilicon 5, such as... Figure 2 As shown. When removing the N-type polysilicon 5, a laser is used to remove the mask layer 6 in the non-N region, and then a wet process is used to remove the N-type polysilicon 5 and oxide layer 4 in the P-type region.

[0059] Step 6: Deposit a semiconductor stack 8 on the first side of silicon wafer 1, such as... Figure 3 As shown, the semiconductor stack 8 includes an intrinsic amorphous silicon layer 81, a P-type doped layer 82, and a protective layer 83, which are deposited in the same chamber of a PECVD equipment.

[0060] Step 7: Open the protective layer of the N-region, then remove the intrinsic amorphous silicon layer 81 and the P-type doped layer 82 at the opening, as follows. Figure 4 and Figure 5 As shown. First, an opening is made in the silicon nitride in the N-region using a laser or wet process, and then the intrinsic amorphous silicon layer 81 and the P-type doped layer 82 in the opening region are removed by a wet process.

[0061] Step 8: Wet removal of protective layer 83 and mask layer 6 corresponding to the opening area, such as... Figure 6 As shown.

[0062] Step 9: A transparent conductive layer 9 is deposited on the first side of silicon wafer 1 using a PVD device. This conductive layer covers the N-type doped layer 5 and the P-type doped layer 82, as shown below. Figure 7 As shown.

[0063] Step 10: Using a laser, an isolation groove 10 is formed on the transparent conductive layer 9. This isolation groove 10 is located between the N-region and the p-region, such as... Figure 8 As shown.

[0064] Step 11: Print metal electrodes 11 on the transparent conductive layers 9 in the N-region and P-region respectively, and sinter them, as shown below. Figure 9 As shown.

[0065] On the other hand, one embodiment of the present invention provides a back contact battery, which is manufactured using the above-described preparation method.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for preparing a back contact battery, characterized in that, include: A substrate is provided, the substrate having a first surface and a second surface opposite to each other, the first surface having alternately spaced N-type regions and P-type regions; An N-type doped layer is formed in the N-type region; A semiconductor stack is formed in the P-type region, the semiconductor stack comprising a P-type doped layer and a protective layer formed sequentially, the semiconductor stack being fabricated in the same chamber; Remove the protective layer; A transparent conductive layer is formed covering the N-type doped layer and the P-type doped layer, respectively.

2. The preparation method according to claim 1, characterized in that, The semiconductor stack is fabricated in the same chamber, including: Within the cavity, an intrinsic amorphous silicon layer, a P-type doped layer, and a protective layer are deposited in the P-type region.

3. The preparation method according to claim 2, characterized in that, P-type doped layers are either doped microcrystalline silicon or doped amorphous silicon.

4. The preparation method according to claim 1 or 2, characterized in that, The chamber is a PECVD chamber.

5. The preparation method according to claim 1, characterized in that: The N-type doped layer formed in the N-type region further includes a mask layer formed on the N-type doped layer.

6. The preparation method according to claim 2, characterized in that, The intrinsic amorphous silicon layer has a thickness of less than 7 nanometers, the P-type doped layer has a thickness of less than 7 nanometers, and the protective layer has a thickness of less than 50 nanometers.

7. The preparation method according to claim 2, characterized in that, The protective layer is made of silicon nitride, silicon dioxide, or intrinsic silicon.

8. The preparation method according to claim 1, characterized in that, Before forming the semiconductor stack of the P-type region, a passivation layer and an antireflection layer are sequentially formed on the second surface of the substrate.

9. The preparation method according to claim 1, characterized in that, Electrodes are formed on the transparent conductive layers in the N-type and P-type regions, respectively.

10. A back-contact battery, characterized in that, It is prepared by the preparation method according to any one of claims 1-9.

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