A pécvd single chamber stack production process and back contact cells

Abstract

This invention relates to a PECVD single-chamber stack fabrication process and a back contact cell. A PECVD single-chamber deposition stack fabrication process includes: providing a substrate placed in a chamber; and sequentially depositing an intrinsic silicon layer, a doped silicon layer, and a sacrificial layer on the substrate. The stack deposited in this single-chamber configuration includes a protective layer that forms a protective film within the chamber, preventing the escape of dopant sources from the doped silicon layer in subsequent processes and ensuring the cleanliness of subsequent deposition.

Description

Technical Field

[0001] This invention relates to the field of solar module manufacturing technology, and in particular to a PECVD single-chamber stacked fabrication process and a back contact cell. Background Technology

[0002] Existing heterojunction solar cells employ a stacked structure consisting of an intrinsic silicon layer and a doped layer. To ensure the cleanliness of the intrinsic silicon layer during formation, the intrinsic silicon layer and the doped layer are deposited in separate chambers. This results in a longer overall process time, increased equipment length, decreased reliability, and no improvement in production efficiency. If the stacked structure is deposited entirely within a single chamber, residual doped layers within the chamber can affect the passivation effect of the intrinsic silicon in subsequent processes. Summary of the Invention

[0003] Therefore, it is necessary to provide a PECVD single-chamber stack fabrication process to address the problem that stacks cannot be deposited in a single chamber.

[0004] This disclosure provides a PECVD single-chamber deposition stack fabrication process, including:

[0005] Provide a base, which is placed in a chamber;

[0006] An intrinsic silicon layer, a doped silicon layer, and a sacrificial layer are sequentially deposited on the substrate.

[0007] In one embodiment, the intrinsic silicon layer has a thickness of 5-10 nm;

[0008] And / or, the thickness of the doped silicon layer is 5-10 nm;

[0009] And / or, the thickness of the sacrificial layer is 5-50 nm.

[0010] In one embodiment, the preparation process includes:

[0011] After introducing SiH4 and H2 into the chamber to a preset pressure, the RF is turned on. After depositing the intrinsic silicon of a preset thickness on the substrate, the doping gas is introduced into the chamber. After depositing the doped silicon layer of a preset thickness on the substrate, the RF is turned off and the introduction of the doping gas is stopped. Then, ammonia or nitrogen dioxide is introduced into the chamber to a preset pressure, the RF is turned on, the sacrificial layer is deposited to a preset thickness, the RF power supply is turned off and all reactive gas introduction is stopped.

[0012] In one embodiment, the preset pressure is 0.5-5 Torr;

[0013] And / or, the cavity is provided with a heating plate, the temperature of which is 150℃-250℃.

[0014] In one embodiment, the SiH4 flow rate is 0.5-2.0 slm, and the flow rate ratio of H2 to SiH4 is H2:SiH4 = 1-10.

[0015] In one embodiment, the flow rate of the dopant gas is 0.5%-5% of the SiH4 flow rate.

[0016] In one embodiment, the doping gas is a phosphorus source or a boron source.

[0017] In one embodiment, during the deposition of the sacrificial layer, the inlet flow rate of ammonia or nitrogen dioxide is 5-10 times that of the inlet flow rate of SiH4.

[0018] In one embodiment, the RF power density is 0.01-0.2 W / cm². 2 .

[0019] Another method, according to embodiments of this disclosure, is to provide a back contact battery, wherein the N-region or P-region of the back contact battery is fabricated using the above-described preparation process.

[0020] The aforementioned fabrication process simultaneously prepares a sacrificial layer during the fabrication of the semiconductor stack, thereby achieving stack deposition within a single PECVD chamber. When the semiconductor stack is fabricated within the same chamber, an intrinsic silicon layer, a doped silicon layer, and a sacrificial layer are formed sequentially. The sacrificial layer is also deposited within the chamber, covering the previously formed doped silicon layer. This sacrificial layer forms a protective film within the chamber, preventing the escape of dopant sources from the covered doped silicon layer and thus avoiding chamber contamination during subsequent depositions. This ensures the cleanliness of subsequent depositions and achieves a single-chamber stack deposition scheme. This saves the auxiliary time required for transferring between different chambers during stack production, thereby shortening the stack formation process time and improving production efficiency. Attached Figure Description

[0021] Figure 1 This is a flow chart of the PECVD single-chamber deposition stack fabrication process;

[0022] Figure 2 Schematic diagram of PECVD equipment Figure 1 ;

[0023] Figure 3 Schematic diagram of PECVD equipment Figure 2 .

[0024] The following are the reference numerals: 1. Loadlock chamber; 2. Process chamber; 21. Heating plate; 22. Lifting mechanism; 3. Unloadlock chamber; 4. Carrier; 5. Transmission mechanism; 6. Gap valve. Detailed Implementation

[0025] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0026] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0028] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0030] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0031] The following description, in conjunction with the accompanying drawings, illustrates the fabrication process of the PECVD single-chamber deposition stack and the back contact battery according to embodiments of this application.

[0032] Figure 2 and Figure 3 This is a schematic diagram of the PECVD equipment used in the PECVD single-chamber deposition stack fabrication process provided in the embodiments of this application.

[0033] In this embodiment, a PECVD device is used to deposit a stack on a substrate, and during the fabrication process, the substrate is placed on a carrier 4. For example, as shown... Figure 2 As shown, the PECVD equipment may include a loadlock chamber 1 and a process chamber 2. The substrate is transferred from the loadlock chamber 1 to the process chamber 2 via a transfer mechanism 5 for layer deposition, and then transferred back to the loadlock chamber 1. The transfer mechanism 5 can be a roller or a robotic arm. To facilitate the transfer of the carrier 4, the transfer mechanism 5 can be configured as a double-layer structure. Alternatively, it can be as follows: Figure 3 As shown, the PECVD equipment includes a loadlock chamber 1, a process chamber 2, and an unloadlock chamber 3. The substrate is transferred from the loadlock chamber 1 to the process chamber 2 via a transfer mechanism 5 for stack deposition, and then transferred to the unloadlock chamber 3.

[0034] Figure 1 This is a schematic flowchart illustrating the fabrication process of a PECVD single-chamber deposition stack provided in an embodiment of this application.

[0035] In a first aspect, embodiments of this application provide a fabrication process for a PECVD single-chamber deposition stack, the fabrication process including:

[0036] S10. Provide a substrate, which is placed in a chamber;

[0037] S20. An intrinsic silicon layer, a doped silicon layer, and a sacrificial layer are sequentially deposited on the substrate.

[0038] In the above scheme, after depositing a conventional stack including an intrinsic silicon layer and a doped silicon layer, a sacrificial layer is deposited. This allows the sacrificial layer to cover the doped silicon layer on the substrate and the entire interior of the cavity. The sacrificial layer forms a protective film inside the cavity, preventing the dopant source in the doped silicon layer from escaping and causing contamination of the cavity in the next deposition process. This ensures the cleanliness of the intrinsic silicon layer in the next process of the cavity.

[0039] In one embodiment, the intrinsic silicon layer thickness is 5-10 nm, the doped silicon layer thickness is 5-10 nm, and the sacrificial layer thickness is 5-50 nm. For example, the intrinsic silicon thickness can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or any value within the range of any two of the above values; the doped silicon layer thickness can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or any value within the range of any two of the above values; and the sacrificial layer thickness can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, or any value within the range of any two of the above values.

[0040] In one embodiment, the fabrication process includes: introducing SiH4 and H2 into a chamber to a preset pressure, turning on the RF, depositing intrinsic silicon of a preset thickness on a substrate, then introducing a doping gas into the chamber, depositing a doped silicon layer of a preset thickness on the substrate, turning off the RF and stopping the introduction of the doping gas, then introducing ammonia or nitrogen dioxide into the chamber to a preset pressure, turning on the RF, depositing a sacrificial layer to a preset thickness, turning off the RF power and stopping the introduction of all reactive gases. This achieves a process of depositing a multilayer stack within a single chamber.

[0041] Furthermore, the preset pressure is 0.5-5 Torr. The preset pressure can be 0.5 Torr, 1 Torr, 1.5 Torr, 2 Torr, 2.5 Torr, 3 Torr, 3.5 Torr, 4 Torr, 4.5 Torr, 5 Torr, or any value within the range of any two of the above values.

[0042] Furthermore, the temperature inside the chamber is 150-250℃. The temperature inside the chamber can be any value within the range of 150℃, 160℃, 170℃, 180℃, 190℃, 200℃, 210℃, 220℃, 230℃, 240℃, 250℃, or any two of the above values.

[0043] Furthermore, the SiH4 flow rate is 0.5-2.0 slm, and the flow rate ratio of H2 to SiH4 is H2:SiH4 = 1-10. The SiH4 flow rate can be 0.5 slm, 1.0 slm, 1.5 slm, 2.0 slm, or any value within any two of the above ranges. The flow rate ratio of H2 to SiH4 can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or any value within any two of the above ranges.

[0044] Furthermore, the flow rate of the dopant gas is 0.5%-5% of the SiH4 flow rate. The flow rate of the dopant gas can be any value within the range of 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5% of the SiH4 flow rate, or any value between any two of the above values.

[0045] Furthermore, the doping gas is either a phosphorus source or a boron source. When the doping gas is a phosphorus source, it is used to form an N-type doped layer; when the doping gas is a boron source, it is used to form a P-type doped layer. The phosphorus source can be PH3 or other phosphorus sources, and the boron source can be B2H6, TMB, BCL3, or other boron sources.

[0046] In one embodiment, during the deposition of the sacrificial layer, the inlet flow rate of ammonia or nitrogen dioxide is 5-10 times that of SiH4. NH3 or NO2 is introduced, with an NH3 or NO2 to SiH4 flow rate ratio of 5-10. The RF power supply is turned on, and the power density is set to 0.05-0.2 W / cm³. 2 This allows for the rapid deposition and formation of the sacrificial layer.

[0047] When depositing a sacrificial layer, the RF power is 5-10 times that when depositing intrinsic silicon and doped silicon layers, enabling rapid deposition of the sacrificial layer.

[0048] In one embodiment, the RF power density is 0.01-0.2 W / cm². 2 The RF power density can be 0.01 W / cm². 2 0.02W / cm 2 0.03W / cm 2 0.04W / cm 2 0.05W / cm 2 0.06W / cm 2 0.07W / cm2 0.08W / cm 2 0.09W / cm 2 0.1W / cm 2 0.11W / cm 2 0.12W / cm 2 0.13W / cm 2 0.14W / cm 2 0.15W / cm 2 0.16W / cm 2 0.17W / cm 2 0.18W / cm 2 0.19W / cm 2 0.2W / cm 2 And any value within the range between any two of the above values.

[0049] In specific implementation, the PECVD single-chamber deposition stack fabrication process of this application embodiment includes:

[0050] Step 1: Loading materials

[0051] The substrate to be deposited is placed on the carrier 4. The transfer mechanism 5 drives the carrier 4 through the Lockload chamber into the process chamber 2, which is in a vacuum state. The gap valve 6 between the Lockload chamber and the process chamber 2 is closed. The carrier 4 is placed on the heating plate 21, which is in a heated state. The lifting mechanism 22 in the process chamber 2 lifts the carrier 4 to the set height.

[0052] Step 2, Layered Deposition

[0053] SiH4 and H2 are introduced into process chamber 2 until the pressure in process chamber 2 reaches the preset pressure. The RF in process chamber 2 is turned on, and 20s-60s are waited for the deposition of the intrinsic silicon layer. Then, doping gas is introduced into the chamber, and 20s-60s are waited for the deposition of the doped silicon layer. After that, the introduction of doping gas is stopped, and the RF is turned off. Then, ammonia or nitrogen dioxide is introduced into process chamber 2 until the pressure in process chamber 2 reaches the preset pressure. The RF is turned on, and 20s-60s are waited for the deposition of the sacrificial layer. After that, the RF is turned off, all gas introduction is stopped, and process chamber 2 is evacuated.

[0054] Step 3, Material feeding

[0055] The lifting mechanism 22 in the process chamber 2 drives the carrier 4 to descend to a preset height, opens the gap valve 6 between the Lockload chamber and the process chamber 2, and the transmission mechanism 5 drives the carrier 4 back to the Lockload chamber through the process chamber 2.

[0056] The following are several specific embodiments illustrating the method for preparing the stacked layers according to the embodiments of this application.

[0057] Example 1

[0058] Heating plate 21 is heated to 150°C. 0.5 slm of SiH4 and 0.5 slm of H2 are introduced into process chamber 2. When the pressure inside process chamber 2 reaches 0.5 Torr, the RF power density of 0.01 W / cm² is turned on. 2 RF power supply: Wait 60 seconds for intrinsic silicon deposition, then introduce 0.0025 slm of PH3 into process chamber 2 and wait 60 seconds for doped silicon layer deposition. Stop introducing PH3 and turn off the RF power supply. Introduce 2.5 slm of NH3 into process chamber 2. When the pressure in process chamber 2 reaches 0.5 Torr, turn on the RF power density of 0.05 W / cm². 2 RF, wait 60s to deposit the sacrificial layer, then turn off RF and stop all gas supply, and evacuate process chamber 2.

[0059] Example 2

[0060] Heating plate 21 is heated to 250°C. 2.0 slm of SiH4 and 20.0 slm of H2 are introduced into process chamber 2. When the pressure inside process chamber 2 reaches 5 Torr, the RF power density of 0.02 W / cm² is turned on. 2 RF power supply: Wait 20 seconds for intrinsic silicon deposition, then introduce 0.1 slm of PH3 into process chamber 2 and wait 20 seconds for doped silicon layer deposition. Stop introducing PH3 and turn off the RF power supply. Introduce 20.0 slm of NH3 into process chamber 2. When the pressure in process chamber 2 reaches 5 Torr, turn on the RF power density of 0.12 W / cm². 2 RF, wait 20s to deposit the sacrificial layer, then turn off RF and stop all gas supply, and evacuate process chamber 2.

[0061] Example 3

[0062] Heating plate 21 is heated to 200℃. 1.0 slm of SiH4 and 5.0 slm of H2 are introduced into process chamber 2. When the pressure inside process chamber 2 reaches 2.5 Torr, the RF power density of 0.02 W / cm² is turned on. 2 RF power supply: Wait 40 seconds for intrinsic silicon deposition, then introduce 0.025 slm of PH3 into process chamber 2 and wait 40 seconds for doped silicon layer deposition. Stop introducing PH3 and turn off the RF power supply. Introduce 8.0 slm of NH3 into process chamber 2. When the pressure in process chamber 2 reaches 2.5 Torr, turn on the RF power density of 0.1 W / cm². 2 RF, wait 40s to deposit the sacrificial layer, then turn off RF and stop all gas supply, and evacuate process chamber 2.

[0063] Example 4

[0064] Heating plate 21 is heated to 180°C. 1.5 slm of SiH4 and 4.5 slm of H2 are introduced into process chamber 2. When the pressure inside process chamber 2 reaches 2.0 Torr, the RF power density of 0.03 W / cm² is turned on. 2 RF power supply: Wait 50 seconds for intrinsic silicon deposition, then introduce 0.075 slm of B2H6 into process chamber 2 and wait 50 seconds for doped silicon layer deposition. Stop introducing B2H6 and turn off the RF power supply. Introduce 8.0 slm of NO2 into process chamber 2. When the pressure in process chamber 2 reaches 2.0 Torr, turn on the RF power density of 0.18 W / cm². 2 RF, wait 50s to deposit the sacrificial layer, then turn off RF and stop all gas supply, and evacuate process chamber 2.

[0065] Example 5

[0066] Heating plate 21 is heated to 220℃. 2.5 slm of SiH4 and 7.5 slm of H2 are introduced into process chamber 2. When the pressure inside process chamber 2 reaches 3.0 Torr, the RF power density of 0.04 W / cm² is turned on. 2 RF power supply is activated, and after a 30-second delay, intrinsic silicon deposition is performed. Then, 0.01 slm of BCL3 is introduced into process chamber 2, and the delay is 30 seconds to deposit a doped silicon layer. The BCL3 introduction is stopped, and the RF power supply is turned off. 17.5 slm of NO2 is then introduced into process chamber 2. Once the pressure in process chamber 2 reaches 3.0 Torr, the RF power density is increased to 0.2 W / cm². 2 RF, wait 30s to deposit the sacrificial layer, then turn off RF and stop all gas supply, and evacuate process chamber 2.

[0067] On the other hand, one embodiment of the present invention provides a back contact battery, wherein the N-region or P-region stack of the back contact battery is fabricated using the above-described fabrication process. The back contact battery may involve forming a P-type doped layer in the N-region, followed by depositing a P-type stack in a PECVD chamber. After the stack deposition is complete, the sacrificial layer of the stack and the N-region stack are removed, and then conductive materials are formed in the P-region and N-region respectively. Alternatively, a P-type doped layer may be formed in the P-region, followed by depositing a stack with an N-type doped silicon layer in the N-region using the above-described fabrication process. Then, the sacrificial layer of the stack and the P-region stack are removed, and then conductive materials are formed in the P-region and N-region respectively.

[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A PECVD single-chamber deposition stack fabrication process, characterized in that, include: Provide a base, which is placed in a chamber; An intrinsic silicon layer, a doped silicon layer, and a sacrificial layer are sequentially deposited on the substrate.

2. The preparation process according to claim 1, characterized in that, The intrinsic silicon layer has a thickness of 5-10 nm; And / or, the thickness of the doped silicon layer is 5-10 nm; And / or, the thickness of the sacrificial layer is 5-50 nm.

3. The preparation process according to claim 1, characterized in that, The preparation process includes: After introducing SiH4 and H2 into the chamber to a preset pressure, the RF is turned on. After depositing the intrinsic silicon of a preset thickness on the substrate, the doping gas is introduced into the chamber. After depositing the doped silicon layer of a preset thickness on the substrate, the RF is turned off and the introduction of the doping gas is stopped. Then, ammonia or nitrogen dioxide is introduced into the chamber to a preset pressure, the RF is turned on, the sacrificial layer is deposited to a preset thickness, the RF power supply is turned off and all reactive gas introduction is stopped.

4. The preparation process according to claim 3, characterized in that, The preset pressure is 0.5-5 Torr; and / or, the chamber is equipped with a heating plate, the temperature of which is 150℃-250℃.

5. The preparation process according to claim 3, characterized in that, The SiH4 flow rate is 0.5-2.0 slm, and the flow rate ratio of H2 to SiH4 is H2:SiH4 = 1-10.

6. The preparation process according to claim 3 or 5, characterized in that, The flow rate of the doped gas is 0.5%-5% of the flow rate of SiH4.

7. The preparation process according to claim 6, characterized in that, The doping gas is a phosphorus source or a boron source.

8. The preparation process according to claim 3, characterized in that, When depositing the sacrificial layer, the inlet flow rate of ammonia or nitrogen dioxide is 5-10 times that of the inlet flow rate of SiH4.

9. The preparation process according to claim 3, characterized in that, The RF power density is 0.01-0.2 W / cm². 2 .

10. A back-contact battery, characterized in that, The N-region or P-region stack of the back contact battery is fabricated using the fabrication process described in any one of claims 1-9.

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