A method for preparing a thin film lithium niobate / lithium tantalate integrated photoelectric detection device

Abstract

This application discloses a method for fabricating a thin-film lithium niobate / lithium tantalate integrated photodetector, comprising: forming a distributed Bragg mirror on one side of a first substrate; depositing a first bonding dielectric layer on the side of the distributed Bragg mirror away from the first substrate; forming a buried electrode on one side of a second substrate; forming a superconducting nanowire on the side of the second substrate where the buried electrode is located; depositing a second bonding dielectric layer on the side of the second substrate where the buried electrode is located; bonding the first and second bonding dielectric layers together, then thinning the second substrate to form a thin film layer; etching the thin film layer to form a waveguide structure, thereby obtaining the integrated photodetector. Thus, by sequentially fabricating the distributed Bragg mirror and the superconducting nanowire on the flat initial substrate surface before bonding, a bottom-up distributed Bragg mirror, superconducting nanowire, and lithium niobate / lithium tantalate conical waveguide structure is obtained.

Description

Technical Field

[0001] This application relates to the field of integrated photonics, specifically to a method for fabricating a thin-film lithium niobate / lithium tantalate integrated photodetector. Background Technology

[0002] Thin-film lithium niobate / lithium tantalate materials have become an ideal platform for on-chip quantum integrated circuits due to their excellent electro-optic modulation efficiency, wide transparency window, and high second-order nonlinear coefficient. Superconducting nanowire single-photon detectors, with their high detection efficiency, low dark count, and excellent temporal resolution, are the preferred solution for on-chip single-photon detection. Integrating these two materials monolithically to realize a fully functional quantum chip incorporating light source, modulation, and detection is an important development direction in this field. To improve on-chip detection efficiency, a vertical stacked structure has been proposed: consisting of a distributed Bragg reflector, superconducting nanowires, and a lithium niobate / lithium tantalate tapered waveguide from bottom to top. In this structure, the distributed Bragg reflector reflects transmitted photons back to the nanowires for secondary absorption, and the tapered waveguide compresses the light field losslessly to the nanoscale; the two work synergistically to significantly enhance the interaction efficiency between light and the superconducting material.

[0003] However, existing processes face numerous challenges in fabricating this structure. One approach is the waveguide-then-detector route, which involves etching a ridged waveguide and tapered coupling region onto a lithium niobate / lithium tantalate film, followed by the deposition of superconducting nanowires on the surface. In this route, surface roughness after waveguide etching and the redeposition of contaminants can affect the uniformity of the superconducting nanowires. Furthermore, the superconducting nanowires require high-temperature annealing above 300°C to optimize the film's lattice order and critical temperature. If annealing is performed after waveguide fabrication, the waveguide morphology and electro-optic properties may undergo thermal degradation; if annealing is performed before waveguide fabrication, high-energy ion bombardment during dry etching of the waveguide may damage the already formed superconducting nanowires. Another approach is a hybrid route: detector-then-transfer integration. This involves pre-fabricating the superconducting nanowire detector on a separate substrate and then transferring it onto the etched waveguide using micro-transfer or pick-and-place techniques. This approach avoids the impact of high-temperature detector processing on the waveguide. However, inserting a distributed Bragg reflector multilayer film between the waveguide and the detector significantly increases the complexity and difficulty of the transfer interface. Most existing transfer integration schemes abandon the distributed Bragg reflector, resulting in the detector relying solely on single-pass absorption, which limits efficiency. During the transfer bonding process, nanoscale air gaps or organic contaminants can easily remain between the nanowire and the waveguide surface, affecting the stability and consistency of evanescent wave coupling. At the same time, single-device-level micro-transfer printing processes still face challenges in terms of alignment accuracy and wafer-level mass production scalability.

[0004] To address the aforementioned issues, this application provides a method for fabricating a thin-film lithium niobate / lithium tantalate integrated photodetector device. This method employs a reverse process sequence, first the detector, then the waveguide structure, to achieve a bottom-up distributed Bragg reflector, superconducting nanowires, and a lithium niobate / lithium tantalate conical waveguide structure, thus resolving the thermal budget conflict problem.

[0005] It should be noted that the above statements are only used to provide background information related to this application and do not necessarily constitute prior art. Summary of the Invention

[0006] In a first aspect of this application, a method for fabricating an integrated photodetector device is proposed, comprising: A first refractive index layer and a second refractive index layer are alternately deposited on one side of a first substrate to form a distributed Bragg reflector on one side of the first substrate to obtain a first intermediate structure. A first bonding dielectric layer is deposited on one side of the first intermediate structure where the distributed Bragg mirror is disposed, to obtain a first pre-bonded substrate; An electrode trench is formed on one side of the second substrate, and an electrode layer and an adhesion layer are sequentially deposited in the electrode trench to form a buried electrode on one side of the second substrate to obtain a second intermediate structure. A superconducting material is deposited on one side of the second intermediate structure where a buried electrode is disposed, and the superconducting material is subjected to a first photolithography etching process and an annealing process in sequence to form a superconducting nanowire on one side of the second substrate. At least a portion of the superconducting nanowire is in contact with the buried electrode to obtain a third intermediate structure. A second bonding dielectric layer is deposited on one side of the third intermediate structure where the superconducting nanowire is disposed to obtain a second pre-bonded substrate; The first bonding dielectric layer of the first pre-bonded substrate and the second bonding dielectric layer of the second pre-bonded substrate are bonded together so that the orthographic projection of the superconducting nanowire on the first substrate is located within the orthographic projection of the distributed Bragg mirror on the first substrate, so as to obtain a bonding structure. The side of the second substrate of the bonding structure away from the superconducting nanowire is thinned to form a thin film layer on one side of the second bonding dielectric layer to obtain a fourth intermediate structure. The thin film layer in the fourth intermediate structure is subjected to a second photolithographic etching process to form a waveguide structure, thereby obtaining the integrated photodetector device.

[0007] Therefore, by sequentially fabricating both the distributed Bragg reflector and the superconducting nanowires on the flat initial substrate surface before bonding, the device thin film fracture and interface roughness problems caused by waveguide structure steps are reduced. Simultaneously, the high-temperature annealing of the superconducting nanowires is completed independently before the second substrate thinning and waveguide structure etching, ensuring the waveguide structure and bonding interface remain in a low-temperature environment throughout, reducing thermal budget conflicts. During waveguide structure etching, the superconducting nanowires are protected by the second bonding dielectric layer and the thin film layer, reducing the risk of potential damage to the superconducting nanowires caused by dry etching of the waveguide structure.

[0008] In some embodiments, the gradient coupling cone region of the waveguide structure is in contact with the superconducting nanowire.

[0009] In some embodiments, the distributed Bragg reflector includes multiple stacked pairs of refractive index layers, each pair comprising a first refractive index layer and a second refractive index layer, wherein the refractive index of the second refractive index layer is greater than that of the first refractive index layer, and refractive index layers with the same refractive index are spaced apart; optionally, the number of refractive index layer pairs is 5 to 8. Thus, by alternately depositing the first and second refractive index layers, the constructive interference conditions required for high reflectivity are achieved, thereby realizing the high reflectivity of the distributed Bragg reflector.

[0010] In some embodiments, the buried electrode includes a stacked electrode layer and an adhesive layer, wherein the electrode layer is located on the side of the adhesive layer away from the first bonding dielectric layer, wherein the thickness of the buried electrode is 105nm-210nm; and / or, the thickness of the electrode layer in the buried electrode is 100nm-200nm; and / or, the thickness of the adhesive layer in the buried electrode is 5nm-10nm.

[0011] Therefore, by setting an electrode layer and an adhesion layer in the buried electrode, the buried electrode can be designed as a self-stopping layer for thinning, stopping thinning when it reaches the location of the buried electrode, allowing for flexible control of the thin film thickness. The thinned and exposed buried electrode directly serves as an alignment mark for waveguide structure photolithography, enabling precise alignment of the waveguide structure with the superconducting nanowires and reducing the cumulative alignment error from multiple photolithography steps.

[0012] In some embodiments, the target wavelength of the distributed Bragg reflector is 635nm-850nm or 1520nm-1630nm.

[0013] Therefore, by defining the target wavelength of the distributed Bragg reflector, the physical thickness of each refractive index layer of the distributed Bragg reflector can be designed to make the reflected light from each interface tend to be phase-consistent at the target wavelength, thereby obtaining a higher reflectivity.

[0014] In some embodiments, the thickness of the superconducting nanowire is 5 nm-10 nm; and / or, the thicknesses of the first bonding dielectric layer and the second bonding dielectric layer are independently 100 nm-1000 nm; and / or, the thickness of the thin film layer is 200 nm-1000 nm; and / or, the optical thickness of the monolayer first refractive index layer is one-quarter of the target wavelength; and / or, The optical thickness of the monolayer second refractive index layer is one-quarter of the target wavelength; and / or, the thickness of the first substrate is 300µm-500µm.

[0015] In some embodiments, the electrode layer comprises one or more of platinum and gold; and / or, the adhesion layer comprises one or more of titanium and chromium; and / or, the superconducting nanowire is made of one or more of niobium nitride and niobium titanium nitride; and / or, the thin film layer is made of one or more of lithium niobate and lithium tantalate; and / or, the materials of the first bonding dielectric layer and the second bonding dielectric layer have the same chemical composition; and / or, the material of the first refractive index layer comprises one or more of silicon dioxide and aluminum oxide; and / or, the material of the second refractive index layer comprises one or more of tantalum pentoxide and silicon nitride; and / or, the material of the first substrate comprises one or more of silicon and aluminum oxide.

[0016] Therefore, by expanding the types of materials used in each functional layer of waveguide-integrated photodetectors, the performance limitations of single-material systems can be effectively overcome, while also expanding the application range of waveguide-integrated photodetectors.

[0017] In some embodiments, the annealing temperature is greater than 300°C, and the annealing time is 1 min to 30 min.

[0018] Therefore, by subjecting superconducting nanowires to high-temperature annealing, the lattice order and critical temperature of superconducting thin film materials can be optimized.

[0019] In some embodiments, the bonding treatment includes one or more of plasma-activated bonding and resin-assisted bonding, wherein the temperature of the plasma-activated bonding annealing treatment is 150℃-350℃, and the annealing time is 1h-4h.

[0020] In a second aspect of this application, an integrated photodetector device fabricated using the aforementioned method is provided, comprising: a first bonding dielectric layer located on the side of the distributed Bragg reflector away from the first substrate; a second bonding dielectric layer located on the side of the first bonding dielectric layer away from the distributed Bragg reflector; a thin film layer located on the side of the second bonding dielectric layer away from the first bonding dielectric layer, the thin film layer comprising: a waveguide structure located within the thin film layer; a superconducting nanowire embedded within the second bonding dielectric layer and located on the side of the second bonding dielectric layer away from the first bonding dielectric layer; a buried electrode embedded within the thin film layer, located on the side of the second bonding dielectric layer away from the first bonding dielectric layer, and in contact with the superconducting nanowire; the waveguide structure in contact with the superconducting nanowire, the waveguide structure and the buried electrode being located in the same layer and spaced apart.

[0021] Thus, a bottom-up integration of a distributed Bragg reflector, superconducting nanowires, and waveguide structure is achieved through reverse engineering. Light entering the waveguide structure is confined and guided to the vicinity of the superconducting nanowires, where the nanowires absorb photons to generate electrical pulses, enabling single-photon detection. Unabsorbed residual light is reflected back to the waveguide structure by the distributed Bragg reflector below, and is absorbed again by the superconducting nanowires, significantly improving the overall detection efficiency. The first substrate provides physical support for the distributed Bragg reflector. Bonding of the distributed Bragg reflector and superconducting nanowires is achieved through the placement of a first and second bonding dielectric layer. Buried electrodes subsequently contact the pads, connecting the photodetector to external circuitry, thereby enabling efficient detection of optical signals. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart illustrating the fabrication of the integrated photodetector device in this application.

[0023] Figure 2 This is a flowchart illustrating the fabrication of the integrated photodetector device in this application.

[0024] Figure 3 This is a structural diagram of the integrated photodetector device in this application.

[0025] Explanation of reference numerals in the attached figures: 1-Waveguide structure, 2-Buried electrode, 3-Second bonding dielectric layer, 4-First bonding dielectric layer, 5-Distributed Bragg mirror, 6-First substrate, 7-Thin film layer, 8-Superconducting nanowire, 9-Second substrate, 10-Electrode groove. Detailed Implementation

[0026] The embodiments of this application are described in detail below, with examples of these embodiments shown in the accompanying drawings. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repetitive descriptions of practically identical structures may be omitted. This is to avoid unnecessarily lengthy descriptions and to facilitate understanding by those skilled in the art. Furthermore, the accompanying drawings and the following description are provided to enable those skilled in the art to fully understand this application and are not intended to limit the subject matter of the claims.

[0027] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit this application; unless otherwise stated, the values ​​of the parameters mentioned in this application can be measured using various measurement methods commonly used in the art (e.g., they can be tested according to the methods given in the embodiments of this application).

[0028] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are open-ended expressions, meaning they include what is specified in this application but do not exclude other aspects.

[0029] In the description of this application, all figures disclosed herein, whether or not the words "approximately" or "about" are used, are approximate values. Each figure may vary by less than 10% or by a difference that is considered reasonable by one of the art, such as 1%, 2%, 3%, 4%, or 5%.

[0030] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0031] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0032] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. "First feature" and "second feature" may include one or more of the indicated feature.

[0033] In the description of this application, "multiple" means two or more.

[0034] In the description of this application, "A and / or B" can include any of the cases of A alone, B alone, or A and B, where A and B are merely examples and can be any technical feature connected by "and / or" in this application.

[0035] In the description of this application, "same chemical composition" should be interpreted broadly, that is, the main components of the two have the same chemical composition, or the two have substantially the same chemical composition, but may have errors or impurities within the acceptable range that can be understood by those skilled in the art.

[0036] In this application, the order in which the steps are written does not imply a strict execution order and does not limit the implementation process. The specific execution order of each step should be determined by its function and possible internal logic. Unless otherwise specified, all steps in this application can be performed sequentially or randomly, preferably sequentially. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, if the method may also include step (c), it means that step (c) can be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0037] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.

[0038] Unless otherwise specified, all technical features and optional technical features of this application may be combined to form new technical solutions.

[0039] Integrated optoelectronic detectors represent a significant development direction in integrated photonics. These detectors involve vertically stacked structures, including distributed Bragg mirrors, superconducting nanowires, and waveguide structures. In fabrication, if the waveguide structure is fabricated first, followed by the deposition of superconducting nanowires on its surface, the surface roughness after etching the waveguide structure and the redeposition of contaminants can affect the uniformity of the superconducting nanowires. Furthermore, the high-temperature annealing step of the superconducting nanowires can cause thermal degradation of the waveguide structure. Conversely, if the superconducting nanowires are fabricated first, followed by etching the waveguide structure, the completed superconducting nanowires are susceptible to damage from high-energy ion bombardment during dry etching of the waveguide structure. A more suitable approach is to pre-fabricate the superconducting nanowires on a separate substrate and then transfer them onto the etched waveguide structure using micro-transfer or pick-and-place techniques. While avoiding the impact of high-temperature annealing of superconducting nanowires on the waveguide structure, inserting a multilayer film of distributed Bragg reflectors between the waveguide structure and the superconducting nanowires significantly increases the complexity of the transfer interface and the difficulty of the process. Abandoning the distributed Bragg reflectors would cause the superconducting nanowires to rely solely on single-pass absorption, which would limit efficiency. During the transfer and bonding process, nanoscale air gaps or organic contaminants are easily left between the superconducting nanowires and the surface of the waveguide structure, affecting the stability and consistency of evanescent wave coupling. At the same time, the micro-transfer process at the single-device level still faces challenges in terms of alignment accuracy and wafer-level mass production scalability.

[0040] In this application, an integrated photodetector device with a bottom-up structure of distributed Bragg reflector, superconducting nanowires, and waveguide is fabricated by employing a reverse process sequence: first, the distributed Bragg reflector and superconducting nanowires are fabricated independently; then, the waveguide structure is etched after bonding. This reduces the thin film fracture and interface roughness issues caused by waveguide structure steps. Furthermore, the waveguide structure and bonding interface are kept in a low-temperature environment throughout the process, resolving thermal budget conflicts. The superconducting nanowires are well protected by the bonding dielectric layer and thin film layer during waveguide structure etching, reducing potential damage to the superconducting nanowires caused by dry etching of the waveguide structure.

[0041] In a first aspect of this application, a method for fabricating an integrated photodetector device is proposed, see [link to relevant documentation]. Figure 1 and Figure 2 ,include: S10: A first refractive index layer and a second refractive index layer are alternately deposited on one side of the first substrate to form a distributed Bragg mirror on one side of the first substrate to obtain a first intermediate structure.

[0042] In some embodiments, see Figure 1 In step S10, a first refractive index layer and a second refractive index layer are alternately deposited on one side of the first substrate 6 to form a distributed Bragg reflector 5 on one side of the first substrate to obtain a first intermediate structure.

[0043] In some embodiments, the thickness of the first substrate is 300µm-500µm. As an example, the thickness of the first substrate can be any one of 300µm, 322µm, 344µm, 367µm, 389µm, 411µm, 433µm, 456µm, 478µm, and 500µm, or a range between any two.

[0044] In some embodiments, the material of the first substrate includes one or more of silicon and aluminum oxide. Thus, by selecting a material with high mechanical rigidity as the first substrate, a good supporting substrate is provided for the photodetector device.

[0045] In some embodiments, the distributed Bragg reflector includes multiple stacked pairs of refractive index layers, each pair comprising a first refractive index layer and a second refractive index layer, wherein the refractive index of the second refractive index layer is greater than that of the first refractive index layer, and refractive index layers with the same refractive index are spaced apart; optionally, the number of refractive index layer pairs is 5 to 8. Thus, by alternately depositing the first and second refractive index layers, the constructive interference conditions required for high reflectivity are achieved, thereby realizing the high reflectivity of the distributed Bragg reflector.

[0046] As an example, the number of refractive index layer pairs can be 5, 6, 7, or 8.

[0047] In some embodiments, the optical thickness of the monolayer first refractive index layer is one-quarter of the target wavelength, and the optical thickness of the monolayer second refractive index layer is one-quarter of the target wavelength.

[0048] Therefore, by determining the optical thickness of the refractive index layer, the physical thickness of the refractive index layer can be further designed so that the reflected light generated at the interface of each refractive index layer tends to be in phase at the target wavelength, and a higher reflectivity can be obtained after superposition.

[0049] In some embodiments, the target wavelength of the distributed Bragg reflector is 635nm-850nm or 1520nm-1630nm.

[0050] Therefore, by defining the target wavelength of the distributed Bragg reflector, the physical thickness of each refractive index layer of the distributed Bragg reflector can be designed to make the reflected light from each interface tend to be phase-consistent at the target wavelength, thereby obtaining a higher reflectivity.

[0051] As an example, the target wavelength of the distributed Bragg reflector can be any one of 635nm, 659nm, 683nm, 707nm, 731nm, 755nm, 779nm, 803nm, 827nm, and 850nm, or a range between any two; the target wavelength of the distributed Bragg reflector can be any one of 1520nm, 1532nm, 1544nm, 1557nm, 1569nm, 1581nm, 1593nm, 1606nm, 1618nm, and 1630nm, or a range between any two.

[0052] In some embodiments, the material of the first refractive index layer includes one or more of silicon dioxide and aluminum oxide, and the material of the second refractive index layer includes one or more of tantalum pentoxide and silicon nitride. Thus, by utilizing the difference in refractive indices of the two refractive index layer materials, a refractive index layer pair is constructed, achieving the effects of tightly confining the optical field, reducing transmission loss, and improving photon detection efficiency.

[0053] S20: A first bonding dielectric layer is deposited on the side of the first intermediate structure where the distributed Bragg mirror is disposed to obtain a first pre-bonded substrate.

[0054] In some embodiments, see Figure 1 In step S20, a first bonding medium layer 4 is deposited on the side of the first intermediate structure where the distributed Bragg reflector 5 is disposed, to obtain a first pre-bonded substrate.

[0055] In some embodiments, the material of the first bonding dielectric layer includes one or more of silicon dioxide and benzocyclobutene. Thus, the excellent insulation properties, extremely high surface smoothness, and good chemical stability of the aforementioned materials are utilized to meet the requirements of the bonding dielectric layer.

[0056] In some embodiments, the thickness of the first bonding dielectric layer is 100nm-1000nm.

[0057] As an example, the thickness of the second bonding dielectric layer can be any one of 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, and 1000nm, or a range between any two.

[0058] S30: An electrode trench is formed on one side of the second substrate, and an electrode layer and an adhesion layer are sequentially deposited in the electrode trench to form a buried electrode on one side of the second substrate to obtain a second intermediate structure.

[0059] In some embodiments, see Figure 1 In step S30, an electrode trench 10 is formed on one side of the second substrate 9, and an electrode layer and an adhesion layer are sequentially deposited in the electrode trench to form a buried electrode 2 on one side of the second substrate to obtain a second intermediate structure.

[0060] In some embodiments, the thickness of the second substrate is 300µm-500µm.

[0061] As an example, the thickness of the second substrate can be any one of the following values ​​or a range between any two: 300µm, 310µm, 320µm, 330µm, 340µm, 350µm, 360µm, 370µm, 380µm, 390µm, 400µm, 410µm, 420µm, 430µm, 440µm, 450µm, 460µm, 470µm, 480µm, 490µm, and 500µm.

[0062] In some embodiments, the depth of the electrode groove is greater than or equal to the thickness of the thin film layer.

[0063] In some embodiments, the buried electrode includes a stacked electrode layer and an adhesive layer, wherein the electrode layer is located on the side of the adhesive layer away from the first bonding dielectric layer.

[0064] Therefore, by setting an electrode layer and an adhesion layer in the buried electrode, the buried electrode can be designed as a thinning self-stopping layer, stopping thinning when it reaches the location of the buried electrode, allowing for flexible control of the thin film thickness. The thinned and exposed buried electrode directly serves as an alignment mark for waveguide structure photolithography, enabling precise alignment of the waveguide structure with the superconducting nanowires and reducing the cumulative alignment error from multiple photolithography steps.

[0065] In some embodiments, the thickness of the buried electrode is 200nm-1000nm. As an example, the thickness of the buried electrode can be any one of 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, and 1000nm, or a range between any two.

[0066] In some embodiments, the thickness of the electrode layer in the buried electrode is 195nm-990nm. As an example, the thickness of the electrode layer in the buried electrode can be any one of 195nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, and 990nm, or a range between any two.

[0067] In some embodiments, the thickness of the adhesion layer in the buried electrode is 5 nm to 10 nm. As an example, the thickness of the adhesion layer in the buried electrode can be any one of 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, and 10 nm, or a range between any two.

[0068] In some embodiments, after the electrode layer and the adhesion layer are sequentially deposited in the electrode trench, a chemical mechanical polishing (CMP) or stripping process is further included. Thus, the excess electrode layer material on the surface of the second substrate, excluding the electrode trench area, is removed by the CMP or stripping process, leaving only the buried electrode filling the electrode trench, and making the top surface of the buried electrode flush with the surface of the second substrate.

[0069] In some embodiments, the electrode layer comprises one or more of platinum and gold. In some embodiments, the adhesion layer comprises one or more of titanium and chromium. Thus, by selecting the above material combination as the buried electrode, and utilizing the characteristic that the hardness of the above materials is greater than the hardness of the thin film layer, it can act as a mechanically self-stopping layer during the thinning process, thereby controlling the film thickness.

[0070] S40: Deposit superconducting material on one side of the second intermediate structure where the buried electrode is disposed, and perform a first photolithography etching process and an annealing process on the superconducting material in sequence to form a superconducting nanowire on one side of the second substrate, wherein at least a portion of the superconducting nanowire is in contact with the buried electrode to obtain a third intermediate structure.

[0071] In some embodiments, see Figure 1 In step S40, a superconducting material is deposited on the side of the second intermediate structure where the buried electrode 2 is disposed, and the superconducting material is subjected to a first photolithography etching process and an annealing process in sequence to form a superconducting nanowire 8 on one side of the second substrate. At least a portion of the superconducting nanowire is in contact with the buried electrode to obtain a third intermediate structure.

[0072] In some embodiments, the annealing temperature is greater than 300°C.

[0073] As an example, the annealing temperature can be any one of 301℃, 400℃, 500℃, 600℃, 700℃, 800℃, or 900℃, or a range between any two.

[0074] In some embodiments, the annealing process takes 1-30 minutes.

[0075] As an example, the annealing time can be any one of the following values ​​or a range between any two: 1 min, 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min, 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, 16 min, 17 min, 18 min, 19 min, 20 min, 21 min, 22 min, 23 min, 24 min, 25 min, 26 min, 27 min, 28 min, 29 min, and 30 min.

[0076] Therefore, by controlling the temperature and time of high-temperature annealing of superconducting nanowires, the lattice order and critical temperature of superconducting materials can be optimized.

[0077] In some embodiments, the thickness of the superconducting nanowire is 5nm-10nm. As an example, the thickness of the superconducting nanowire can be any one of 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm, or a range between any two.

[0078] In some embodiments, the width of the superconducting nanowire is 70nm-120nm. As an example, the width of the superconducting nanowire can be any one of 70nm, 80nm, 90nm, 100nm, 110nm, or 120nm, or a range between any two.

[0079] In some embodiments, the duty cycle of the superconducting nanowire is 30%-70%. As an example, the duty cycle of the superconducting nanowire can be any one of 30%, 40%, 50%, 60%, 70%, or any range between two values.

[0080] In some embodiments, the coverage length of the superconducting nanowire along the light propagation direction is 15µm-30µm. As an example, the coverage length of the superconducting nanowire along the light propagation direction can be any one of 15µm, 16µm, 17µm, 18µm, 19µm, 20µm, 21µm, 22µm, 23µm, 24µm, 25µm, 26µm, 27µm, 28µm, 29µm, or 30µm, or a range between any two.

[0081] In some embodiments, the superconducting nanowires are made of one or more of niobium nitride and titanium niobium nitride. Therefore, by using these materials as the superconducting nanowires, and leveraging their superior photon trapping and counting performance and the ability to finely adjust superconducting electrical parameters, these materials are well-suited for the field of waveguide-integrated optoelectronic detection.

[0082] S50: A second bonding medium layer is deposited on one side of the third intermediate structure where the superconducting nanowire is disposed, to obtain a second pre-bonded substrate.

[0083] In some embodiments, see Figure 1 In step S50, a second bonding medium layer 3 is deposited on one side of the third intermediate structure where the superconducting nanowire 8 is disposed, to obtain a second pre-bonded substrate.

[0084] In some embodiments, the material of the second bonding dielectric layer includes one or more of silicon dioxide and benzocyclobutene. Thus, by utilizing the excellent insulation properties, extremely high surface smoothness, and good chemical stability of the aforementioned materials, the requirements for the bonding dielectric layer are met.

[0085] In some embodiments, the thickness of the second bonding dielectric layer is 100nm-1000nm.

[0086] As an example, the thickness of the second bonding dielectric layer can be any one of 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, and 1000nm, or a range between any two.

[0087] S60: The first bonding dielectric layer of the first pre-bonded substrate and the second bonding dielectric layer of the second pre-bonded substrate are bonded together so that the orthographic projection of the superconducting nanowire on the first substrate is located within the orthographic projection of the distributed Bragg mirror on the first substrate, thereby obtaining a bonding structure.

[0088] In some embodiments, see Figure 1In step S60, the first bonding dielectric layer 4 of the first pre-bonded substrate and the second bonding dielectric layer 3 of the second pre-bonded substrate are bonded together so that the orthographic projection of the superconducting nanowire 8 on the first substrate 6 is located within the orthographic projection of the distributed Bragg mirror 5 on the first substrate 6, thereby obtaining a bonding structure.

[0089] In some embodiments, the bonding process is further included before polishing, and the root mean square surface roughness values ​​of the first bonding dielectric layer and the second bonding dielectric layer after polishing are each independently less than 0.5 nm.

[0090] As an example, the root mean square values ​​of the surface roughness of the first bonding dielectric layer and the second bonding dielectric layer can be independently any one of 0.1nm, 0.2nm, 0.3nm, 0.4nm, and 0.5nm, or any range between the two.

[0091] In some embodiments, the bonding process includes one or more of plasma-activated bonding and resin-assisted bonding. Thus, superconducting nanowires and distributed Bragg mirrors can be effectively integrated through the bonding process.

[0092] In some embodiments, the plasma-activated bonding includes a bonding annealing process. This bonding annealing process makes the bond between the first and second bonding dielectric layers stronger and more permanent.

[0093] In some embodiments, the bonding annealing temperature is 150°C-350°C.

[0094] As an example, the bonding annealing temperature can be any one of 150℃, 160℃, 170℃, 180℃, 190℃, 200℃, 210℃, 220℃, 230℃, 240℃, 250℃, 260℃, 270℃, 280℃, 290℃, 300℃, 310℃, 320℃, 330℃, 340℃, or 350℃, or a range between any two.

[0095] In some embodiments, the bonding annealing process takes 1-4 hours.

[0096] As an example, the bonding annealing time can be any one of 1h, 2h, 3h, or 4h, or a range between any two.

[0097] Therefore, by controlling the temperature and time of the bonding annealing process, the bonding strength of the bonding interface is effectively improved, and delamination and cracking during processing are reduced.

[0098] S70: Thinning is performed on the side of the second substrate of the bonding structure away from the superconducting nanowire to form a thin film layer on one side of the second bonding dielectric layer to obtain a fourth intermediate structure.

[0099] In some embodiments, see Figure 1 In step S70, the side of the second substrate 9 of the bonding structure away from the superconducting nanowire 8 is thinned to form a thin film layer 7 on one side of the second bonding dielectric layer to obtain a fourth intermediate structure.

[0100] In some embodiments, the thinning process includes grinding thinning and polishing thinning.

[0101] Therefore, by thinning the second substrate to expose the electrode layer of the buried electrode, the buried electrode becomes a conductive via penetrating the second substrate. The buried electrode can then serve as a photolithographic alignment marker, ensuring that the gradient coupling cone region in the optical waveguide pattern is precisely positioned above the superconducting nanowire. Simultaneously, the physical thinning method, rather than ion implantation and stripping, allows the thin film to retain the intrinsic electro-optic coefficient and low optical loss characteristics of the bulk material. The entire process, based on wafer-level bonding, thinning, and photolithography, has the potential for large-scale, low-cost mass production.

[0102] In some embodiments, the thickness of the thin film layer is 200nm-1000nm. As an example, the thickness of the thin film layer can be any one of 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, and 1000nm, or a range between any two.

[0103] In some embodiments, the material of the thin film layer includes one or more of lithium niobate and lithium tantalate. Thus, by utilizing the high electro-optic modulation efficiency, wide transparency window, and high second-order nonlinear coefficient of the above materials, an ideal platform is provided for on-chip quantum integrated circuits.

[0104] S80: Perform a second photolithographic etching process on the thin film layer in the fourth intermediate structure to form a waveguide structure and obtain the integrated photodetector device.

[0105] In some embodiments, see Figure 1 In step S80, the thin film layer 7 in the fourth intermediate structure is subjected to a second photolithography etching process to form the waveguide structure 1, thereby obtaining the photodetector device.

[0106] In some embodiments, the optical waveguide pattern is placed in the region between two buried electrodes in the second photolithography etching process, and the second photolithography etching process includes a dry etching process.

[0107] Thus, through a second photolithography etching process, the thin film material in the region between the two buried electrodes is etched through, forming an air-clad strip waveguide structure, while the thin film material around the two buried electrodes is preserved. The high-temperature annealing of the superconducting nanowires is performed independently before the second substrate thinning and waveguide structure etching. The waveguide structure and bonding interface remain in a low-temperature environment throughout, reducing thermal budget conflicts. During waveguide structure etching, the superconducting nanowires are completely protected by the second bonding dielectric layer and the thin film layer, reducing the risk of potential damage to the superconducting nanowires caused by dry etching of the waveguide structure. The entire process is based on wafer-level bonding, thinning, and photolithography technologies, possessing the potential for large-scale, low-cost mass production.

[0108] In some embodiments, the gradient coupling cone region of the waveguide structure is in contact with the superconducting nanowire.

[0109] Therefore, by contacting the gradient coupling cone region with the superconducting nanowire, the compressed subwavelength light field is confined within the absorption region of the superconducting nanowire, thereby reducing photon leakage and achieving a photon capture efficiency close to 100%.

[0110] In some embodiments, the gradient coupling cone region of the waveguide structure is a strip waveguide structure. Thus, by forming a strip waveguide structure, the confinement of the optical field in the vertical direction is enhanced.

[0111] In some embodiments, the initial width of the gradient coupling cone region of the waveguide structure is 1µm-2µm. As an example, the initial width of the gradient coupling cone region of the waveguide structure can be any one of 1µm, 1.1µm, 1.2µm, 1.3µm, 1.4µm, 1.5µm, 1.6µm, 1.7µm, 1.8µm, 1.9µm, or 2µm, or a range between any two.

[0112] In some embodiments, the final width of the gradient coupling cone region of the waveguide structure is 200nm-300nm. As an example, the final width of the gradient coupling cone region of the waveguide structure can be any one of 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, and 300nm, or a range between any two.

[0113] In some embodiments, the length of the contraction segment of the gradient coupling cone region of the waveguide structure is not less than 10µm. As an example, the length of the contraction segment of the gradient coupling cone region of the waveguide structure can be any one of 10µm, 20µm, 30µm, 40µm, 50µm, 60µm, 70µm, 80µm, 90µm, and 100µm, or a range between any two.

[0114] In some embodiments, the superconducting nanowires are arranged in a meandering or comb-like pattern directly below the gradient coupling cone region.

[0115] In a second aspect of this application, an integrated photodetector device prepared using the aforementioned method is proposed, see [link to relevant documentation]. Figure 3 The system includes: a first substrate 6; a distributed Bragg reflector 5 located on one side of the first substrate; a first bonding dielectric layer 4 located on the side of the distributed Bragg reflector away from the first substrate; a second bonding dielectric layer 3 located on the side of the first bonding dielectric layer away from the distributed Bragg reflector; and a thin film layer 7 located on the side of the second bonding dielectric layer away from the first bonding dielectric layer. The thin film layer includes: a waveguide structure 1 located within the thin film layer; a superconducting nanowire 8 embedded in the second bonding dielectric layer and located on the side of the second bonding dielectric layer away from the first bonding dielectric layer; and a buried electrode 2 embedded in the thin film layer, located on the side of the second bonding dielectric layer away from the first bonding dielectric layer, and in contact with the superconducting nanowire; the waveguide structure is in contact with the superconducting nanowire, and the waveguide structure and the buried electrode are located in the same layer and spaced apart.

[0116] Thus, a bottom-up integration of a distributed Bragg reflector, superconducting nanowires, and waveguide structure is achieved through reverse engineering. Light entering the waveguide structure is confined and guided to the vicinity of the superconducting nanowires, where the nanowires absorb photons to generate electrical pulses, enabling single-photon detection. Unabsorbed residual light is reflected back to the waveguide structure by the distributed Bragg reflector below, and is absorbed again by the superconducting nanowires, significantly improving the overall detection efficiency. The first substrate provides physical support for the distributed Bragg reflector. Bonding of the distributed Bragg reflector and superconducting nanowires is achieved through the placement of a first and second bonding dielectric layer. Buried electrodes subsequently contact the pads, connecting the photodetector to external circuitry, thereby enabling efficient detection of optical signals.

[0117] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0118] The following specific embodiments illustrate the solution of this application. It should be noted that these embodiments are for illustrative purposes only and should not be considered as limiting the scope of this application. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Reagents or instruments whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0119] Example 1 The distributed Bragg reflector has a target operating wavelength of 1550 nm and a target thin film thickness of 600 nm.

[0120] (1) Fabrication of distributed Bragg mirrors: A double-sided polished silicon wafer was selected as the first substrate. Ion-assisted reactive magnetron sputtering was used to alternately deposit silicon dioxide and silicon nitride thin films on the silicon wafer surface. Each layer had an optical thickness of one-quarter of the target wavelength, with the silicon dioxide layer approximately 270 nm and the silicon nitride layer approximately 195 nm. Six cycles were deposited to form a distributed Bragg reflector, achieving a reflectivity greater than 99% at a wavelength of 1550 nm. A 200 nm thick silicon dioxide layer was deposited on the surface of the distributed Bragg reflector as the first bonding dielectric layer, and the surface roughness was reduced to a root mean square value of 0.3 nm using chemical mechanical polishing.

[0121] (2) Fabrication of buried electrode: A 500µm thick X-cut lithium niobate wafer was selected as the second substrate. Two electrode trenches with a depth of 800nm ​​were formed on the wafer surface using photolithography and dry etching. A 595nm thick platinum electrode layer and a 5nm thick titanium adhesion layer were sequentially deposited on the wafer surface and within the electrode trenches using magnetron sputtering to form a titanium / platinum composite buried electrode. Excess metal outside the electrode trench area on the wafer surface was removed by chemical mechanical polishing, leaving only the titanium / platinum composite buried electrode filling the electrode trenches, and polished until the top surface of the electrode was flush with the lithium niobate surface.

[0122] (3) Fabrication of superconducting nanowires: A 6 nm thick niobium nitride superconducting film was deposited on the surface of a titanium / platinum composite buried electrode and lithium niobate using reactive magnetron sputtering. A meandering nanowire pattern with a linewidth of 100 nm and a coverage length of 20 µm was defined using electron beam lithography and reactive ion etching, with the two ends of the nanowires overlapping and contacting the two buried electrodes below. The sample was then subjected to high-temperature annealing at 850 °C for 30 minutes in a vacuum environment to optimize the lattice order and superconducting critical temperature of the niobium nitride film. After annealing, a 200 nm thick silicon dioxide layer was deposited as a second bonding dielectric layer using plasma-enhanced chemical vapor deposition, and the surface roughness was reduced to a root mean square value of 0.3 nm by chemical mechanical polishing.

[0123] (4) Bonding and thinning processes: The second substrate was flipped so that the side with the superconducting nanowires faced the distributed Bragg reflector of the first substrate. High-precision alignment was performed in a bonding machine to align the nanowire region with the central region of the reflector. The silicon dioxide surfaces of both wafers were activated by oxygen plasma, bonded at room temperature, and then annealed at 250°C for 2 hours to form a covalent bonding interface. The back side of the second substrate of the bonded assembly was mechanically ground to reduce the lithium niobate thickness from 500µm to approximately 5µm. Subsequently, chemical mechanical polishing was used to further thin the film; the polishing slurry had a high selectivity for both lithium niobate and platinum. Polishing was stopped when the bottom surfaces of the platinum layers of both buried electrodes were completely exposed. At this point, the remaining lithium niobate film thickness was approximately 600nm, with the exposed electrode surfaces being the platinum layer.

[0124] (5) Waveguide structure fabrication: Electron beam photoresist was spin-coated onto the exposed lithium niobate film. A ridge waveguide pattern was defined using the two exposed buried electrodes as alignment markers. The waveguide pattern was located in the region between the two electrodes, excluding the lithium niobate surrounding the electrodes from the etching pattern. The waveguide was designed as an adiabatic cone in the coupling region, gradually tapering from 1.5 µm in width to 250 nm, with a tapering length of 15 µm. Dry etching using argon plasma milling transferred the waveguide pattern to the lithium niobate film to a depth of 600 nm, forming an air-clad strip waveguide. The lithium niobate film surrounding the electrodes was retained to provide lateral mechanical support. The photoresist was removed after etching. Titanium / gold lead pads were fabricated above the exposed buried electrode terminals using photolithography, sputtering, and lift-off processes to complete the device fabrication.

[0125] Example 2 Example 2 is consistent with Example 1, except that the X-cut lithium niobate wafer in Example 1 is replaced with a Z-cut lithium tantalate wafer, the silicon dioxide / silicon nitride alternating layer is replaced with a silicon dioxide / tantalum pentoxide alternating layer, the 6 cycles are replaced with 5 cycles, and the process of "performing oxygen plasma activation treatment on the silicon dioxide surfaces of the two wafers, bonding them at room temperature, and annealing at 250°C for 2 hours to form a covalent bonding interface" is replaced with "bonding the two wafers with benzocyclobutene resin, spin-coating benzocyclobutene resin on the surfaces of the first and second bonding dielectric layers respectively, pre-baking and then bonding, and curing at 250°C for 1 hour," and the target working wavelength of the distributed Bragg reflector is replaced with 1310nm instead of 1550nm.

[0126] Example 3 Example 3 is consistent with Example 1, except that the distributed Bragg reflector in Example 3 is fabricated using a local fabrication method: after depositing a multilayer film of the reflector on the first substrate, the multilayer film in the surrounding area is removed by photolithography and etching, leaving only the reflector structure in the corresponding superconducting nanowire region.

[0127] Example 4 Example 4 is the same as Example 1, except that the niobium nitride superconducting film is replaced with a niobium titanium nitride superconducting film, the thickness of the superconducting film is changed from 6 nm to 8 nm, the high-temperature annealing temperature is changed from 850°C to 800°C, and the annealing time is changed from 30 minutes to 20 minutes.

[0128] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.

Claims

1. A method for fabricating an integrated photodetector device, characterized in that, include: A first refractive index layer and a second refractive index layer are alternately deposited on one side of a first substrate to form a distributed Bragg reflector on one side of the first substrate to obtain a first intermediate structure. A first bonding dielectric layer is deposited on one side of the first intermediate structure where the distributed Bragg mirror is disposed, to obtain a first pre-bonded substrate; An electrode trench is formed on one side of the second substrate, and an electrode layer and an adhesion layer are sequentially deposited in the electrode trench to form a buried electrode on one side of the second substrate to obtain a second intermediate structure. A superconducting material is deposited on one side of the second intermediate structure where a buried electrode is disposed, and the superconducting material is subjected to a first photolithography etching process and an annealing process in sequence to form a superconducting nanowire on one side of the second substrate. At least a portion of the superconducting nanowire is in contact with the buried electrode to obtain a third intermediate structure. A second bonding dielectric layer is deposited on one side of the third intermediate structure where the superconducting nanowire is disposed to obtain a second pre-bonded substrate; The first bonding dielectric layer of the first pre-bonded substrate and the second bonding dielectric layer of the second pre-bonded substrate are bonded together so that the orthographic projection of the superconducting nanowire on the first substrate is located within the orthographic projection of the distributed Bragg mirror on the first substrate, so as to obtain a bonding structure. The side of the second substrate of the bonding structure away from the superconducting nanowire is thinned to form a thin film layer on one side of the second bonding dielectric layer to obtain a fourth intermediate structure. The thin film layer in the fourth intermediate structure is subjected to a second photolithographic etching process to form a waveguide structure, thereby obtaining the integrated photodetector device.

2. The method according to claim 1, characterized in that, The gradually increasing coupling cone region of the waveguide structure is in contact with the superconducting nanowire.

3. The method according to claim 1 or 2, characterized in that, The distributed Bragg reflector includes multiple stacked pairs of refractive index layers, each pair including a first refractive index layer and a second refractive index layer, wherein the refractive index of the second refractive index layer is greater than that of the first refractive index layer, and refractive index layers with the same refractive index are spaced apart. Optionally, the number of refractive index layer pairs is 5 to 8.

4. The method according to claim 3, characterized in that, The thickness of the buried electrode is 200nm-1000nm; and / or, the thickness of the electrode layer in the buried electrode is 195nm-990nm; and / or, the thickness of the adhesion layer in the buried electrode is 5nm-10nm.

5. The method according to claim 4, characterized in that, The target wavelength of the distributed Bragg reflector is 635nm-850nm or 1520nm-1630nm.

6. The method according to claim 5, characterized in that, The thickness of the superconducting nanowires is 5 nm-10 nm; and / or, The thicknesses of the first bonding dielectric layer and the second bonding dielectric layer are independently 100 nm to 1000 nm; and / or, The thickness of the thin film layer is 200nm-1000nm; and / or, The optical thickness of the first refractive index layer is one-quarter of the target wavelength; and / or, The optical thickness of the single-layer second refractive index layer is one-quarter of the target wavelength; and / or, The thickness of the first substrate is 300µm-500µm.

7. The method according to any one of claims 4-6, characterized in that, The electrode layer comprises one or more of platinum and chromium; and / or, The adhesive layer comprises one or more of titanium and chromium; and / or, The superconducting nanowires are made of one or more of niobium nitride and titanium niobium nitride; and / or, The material of the thin film layer includes one or more of lithium niobate and lithium tantalate; and / or, The first bonding dielectric layer and the second bonding dielectric layer have the same material and chemical composition; and / or, The material of the first refractive index layer includes one or more of silicon dioxide and aluminum oxide; and / or, The material of the second refractive index layer includes one or more of tantalum pentoxide and silicon nitride; and / or, The material of the first substrate includes one or more of silicon and aluminum oxide.

8. The method according to claim 7, characterized in that, The annealing temperature is greater than 300°C, and the annealing time is 1 min to 30 min.

9. The method according to claim 8, characterized in that, The bonding treatment includes one or more of plasma-activated bonding and resin-assisted bonding. The plasma-activated bonding includes a bonding annealing treatment, the temperature of which is 150℃-350℃ and the time of which is 1h-4h.

10. An integrated photodetector device prepared by the method according to any one of claims 1-9, characterized in that, include: First substrate; A distributed Bragg reflector, wherein the distributed Bragg reflector is located on one side of the first substrate; A first bonding dielectric layer is located on the side of the distributed Bragg mirror away from the first substrate; A second bonding medium layer is located on the side of the first bonding medium layer away from the distributed Bragg mirror; A thin film layer is located on the side of the second bonding dielectric layer away from the first bonding dielectric layer, and the thin film layer includes a waveguide structure located in the thin film layer; A superconducting nanowire is embedded in the second bonding medium layer and is located on the side of the second bonding medium layer away from the first bonding medium layer. A buried electrode is embedded within the thin film layer and is in contact with the superconducting nanowire. The waveguide structure is in contact with the superconducting nanowire, and the waveguide structure and the buried electrode are located in the same layer and spaced apart.

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