Back contact cells and photovoltaic modules

Abstract

This application provides a back-contact battery and a photovoltaic module, belonging to the field of semiconductor technology. The back-contact battery includes: a semiconductor substrate, comprising a first surface and a second surface opposite to each other; the first surface includes a first region and a second region spaced apart, and a third region located between adjacent first and second regions; the third region is recessed into the semiconductor substrate relative to the first and second regions; the surface of the first region extends into the third region with a first sidewall having a buffer portion; a first doped conductive layer located within or above the first region of the semiconductor substrate; and a second doped conductive layer located on the second region of the semiconductor substrate and on the buffer portion of the first sidewall, the second doped conductive layer and the buffer portion being in conductive contact; the first doped conductive layer and the second doped conductive layer having opposite conductivity types.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to a back-contact battery and a photovoltaic module. Background Technology

[0002] Back-contact solar cells are a significant innovation in the field of photovoltaic technology. They integrate the positive and negative electrodes of traditional solar cells on the back of the cell, thereby eliminating the shading of light by the front electrodes, maximizing the light-receiving area, and thus improving cell efficiency.

[0003] Using a tunnel oxide passivated contact (TOPCon) structure in at least one conductive region (N-region and / or P-region) of the back contact battery has the advantages of good passivation effect and high efficiency potential, and is currently a key direction for industrialization.

[0004] Back-contact batteries typically employ trench isolation between the P and N regions; however, the coating and carrier collection in the trench region require further improvement. Summary of the Invention

[0005] In view of this, in order to at least partially solve at least one of the aforementioned technical problems, this application provides a back contact battery and a photovoltaic module.

[0006] To achieve the above objectives, the technical solution of this application is as follows:

[0007] According to one embodiment of this application, a back contact battery is provided, comprising: a semiconductor substrate including opposing first and second surfaces, the first surface including spaced-apart first and second regions, and a third region located between adjacent first and second regions, the third region being recessed into the semiconductor substrate relative to the first and second regions, the surface of the first region extending into the third region having a first sidewall, the first sidewall having a buffer portion; a first doped conductive layer located within or above the first region of the semiconductor substrate; and a second doped conductive layer located on the second region of the semiconductor substrate and on the buffer portion of the first sidewall, the second doped conductive layer and the buffer portion being in conductive contact, the first doped conductive layer and the second doped conductive layer having opposite conductivity types.

[0008] According to some embodiments of this application, the back contact battery further includes: a passivation antireflection layer, the passivation antireflection layer including a first passivation antireflection portion on a first doped conductive layer in a first region, and a second passivation antireflection portion on a second doped conductive layer in a second region; wherein, in the thickness direction of the semiconductor substrate, the height difference between the surface of the first passivation antireflection portion away from the semiconductor substrate and the surface of the second passivation antireflection portion away from the semiconductor substrate is 0.5~5μm; and / or, the difference between the reflectivity of the surface of the first passivation antireflection portion away from the semiconductor substrate and the reflectivity of the surface of the second passivation antireflection portion away from the semiconductor substrate is greater than or equal to 4%; and / or, the surface of the first passivation antireflection portion has a textured microstructure, and the surface of the second passivation antireflection portion has a polished microstructure.

[0009] According to some embodiments of this application, the third region has a polished microstructure, and the height difference between the surface of the buffer portion and the surface of the third region is greater than or equal to the doping depth of the doping element of the second doped conductive layer in the semiconductor substrate; the buffer portion is located in the lower half of the first sidewall. Alternatively, the third region has a textured microstructure, and along the thickness direction of the semiconductor substrate, the height difference between the surface of the buffer portion and the surface of the third region is greater than or equal to 2 μm; the buffer portion is located in the upper half of the first sidewall.

[0010] According to some embodiments of this application, the first region and the second region are alternately distributed along the first direction and each extends along the second direction; the buffer has a first side line extending along the second direction and close to the third region, and a second side line opposite to the first side line; wherein, at least one of the second side lines includes a synchronous segment that undulates synchronously with the first side line and an asynchronous segment that undulates asynchronously with the first side line.

[0011] According to some embodiments of this application, the length of the synchronous segment is greater than the length of the asynchronous segment, and / or the length of the synchronous segment is greater than or equal to 20 μm, and the length of the asynchronous segment is greater than or equal to 20 μm.

[0012] According to some embodiments of this application, the edge of the first doped conductive layer near the second edge has an inverted pyramid; the distribution density of the inverted pyramid in the region corresponding to the synchronous segment is greater than the distribution density of the inverted pyramid in the region corresponding to the asynchronous segment.

[0013] According to some embodiments of this application, at the first edge, the second doped conductive layer on the buffer portion is recessed relative to the buffer portion; and / or, the second doped conductive layer on the second region is recessed relative to the edge of the second region.

[0014] According to some embodiments of this application, the first region and the second region are alternately distributed along a first direction and each extends along a second direction; along the first direction, the width of the buffer portion is ≤30µm; and / or, along the second direction, the length of the buffer portion is less than or equal to the length of the second doped conductive layer recessed relative to the edge of the second region; and / or, along the thickness direction of the semiconductor substrate, the height of the buffer portion and the height of the second region are the same; and / or, along the thickness direction of the semiconductor substrate, the height of the surface of the second region and / or the buffer portion is less than the height of the surface of the first region; and / or, along the thickness direction of the semiconductor substrate, the height difference between the surface of the buffer portion and the surface of the first doped conductive layer is greater than or equal to the doping depth of the first doped conductive layer.

[0015] According to some embodiments of this application, the second doped conductive layer on the buffer portion has a third side line extending along the second direction and close to the third region, and the third side line and the first side line undulate synchronously; and / or, the second region has a fourth side line extending along the second direction and close to the third region, and the second doped conductive layer on the second region has a fifth side line extending along the second direction and close to the third region, and the fifth side line and the fourth side line undulate synchronously.

[0016] According to some embodiments of this application, the second doped conductive layer on the buffer portion has a third edge line extending along the second direction and close to the third region; the second doped conductive layer on the second region has a fifth edge line extending along the second direction and close to the third region; wherein the degree of undulation of the third edge line is greater than the degree of undulation of the fifth edge line; and / or, the undulation frequency of the third edge line is greater than the undulation frequency of the fifth edge line.

[0017] According to some embodiments of this application, the buffer portion has a first side line extending along a second direction and close to a third region, and the second region has a fourth side line extending along a second direction and close to the third region; wherein the degree of undulation of the first side line and the degree of undulation of the fourth side line are different; and / or, the degree of undulation of the first side line is greater than the degree of undulation of the fourth side line; and / or, the undulation frequency of the first side line is greater than the undulation frequency of the fourth side line.

[0018] According to some embodiments of this application, the first sidewall further includes a first inclined wall region and a second inclined wall region adjacent to the two side edges of the buffer portion, wherein the first inclined wall region is closer to the first doped conductive layer than the second inclined wall region; wherein at least one of the first inclined wall region and the second inclined wall region is not covered by the second doped conductive layer.

[0019] According to some embodiments of this application, the second doped conductive layer further includes an extension extending from the buffer portion to the first inclined wall region, the extension overlapping the edge of the first doped conductive layer.

[0020] According to some embodiments of this application, the second doped conductive layer further includes an extension extending from the buffer portion to the first inclined wall region, and the back contact battery further includes a second inner expansion layer located within the surface of the semiconductor substrate and at a position corresponding to the second doped conductive layer. The second inner expansion layer and the second doped conductive layer have the same doping type. The first doped conductive layer is connected to the extension portion through the second inner expansion layer, and the surface doping concentration of the second inner expansion layer is greater than or equal to 1×10⁻⁶. 19 cm -3 Alternatively, the second inner layer corresponding to the extension has an extension end extending from the extension, the distance between the extension end and the relative edge of the first doped conductive layer is less than or equal to 1 μm, and the resistivity of the semiconductor substrate is less than 5 Ω·cm; or, the distance between the extension end and the relative edge of the first doped conductive layer is less than or equal to 0.5 μm, and the resistivity of the semiconductor substrate is 5~50 Ω.

[0021] According to some embodiments of this application, the buffer portion includes a plurality of discontinuously distributed sub-buffer portions, and the second doped conductive layer includes a plurality of discontinuously distributed sub-extension portions on the surface of the first inclined wall region; the positions of the plurality of sub-buffer portions and the plurality of sub-extension portions correspond to each other.

[0022] According to some embodiments of this application, the surface of the first inclined wall region is covered with a second doped conductive layer, wherein the first doped conductive layer is a P-type doped conductive layer and the second doped conductive layer is an N-type doped conductive layer; wherein the first inclined wall region and the second inclined wall region each have multiple side edges extending in the same direction, and the distribution density of the side edges on the first inclined wall region is less than the distribution density of the side edges on the second inclined wall region.

[0023] According to some embodiments of this application, the buffer portion includes a plurality of discontinuously distributed sub-buffer portions; the first sidewall also includes a first inclined wall region and a second inclined wall region adjacent to the two side edges of the sub-buffer portions, and a third inclined wall region located between adjacent sub-buffer portions, wherein the first inclined wall region is closer to the first doped conductive layer than the second inclined wall region; wherein the first inclined wall region, the second inclined wall region and the third inclined wall region each have a plurality of side edges extending in the same direction, the bend of the side edges located in the third inclined wall region is smaller than the bend of the side edges located in the first inclined wall region or the second inclined wall region; and / or, the undulation of the third inclined wall region is smaller than the undulation of the first inclined wall region or the second inclined wall region; and / or, the roughness of the third inclined wall region is smaller than the roughness of the first inclined wall region or the second inclined wall region.

[0024] According to some embodiments of this application, the buffer portion includes a plurality of discontinuously distributed sub-buffer portions; the first sidewall also includes a third oblique wall region located between adjacent sub-buffer portions along the second direction, the third oblique wall region including two adjacent sub-connection regions, each sub-connection region having a plurality of side ridges extending in the same direction; or the portion of the third oblique wall region near the first doped conductive layer has a double-layer structure formed by stacking an upper structure and a lower structure, and the length of the upper structure is shorter than the length of the lower structure.

[0025] According to some embodiments of this application, the buffer portion includes a plurality of sub-buffer portions distributed discontinuously; the first doped conductive layer has a plurality of brim portions protruding from the first sidewall toward the third region, and the positions of the plurality of sub-buffer portions and the plurality of brim portions correspond to each other.

[0026] According to some embodiments of this application, the first sidewall further includes a first inclined wall region and a second inclined wall region adjacent to the two side edges of the buffer portion, wherein the first inclined wall region is closer to the first doped conductive layer than the second inclined wall region; wherein the first inclined wall region and the second inclined wall region have the same inclination angle; and / or, the inclination angle of the first inclined wall region and the second inclined wall region is 20° to 70° respectively.

[0027] According to some embodiments of this application, the surface of the second region extends into the third region with a second sidewall; the inclination angle of the first inclined wall region is the same as the inclination angle of the second sidewall; and / or, the inclination angle of the second inclined wall region is the same as the inclination angle of the second sidewall.

[0028] According to some embodiments of this application, at least one side edge of the back contact battery has an edge buffer portion, at least on the sidewall of the outermost first region facing one side edge, and a second doped conductive layer is located on the edge buffer portion.

[0029] According to some embodiments of this application, each of the two opposing sidewalls of the outermost first region has an edge buffer portion, wherein the width of the edge buffer portion facing one side edge is greater than the width of the edge buffer portion away from one side edge; or, the back contact cell has another side edge opposite to one side edge, and the width of the buffer portion of the first region located on the other side edge near one side edge is smaller than the width of the edge buffer portion near one side edge; or, the width of the buffer portion of the first region located in the middle near one side edge is smaller than the width of the edge buffer portion near one side edge. According to some embodiments of this application, the first doped conductive layer is a P-type doped monocrystalline silicon layer, the second doped conductive layer is an N-type doped polycrystalline silicon layer, and the back contact cell further includes a tunneling layer located between the semiconductor substrate and the second doped conductive layer.

[0030] According to some embodiments of this application, the first doped conductive layer is a P-type doped conductive layer, the second doped conductive layer is an N-type doped conductive layer, and the surface of the first region is rougher than that of the second region; or, the first doped conductive layer is an N-type doped conductive layer, the second doped conductive layer is a P-type doped conductive layer, and the surface of the second region is rougher than that of the first region.

[0031] According to some embodiments of this application, the surface of the buffer portion is a flat surface or an uneven surface.

[0032] According to one embodiment of this application, a photovoltaic module is also provided, comprising: a plurality of back contact cells as described above; an interconnecting member electrically interconnected with the plurality of contact cells to connect the back contact cells into a solar cell string; and an encapsulation layer covering the surface of the plurality of back contact cells.

[0033] According to the embodiment of this application, the back contact battery, due to the buffer portion formed on the first sidewall, can reduce the equivalent resistance of the third region located between the first and second regions by forming a second doped conductive layer on the buffer portion, thereby reducing the loss of charge carriers transported from the third region to the conductive regions on both sides. Furthermore, the buffer portion located at the edge of the first region can reduce the impact of stress, reducing the breakage rate during manufacturing and transportation. Further, the second doped conductive layer formed on the buffer portion allows for more uniform formation of the second doped conductive layer when the surface of the buffer portion is relatively flat, resulting in good film quality and thus better passivation of the region. Attached Figure Description

[0034] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0035] Figure 1 This is a cross-sectional schematic diagram of the back contact battery according to an embodiment of this application;

[0036] Figure 2 for Figure 1 A partially enlarged schematic diagram of the first doped conductive layer at the buffer section of the first sidewall;

[0037] Figure 3 This is a scanning electron microscope (SEM) image of the undulation morphology of the buffer portion and the first doped conductive layer in the back contact battery of this application embodiment.

[0038] Figure 4 A scanning electron microscope (SEM) image of the undulation morphology of the buffer portion and the first doped conductive layer in a back contact battery according to another embodiment of this application.

[0039] Figure 5SEM image of the undulation morphology of the buffer portion and the first doped conductive layer in a back contact battery according to another embodiment of this application.

[0040] Figure 6 This is a schematic diagram of the structure of the second doped conductive layer located on the buffer section and the second region according to another embodiment of this application;

[0041] Figure 7 This is a top view of the buffer section and the second doped conductive layer in an embodiment of this application.

[0042] Figure 8 This is a partial detailed schematic diagram of the first sidewall of the back contact battery according to an embodiment of this application;

[0043] Figure 9 This is a top view detailed SEM image of the first sidewall of the back contact battery according to an embodiment of this application;

[0044] Figure 10 This is a side view detail SEM image of the first sidewall of the back contact battery according to an embodiment of this application;

[0045] Figure 11 This is a SEM image of the structure of the second inner expansion layer in the back contact battery according to an embodiment of this application;

[0046] Figure 12 This is a side view detail SEM image of a sub-buffer section of the first sidewall according to another embodiment of this application;

[0047] Figure 13 This is a side view detail SEM image of the third inclined wall region in the first sidewall of another embodiment of this application;

[0048] Figure 14 This is a side view detail SEM image of the first sidewall of the back contact battery according to another embodiment of this application;

[0049] Figure 15 This is a schematic cross-sectional view of a battery according to another embodiment of this application;

[0050] Figure 16 This is a schematic diagram of the structure of the buffer section according to another embodiment of this application.

[0051] Figure 17 This is a process flow diagram of the back contact battery of this application.

[0052] In the above figures, the meanings of the reference numerals are as follows:

[0053] 1. Semiconductor substrate; 11. First surface; 111. First region; 112. Second region; 113. Third region; 114. First sidewall; 1141. Buffer portion; 1141a. Sub-buffer portion; 1142. First sloping wall region; 1143. Second sloping wall region; 1144. Third sloping wall region; 1144a. Sub-connection region; 1144b. Upper structure; 1144c. Lower structure; 115. Second sidewall; 1161. Edge buffer portion; 12. Second surface; 2. First doped conductive layer; 21. Cap brim; 3. Second doped conductive layer; 31. Extension portion; 31a. Sub-extension portion; 4. Second inner expansion layer; 5. Passivation and antireflection layer; 51. First passivation and antireflection portion; 52. Second passivation and antireflection portion; 6. Tunneling layer; 7. First electrode; 8. Second electrode; X. First direction; Y. Second direction; Z. Thickness direction of semiconductor substrate. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0055] In the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments of this application. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "comprising" as used herein indicates the presence of features, steps, or operations, but does not exclude the presence or addition of one or more other features.

[0057] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0058] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "on," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0059] In a back-contact battery, an alternating first-doped conductive layer and a second-doped conductive layer are formed on the back side of the battery, thereby enabling metallization contact on the back side and eliminating light-shielding losses on the front side. At least one of the first-doped conductive layer and the second-doped conductive layer can employ a TOPCon structure, resulting in a tunneling oxide passivation back contact (TOPCon-Back Contact, or TBC) battery. The TOPCon structure can reduce recombination and contact resistance, thereby improving battery efficiency.

[0060] When fabricating back-contact batteries, trench isolation is required between the P-region and the N-region. However, the uneven morphology of the trench can easily lead to uneven film deposition, and the large transmission resistance in the trench region can easily affect the collection of charge carriers. Therefore, the film quality and charge carrier collection effect in the trench region need to be further improved.

[0061] Therefore, this application proposes a back contact battery. Figure 1 This is a cross-sectional schematic diagram of the back contact battery according to an embodiment of this application, as shown. Figure 1As shown, the back contact battery of this application includes: a semiconductor substrate 1, a first doped conductive layer 2, and a second doped conductive layer 3. The semiconductor substrate 1 includes a first surface 11 and a second surface 12 opposite to each other. The first surface 11 includes a first region 111 and a second region 112 spaced apart, and a third region 113 located between adjacent first regions 111 and second regions 112. The third region 113 is recessed into the semiconductor substrate 1 relative to the first regions 111 and second regions 112. The first doped conductive layer 2 is located within or above the first region 111 of the semiconductor substrate 1, and the second doped conductive layer 3 is located on the second region 112 of the semiconductor substrate 1. The conductivity types of the first doped conductive layer 2 and the second doped conductive layer 3 are opposite.

[0062] Thus, when alternatingly spaced first doped conductive layers 2 and second doped conductive layers 3 are fabricated on the first surface 11 of the semiconductor substrate 1, the corresponding positive and negative electrodes are integrated on the back of the battery, thereby eliminating the light blocking by the front electrode, maximizing the light-receiving area, and thus improving battery efficiency.

[0063] According to some embodiments of this application, the first doped conductive layer 2 is formed within the first surface 11 of the semiconductor substrate 1. Its surface doping concentration is much lower than that of the substrate surface doping concentration of the corresponding doped region of the TBC, which can reduce parasitic absorption and increase the power generation on the back side, thereby improving the bifaciality. At the same time, it can also simplify the process steps and increase production capacity.

[0064] According to some embodiments of this application, a first sidewall 114 extends from the surface of the first region 111 towards the third region 113, and the first sidewall 114 has a buffer portion 1141. A second doped conductive layer 3 is also located on the buffer portion 1141 of the first sidewall 114, and the second doped conductive layer 3 and the buffer portion 1141 are in conductive contact. Here, "conductive contact" means that charge carriers can pass through between them, and there may be other films between them, such as tunneling passivation layers, but they cannot block the passage of charge carriers between them. In this way, the equivalent resistance of the third region 113 located between the first region 111 and the second region 112 can be reduced by the second doped conductive layer 3 formed on the buffer portion 1141, thereby reducing the loss of charge carriers in the third region 113 transported to the conductive regions on both sides.

[0065] It is worth noting that when there is a height difference on the same surface of the back contact battery, abrupt changes in geometry will form at the root of the height difference. When the battery cell is subjected to bending, vibration, or thermal stress, the stress induced by the external force will be amplified sharply at these abrupt changes, generating localized stress (stress concentration) much higher than the average level, causing microcracks or even fragmentation of the battery. The buffer section formed on one or both sides of the first region acts as a stress transition zone, allowing the stress originally concentrated at a single root to be dispersed to the roots of the two steps, avoiding single-point stress overload. Therefore, by setting up the buffer section, the impact of stress can be reduced, thus reducing the fragmentation rate during manufacturing and transportation.

[0066] Furthermore, when the surface of the buffer portion 1141 is relatively flat, such as when the substrate corresponding to the buffer portion has a polished or smooth surface, the film quality of the second doped conductive layer 3 can be improved, thus enhancing the passivation effect. Even further, after a passivation antireflection layer, such as a stack of aluminum oxide and silicon nitride, is applied to the buffer portion 1141, the film quality of the passivation antireflection layer can be further improved, enhancing the passivation and antireflection effect. It should be noted that the buffer portion can be approximately horizontal, for example, at an angle of ±10° to the horizontal direction, which is more conducive to the adhesion of the doped conductive layer and the passivation antireflection layer, improving the passivation and antireflection effects.

[0067] In some more specific embodiments, along the thickness direction Z of the semiconductor substrate, the height difference between the surface of the buffer portion 1141 and the surface of the first doped conductive layer 2 is greater than or equal to the doping depth of the first doped conductive layer 2. It should be noted that when the first doped conductive layer 2 is located within the first region of the semiconductor substrate 1, the "doping depth" of the first doped conductive layer 2 refers to the distance from the surface of the semiconductor substrate 1 until the doping concentration decreases to 1*102. 17 cm -3 The distance at which the doping concentration is located refers to the concentration of the doped element in the first doped conductive layer 2. When the first doped conductive layer 2 is located on the first region of the semiconductor substrate 1, the back contact battery also includes a first inner extension layer, which can be located within the surface of the semiconductor substrate 1 and at a position corresponding to the first doped conductive layer 2. The doping depth of the first doped conductive layer 2 refers to the doping concentration of the first inner extension layer 41 of the semiconductor substrate 1 being 1*10. 17 cm -3 The depth corresponding to the cutoff concentration at that point.

[0068] For ease of understanding, Figure 2 for Figure 1 A partially enlarged schematic diagram of the first doped conductive layer at the buffer portion of the first sidewall, as shown below. Figure 2As shown, taking the first doped conductive layer 2 located within the first region 111 as an example, the height difference between the surface of the buffer portion 1141 and the surface of the first doped conductive layer 2 is denoted as H1, and the doping depth of the first doped conductive layer 2 is denoted as H2, where H1 ≥ H2. In this application, to determine the height difference between one surface and another, when the surface in question has a textured structure such as a velvety microstructure or a polished microstructure, the plane where the bottom of the textured structure is located is used as a reference. For example, when the surface of the first doped conductive layer 2 has a pyramid-shaped velvety microstructure, the plane where the bottom of the pyramid is located is used as the surface of the first doped conductive layer 2.

[0069] Thus, the equivalent resistance of the third region 113 located between the first region 111 and the second region 112 can be reduced by the second doped conductive layer 3 formed on the buffer portion 1141, thereby reducing the loss of charge carriers in the third region 113 transporting to the conductive regions on both sides. At the same time, the risk of leakage caused by excessive overlap area between the first doped conductive layer 2 and the second doped conductive layer 3 can be reduced by controlling the surface height of the buffer portion 1141. Furthermore, if the height difference is less than the doping depth of the first doped conductive layer 2, the passivation effect on the buffer portion 1141 is also prone to be poor due to co-doping of different types of dopants. Therefore, by controlling the relative surface height of the buffer portion 1141, both the risk of leakage and the loss of charge carrier recombination and transport can be reduced, thereby improving battery efficiency.

[0070] It is understood that those skilled in the art can measure the doping depth and concentration using conventional methods. For example, the concentration distribution of the dopant element in the first doped conductive layer 2 along the thickness direction Z of the semiconductor substrate can be measured using the capacitance-voltage method (CV method), thereby determining the concentration of the dopant element to be 1*10. 17 cm -3 The location of the first doped conductive layer 2 can be used to determine its doping depth.

[0071] According to embodiments of this application, the semiconductor substrate 1 can be an N-type, P-type, or intrinsic crystalline silicon substrate, such as a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. Cells based on monocrystalline silicon substrates have higher conversion efficiency compared to other types, such as polycrystalline silicon cells. An N-type crystalline silicon substrate is obtained by introducing donor impurities such as group VA elements like phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type crystalline silicon substrate is obtained by introducing acceptor impurities such as group IIIA elements like boron (B), aluminum (Al), or gallium (Ga).

[0072] According to some embodiments of this application, the first surface 11 of the semiconductor substrate 1 can be the back side of the battery. Generally, the front side of the battery serves as the light-receiving surface and the back side as the backlighting surface, or it can be light-receiving on both sides, in which case both the front and back sides serve as light-receiving surfaces. By disposing the first doped conductive layer 2 within the first region 111 of the semiconductor substrate 1, parasitic light absorption caused when the doped conductive layer is formed on the first region 111 is avoided.

[0073] According to some embodiments of this application, the first doped conductive layer 2 and the second doped conductive layer 3 have different conductivity types, one of which is an N-type doped conductive layer and the other is a P-type doped conductive layer, which can be determined according to the battery type and the structure of the semiconductor substrate 1. Further, for example, N-type doping can be achieved by introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into the semiconductor material; and P-type doping can be achieved by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into the aforementioned semiconductor material.

[0074] In some examples of this application, the first doped conductive layer 2 is a P-type doped conductive layer, and the second doped conductive layer 3 is an N-type doped conductive layer. Since the diffusion process temperature of the P-type doped conductive layer is higher, it is generally prepared before the N-type doped conductive layer to avoid adverse effects on other pre-prepared layers if the P-type doped conductive layer is prepared later. Furthermore, research has found that if the doped conductive layer is deposited on the surface of the semiconductor substrate 1 using a deposition method, the P-type doped conductive layer is more prone to developing a visor structure than the N-type doped conductive layer. This can easily lead to leakage due to direct overlap between the N-type and P-type doped conductive layers. By placing the P-type doped conductive layer within the surface of the semiconductor substrate 1, the formation of the visor structure can be more effectively reduced.

[0075] In some more specific examples of this application, when the first doped conductive layer 2 is a P-type doped conductive layer and the second doped conductive layer 3 is an N-type doped conductive layer, the surface of the battery surface corresponding to the first region 111 is rougher than the surface of the battery surface corresponding to the second region 112. For example, the first region is textured and the second region is polished. This is beneficial to improving the anti-reflection effect of the P region, increasing photogenerated carriers, and increasing current. In contrast, the N region is relatively smooth, and the passivation quality through the second doped conductive layer is improved. Alternatively, if both the first and second regions are polished, this is beneficial to improving the film formation quality of the P and N regions and enhancing the passivation and anti-reflection effect of the P and N regions. The rougher first region increases photogenerated carriers and increases current. Of course, in some other embodiments, the first doped conductive layer 2 can be a P-type doped conductive layer and the second doped conductive layer 3 can be an N-type doped conductive layer. In this case, the surface of the battery surface corresponding to the second region 112 is rougher than the surface of the battery surface corresponding to the first region 111. This is beneficial to improve the quality of the P-region passivation and anti-reflection layer and improve the passivation and anti-reflection effect of the P-region. The N-region surface has a doped conductive layer for passivation, thereby balancing the passivation effect of the two regions.

[0076] According to some embodiments of this application, the material of the first doped conductive layer 2 may include single-crystal silicon, and N-type doping is achieved by introducing the aforementioned donor impurities into the single-crystal silicon, or P-type doping is achieved by introducing the aforementioned acceptor impurities. In some examples, the first doped conductive layer 2 can be obtained within the surface of the semiconductor substrate 1 by a diffusion process or an ion implantation process.

[0077] In other embodiments, the material of the first doped conductive layer 2 may also include one or more semiconductor materials such as polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In some examples, the first doped conductive layer 2 can be deposited on the surface of the semiconductor substrate 1, for example, on the first region 111, by means of a chemical vapor deposition process or the like.

[0078] The material of the second doped conductive layer 3 may include one or more semiconductor materials such as amorphous silicon, polycrystalline silicon, or microcrystalline silicon. N-type doping is achieved by introducing the aforementioned donor impurities into the semiconductor material, or P-type doping is achieved by introducing the aforementioned acceptor impurities. In some examples, the second doped conductive layer 3 can be deposited on the surface of the semiconductor substrate 1, such as the second region 112 and the buffer portion 1141, by means of chemical vapor deposition or other methods.

[0079] According to some embodiments of this application, the formation of the buffer portion 1141 on the first sidewall 114 is related to the height difference and / or reflectivity difference between the N region and the P region. The formation of the buffer portion 1141 on the first sidewall 114 is controlled by controlling the height difference and / or reflectivity. Then, a second doped conductive layer 3 is deposited on the buffer portion 1141 to reduce the sheet resistance of the third region 113, thereby reducing the carrier transport loss of the third region 113 to both sides.

[0080] Specifically, for example Figure 1 As shown, the back contact battery may further include a passivation antireflection layer 5. The passivation antireflection layer 5 may include a first passivation antireflection portion 51 located on a first doped conductive layer 2 in a first region 111, and a second passivation antireflection portion 52 located on a second doped conductive layer 3 in a second region 112. In some examples, the height difference between the surface of the first passivation antireflection portion 51 away from the semiconductor substrate 1 and the surface of the second passivation antireflection portion 52 away from the semiconductor substrate 1 in the thickness direction Z of the semiconductor substrate is 0.5~5μm, for example, it may be 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, etc.

[0081] In some examples, the difference in reflectivity between the surface of the first passivation antireflection portion 51 away from the semiconductor substrate 1 and the surface of the second passivation antireflection portion 52 away from the semiconductor substrate 1 is greater than or equal to 4%, for example, it can be 4%, 4.2%, 4.5%, 4.8%, 5%, 5.2%, 5.5%, 5.8%, 6.0%, 6.2%, 6.5%, etc.

[0082] Thus, since the passivation antireflection layer 5 is generally thin, for example, on the order of hundreds of nanometers, and is deposited relatively conformally on the first doped conductive layer 2 and the second doped conductive layer 3, the surface height difference and / or reflectivity difference between the first passivation antireflection portion 51 and the second passivation antireflection portion 52 can correspondingly represent the height difference and / or reflectivity difference between the first doped conductive layer 2 and the second doped conductive layer 3. At this time, by controlling the height difference and / or reflectivity within the aforementioned range, when laser etching is used to pattern the second doped conductive layer 3, the laser action within a certain range near the edge of the first doped conductive layer 2 differs significantly from the laser action within other ranges. In subsequent chemical etching processes, such as alkaline polishing, a buffer portion 1141 is formed on the first sidewall 114.

[0083] According to some embodiments of this application, such as Figure 1As shown, the surface of the first region 111 has a textured microstructure, and the surface of the second region 112 has a polished microstructure. Correspondingly, the surface of the first passivation and antireflection part 51 has a textured microstructure, and the surface of the second passivation and antireflection part 52 has a polished microstructure. This is suitable for applications that require high double-sidedness, but may result in a slight loss of passivation or antireflection performance, leading to a slight reduction in frontal power. It is understood that the textured microstructure can exhibit at least one of the following: convex prisms, pyramids, approximate prisms, approximate pyramids, or irregular protrusions. The polished microstructure can exhibit a morphological structure different from the flat surface, such as a textured structure composed of multiple grooves, or a textured structure composed of grooves and protrusions. The bottom surface of the groove can be a polygonal plane, and the shape of the polygonal plane includes at least one of the following: rhombus, square, trapezoid, approximate rhombus, approximate square, or approximate trapezoid.

[0084] Since the thicknesses of the first doped conductive layer 2, the second doped conductive layer 3, and the passivation antireflection layer 5 are all relatively thin, for example, on the order of hundreds of nanometers, they can be deposited relatively conformally on the semiconductor substrate 1. Therefore, the first region 111 of the corresponding semiconductor substrate 1 has the same texture structure as the first passivation antireflection portion 51, i.e., a textured microstructure, and the second region 112 has the same texture structure as the second passivation antireflection portion 52, i.e., a polished microstructure. At this time, the surface reflectivity of the first passivation antireflection portion 51 is low, which is beneficial to improving the bifaciality; while the surface reflectivity of the second passivation antireflection portion 52 is high, which is beneficial to ensuring the reflectivity difference between the first passivation antireflection portion 51 and the second passivation antireflection portion 52, thereby facilitating the formation of a buffer portion 1141 on the first sidewall 114. Furthermore, since the corresponding second region 112 is a polished microstructure, it is beneficial to improve the deposition quality of the upper film layer, thereby improving the passivation effect and effectively reducing metal recombination.

[0085] According to other embodiments of this application, both the first region 111 and the second region 112 have polished microstructures. Correspondingly, the surfaces of the first passivation anti-reflection portion 51 and the second passivation anti-reflection portion 52 can also have polished microstructures, which is suitable for applications that pursue high passivation, ensuring high power on the front side of the battery, but the power on the back side may be slightly lower. In some examples, the polished microstructures of the two regions can be the same size, which is beneficial to ensuring the consistency of the morphology on the back side of the battery and is more conducive to the optimization and control of subsequent passivation and metallization process conditions. In other examples, the polished microstructures of the two regions can be different sizes, which is more conducive to taking into account the differentiated requirements of the N-region and the P-region. For example, when the first doped conductive layer 2 is a P-type doped conductive layer, a polished microstructure with a smaller bottom surface size and / or a larger height can be selected to ensure the electrical contact performance of the P-region. When the second doped conductive layer 3 is an N-type doped conductive layer, a polished microstructure with a larger bottom surface size and / or a smaller height can be selected to ensure the passivation effect of the N-region, thereby taking into account the balance of carrier transport and collection in the N-region and the passivation effect.

[0086] According to some embodiments of this application, such as Figure 2 As shown, the third region 113 is an isolation region, a physical separation between the first region 111 and the second region 112, and the third region 113 is concave relative to both the first region 111 and the second region 112. This reduces P- and N-type co-doping in the third region 113, thus lowering leakage current caused by co-doping in the isolation region.

[0087] According to some embodiments of this application, such as Figure 2 As shown, the third region 113 may have a velvety microstructure, and the height difference H3 between the surface of the buffer portion 1141 and the surface of the third region 113 is greater than or equal to 2μm; the buffer portion 1141 is located in the upper half of the first sidewall 114.

[0088] Thus, by controlling the height difference within the aforementioned range, or by placing the buffer portion 1141 in the upper half of the first sidewall 114, the inner expansion layer formed by the doped conductive layer in the third region 113 can be effectively removed, avoiding the risk of leakage due to residual material, and ensuring the passivation effect of the third region 113. If the height difference is too small, for example, less than 2 μm, leakage risk and carrier recombination are likely to occur due to the residue of the inner expansion layer, which is not conducive to the passivation effect of the passivation and antireflection layer 5 on the semiconductor substrate 1.

[0089] In some more specific embodiments, taking the first doped conductive layer 2 as a P-type doped conductive layer and the second doped conductive layer 3 as an N-type doped conductive layer as an example, the doping depth of the first doped conductive layer 2 in the semiconductor substrate 1 is typically less than or equal to 1.2 μm, and the doping depth of the second doped conductive layer 3 in the semiconductor substrate 1 is typically less than or equal to 0.3 μm. In this case, by setting the height difference H3 to be greater than or equal to 2 μm, or by setting the buffer portion 1141 in the upper half of the first sidewall 114, when the textured microstructure has a large undulating morphology, the risk of leakage due to the inner expansion layer remaining in the third region 113 can be reduced or avoided. Simultaneously, the textured microstructure can increase light absorption when the back surface is used as a light incident surface, thereby improving the power of the battery's back surface.

[0090] According to some embodiments of this application, the third region 113 may have a polished microstructure, and the height difference H3 between the surface of the buffer portion 1141 and the surface of the third region 113 is greater than or equal to the doping depth of the dopant element of the second doped conductive layer 3 in the semiconductor substrate 1; the buffer portion 1141 is located in the lower half of the first sidewall 114. Here, "the doping depth of the dopant element of the second doped conductive layer 3 in the semiconductor substrate 1" refers to the distance from the surface of the semiconductor substrate 1 until the doping concentration of the dopant element drops to 1*10. 17 cm -3 The distance at that location.

[0091] Thus, by controlling the height difference within the aforementioned range, or by placing the buffer portion 1141 in the lower half of the first sidewall 114, the inner diffusion layer formed by the diffusion of the doped conductive layer in the third region 113 can be effectively removed, avoiding the risk of leakage due to residual material, and ensuring the passivation effect of the third region 113. If the height difference is too small, for example, less than the doping depth of the doped element in the second doped conductive layer 3 within the semiconductor substrate 1, leakage risk and carrier recombination are easily caused by the residue of the inner diffusion layer, which is detrimental to the passivation effect of the passivation and antireflection layer 5 on the semiconductor substrate 1.

[0092] In some specific embodiments, taking the first doped conductive layer 2 as a P-type doped conductive layer and the second doped conductive layer 3 as an N-type doped conductive layer as an example, the doping depth of the first doped conductive layer 2 in the semiconductor substrate 1 is typically less than or equal to 1.2 μm, and the doping depth of the second doped conductive layer 3 in the semiconductor substrate 1 is typically less than or equal to 0.3 μm. In this case, by setting the height difference H3 to be greater than or equal to the doping depth of the doped element in the second doped conductive layer 3 in the semiconductor substrate 1, or by arranging the buffer portion 1141 in the lower half of the first sidewall 114, it is beneficial to reduce or avoid the risk of leakage and reduced passivation effect caused by the inner expansion layer remaining in the third region 113.

[0093] According to some specific embodiments of this application, such as Figure 1 As shown, the first doped conductive layer 2 can be a P-type doped monocrystalline silicon layer, and the second doped conductive layer 3 can be an N-type doped polycrystalline silicon layer. The back contact cell also includes a tunneling layer 6, located between the semiconductor substrate 1 and the second doped conductive layer 3. The tunneling layer 6 and the N-type doped polycrystalline silicon layer form a tunneling passivation contact structure. The P-type dopant in the P-type doped conductive layer leads to a decrease in the corrosion rate, while the corrosion rate of the semiconductor substrate 1 is relatively high. Therefore, when there is a tunneling passivation contact structure in the P-region, it is easy to form a visor. In this application, the P-type doped monocrystalline silicon layer is directly formed in the substrate, which can reduce the doping concentration of the P-type dopant and reduce the difference in corrosion rate between the P-type dopant and the semiconductor substrate 1. The visor structure is shortened, reducing the risk of leakage at the visor structure. The tunneling layer 6 and the N-type doped polycrystalline silicon layer form a tunneling passivation contact structure, ensuring that the N-region has a high passivation and contact effect.

[0094] In some examples, the tunneling layer 6 can be made of alumina, silicon oxide, titanium oxide, etc., to selectively pass through majority carriers and achieve field passivation, improve carrier separation and collection, and also prevent the electrode from corroding the semiconductor substrate 1 inward. The tunneling layer 6 can be prepared by low-temperature chemical vapor deposition (LPCVD), and its thickness can be 0.5~10 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0095] According to some embodiments of this application, the passivation antireflection layer 5 can be a single-layer film formed of silicon dioxide, aluminum dioxide, silicon nitride, or silicon oxynitride, or it can be a stacked film of one or more of the aforementioned materials. Exemplarily, the passivation antireflection layer 5 is a stacked structure of aluminum oxide and silicon nitride disposed on the side of the aluminum oxide layer facing away from the semiconductor substrate 1, or the passivation antireflection layer 5 is a stacked structure of aluminum oxide and silicon nitride and silicon oxynitride disposed on the side of the aluminum oxide layer facing away from the silicon substrate. The passivation antireflection layer can simultaneously provide protection and passivation for the underlying semiconductor substrate or functional layers, such as the first doped conductive layer and the second doped conductive layer, as well as reduce the reflection of light incident on the first surface 11.

[0096] According to some embodiments of this application, when patterning the first doped conductive layer 2 and the second doped conductive layer 3 using laser etching, the edges of the first doped conductive layer 2 are affected by the uniformity of laser spot energy and the thickness uniformity of the film layer on the first doped conductive layer 2, such as the dopant source (phosphosilicate glass or borosilicate glass), resulting in a certain undulating morphology on the two oppositely disposed sides of the buffer portion 1141 after subsequent chemical etching. The undulating morphology of this application can be at least one of the following shapes: wavy, zigzag, sawtooth, etc.

[0097] In some more specific embodiments, after subsequent chemical etching processes, it was found that if the difference in reflectivity between the edge of the first doped conductive layer 2 and the second doped conductive layer 3 is relatively small, the fluctuations caused by the influence of reflectivity on laser etching are small, and a synchronous undulating morphology will be formed between the two side lines of the buffer portion 1141.

[0098] Figure 3 Here are scanning electron microscope (SEM) images of the undulation morphology of the buffer portion and the first doped conductive layer in the back contact battery of this application embodiment, as shown. Figure 3 As shown, in some examples, the buffer portion 1141 has a first edge extending along the second direction Y and close to the third region, and a second edge opposite to the first edge. The first edge is the boundary line between the buffer portion and the third region as seen from above the first surface, and the first edge has an undulating topography. The second edge is the boundary line between the first region and the buffer portion as seen from above the first surface, and the second edge also has an undulating topography. The two topography can be synchronous, forming a synchronous segment, or asynchronous, forming an asynchronous segment.

[0099] In some embodiments, at least one second edge line includes a synchronous segment that undulates synchronously with the first edge line. Thus, by controlling the undulating morphology between the two sides of the buffer portion 1141 to have synchronous undulations, after depositing the second doped conductive layer 3 on the buffer portion 1141, the leakage current generated by the local conductive contact between the first doped conductive layer 2 and the second doped conductive layer 3 can be dispersed, avoiding the risk of failure due to local overheating. This is beneficial for the battery to heat up evenly across the entire surface during operation, thereby improving the thermal stability and reliability of the battery.

[0100] In some more specific embodiments, after subsequent chemical etching processes, it was found that if the difference in reflectivity between the edge of the first doped conductive layer 2 and the second doped conductive layer 3 is relatively large, the fluctuations caused by the influence of reflectivity in laser etching will be large, and an asynchronous undulating morphology will be formed between the two sides of the buffer portion 1141.

[0101] Figure 4 Here is a scanning electron microscope (SEM) image of the undulation morphology of the buffer portion and the first doped conductive layer in a back contact battery according to another embodiment of this application, as shown below. Figure 4 As shown, in some examples, the buffer portion 1141 has a first edge extending along the second direction Y and close to the third region 113, and a second edge opposite to the first edge. The second edge may include asynchronous segments that undulate asynchronously with the first edge. Thus, by controlling the asynchronous undulation morphology between the two edges of the buffer portion 1141, it is beneficial to interrupt the continuous stress transmission path at the edge positions of the first doped conductive layer 2 and the buffer portion 1141, thereby reducing the adverse effects of edge stress and improving the stability and reliability of the battery structure.

[0102] According to some embodiments of this application, Figure 5 Here is a SEM image of the undulation morphology of the buffer portion and the first doped conductive layer in a back contact battery according to another embodiment of this application, as shown below. Figure 5 As shown, at least one second edge line includes a synchronous segment that undulates synchronously with the first edge line and an asynchronous segment that undulates asynchronously with the first edge line. The length of the synchronous segment is greater than the length of the asynchronous segment. In this case, while considering the adverse effects of reducing edge stress, it is more conducive to dispersing leakage current, thereby ensuring more uniform heating across the entire battery surface and guaranteeing thermal stability and reliability.

[0103] To determine the lengths of the synchronous and asynchronous segments, in SEM testing, a magnification of up to 2000x can be used, or a region of at least 60μm can be selected along the extension direction of the first region (i.e., the second direction Y) to measure the lengths of the synchronous and asynchronous segments. The synchronous and asynchronous segments are defined as follows: Select one of the first or second edge lines as a reference. On the reference edge line, select two adjacent reference valleys. If a peak exists at the corresponding position on the other edge line, the length between the two adjacent reference valleys is counted as the synchronous segment. If no peak exists at the corresponding position on the other edge line, or if the peak aligns perfectly with the two reference valleys, the length between the two adjacent reference valleys is counted as the asynchronous segment. The total length of the synchronous and asynchronous segments observed in the test area along the second direction Y is measured and calculated. Based on the calculation results, the size relationship between the synchronous and asynchronous segments is determined.

[0104] According to some embodiments of this application, the length of the synchronous segment is greater than or equal to 20 μm, for example, it can be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, etc., and the length of the asynchronous segment is greater than or equal to 20 μm, for example, it can be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, etc. If the length of the synchronous segment is too short, it is difficult to form a stable passivation and cannot provide a continuous low-resistance carrier transport path. If the length of the asynchronous segment is too short, it is difficult to achieve a good effect of improving edge stress and improving the stability and reliability of the battery structure.

[0105] According to some embodiments of this application, for example... Figures 3 to 5 As shown, the first doped conductive layer 2 has an inverted pyramid at its edge near the second edge; the distribution density of the inverted pyramid in the region corresponding to the synchronous segment is greater than the distribution density of the inverted pyramid in the region corresponding to the asynchronous segment. Here, the "distribution density" of the inverted pyramid can be a unit area region (e.g., 100 μm) at the edge of the first doped conductive layer 2. 2 Within ), the number of inverted pyramids or the area percentage of inverted pyramids.

[0106] Thus, by controlling the distribution density of the inverted pyramid, the difference in reflectivity between the edge position of the first doped conductive layer 2 and the second doped conductive layer 3 is controlled, thereby controlling the difference in undulation morphology between the two side lines (i.e., the first side line and the second side line) of the buffer portion 1141. Specifically, when the distribution density of the inverted pyramid is large, the degree of destruction of the texture structure at the edge position of the first doped conductive layer 2 is also correspondingly large. At this time, the reflectivity at the edge position of the first doped conductive layer 2 can be controlled more effectively to form a synchronous segment on the second side line that undulates synchronously with the first side line. Conversely, when the distribution density of the inverted pyramid is small, it is difficult to effectively control the reflectivity at the edge position of the first doped conductive layer 2. At this time, due to the large difference in reflectivity between the first doped conductive layer 2 and the second doped conductive layer 3, an asynchronous segment on the second side line that undulates asynchronously with the first side line is easily formed.

[0107] Especially in some more specific embodiments, where the first region 111 has a textured microstructure and the second region 112 has a polished microstructure, forming an inverted pyramid with a large distribution density at the edge of the first doped conductive layer 2 helps to reduce the reflectivity difference between the first doped conductive layer 2 and the second doped conductive layer 3, thereby enabling more effective control over the formation of a synchronous segment on the second edge line, and conversely, enabling more effective control over the formation of an asynchronous segment on the second edge line.

[0108] Of course, this is not the only possibility. In some more specific embodiments, both the first region 111 and the second region 112 may also have polished microstructures. In this case, since the first doped conductive layer 2 is conformally disposed on the first region 111 and the second doped conductive layer 3 is conformally disposed on the second region 112, correspondingly, both the first doped conductive layer 2 and the second doped conductive layer 3 also have polished microstructures. Similarly, the first region 111 and the second region 112 may also both have textured microstructures, and the first doped conductive layer 2 and the second doped conductive layer 3 will also correspondingly have textured microstructures.

[0109] At this time, the first doped conductive layer has a first texture structure, and the second doped conductive layer has a second texture structure. The height of the first texture structure can be greater than the height of the second texture structure, and / or the lateral dimension of the first texture structure can be smaller than the lateral dimension of the second texture structure. This makes the reflectivity difference between the first doped conductive layer 2 and the second doped conductive layer 3 large. The difference in the distribution density of the inverted pyramid is used to control the edge position of the first doped conductive layer 2 and the reflectivity difference between the second doped conductive layer 3. In this way, the difference in the undulation morphology of the two side edges of the buffer part 1141 can also be controlled.

[0110] According to some embodiments of this application, Figure 6 This is a schematic diagram of the structure of the second doped conductive layer located on the buffer portion and the second region according to another embodiment of this application, as shown below. Figure 6 As shown, at the first edge, the second doped conductive layer 3 on the buffer portion 1141 is recessed relative to the buffer portion 1141; and / or, the second doped conductive layer 3 on the second region 112 is recessed relative to the edge of the second region 112. By controlling the chemical etching process, such as by appropriately selecting the alkaline polishing time, the edge of the second doped conductive layer 3 can easily be recessed relative to the edge of the buffer portion and / or the edge of the second region 112. At this time, the formation of a cap structure can be avoided, thereby not affecting the deposition of subsequent film layers, such as the passivation antireflection layer 5, and thus not causing poor passivation. Furthermore, since a portion of the buffer portion 1141 or the second region 112 can be exposed, a good passivation effect is formed between the semiconductor substrate 1 and the passivation antireflection layer 5, which helps to reduce carrier recombination and improve battery efficiency during battery operation.

[0111] According to some embodiments of this application, the difference in reflectivity between the second doped conductive layer 3 located on the buffer portion 1141 and the second doped conductive layer 3 located on the second region 112 is relatively small. After patterning the second doped conductive layer 3 by laser etching and then performing subsequent chemical etching processes, the fluctuations caused by the influence of reflectivity on laser etching are small, and a synchronous undulating morphology is easily formed between the edge of the buffer portion 1141 and the edge of the second doped conductive layer 3.

[0112] Furthermore, in some more specific embodiments, such as Figures 3 to 5 As shown, the buffer portion 1141 has a first edge extending along the second direction Y and close to the third region 113. The second doped conductive layer 3 on the buffer portion 1141 has a third edge extending along the second direction Y and close to the third region. The third edge undulates synchronously with the first edge. In this way, by controlling the undulating morphology of the second doped conductive layer 3 and the buffer portion 1141 to have synchronous undulations, after depositing the second doped conductive layer 3 on the buffer portion 1141, it is beneficial to form an inner expansion layer within the surface of the buffer portion 1141, fully utilize the field passivation effect of the inner expansion layer, and effectively reduce the transmission resistance of the third region 113, thereby further reducing the loss of carrier transmission to the conductive regions on both sides.

[0113] In some more specific embodiments, similar to the undulations of the first edge of the buffer portion 1141 and the third edge of the second doped conductive layer 3 on the buffer portion 1141, the second region 112 has a fourth edge extending along the second direction Y and close to the third region, and the second doped conductive layer 3 on the second region 112 has a fifth edge extending along the second direction Y and close to the third region, with the fifth edge undulating synchronously with the third edge. Similarly, by controlling the undulations of the second doped conductive layer 3 and the second region 112 to have synchronous undulations, after depositing the second doped conductive layer 3 on the second region 112, it is beneficial to form an inner expansion layer within the surface of the second region 112, fully utilizing the field passivation effect of the inner expansion layer, and effectively reducing the transmission resistance of the third region 113, thereby further reducing the loss of carrier transport to the conductive regions on both sides.

[0114] According to some embodiments of this application, since the second doped conductive layer 3 on the buffer portion 1141 is closer to the first doped conductive layer 2 than the second region 112, when patterning is performed by laser etching, the laser etching near the buffer portion 1141 is more susceptible to the influence of the reflectivity difference and / or height difference between the first doped conductive layer 2 and the second doped conductive layer 3, thereby producing a more obvious undulating morphology, specifically manifested as a larger degree of undulation and / or undulation frequency.

[0115] In some more specific embodiments, the second doped conductive layer 3 on the buffer portion 1141 has a third edge extending along the second direction Y and close to the third region; the second doped conductive layer 3 on the second region 112 has a fifth edge extending along the second direction Y and close to the third region; wherein the undulation degree of the third edge is greater than that of the fifth edge; and / or, the undulation frequency of the third edge is greater than that of the fifth edge. Thus, by setting the undulation degree and / or undulation frequency of the third edge of the second doped conductive layer 3 on the buffer portion 1141 to be larger, the contact area between the second doped conductive layer 3 and the buffer portion 1141 is larger, which is more conducive to reducing the transmission resistance of the third region 113, thereby helping to reduce the loss of charge carriers transported to the conductive regions on both sides. Furthermore, when the third region 113 has a textured microstructure, by increasing the area of ​​the first sidewall (including the first sloping wall region and / or the second sloping wall region), it can cooperate with the third region 113 to form increased multipath light absorption, thereby improving the power on the back of the battery. By setting the degree of undulation and / or the frequency of undulation of the fifth edge of the second doped conductive layer 3 on the second region 112 to be smaller, it is beneficial to reduce the number of edge defects on the second doped conductive layer 3 on the second region 112, thereby reducing the recombination of edge carriers and improving carrier collection efficiency.

[0116] It can be understood that "degree of undulation" can represent the fluctuation amplitude of the target object, such as the third or fifth edge of the second doped conductive layer 3, as it extends along the second direction Y, i.e., the maximum or average distance by which the edge deviates from an average center line (or reference straight line). "Frequency of undulation" can refer to the number of times undulations occur per unit length when the edge of the target object extends in a bent manner. To determine the "degree of undulation" of the edge, a strip-shaped region can be taken along the second direction Y at the edge of the target object in the SEM test image of the battery surface. Then, the edge line in the strip-shaped region is extracted, the average center line is determined, and several sampling points are taken on the edge line. The maximum or average distance by which these sampling points deviate from the average center line is calculated. To determine the "frequency of undulation" of the edge, the number of times undulations occur in the strip-shaped region can be calculated, thereby determining the number of times undulations occur per unit length along the second direction Y, i.e., the frequency of undulation.

[0117] According to some embodiments of this application, similarly, the buffer portion 1141 has a first sideline extending along the second direction Y and close to the third region 113, and the second region 112 has a fourth sideline extending along the second direction Y and close to the third region; wherein the undulation degree of the first sideline and the undulation degree of the fourth sideline are different; and / or, the undulation degree of the first sideline is greater than the undulation degree of the fourth sideline; and / or, the undulation frequency of the first sideline is greater than the undulation frequency of the fourth sideline. Thus, by setting the undulation degree and / or undulation frequency of the first sideline of the buffer portion 1141 to be larger, the area of ​​the first sidewall (including the first inclined wall region and / or the second inclined wall region) can be increased, thereby increasing the coverage area of ​​the passivation antireflection layer, improving the passivation quality of the first sidewall 114 (including the first inclined wall region and / or the second inclined wall region), and reducing the transmission resistance of the third region 113, thereby helping to reduce the loss of charge carriers transported to the conductive regions on both sides. Furthermore, when the third region 113 has a textured microstructure, the increased area of ​​the first sidewall 114 (including the first sloping wall region and / or the second sloping wall region) can work in conjunction with the third region 113 to increase multipath light absorption and improve the power on the back of the battery. By setting the undulation degree and / or undulation frequency of the fourth edge of the second region 112 to be smaller, the edge position of the second region can be made smoother, the field passivation effect more uniform, thereby reducing the recombination of edge carriers and improving carrier collection efficiency.

[0118] According to some embodiments of this application, for example... Figure 6As shown, along the first direction X, the width W1 of the buffer portion 1141 is ≤ 30 μm, and can be, for example, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm, 24 μm, 26 μm, 28 μm, 30 μm, etc. If the width of the buffer portion 1141 is too narrow, it will be difficult to provide sufficient area to form a high-quality second doped conductive layer 3 on it and to reduce the transmission resistance in the third region 113. If the width of the buffer portion 1141 is too wide, it will easily lead to an excessively large proportion of the second doped conductive layer 3 on the buffer portion 1141, which will additionally increase light absorption loss and thus reduce the battery efficiency. It should be noted that the buffer portion can be locally distributed on the sidewall of a first region, and / or the second doped conductive layer 3 can be locally distributed on the buffer portion of a first region, but the length of the buffer portion with the second doped conductive layer 3 is ≥ 1 / 3 of the length of a first region, to ensure that the transmission resistance on the buffer portion is small enough to reduce the transverse transport loss of charge carriers.

[0119] In some examples, at the first edge, the width W2 of the second doped conductive layer 3 on the buffer portion 1141 that is recessed relative to the buffer portion 1141, or at the fourth edge, the width W2' of the second doped conductive layer 3 on the second region 112 that is recessed relative to the second region 112, is ≤10μm. For example, it can be 0.5μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc. If the width of the second doped conductive layer 3 that is recessed relative to the edge of the buffer portion 1141 or the second region 112 is too large, it is difficult to provide sufficient contact area with the buffer portion 1141 or the second region 112 to ensure the reduction of the transmission resistance in the third region 113 and the field passivation effect in the second region 112.

[0120] According to some embodiments of this application, along the second direction Y, the length of the buffer portion 1141 is less than or equal to the length of the second doped conductive layer 3 recessed relative to the edge of the second region 112. It is understood that, in this comparison, "length" refers to the length of the object being compared, whether it extends continuously or discontinuously along the second direction Y, and in the case of discontinuous extension, the length at the break point is not included.

[0121] In some examples, for ease of understanding, Figure 7 This is a top view of the buffer section and the second doped conductive layer in an embodiment of this application, as shown below. Figure 7As shown, taking the case where the buffer portion 1141 and the second doped conductive layer 3 extend discontinuously relative to the inward extension of the second region 112 as an example, along the second direction Y, the length (L1,1+L1,2) of the buffer portion 1141 is less than or equal to the length (L2,1+L2,2) of the second doped conductive layer 3 inward extension relative to the edge of the second region 112.

[0122] In this way, the length of the buffer portion 1141 is not too long, ensuring that the length of the second doped conductive layer 3 on the buffer portion 1141 is not too long, thereby preventing excessive optical parasitic absorption caused by the second doped conductive layer 3. Furthermore, the length of the second doped conductive layer 3 on the second region 112 relative to the edge of the second region 112 is not too short, to avoid the formation of a brim structure, thus contributing to improved passivation. Therefore, a better balance is achieved between improving optical parasitic absorption and passivation.

[0123] According to some embodiments of this application, the height of the buffer portion 1141 and the height of the second region 112 can be the same along the thickness direction Z of the semiconductor substrate. Since, during the fabrication of the back contact battery, after the patterned first doped conductive layer 2 is fabricated using laser etching and chemical etching processes, the second doped conductive layer 3, which is fabricated over the entire surface, can then be patterned using appropriate laser etching and chemical etching processes. In this case, since the conductive regions corresponding to the buffer portion 1141 and the second region 112 can be formed simultaneously, it is relatively easy to set the height of the buffer portion 1141 and the height of the second region 112 to be the same. Furthermore, since the heights of the buffer portion 1141 and the second region 112 are the same, the buffer portion can be formed simultaneously with the formation of the second region, eliminating the need for additional processes to implement the buffer portion structure, shortening the process flow, and improving the process cycle time.

[0124] According to some embodiments of this application, along the thickness direction Z of the semiconductor substrate, the height of the surface of the second region 112 and / or the buffer portion 1141 is less than the height of the surface of the first region 111. This configuration creates a height difference between the second region and / or the buffer portion and the surface of the first region, which facilitates the removal of co-doping in the second region and / or the buffer portion, reduces carrier recombination losses, and thus improves battery efficiency.

[0125] In some examples, cross-sectional SEM images of the first surface show that the first region has the highest height, followed by the second region and / or buffer region, and the third region has the lowest height. This facilitates the removal of co-doping in the second region and / or buffer region, increases the doping intensity in the second region and / or buffer region, improves passivation and low-resistance transport capabilities, and ensures low doping in the third region to reduce carrier recombination losses or leakage, thereby improving battery efficiency. The height here can be either the height of the substrate surface corresponding to that region or the height of the battery surface corresponding to that region.

[0126] According to some embodiments of this application, Figure 8 This is a partial detailed schematic diagram of the first sidewall of the back contact battery according to an embodiment of this application, as shown below. Figure 8 and Figure 2 As shown, the first sidewall 114 may further include a first inclined wall region 1142 and a second inclined wall region 1143 adjacent to the two side edges of the buffer portion 1141. The first inclined wall region 1142 is closer to the first doped conductive layer 2 than the second inclined wall region 1143. It can be understood that the first inclined wall region and the second inclined wall region refer to sidewall regions with a certain inclination angle. The inclination angle can be, for example, between 10° and 90°, such as 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, etc., and further between 20° and 80°.

[0127] In some more specific embodiments, at least the surface of the second sloped wall region 1143 is not covered by the second doped conductive layer 3. In some examples, Figure 9 This is a top view detailed SEM image of the first sidewall of the back contact battery according to an embodiment of this application. Figure 10 This is a side view SEM image showing the details of the first sidewall of the back-contact battery according to an embodiment of this application. Figures 8 to 10 As shown, the second doped conductive layer 3 further includes an extension 31 extending from the buffer portion 1141 to the first inclined wall region 1142. In this case, the second doped conductive layer 3 is disposed on the surfaces of the first inclined wall region 1142 and the buffer portion 1141, but not on the second inclined wall region 1143. In other examples, it may also be as follows... Figure 1 As shown, the second doped conductive layer 3 is provided only on the buffer section 1141.

[0128] In this way, it is possible to avoid having too many second-doped conductive layers 3 on the first sidewall 114, which would cause photoparasitic absorption loss or more leakage points. Furthermore, the passivation and antireflection layer 5 is directly formed on the surfaces of the first inclined wall region 1142 and the second inclined wall region 1143 where no second-doped conductive layer 3 is provided. This allows the passivation and antireflection layer 5 to exert its good passivation performance on the semiconductor substrate 1, reduce carrier recombination, and thus improve battery efficiency.

[0129] According to some embodiments of this application, such as Figure 9 and Figure 10 As shown, the surface of the first inclined wall region 1142 is covered with a second doped conductive layer 3. The first doped conductive layer 2 is a P-type doped conductive layer, and the second doped conductive layer 3 is an N-type doped conductive layer. The first inclined wall region 1142 and the second inclined wall region 1143 each have multiple side edges extending in the same direction. The distribution density of the side edges on the first inclined wall region 1142 is less than the distribution density of the side edges on the second inclined wall region 1143. Here, the "distribution density" of the side edges can refer to the density within a unit area (e.g., 100 μm). 2 The number of inner edges.

[0130] At this point, since the first oblique wall region 1142 is P-type doped and the second oblique wall region 1143 is N-type doped, when patterning the first doped conductive layer 2, by selecting a suitable chemical etching process, such as alkaline etching, the etching rate of the first oblique wall region 1142 is lower than that of the second oblique wall region 1143, resulting in a lower distribution density of the upper side edges of the first oblique wall region 1142 than that of the second oblique wall region 1143. Since the first oblique wall region 1142 is relatively flat, setting the second doped conductive layer 3 on the first oblique wall region 1142 is beneficial to improving the passivation effect of the first oblique wall region 1142; while the second oblique wall region 1143 is relatively rough, and in conjunction with the third region 113, it increases the multiple reflection paths of light, thereby improving the light absorption effect.

[0131] According to some embodiments of this application, such as Figure 9 and Figure 10 As shown, the second doped conductive layer 3 may further include an extension 31 extending from the buffer portion 1141 to the first inclined wall region 1142, with the extension 31 overlapping the edge of the first doped conductive layer 2. Thus, through the overlap of the extension 31 and the second doped conductive layer 3, the doping element of the second doped conductive layer 3 forms a non-uniform doped region on the first doped conductive layer 2, resulting in uneven local electric field distribution or the generation of a local high electric field. In this case, if the back contact battery is shielded and subjected to reverse bias during operation, the increased local resistance in the doped region will increase the current density in that region, leading to a local temperature rise. Furthermore, the heat generated by this local temperature rise can disperse the heat generation of the back contact battery, improving the hot spot effect.

[0132] Of course, it is not limited to forming the doped region by overlapping the extension 31 and the first doped conductive layer 2 as described above. Alternatively, the non-uniform doped region can be formed by using the second doped conductive layer 3 as an inner extension layer formed in the semiconductor substrate 1, based on at least one of the following optional embodiments.

[0133] Specifically, the second doped conductive layer 3 may also include an extension 31 extending from the buffer portion 1141 to the first inclined wall region 1142. The back contact battery also includes a second inner expansion layer 4 located within the surface of the semiconductor substrate 1 and at a position corresponding to the second doped conductive layer 3. The second inner expansion layer 4 and the second doped conductive layer 3 have the same doping type. Figure 11 This is a SEM image of the structure of the second inner expansion layer in the back contact battery according to an embodiment of this application. Figure 6 and Figure 11 As shown, in the chemical etching process, due to the difference in doping type and / or concentration between the second inner expansion layer 4 and the semiconductor substrate 1, and the masking effect of the second doped conductive layer 3 on the first inclined wall region 1142 on the second inner expansion layer 4, the second inner expansion layer 4 and the semiconductor substrate 1 exhibit a difference in etching rate, which makes the second inner expansion layer 4 located on the first sidewall 114 appear as a step.

[0134] In an optional embodiment, the first doped conductive layer 2 is connected to the extension 31 via a second inner expansion layer 4, wherein the surface doping concentration of the second inner expansion layer 4 is greater than or equal to 1×10⁻⁶. 19 cm -3 .like Figure 11 As shown in the dashed box, the second inner expansion layer 4 and the first doped conductive layer 2 corresponding to the extension overlap, so that the first doped conductive layer 2 is connected to the extension 31. At this time, when the doping concentration of the second inner expansion layer 4 meets the predetermined condition, the above-mentioned non-uniform doped region is formed by the overlap of the second inner expansion layer 4 and the first doped conductive layer 2.

[0135] In another alternative embodiment, such as Figure 11 As indicated by the dashed box, the second inner layer 4 may not directly overlap with the first doped conductive layer 2. In this case, the distance between the relative edges of the second inner layer 4 and the first doped conductive layer 2 is less than or equal to 1 μm, for example, it can be 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, etc., and the resistivity of the semiconductor substrate 1 is less than 5 Ω·cm, for example, it can be 0.5 Ω·cm, 1 Ω·cm, 1.5 Ω·cm, 2 Ω·cm, 2.5 Ω·cm, 3 Ω·cm, 3.5 Ω·cm, 4 Ω·cm, 4.5 Ω·cm, 4.8 Ω·cm, etc.

[0136] In another optional embodiment, the spacing between the relative edges of the second inner layer 4 and the first doped conductive layer 2 is less than or equal to 0.5 μm, for example, it can be 0.05 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, or 0.5 μm; the resistivity of the semiconductor substrate 1 is 5~50 Ω·cm, for example, it can be 5 Ω·cm, 6 Ω·cm, 8 Ω·cm, 10 Ω·cm, 15 Ω·cm, 20 Ω·cm, 25 Ω·cm, 30 Ω·cm, 35 Ω·cm, 45 Ω·cm, or 50 Ω·cm.

[0137] It can be understood that, along the surface extension direction of the first sidewall 114, the relative edges of the second inner expansion layer 4 and the first doped conductive layer 2 are two edges that are close to each other, and the edges of the second inner expansion layer 4 and the first doped conductive layer are both doped to a concentration of 1*10. 17 cm -3 The position. At this time, when the resistivity of the semiconductor substrate 1 meets the predetermined conditions, the above-mentioned non-uniform doped region can be formed by controlling the spacing between the second inner expansion layer 4 and the first doped conductive layer 2 within the above range.

[0138] According to some embodiments of this application, Figure 12 Here is a side view detail SEM image of a sub-buffer section of the first sidewall according to another embodiment of this application, as shown. Figure 12 As shown, the buffer portion 1141 may include a plurality of discontinuously distributed sub-buffer portions 1141a, and the second doped conductive layer 3 may include a plurality of discontinuously distributed sub-extensions 31a on the surface of the first inclined wall region 1142; the positions of the plurality of sub-buffer portions 1141a and the plurality of sub-extensions correspond to each other. In some more specific embodiments, the plurality of sub-buffer portions 1141a and the plurality of sub-extensions 31a are each discontinuously distributed along the second direction Y. Thus, since the length of the first sidewall located at the position of the buffer portion 1141 is longer, the lateral transport resistance of the charge carriers can be reduced by the second doped conductive layer 3, thereby reducing the resistance to the transport of charge carriers through the first sidewall at the positions of the buffer portion 1141 and non-buffer portions.

[0139] According to some embodiments of this application, for example... Figure 12 As shown, the buffer section 1141 may include a plurality of discontinuously distributed sub-buffer sections 1141a, with the first inclined wall region 1142 and the second inclined wall region 1143 respectively adjacent to the two side edges of the sub-buffer sections 1141a. The first sidewall 114 may also include a third inclined wall region 1144 located between adjacent sub-buffer sections 1141a.

[0140] In some examples, such as Figure 12As shown, the first inclined wall region 1142, the second inclined wall region 1143, and the third inclined wall region 1144 each have multiple side edges extending in the same direction. The bend degree of the side edges located in the third inclined wall region 1144 is smaller than that of the side edges located in the first inclined wall region 1142 or the second inclined wall region 1143. In some examples, the undulation degree of the third inclined wall region 1144 is smaller than that of the first inclined wall region 1142 or the second inclined wall region 1143. In some examples, the roughness of the third inclined wall region 1144 is larger than that of the first inclined wall region 1142 or the second inclined wall region 1143. Thus, by setting the measured bend degree, undulation degree, and / or roughness of the third inclined wall region 1144 to be smaller and / or larger, it is more beneficial to improve the quality of the passivation and antireflection layer on the back of the battery, thereby improving the passivation and antireflection effect on the back of the battery.

[0141] According to some embodiments of this application, for example... Figure 12 As shown, the third inclined wall region 1144 may include two adjacent sub-connecting regions 1144a, each of which has multiple side edges extending in the same direction. It can be understood that the side edges of these two sub-connecting regions 1144a extend in different directions. Thus, the two sub-connecting regions 1144a enclose and form multiple reflection paths for the optical path, thereby increasing light absorption on the back side of the battery and improving back-side power.

[0142] According to some embodiments of this application, for example... Figure 12 As shown, the buffer portion 1141 may include a plurality of discontinuously distributed sub-buffer portions 1141a; the first doped conductive layer 2 has a plurality of brim portions 21 protruding from the first sidewall 114 toward the third region 113, and the positions of the plurality of sub-buffer portions 1141a and the plurality of brim portions 21 correspond. In this way, the combination between the sub-buffer portions 1141a and the brim portions 21 can enclose and form a multiple reflection path of the light path, thereby increasing the light absorption on the back of the battery and improving the back power.

[0143] According to some embodiments of this application, Figure 13 This is a side view detail SEM image of the third inclined wall region in the first sidewall of another embodiment of this application; as shown Figure 13 As shown, the portion of the third sloping wall region 1144 near the first doped conductive layer 2 has a double-layer structure composed of an upper structure 1144b and a lower structure 1144c. The upper structure 1144b is further away from the semiconductor substrate 1 than the lower structure 1144c. Thus, the double-layer structure further increases the undulation of the first sidewall, thereby increasing the multiple refractions of light. Matching the multiple side edges of the first sidewall itself, this further increases the light utilization rate.

[0144] In some more specific embodiments, the lower structure 1144c may be doped monocrystalline silicon, such as the same material as the first doped conductive layer, and the upper structure 1144b and the second doped conductive layer may be made of the same material, such as doped polycrystalline silicon.

[0145] In some more specific embodiments, such as Figure 13 As shown, along the inclined extension direction of the third inclined wall region 1144, the length of the upper structure 1144b is shorter than the length of the lower structure 1144c. This allows for the consideration of light utilization while avoiding the setting of too many double-layer structures. In particular, when the upper structure 1144b includes the same material as the second doped conductive layer, it is easy to cause large photoparasitic absorption. By setting the length of the upper structure 1144b to be shorter, photoparasitic absorption is reduced.

[0146] According to some embodiments of this application, for example... Figure 8 or Figure 10 As shown, the first inclined wall region 1142 and the second inclined wall region 1143 have the same tilt angle, i.e., θ1=θ2. By setting the tilt angles of the first inclined wall region 1142 and the second inclined wall region 1143 to be the same, it is beneficial to achieve a uniform distribution of edge stress at the edge positions of the first doped conductive layer 2 and the buffer portion 1141, thus avoiding cracking caused by uneven stress. Here, "tilt angle" refers to the angle between the surface of the first inclined wall region 1142 or the second inclined wall region 1143 and the surface extension direction of the semiconductor substrate 1.

[0147] According to some embodiments of this application, Figure 14 This is a side view SEM image showing the details of the first sidewall of the back-contact battery according to another embodiment of this application, as shown below. Figure 14 As shown, the tilt angles of the first inclined wall region 1142 and the second inclined wall region 1143 can be different, i.e., θ1≠θ2. Since the first inclined wall region 1142 and the second inclined wall region 1143 are formed in different patterning processes, it is easy to adjust their tilt angles. In this way, the different requirements of the first inclined wall region 1142 and the second inclined wall region 1143 for film deposition or edge stress can be better accommodated.

[0148] In some examples, such as Figure 14 As shown, the tilt angle of the first sloping wall region 1142 can be smaller than that of the second sloping wall region 1143, i.e., θ1 < θ2. This is more conducive to relieving the edge stress of the first doped conductive layer 2 and ensuring the deposition quality of the passivation antireflection layer 5 on the first sloping wall region 1142, thereby reducing the recombination of edge carriers and improving carrier collection efficiency. The second sloping wall region 1143 has a larger tilt angle, which can better cooperate with the textured microstructure of the third region to improve the light trapping effect.

[0149] In some more specific embodiments, the tilt angle θ1 of the first inclined wall region 1142 can be 20°~70°, for example, 20°, 30°, 40°, 50°, 60°, 70°, etc.; the tilt angle of the second inclined wall region 1143 is 20°~70°, for example, 20°, 30°, 40°, 50°, 60°, 70°, etc. If the tilt angle is too large, it is not conducive to the adhesion and uniform deposition of film layers such as the second doped conductive layer 3 or the passivation antireflection layer 5 on the first inclined wall region 1142 and the second inclined wall region 1143, which is detrimental to the passivation effect; if the tilt angle is too small, the space for the conductive region will be squeezed more under the effective buffer portion 1141 size, and the lateral transport distance of charge carriers will also be extended, which is not conducive to the improvement of battery efficiency.

[0150] According to some embodiments of this application, for example... Figure 2 As shown, a second sidewall 115 extends from the surface of the second region 112 toward the third region 113; the tilt angle of the first inclined wall region 1142 is the same as the tilt angle of the second sidewall 115; and / or, the tilt angle of the second inclined wall region 1143 is the same as the tilt angle of the second sidewall 115. Thus, the first sidewall 114 and the second sidewall 115 can be formed simultaneously in one step using the same laser etching and etching process, simplifying the process and reducing costs.

[0151] According to some embodiments of this application, Figure 15 This is a schematic cross-sectional view of a battery according to another embodiment of this application, as shown below. Figure 15 As shown, at least one edge of the back-contact battery has an edge buffer portion 1161 on the sidewall of the outermost first region 111 facing one edge, and the second doped conductive layer is located on the edge buffer portion. It is understood that "outermost" refers to the first region closest to one edge of the battery in the direction perpendicular to the extension of the first region; "at least" means that the edge buffer portion may be present only on the sidewall of the outermost first region facing the battery edge, or it may be present on both opposite sidewalls of the outermost first region. Other locations of the first region may also have a similar design. Thus, the four edges of the battery are "weak points" of stress concentration during manufacturing and transportation, and in most cases, they directly bear mechanical contact. By providing an edge buffer portion on the sidewall of the outermost first region facing one edge, stress can be better dispersed, reducing the breakage rate during battery manufacturing and transportation.

[0152] According to some more specific embodiments of this application, each of the two opposing sidewalls of the outermost first region 111 has an edge buffer portion 1161, wherein the width of the edge buffer portion 1161 facing one side edge is greater than the width of the edge buffer portion 1161 away from one side edge. Thus, a wider buffer portion can be used at the position of the outermost first region 111 facing that side edge to better disperse stress and reduce the risk of microcracks or fragmentation, while a narrower edge buffer portion is provided at the position away from that side edge to ensure less parasitic absorption loss. Furthermore, a second doped conductive layer is located on the edge buffer portions on the two opposing sidewalls, wherein the width of the second doped conductive layer on the edge buffer portion 1161 facing one side edge is greater than the width of the second doped conductive layer on the edge buffer portion away from one side edge. In addition to meeting the above requirements for stress dispersion and reducing parasitic absorption, the transmission resistance of the two opposing sidewalls can be further reduced and the passivation effect improved.

[0153] According to some embodiments of this application, the back contact battery has an edge opposite to one side edge, and the width of the buffer portion of the first region located on the other side edge near that side edge is smaller than the width of the edge buffer portion near that side edge. It is understood that the first region located on the other side edge refers to the first region closest to the other side edge of the battery, perpendicular to the extension direction of the first region. When the back contact battery is a sliced ​​battery, for example, a half-cell battery, it is formed by dividing a whole battery along the extension direction of the first region. In this case, for the whole battery, the buffer portion at the middle position is narrow, and the buffer portions at both sides are wide. After dividing it into half-cell batteries from the middle position, the buffer portion at the other side edge is narrow, and the buffer portion at one side edge is wide; all of the above refer to the width of the buffer portion near that side edge. For half-cell batteries directly fabricated using half-wafers, a similar pattern exists as for whole-cell batteries.

[0154] This design serves two purposes. First, the closer to the battery edge, the greater the stress from mechanical contact at the edge of the first region 111. By making the buffer portion at the battery edge of the first region 111 wider, stress can be dispersed, thus reducing its impact. Second, in the printing electrode, the tension changes due to repeated use of the screen, causing the ink (paste) to shift towards the battery edge, and the pressure on the battery cell also shifts. By making the buffer portion at the battery edge of the first region 111 wider, the pressure generated during electrode manufacturing can be dispersed, thereby reducing the breakage rate.

[0155] According to some embodiments of this application, the width of the buffer portion near one side edge of the first region in the middle is smaller than the width of the edge buffer portion near that side edge. It is understood that the first region in the middle refers to the first region located in the very center. If the number of first regions is even, there are two first regions in the very center; if the number of first regions is odd, there is one first region in the very center. Thus, for both whole-cell and sliced ​​cells, this is beneficial for dispersing stress generated by mechanical contact at the first region of the battery edge during the manufacturing or transportation of the back-contact battery, thereby reducing the impact of stress. On the other hand, it is beneficial for dispersing the larger stress generated near the battery edge due to ink outlet position offset in the printed electrode, thereby reducing the breakage rate. According to some embodiments of this application, the surface of the buffer portion 1141 can be a flat surface or an uneven surface.

[0156] In some examples, such as Figures 9 to 14 As shown, the surface of the buffer portion 1141 can be a flat surface, such as a smooth surface, which is beneficial to further improve the quality of the second doped conductive layer 3 located on the buffer portion 1141. The loss of charge carriers transport to the conductive regions on both sides can be effectively reduced based on the second doped conductive layer 3.

[0157] In other examples, such as Figure 4 As shown, the surface of the buffer portion 1141 can be an uneven surface, or more specifically, an uneven surface with polished microstructures. This is beneficial for further improving the quality of the second doped conductive layer 3 located on the buffer portion 1141, and can effectively reduce the loss of charge carrier transport to the conductive regions on both sides based on the second doped conductive layer 3.

[0158] In yet another example, Figure 16 This is a schematic diagram of the structure of a buffer section according to another embodiment of this application. Figure 16 As shown, the local surface of the buffer portion 1141 can be an uneven surface, or more specifically, an uneven surface with a textured microstructure. In this case, the second doped conductive layer 3 on the surface of the textured microstructure may be locally damaged. Thus, the uneven surface of the buffer portion can be used to further improve the light-trapping effect. Furthermore, a local area of ​​the buffer portion can have an uneven surface with a textured microstructure, while other areas have an uneven surface with a flat surface or a polished microstructure. This can balance carrier transport loss and light-trapping effect, i.e., balance both the front and back sides to obtain higher front and back power.

[0159] It can be understood that the morphology of the surface of the buffer part 1141 can be formed by chemical etching conditions. For example, using an alkaline etching solution containing texturing additives is conducive to forming a textured surface with a textured microstructure, while an alkaline etching solution containing polishing additives combined with appropriate etching conditions is conducive to forming a textured surface or a flat surface with a polished microstructure.

[0160] According to some embodiments of this application, for example... Figure 1 As shown, the back contact battery of this application may further include a first electrode 7 and a second electrode 8. The first electrode 7 is electrically contacted through the first passivation anti-reflection portion 51 and the first doped conductive layer 2, and the second electrode 8 is in contact through the second passivation anti-reflection portion 52 and the second doped conductive layer 3.

[0161] The following is Figure 1 Using the simplified TBC battery shown as an example, the manufacturing method of the back contact battery of this application will be explained. Specifically, Figure 17 This is a process flow diagram of the back contact battery manufacturing process of this application, as shown below. Figure 17 As shown, the method for manufacturing the back contact battery of this application includes operations S1 to S3:

[0162] In operation S1, such as Figure 17 As shown in Figures (a) and (b), a patterned first doped conductive layer 2 is fabricated on the first surface 11 of the semiconductor substrate 1, such that the first doped conductive layer 2 is disposed within the first region 111.

[0163] In operation S2, such as Figure 17 As shown in Figure (c), a second doped conductive layer 3 is fabricated on the first surface 11 of the semiconductor substrate 1, covering the entire surface.

[0164] When operating S3, such as Figure 17 As shown in Figure (d), the second doped conductive layer 3 covering the entire surface is patterned, and the second doped conductive layer 3 located in the third region 113 is removed, such that the remaining second doped conductive layer 3 is disposed on the second region 112 and on the buffer portion 1141 of the first sidewall 114 extending from the first region 111 to the third region 113.

[0165] According to some embodiments of this application, in operation S1, after patterning, the height difference between the first region 111 and the rest of the region excluding the first region 111 is greater than or equal to the doping depth of the first doped conductive layer 2. Accordingly, it can be ensured that the height difference between the surface of the buffer portion 1141 and the surface of the first doped conductive layer 2 is greater than or equal to the doping depth of the first doped conductive layer 2.

[0166] According to some embodiments of this application, before operation S1, in order to form a textured or polished microstructure on the first region 111, a first alkaline etching solution can be used to perform alkaline etching on the semiconductor substrate 1. The first alkaline etching solution may include an alkali with a concentration of 0.2wt% to 8wt% and an additive with a concentration of 0.1wt% to 3wt%. The type of additive can be a texturing additive or a polishing additive, depending on the morphology of the first region 111. The alkaline etching temperature can be 40 to 95°C, and the etching time can be 1 to 20 minutes.

[0167] In some examples, the surface reflectivity after being etched by the first alkaline etchant can be 7% to 40%, for example, 7%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, etc.

[0168] According to some embodiments of this application, in operation S1, a first doped conductive layer 2 can be formed on the entire surface of the first surface 11 of the semiconductor substrate 1 by a boron diffusion process, and then the first doped conductive layer 2 can be patterned by laser etching and chemical etching processes.

[0169] In some examples, the laser etching conditions may include nanosecond or picosecond lasers with a wavelength ≤800nm. Chemical etching can be performed using a second alkaline etchant to etch the semiconductor substrate 1 exposed after laser etching. This second alkaline etchant may include an alkali concentration of 0.2wt%–8wt% and an additive concentration of 0.1wt%–3wt%. The type of additive can be a texturing additive or a polishing additive, depending on the morphology of the second region 112. The alkaline etching temperature can be 40–95℃, and the etching time can be 1–20 min.

[0170] In some examples, the corrosion depth is greater than or equal to 0.5 μm, and the reflectivity of the etched surface is 20% to 45%, resulting in a reflectivity difference of greater than or equal to 4% between the first region 111 and the second region 112.

[0171] According to some embodiments of this application, in operation S2, a second doped conductive layer 3, such as an N-type doped polysilicon layer, can be fabricated on the first surface 11 of the semiconductor substrate 1 by means of chemical vapor deposition or other methods to cover the entire surface.

[0172] Furthermore, taking the second doped conductive layer 3 as an example of an N-type doped polycrystalline silicon layer, the tunneling layer 6 can also be prepared by low-temperature chemical vapor deposition (LPCVD) before fabricating the second doped conductive layer 3.

[0173] According to some embodiments of this application, in operation S3, the second doped conductive layer 3 can be patterned using laser etching and chemical etching processes.

[0174] In some examples, laser etching conditions may include nanosecond or picosecond lasers with a wavelength ≤800nm. Chemical etching processes can use a third alkaline etchant to etch the third region 113 exposed after laser etching. This third alkaline etchant may include an alkali concentration of 0.2wt%–8wt% and an additive concentration of 0.1wt%–3wt%. The type of additive can be a texturing additive or a polishing additive, depending on the morphology of the third region 113. The alkaline etching temperature can be 40–95℃, and the etching time can be 1–20 min.

[0175] According to some embodiments of this application, during patterning in operation S3, since the formation of the buffer portion 1141 on the first sidewall 114 is related to the height difference and / or reflectivity difference between the N-region and the P-region, the formation of the buffer portion 1141 on the first sidewall 114 is controlled by controlling the height difference and / or reflectivity, while retaining the second doped conductive layer 3 deposited on the buffer portion 1141. In this way, the sheet resistance of the third region 113 can be reduced by the second doped conductive layer 3 deposited on the buffer portion 1141, thereby reducing the carrier transport loss to both sides of the third region 113.

[0176] According to some embodiments of this application, the manufacturing method may further include: simultaneously etching the second surface 12 of the semiconductor substrate 1 while performing alkaline etching on the third region 113, to form a textured microstructure on the second surface 12, thus simplifying the manufacturing process. It is understood that the third alkaline etching solution may be a texturing additive.

[0177] According to some embodiments of this application, the fabrication method of this application may further include: in operation S4, fabricating a passivation antireflection layer 5, including a first passivation antireflection portion 51 fabricated on a first doped conductive layer 2, and a second passivation antireflection portion 52 fabricated on a second doped conductive layer 3. Thus, as shown... Figure 1 The diagram shows a simplified back-contact battery.

[0178] According to another embodiment of this application, a photovoltaic module is provided, comprising: a plurality of back contact cells as described above; an interconnecting member electrically interconnected with the plurality of back contact cells to connect the back contact cells into a solar cell string; and an encapsulation layer covering the surface of the plurality of back contact cells.

[0179] According to embodiments of this application, the number of back contact batteries connected in series can be 4 to 80. Multiple back contact batteries can form several battery modules, each module containing the same number of back contact batteries. The battery cells within a module are connected in series, and the modules can be connected in series or in parallel.

[0180] According to embodiments of this application, the interconnecting component may be solder ribbon, metal wire, conductive tape, etc.

[0181] According to embodiments of this application, the encapsulation structure may include a backplate, an encapsulating film, a glass panel, etc., to improve the stability of the solar cell string. The glass panel is located on the front of the solar cell string, and the backplate is located on the back of the solar cell string, both serving a protective function. The adhesive film is the adhesive film between the solar cell string and the glass panel and backplate, serving a bonding and fixing function, and must be made of a transparent material.

[0182] In some examples, the encapsulating film can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. In some examples, the cover or backing plate can be a light-transmitting film layer such as a glass cover or a plastic cover.

[0183] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back-contact battery, comprising: A semiconductor substrate includes opposing first and second surfaces; the first surface includes a first region and a second region spaced apart, and a third region located between adjacent first and second regions; The third region is recessed into the semiconductor substrate relative to the first and second regions; a first sidewall extends from the surface of the first region toward the third region; the first sidewall has a buffer portion. A first doped conductive layer is located within or on the first region of the semiconductor substrate; A second doped conductive layer is located on the second region of the semiconductor substrate and on the buffer portion of the first sidewall; the second doped conductive layer and the buffer portion are in conductive contact, and the conductivity types of the first doped conductive layer and the second doped conductive layer are opposite.

2. The back contact battery according to claim 1, wherein, The back contact battery further includes a passivation anti-reflection layer; the passivation anti-reflection layer includes a first passivation anti-reflection portion on the first doped conductive layer in the first region, and a second passivation anti-reflection portion on the second doped conductive layer in the second region; Wherein, in the thickness direction of the semiconductor substrate, the height difference between the surface of the first passivation anti-reflection portion away from the semiconductor substrate and the surface of the second passivation anti-reflection portion away from the semiconductor substrate is 0.5~5μm; And / or, the difference between the reflectivity of the surface of the first passivation antireflection portion away from the semiconductor substrate and the reflectivity of the surface of the second passivation antireflection portion away from the semiconductor substrate is greater than or equal to 4%; And / or, the surface of the first passivation anti-reflection portion has a textured microstructure, and the surface of the second passivation anti-reflection portion has a polished microstructure.

3. The back contact battery according to claim 1 or 2, wherein: The third region has a polished microstructure; the height difference between the surface of the buffer portion and the surface of the third region is greater than or equal to the doping depth of the doping element of the second doped conductive layer in the semiconductor substrate; the buffer portion is located in the lower half of the first sidewall; or, The third region has a velvety microstructure, and the height difference between the surface of the buffer portion and the surface of the third region is greater than or equal to 2 μm; the buffer portion is located in the upper half of the first sidewall.

4. The back contact battery according to any one of claims 1 to 3, wherein, The first region and the second region are distributed alternately along the first direction and each extends along the second direction; The buffer portion has a first side line extending along the second direction and close to the third region, and a second side line opposite to the first side line. At least one of the second edge lines includes a synchronous segment that fluctuates synchronously with the first edge line, and an asynchronous segment that fluctuates asynchronously with the first edge line.

5. The back contact battery according to claim 4, wherein, The length of the synchronous segment is greater than the length of the asynchronous segment; and / or, the length of the synchronous segment is greater than or equal to 20 μm, and the length of the asynchronous segment is greater than or equal to 20 μm.

6. The back contact battery according to claim 4 or 5, wherein, The first doped conductive layer has an inverted pyramid shape at the edge near the second edge line; The distribution density of the inverted pyramid in the region corresponding to the synchronous segment is greater than the distribution density of the inverted pyramid in the region corresponding to the asynchronous segment.

7. The back contact battery according to any one of claims 4 to 6, wherein: At the first edge line, the second doped conductive layer located on the buffer portion is recessed relative to the buffer portion; And / or, the second doped conductive layer located on the second region is recessed relative to the edge of the second region.

8. The back contact battery according to any one of claims 1 to 7, wherein, The first region and the second region are alternately distributed along a first direction and each extends along a second direction; wherein: Along the first direction, the width of the buffer portion is ≤30um; And / or, along the second direction, the length of the buffer portion is less than or equal to the length of the second doped conductive layer recessed relative to the edge of the second region; And / or, along the thickness direction of the semiconductor substrate, the height of the buffer portion is the same as the height of the second region; And / or, along the thickness direction of the semiconductor substrate, the height of the surface of the second region and / or the buffer portion is less than the height of the surface of the first region; And / or, along the thickness direction of the semiconductor substrate, the height difference between the surface of the buffer portion and the surface of the first doped conductive layer is greater than or equal to the doping depth of the first doped conductive layer.

9. The back contact battery according to claim 7, wherein, The second doped conductive layer located on the buffer portion has a third side line extending along the second direction and close to the third region, and the third side line and the first side line undulate synchronously. And / or, the second region has a fourth side line extending along the second direction and close to the third region, and the second doped conductive layer located on the second region has a fifth side line extending along the second direction and close to the third region, the fifth side line and the fourth side line undulating synchronously.

10. The back contact battery according to claim 7, wherein, The second doped conductive layer located on the buffer portion has a third side line extending along the second direction and close to the third region; the second doped conductive layer located on the second region has a fifth side line extending along the second direction and close to the third region; Wherein, the degree of undulation of the third sideline is greater than that of the fifth sideline; and / or, the undulation frequency of the third sideline is greater than that of the fifth sideline.

11. The back contact battery according to any one of claims 1 to 10, wherein, The buffer section has a first edge line near the third region, and the second region has a fourth edge line near the third region; wherein the degree of undulation of the first edge line and the degree of undulation of the fourth edge line are different; and / or, the degree of undulation of the first edge line is greater than the degree of undulation of the fourth edge line; and / or, the undulation frequency of the first edge line is greater than the undulation frequency of the fourth edge line.

12. The back contact battery according to any one of claims 1 to 11, wherein, The first sidewall also includes a first inclined wall region and a second inclined wall region adjacent to the two sides of the buffer portion, wherein the first inclined wall region is closer to the first doped conductive layer than the second inclined wall region; At least the surface of the second inclined wall region is not covered by the second doped conductive layer.

13. The back contact battery according to claim 12, wherein, The second doped conductive layer further includes an extension extending from the buffer portion to the first sloping wall region, the extension overlapping the edge of the first doped conductive layer.

14. The back contact battery according to claim 12, wherein, The second doped conductive layer further includes an extension extending from the buffer portion to the first sloping wall region, and the back contact cell further includes a second inner expansion layer, which is located within the surface of the semiconductor substrate and at a position corresponding to the second doped conductive layer; the second inner expansion layer and the second doped conductive layer have the same doping type; The first doped conductive layer is connected to the extension portion via the second inner expansion layer, and the surface doping concentration of the second inner expansion layer is greater than or equal to 1×10⁻⁶. 19 cm -3 Alternatively, the distance between the relative edges of the second inner extension layer corresponding to the extension and the first doped conductive layer is less than or equal to 1 μm, and the resistivity of the semiconductor substrate is less than 5 Ω·cm; or, the distance between the relative edges of the second inner extension layer and the first doped conductive layer is less than or equal to 0.5 μm, and the resistivity of the semiconductor substrate is 5~50 Ω·cm.

15. The back contact battery according to claim 12, wherein, The buffer section includes a plurality of discontinuously distributed sub-buffer sections, and the second doped conductive layer includes a plurality of discontinuously distributed sub-extensions on the surface of the first sloping wall region; the positions of the plurality of sub-buffer sections and the plurality of sub-extensions correspond to each other.

16. The back contact battery according to claim 12, wherein, The surface of the first inclined wall region is covered with a second doped conductive layer. The first doped conductive layer is a P-type doped conductive layer, and the second doped conductive layer is an N-type doped conductive layer. The first inclined wall region and the second inclined wall region each have multiple side edges extending in the same direction, and the distribution density of the side edges on the first inclined wall region is less than the distribution density of the side edges on the second inclined wall region.

17. The back contact battery according to any one of claims 1 to 16, wherein, The buffer section includes multiple sub-buffer sections that are discontinuously distributed; The first sidewall also includes a first inclined wall region and a second inclined wall region adjacent to the two sides of the sub-buffer portion, and a third inclined wall region located between adjacent sub-buffer portions, wherein the first inclined wall region is closer to the first doped conductive layer than the second inclined wall region. The first, second, and third inclined wall regions each have multiple side edges extending in the same direction. The bending degree of the side edges located in the third inclined wall region is smaller than that of the side edges located in the first or second inclined wall regions. And / or, the undulation degree of the third inclined wall region is smaller than that of the first or second inclined wall regions. And / or, the roughness of the third inclined wall region is greater than that of the first or second inclined wall regions.

18. The back contact battery according to any one of claims 1 to 17, wherein, The buffer section includes a plurality of intermittently distributed sub-buffer sections; the first sidewall also includes a third inclined wall region located between adjacent sub-buffer sections; The third inclined wall region includes two adjacent sub-connection regions, each having multiple side ridges extending in the same direction; or, the portion of the third inclined wall region near the first doped conductive layer has a double-layer structure composed of an upper structure and a lower structure, and along the inclined extension direction of the third inclined wall region, the length of the upper structure is shorter than the length of the lower structure.

19. The back contact battery according to any one of claims 1 to 18, wherein, The buffer section includes multiple sub-buffer sections that are discontinuously distributed; The first doped conductive layer has a plurality of brim portions protruding from the first sidewall toward the third region, and the positions of the plurality of sub-buffer portions and the plurality of brim portions correspond to each other.

20. The back contact battery according to any one of claims 1 to 19, wherein, The first sidewall also includes a first inclined wall region and a second inclined wall region adjacent to the two sides of the buffer portion, wherein the first inclined wall region is closer to the first doped conductive layer than the second inclined wall region; Wherein, the inclination angles of the first inclined wall region and the second inclined wall region are the same or different; and / or, the inclination angles of the first inclined wall region and the second inclined wall region are each 20°~70°.

21. The back contact battery according to claim 20, wherein, The surface of the second region extends toward the third region with a second sidewall; The inclination angle of the first inclined wall region is the same as the inclination angle of the second sidewall; and / or, the inclination angle of the second inclined wall region is the same as the inclination angle of the second sidewall.

22. The back contact battery according to any one of claims 1 to 21, wherein, At least one side edge of the back contact battery has an edge buffer portion on at least the sidewall of the outermost first region facing the side edge, and the second doped conductive layer is located on the edge buffer portion.

23. The back contact battery according to claim 22, wherein, The two opposite sidewalls of the outermost first region each have an edge buffer portion, wherein the width of the edge buffer portion facing the edge of said one side is greater than the width of the edge buffer portion away from the edge of said one side. Alternatively, the back contact battery has an edge opposite to the one side edge, and the width of the buffer portion located in the first region of the other side edge near the one side edge is smaller than the width of the edge buffer portion near the one side edge; Alternatively, the width of the buffer portion located in the middle of the first region near the edge of one side is smaller than the width of the edge buffer portion near the edge of one side.

24. The back contact battery according to any one of claims 1 to 23, wherein: The first doped conductive layer is a P-type doped monocrystalline silicon layer, the second doped conductive layer is an N-type doped polycrystalline silicon layer, and the back contact cell further includes a tunneling layer located between the semiconductor substrate and the second doped conductive layer.

25. The back contact battery according to any one of claims 1 to 24, wherein, The first doped conductive layer is a P-type doped conductive layer, and the second doped conductive layer is an N-type doped conductive layer. The surface of the first region is rougher than that of the second region. Alternatively, the first doped conductive layer may be an N-type doped conductive layer or a P-type doped conductive layer, and the surface of the second region may be rougher than that of the first region.

26. The back contact battery according to any one of claims 1 to 25, wherein, The surface of the buffer section is either flat or uneven.

27. A photovoltaic module, comprising: Multiple back-contact batteries as described in any one of claims 1 to 26; Interconnectors are electrically interconnected with multiple back contact batteries to connect the back contact batteries into a solar cell string; as well as An encapsulation layer covers the surfaces of the plurality of back contact batteries.

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