Composite passivated back contact cells, methods of making the same, and photovoltaic modules

Abstract

This application discloses a composite passivated back contact solar cell, its fabrication method, and a photovoltaic module. The composite passivated back contact solar cell includes: a crystalline silicon substrate, comprising a first surface and a second surface disposed opposite to each other; the first surface including a first region and a second region spaced apart, and a third region located between the first region and the second region; a first passivation structure located in the first region, the first passivation structure including a first doped layer; a second passivation structure located in the second region, the second passivation structure including a second doped layer; and a first intrinsic layer located in the third region, the first intrinsic layer being in contact with the first doped layer and the second doped layer to block lateral leakage between the first doped layer and the second doped layer. In this application, the first intrinsic layer in the third region can block lateral leakage on the first surface, avoiding PN short circuits, and simultaneously repair damage in the third region, improving the passivation effect.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic cell technology, specifically relating to a composite passivated back contact cell, its preparation method, and photovoltaic module. Background Technology

[0002] Hybrid interdigitated-back-contact cells (HIBCs) combine the advantages of heterojunction (HJT) and top-conducting oxide (TOPCon) cells while mitigating their respective drawbacks, thus achieving theoretically maximum efficiency. The low-temperature amorphous silicon passivation structure from HJT cells is used in the P-type region to effectively reduce interfacial recombination and increase voltage; while the high-temperature polycrystalline silicon passivation structure from TOPCon cells is used in the N-type region to ensure excellent electron selection and collection capabilities and reduce resistance.

[0003] However, in HIBC batteries, the P-type and N-type regions are both located on the back of the battery, with a spacing of only tens to hundreds of micrometers. If there is a slight deviation in the process (such as photolithography misalignment, laser damage, etc.), these two semiconductor layers with opposite conductivity may come into direct contact or form ion channels, resulting in leakage, which directly affects the battery efficiency and exacerbates the risk of hot spots.

[0004] Therefore, it is necessary to provide a composite passivated back contact cell, its preparation method, and a photovoltaic module. Summary of the Invention

[0005] The purpose of this application is to provide a composite passivated back contact battery, its preparation method and photovoltaic module, which blocks lateral leakage current on the first surface through the first intrinsic layer and provides passivation protection for the third region, thereby improving battery efficiency.

[0006] The above-mentioned objective of this application is achieved through the following technical solution:

[0007] In a first aspect, this application provides a composite passivated back contact battery, the composite passivated back contact battery comprising:

[0008] A crystalline silicon substrate includes a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region spaced apart, and a third region located between the first region and the second region;

[0009] A first passivation structure located in the first region, the first passivation structure including a first doped layer, the doping type of the first doped layer being opposite to the doping type of the crystalline silicon substrate;

[0010] A second passivation structure located in the second region, the second passivation structure including a second doped layer, the doping type of the second doped layer being the same as the doping type of the crystalline silicon substrate;

[0011] The first intrinsic layer is located in the third region and is in contact with the first doped layer and the second doped layer to block lateral leakage between the first doped layer and the second doped layer.

[0012] In one or more embodiments of this application, the width of the third region is 5μm to 50μm.

[0013] In one or more embodiments of this application, the first passivation structure includes at least one second intrinsic layer, at least one first doped layer, and a third intrinsic layer stacked along a direction away from the crystalline silicon substrate, wherein the first intrinsic layer covers the sides of the second intrinsic layer and the first doped layer and is connected to the third intrinsic layer.

[0014] In one or more embodiments of this application, the first intrinsic layer and the third intrinsic layer have the same thickness, both being 2nm~10nm; and / or,

[0015] The first intrinsic layer is an intrinsic hydrogenated amorphous silicon layer; and / or,

[0016] The third intrinsic layer is an intrinsic hydrogenated amorphous silicon layer or an intrinsic hydrogenated microcrystalline silicon layer.

[0017] In one or more embodiments of this application, the first intrinsic layer and the third intrinsic layer are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process, wherein the flow ratio of hydrogen to silane in the deposition process is greater than or equal to 10:1, and the thickness of both the first intrinsic layer and the third intrinsic layer is 2nm~3nm; or,

[0018] The first intrinsic layer is an intrinsic hydrogenated amorphous silicon layer, and the third intrinsic layer is an intrinsic hydrogenated microcrystalline silicon layer at least in the electrode region. The thickness of both the first intrinsic layer and the third intrinsic layer is 5 nm to 10 nm.

[0019] In one or more embodiments of this application, the second intrinsic layer is an intrinsic amorphous silicon layer or an intrinsic hydrogenated amorphous silicon layer; and / or,

[0020] The first doped layer is a P-type doped hydrogenated amorphous silicon layer or a hydrogenated microcrystalline silicon layer.

[0021] In one or more embodiments of this application, the second passivation structure includes at least one tunneling layer and at least one second doped layer stacked along a direction away from the crystalline silicon substrate, wherein the first intrinsic layer covers the sides of the tunneling layer and the second doped layer.

[0022] In one or more embodiments of this application, the side surface of the second passivation structure away from the crystalline silicon substrate includes a central region and an outer peripheral region, and a third passivation structure is stacked on the outer peripheral region.

[0023] In one or more embodiments of this application, the third passivation structure includes at least one fourth intrinsic layer, at least one third doped layer, and a fifth intrinsic layer stacked along a direction away from the crystalline silicon substrate. The doping type of the third doped layer is opposite to the doping type of the crystalline silicon substrate. The first intrinsic layer covers the sides of the fourth and third intrinsic layers and is connected to the fifth intrinsic layer.

[0024] In one or more embodiments of this application, the first intrinsic layer and the fifth intrinsic layer have the same thickness, both ranging from 2 nm to 10 nm; and / or,

[0025] The first intrinsic layer is an intrinsic hydrogenated amorphous silicon layer; and / or,

[0026] The fifth intrinsic layer is an intrinsic hydrogenated amorphous silicon layer or an intrinsic hydrogenated microcrystalline silicon layer.

[0027] In one or more embodiments of this application, the first intrinsic layer and the fifth intrinsic layer are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process, wherein the flow ratio of hydrogen to silane in the deposition process is greater than or equal to 10:1, and the thickness of both the first intrinsic layer and the fifth intrinsic layer is 2nm~3nm; or,

[0028] Both the first intrinsic layer and the fifth intrinsic layer are intrinsic hydrogenated amorphous silicon layers, and the thickness of both the first intrinsic layer and the fifth intrinsic layer is 5nm~10nm.

[0029] In one or more embodiments of this application, the tunneling layer is a silicon oxide layer or a silicon oxynitride layer with a thickness of 0.5 nm to 3 nm; and / or,

[0030] The second doped layer is an N-type doped polycrystalline silicon layer.

[0031] In one or more embodiments of this application, the surface of the crystalline silicon substrate in the first region is lower than the surface of the crystalline silicon substrate in the second region; and / or,

[0032] The surface of the crystalline silicon substrate in the third region is lower than the surface of the crystalline silicon substrate in the first region, or the surface of the crystalline silicon substrate in the third region is flush with the surface of the crystalline silicon substrate in the first region.

[0033] In one or more embodiments of this application, the composite passivated back contact battery further includes:

[0034] A first transparent conductive layer located on the first passivation structure, and a first electrode in contact with the first transparent conductive layer;

[0035] A second transparent conductive layer located on the second passivation structure, and a second electrode in contact with the second transparent conductive layer.

[0036] In one or more embodiments of this application, the first transparent conductive layer extends to cover the surface of the first intrinsic layer of the third region; and / or,

[0037] The first transparent conductive layer and the second transparent conductive layer are electrically isolated in the second region.

[0038] In one or more embodiments of this application, the first surface of the crystalline silicon substrate is a pyramid-structured textured surface in a first region; and / or,

[0039] The first surface of the crystalline silicon substrate is a polished surface in the second region; and / or,

[0040] The first surface of the crystalline silicon substrate has a pyramidal textured surface in the third region; and / or

[0041] The second surface of the crystalline silicon substrate is a pyramid-structured textured surface; and / or,

[0042] An antireflection layer is stacked on the first surface of the crystalline silicon substrate, the antireflection layer comprising one or more of an aluminum oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0043] A second aspect of this application provides a method for preparing a composite passivated back contact battery, comprising the following steps:

[0044] A crystalline silicon substrate is provided, including a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region spaced apart, and a third region located between the first region and the second region;

[0045] A second passivation structure is formed in the second region. The second passivation structure includes a second doped layer, and the doping type of the second doped layer is the same as the doping type of the crystalline silicon substrate.

[0046] A first passivation structure is formed in the first region, the first passivation structure including a first doped layer, the doping type of the first doped layer being opposite to the doping type of the crystalline silicon substrate;

[0047] A first intrinsic layer is formed in the third region, and the first intrinsic layer is in contact with the first doped layer and the second doped layer to block lateral leakage between the first doped layer and the second doped layer;

[0048] A first transparent conductive layer is formed on the first passivation structure, and a first electrode is formed on the first transparent conductive layer;

[0049] A second transparent conductive layer is formed on the second passivation structure, and a second electrode is formed on the second transparent conductive layer.

[0050] In one or more embodiments of this application, the formation of the second passivation structure includes:

[0051] A tunneling layer, an N-type doped polycrystalline silicon layer, and a mask layer are prepared on the first surface of the crystalline silicon substrate, and the doping elements are activated by an annealing process to form effective doping.

[0052] The mask layers of the first and third regions are removed by laser technology, and the tunneling layers and N-type doped polysilicon layers of the first and third regions are removed by wet process.

[0053] The mask layer in the second region is removed using a wet process.

[0054] In one or more embodiments of this application, the formation of the first passivation layer and the first intrinsic layer includes:

[0055] An intrinsic amorphous silicon layer and a P-type doped layer are prepared on the first surface;

[0056] The intrinsic amorphous silicon layer and P-type doped layer in the third region are removed by laser technology;

[0057] An intrinsic hydrogenated amorphous silicon layer is prepared on the first surface to form a third intrinsic layer in the first region and a first intrinsic layer in the third region.

[0058] In one or more embodiments of this application, an intrinsic hydrogenated amorphous silicon layer is prepared on the first surface using a PECVD process, wherein the flow ratio of hydrogen to silane in the PECVD process is greater than or equal to 10:1, and the deposition thickness is 2 nm to 3 nm; or,

[0059] An intrinsic hydrogenated amorphous silicon layer with a deposition thickness of 5 nm to 10 nm was prepared on the first surface using PECVD process. Then, the intrinsic hydrogenated amorphous silicon layer in the electrode region was subjected to laser crystallization treatment using laser process to transform the intrinsic hydrogenated amorphous silicon layer in the electrode region into an intrinsic hydrogenated microcrystalline silicon layer.

[0060] In one or more embodiments of this application, after removing the intrinsic amorphous silicon layer and the P-type doped layer in the third region by laser process, the method further includes:

[0061] The third area was cleaned with an alkaline solution, which included 1 wt% to 3 wt% KOH, 5 wt% to 8 wt% isopropanol, and 0.1 wt% to 0.5 wt% corrosion inhibitor.

[0062] In one or more embodiments of this application, the preparation method further includes:

[0063] The intrinsic amorphous silicon layer, P-type doped layer, and intrinsic hydrogenated amorphous silicon layer on the second passivation structure are partially removed by laser technology, forming an electrode window in the middle region of the second region and forming a third passivation structure in the outer peripheral region of the second region.

[0064] In one or more embodiments of this application, the preparation method further includes:

[0065] A transparent conductive layer is prepared on the first surface, and the transparent conductive layer is isolated in the outer peripheral region of the second region to form a first transparent conductive layer in contact with the first passivation structure and a second transparent conductive layer in contact with the second passivation structure; and / or,

[0066] An antireflection layer is prepared on the second surface, the antireflection layer comprising one or more of an alumina layer, a silicon oxynitride layer, and a silicon nitride layer; and / or,

[0067] Alkali texturing is performed on the first and third regions of the first surface and the second surface to form a pyramid-structured texturing surface.

[0068] A third aspect of this application provides a photovoltaic module, the photovoltaic module comprising:

[0069] A battery string, said battery string being formed by electrically connecting multiple composite passivated back contact batteries as described above; and,

[0070] An encapsulation layer that covers the surface of the battery string.

[0071] Compared with the prior art, this application introduces a third region on the first surface of a crystalline silicon substrate and forms an intrinsic layer thereon. The third region achieves physical isolation between two semiconductor layers with different conductivity types, thereby blocking lateral leakage on the first surface and avoiding PN short circuits. The intrinsic layer can repair damage during the formation of the third region and improve passivation effect, thereby improving battery efficiency and reducing the risk of hot spots. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1This is a schematic diagram of the structure of a composite passivated back contact battery in the prior art;

[0074] Figure 2 This is a schematic diagram of the structure of a composite passivated back contact battery in one embodiment of this application;

[0075] Figure 3 for Figure 2 Enlarged view of the local structure at point A;

[0076] Figure 4 This is a schematic diagram of the structure of a composite passivated back contact battery in one embodiment of this application;

[0077] Figure 5 for Figure 4 Enlarged view of the local structure at point B;

[0078] Figure 6 This is a schematic diagram of the structure of a composite passivated back contact battery in one embodiment of this application;

[0079] Figure 7 for Figure 6 Enlarged view of the local structure at point C;

[0080] Figures 8a to 8f This is a flowchart illustrating the fabrication process of a composite passivated back contact battery in one embodiment of this application.

[0081] Explanation of key figure labels:

[0082] 10-Crystal silicon substrate, 21-First intrinsic layer, 22-Second intrinsic layer, 23-Third intrinsic layer, 24-Fourth intrinsic layer, 25-Fifth intrinsic layer, 31-First doped layer, 32-Second doped layer, 33-Third doped layer, 40-Tunneling layer, 51-First transparent conductive layer, 52-Second transparent conductive layer, 53-Isolation trench, 61-First electrode, 62-Second electrode, 70-Antireflection layer;

[0083] S1 - First surface, S2 - Second surface, S11 - First region, S12 - Second region, S13 - Third region. Detailed Implementation

[0084] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0085] In the present application, unless otherwise explicitly specified and defined, when a first feature is "on" or "under" a second feature, the first and second features may be in direct contact, or the first and second features may be in indirect contact via an intermediate medium. Furthermore, when the first feature is "above", "over" and "on" the second feature, it may mean that the first feature is directly or obliquely above the second feature, or merely indicates that the horizontal level of the first feature is higher than that of the second feature. When the first feature is "below", "beneath" and "under" the second feature, it may mean that the first feature is directly or obliquely below the second feature, or merely indicates that the horizontal level of the first feature is lower than that of the second feature.

[0086] In the present application, unless otherwise explicitly specified and defined, the disclosed "range" is defined in the form of a lower limit and / or an upper limit, a given range is defined by selecting one lower limit and / or one upper limit, and the selected lower limit and / or upper limit define the boundaries of the specific range. A range defined in this manner may be inclusive or exclusive of the endpoints, and may be arbitrarily combined, that is, any lower limit may be combined with any upper limit to form a range not explicitly stated, any lower limit may be combined with other lower limits to form a range not explicitly stated, and similarly any upper limit may be combined with any other upper limit to form a range not explicitly stated. In addition, each individually disclosed point or single numerical value may itself serve as a lower limit or upper limit to combine with any other point or single numerical value, or combine with other lower limits or upper limits to form a range not explicitly stated.

[0087] In the present application, the term "and / or" is merely an association relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the presence of A alone, the simultaneous presence of A and B, and the presence of B alone. In addition, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.

[0088] In the present application, unless otherwise explicitly specified and defined, all embodiments and optional embodiments, or all technical features and optional technical features may be combined with each other to form new technical solutions, and such technical solutions shall be deemed to be included in the disclosure of the present application.

[0089] Reference Figure 1 shows a schematic structural diagram of a composite passivation back contact cell in the prior art, in which both the P-type region and the N-type region are distributed on the back surface of the crystalline silicon substrate 10. In the P-type region, a low-temperature amorphous silicon passivation structure in an HJT cell, that is, an intrinsic amorphous silicon layer 21' and a P-type doped microcrystalline silicon layer 31', is adopted, which can effectively reduce interface recombination and increase voltage; in the N-type region, a high-temperature polysilicon passivation structure in a TOPCon cell, that is, a tunneling layer 22' and an N-type doped polysilicon layer 32', is adopted, which can ensure excellent electron selection and collection capability and reduce resistance.

[0090] In the prior art, the intrinsic amorphous silicon layer 21' and the P-type doped microcrystalline silicon layer 31' in the P-type region will partially extend into the N-type region. The distance between the P-type doped microcrystalline silicon layer 31' and the N-type doped polycrystalline silicon layer 32' is usually only tens to hundreds of micrometers. As long as there is a slight deviation in the process (such as photolithography misalignment, laser damage, etc.), these two semiconductor layers with opposite conductivity may directly contact each other or form ion channels, thereby causing leakage.

[0091] Based on the above issues, the applicant redefined the back area of ​​the battery, separating the P-type and N-type regions on the back through an isolation zone, and using an intrinsic layer to passivate the isolation zone. This physically disconnects the possible electrical connection between the P-type and N-type regions, blocking lateral leakage on the back of the battery. The intrinsic layer can repair damage during the formation of the isolation zone and improve the passivation effect.

[0092] Specifically, participants Figure 2 and combined Figure 3 As shown, a composite passivated back contact battery in one embodiment of this application includes:

[0093] The crystalline silicon substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 includes a first region S11 and a second region S12 that are spaced apart, and a third region S13 located between the first region S11 and the second region S12.

[0094] The first passivation structure is located in the first region S11. The first passivation structure includes a first doped layer 31, and the doping type of the first doped layer 31 is opposite to the doping type of the crystalline silicon substrate 10.

[0095] The second passivation structure is located in the second region S12. The second passivation structure includes a second doped layer 32, and the doping type of the second doped layer 32 is the same as that of the crystalline silicon substrate 10.

[0096] The first intrinsic layer 21 is located in the third region S13. The first intrinsic layer 21 is in contact with the first doped layer 31 and the second doped layer 32 to block the lateral leakage between the first doped layer 31 and the second doped layer 32.

[0097] A first transparent conductive layer 51 located on the first passivation structure, and a first electrode 61 in contact with the first transparent conductive layer 51;

[0098] The second transparent conductive layer 52 is located on the second passivation structure, and the second electrode 62 is in contact with the second transparent conductive layer 52.

[0099] In this application, a third region S13 is introduced between the first region S11 and the second region S12. This third region S13 physically isolates the first doped layer 31 and the second doped layer 32, two semiconductor layers with different conductivity types, thereby blocking lateral leakage on the first surface and preventing PN short circuits. Incomplete isolation leading to a PN short circuit will directly result in recombination losses, severely impacting battery performance.

[0100] In some embodiments of this application, in order to ensure the isolation effect between the first doped layer 31 and the second doped layer 32, the width of the third region S13 needs to be no less than 5 μm; in addition, since the third region S13 is a separate isolation region, this region does not belong to the battery power generation region and will not generate photogenerated carriers. In order to ensure battery efficiency, the width of the third region S13 needs to be no more than 50 μm.

[0101] Therefore, the preferred width of the third region S13 in this application is 5μm to 50μm, for example, it can be 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, etc., but is not limited to the listed values. Other unlisted values ​​within the range are also applicable. This ensures PN isolation effect and a high effective power generation area.

[0102] In some embodiments of this application, the material of the crystalline silicon substrate 10 can be an N-type, P-type, or intrinsic crystalline silicon substrate, such as a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. Cells based on monocrystalline silicon substrates have higher conversion efficiency compared to other types, such as polycrystalline silicon cells. An N-type crystalline silicon substrate is obtained by introducing donor impurities such as group VA elements (nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.) or group VIA elements (oxygen (O), sulfur (S), selenium (Se), tellurium (Te), etc.) into these semiconductor materials. Alternatively, a P-type crystalline silicon substrate is obtained by introducing acceptor impurities such as group IIIA elements (boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc.) into these semiconductor materials.

[0103] In some embodiments of this application, the thickness of the crystalline silicon substrate 10 can be 30 μm to 500 μm, for example, 30 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. If the thickness is too thin, it is not conducive to improving light utilization; if it is too thick, carrier recombination will occur due to the limitation of the diffusion distance of photogenerated carriers, thus contributing nothing to the current.

[0104] In some embodiments of the present application, the first surface S1 of the crystalline silicon substrate 10 may be the back surface of the cell, and the second surface S2 may be the front surface of the cell. In general, the front surface of the cell serves as the light-receiving surface, and the back surface of the cell serves as the backlight surface, or the cell may be of a double-sided light-receiving type, in which case both the front surface and the back surface serve as light-receiving surfaces.

[0105] Optionally, the first region S11 and the second region S12 are distributed in an interdigitated pattern respectively, and the interdigitated region distribution is a prior art in IBC (Interdigitated Back Contact) cells, which will not be elaborated herein.

[0106] Refe Figure 2 ring to and in conjunction with Figure 3 the illustration, the first passivation structure comprises at least one second intrinsic layer 22, at least one first doped layer 31, and a third intrinsic layer 23 stacked in a direction away from the crystalline silicon substrate 10, wherein the first intrinsic layer 21 covers the side surfaces of the second intrinsic layer 22 and the first doped layer 31 and is connected to the third intrinsic layer 23.

[0107] The first passivation structure in the present application is a low-temperature amorphous silicon passivation structure in an HJT cell. Taking an N-type crystalline silicon substrate as an example, the second intrinsic layer 22 may be an intrinsic amorphous silicon layer or an intrinsic hydrogenated amorphous silicon layer, with a thickness of 5 nm to 10 nm; the first doped layer 31 is a P-type doped hydrogenated amorphous silicon layer or hydrogenated microcrystalline silicon layer, with a thickness of 20 nm to 40 nm and a doping concentration of 1E17 cm -3 ~1E20 cm -3 .

[0108] The third region S13 in the present application usually needs to be formed by a laser process or the like, and a certain degree of damage will be caused to this region during the formation process of the third region S13, resulting in the loss of cell performance. The first intrinsic layer 21 can cover the third region S13 processed by the laser process, so that a high-quality passivation contact is formed between the first intrinsic layer 21 and the crystalline silicon substrate 10, which effectively suppresses the recombination of photogenerated carriers caused by laser ablation, and significantly improves the passivation performance of the third region S13.

[0109] In some embodiments of the present application, the first intrinsic layer 21 is an intrinsic hydrogenated amorphous silicon layer, and its thickness D1 is 2 nm to 10 nm, for example, may be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc., but is not limited to the listed values, and other unlisted values within the numerical range are also applicable.

[0110] In some embodiments of this application, both the first intrinsic layer 21 and the third intrinsic layer 23 are intrinsic hydrogenated amorphous silicon layers, and the thickness D1 of the first intrinsic layer 21 and the thickness D2 of the third intrinsic layer 23 are the same, both ranging from 2 nm to 10 nm. In other embodiments, the materials and thicknesses of the first intrinsic layer 21 and the third intrinsic layer 23 may be different.

[0111] In some embodiments of this application, the first intrinsic layer 21 and the third intrinsic layer 23 are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process (such as PECVD). In the deposition process, the flow ratio of hydrogen to silane is greater than or equal to 10:1, for example, it can be 10:1, 20:1, 30:1, etc. The thickness of both the first intrinsic layer 21 and the third intrinsic layer 23 is 2nm to 3nm, for example, it can be 2nm, 2.5nm, 3nm, etc. The intrinsic hydrogenated amorphous silicon layer deposited using this process is relatively thin, which can satisfy the requirement of good tunneling performance between the third intrinsic layer 23 and the first transparent conductive layer 51.

[0112] In some embodiments of this application, the first intrinsic layer 21 and the third intrinsic layer 23 are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process (such as PECVD). The thickness of both the first intrinsic layer 21 and the third intrinsic layer 23 is 5nm~10nm, for example, 6nm, 7nm, 8nm, 9nm, 10nm, etc. The intrinsic hydrogenated amorphous silicon layer deposited by this process is relatively thick, which can ensure that the third region S13 has good passivation performance. In addition, in order to improve conductivity and reduce tunneling in the electrode region, a laser process is used to perform laser crystallization treatment on the intrinsic hydrogenated amorphous silicon layer in the electrode region, transforming the intrinsic hydrogenated amorphous silicon layer in the electrode region into an intrinsic hydrogenated microcrystalline silicon layer.

[0113] Continue to participate Figure 2 , Figure 3 As shown, the second passivation structure includes at least one tunneling layer 40 and at least one second doped layer 32 stacked along the direction away from the crystalline silicon substrate 10, and the first intrinsic layer 21 covers the sides of the tunneling layer 40 and the second doped layer 32.

[0114] The second passivation structure in this application is a high-temperature polycrystalline silicon passivation structure in TOPCon cells. Taking an N-type crystalline silicon substrate as an example, the second doped layer 32 is an N-type doped polycrystalline silicon layer with a thickness of 60nm~300nm and a doping concentration of 1E20cm⁻¹. -3 ~1E22cm -3 The tunneling layer can provide good interface passivation effect. It can be one or more of oxide layers such as silicon oxide layer and silicon oxynitride layer, preferably silicon oxide layer, with a thickness of 0.5nm~3nm, more preferably 1nm~2nm, for example, it can be 1nm, 1.5nm, 2nm, etc.

[0115] Furthermore, in some embodiments, the second region S12 further includes a third passivation structure. The surface of the second passivation structure away from the crystalline silicon substrate 10 includes a middle region and an outer peripheral region. The third passivation structure is located in the outer peripheral region, and an electrode window not covered by the third passivation structure is formed on the surface of the second passivation structure. By forming a third passivation structure outside the second passivation structure, the passivation performance of the second region S12 can be further improved while ensuring PN isolation.

[0116] Specifically, the third passivation structure includes at least one fourth intrinsic layer 24, at least one third doped layer 33, and a fifth intrinsic layer 25 stacked along the direction away from the crystalline silicon substrate 10. The doping type of the third doped layer 33 is opposite to the doping type of the crystalline silicon substrate 10. The first intrinsic layer 21 covers the sides of the fourth intrinsic layer 24 and the third doped layer 33 and is connected to the fifth intrinsic layer 25.

[0117] In some embodiments of this application, both the first intrinsic layer 21 and the fifth intrinsic layer 25 are intrinsic hydrogenated amorphous silicon layers, and the thickness D1 of the first intrinsic layer 21 and the thickness D3 of the fifth intrinsic layer 25 are the same, both ranging from 2 nm to 10 nm. In other embodiments, the materials and thicknesses of the first intrinsic layer 21 and the fifth intrinsic layer 25 may be different.

[0118] In some embodiments of this application, the first intrinsic layer 21 and the fifth intrinsic layer 25 are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process (such as PECVD process). In the deposition process, the flow ratio of hydrogen to silane is greater than or equal to 10:1, for example, it can be 10:1, 20:1, 30:1, etc. The thickness of the first intrinsic layer 21 and the fifth intrinsic layer 25 is 2nm~3nm, for example, it can be 2nm, 2.5nm, 3nm, etc.

[0119] In some embodiments of this application, the first intrinsic layer 21 and the fifth intrinsic layer 25 are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process (such as PECVD). The thickness of both the first intrinsic layer 21 and the fifth intrinsic layer 25 is 5nm to 10nm, for example, 6nm, 7nm, 8nm, 9nm, 10nm, etc. The intrinsic hydrogenated amorphous silicon layer deposited by this process is relatively thick, which can ensure that the third region S13 has good passivation performance.

[0120] In some other embodiments of this application, the first intrinsic layer 21, the third intrinsic layer 23 and the fifth intrinsic layer can be formed by a one-step deposition process, the second intrinsic layer 22 and the fourth intrinsic layer 24 can be formed by a one-step deposition process, and the first doped layer 31 and the third doped layer 33 can be formed by a one-step deposition process.

[0121] In some embodiments of the present application, the first transparent conductive layer 51 is at least located on the third intrinsic layer 23 in the first region S11, and may further extend to cover the surface of the first intrinsic layer 21 in the third region S13. The first electrode 61 is in electrical contact with the first transparent conductive layer 51 in the first region S11. The second transparent conductive layer 52 is at least located in the electrode window of the second region S12, and the second electrode 62 is in electrical contact with the second transparent conductive layer 52 in the second region S12.

[0122] In some embodiments of the present application, the first transparent conductive layer 51 and the second transparent conductive layer 52 may be transparent conductive oxide layers, for example, one or more of ITO, AZO, IWO and the like. The first electrode 61 and the second electrode 62 are metal grid line electrodes, and the material thereof may be Ag or Ag / Cu alloy.

[0123] In some embodiments of the present application, an isolation trench 53 is formed in the second region S12 between the first transparent conductive layer 51 and the second transparent conductive layer 52. The arrangement of the isolation trench 53 can isolate the first transparent conductive layer 51 and the second transparent conductive layer 52, so as to avoid a short circuit between the two electrodes. The depth of the isolation trench 53 is greater than or equal to the thickness of the transparent conductive layer, and the width is 20 μm to 100 μm. In some other embodiments, the isolation trench 53 may also be formed in the first region S11, or formed in the third region S13.

[0124] Further, an insulating layer (not shown) is formed in all or part of the region inside the isolation trench 53, and the isolation effect can be further improved by the arrangement of the insulating layer. Preferably, the isolation trench 53 extends to the surface of the fifth intrinsic layer 25, and an extremely thin (with a thickness of about 1 nm) natural oxide layer (i.e., a silicon oxide layer) is formed on the bottom wall and the side wall of the isolation trench 53.

[0125] In some embodiments of the present application, the second surface S2 of the crystalline silicon substrate 10 is the front surface of the cell, and an anti-reflection layer 70 is stacked on the second surface S2. The anti-reflection layer 70 includes one or more of an aluminum oxide layer, a silicon oxynitride layer, and a silicon nitride layer. Exemplarily, one aluminum oxide layer, one silicon nitride layer and one silicon oxynitride layer are sequentially stacked on the second surface S2, the thickness of the aluminum oxide layer is 2 nm to 10 nm, and the total thickness of the silicon nitride layer and the silicon oxynitride layer is 50 nm to 100 nm.

[0126] Refe Figure 3 as shown, in some embodiments of the present application, the surface of the crystalline silicon substrate 10 in the first region S11 is lower than the surface of the crystalline silicon substrate 10 in the second region S12, and the height difference between the two is H1, which is usually formed by a wet process. The surface of the crystalline silicon substrate 10 in the third region S13 is flush with the surface of the crystalline silicon substrate 10 in the first region S11.

[0127] Refe Figure 4 in conjunction with Figure 5 As shown, in some other embodiments of the present application, the surface of the crystalline silicon substrate 10 in the first region S11 is lower than the surface of the crystalline silicon substrate 10 in the second region S12, with a height difference H1 therebetween, and this height difference H1 is usually formed by a wet process. The surface of the crystalline silicon substrate 10 in the third region S13 is lower than the surface of the crystalline silicon substrate 10 in the first region S11, with a height difference H2 therebetween, and this height difference H2 is usually formed by a laser process, wherein a part of the crystalline silicon substrate is removed during the process of forming the isolation region by using the laser process.

[0128] See Figure 2 , Figure 4 As shown, each region of the first surface S1 and the second surface S2 of the crystalline silicon substrate 10 are described by taking a polished surface as an example. See Figure 6 in conjunction with Figure 7 As shown, in some other embodiments, the first region S11 and the third region S13 of the first surface as well as the second surface S2 may be subjected to an alkali texturing process to form a textured surface with a pyramid structure, where the pyramid has a bottom width of 0.5 μm to 5 μm and a pyramid height of 0.5 μm to 5 μm.

[0129] See Figure 3 As shown, when the third region S13 is a polished surface, D1 refers to the thickness of the first intrinsic layer 21 along the thickness direction of the crystalline silicon substrate 10, while see Figure 7 As shown, when the third region S13 is a textured surface with a pyramid structure, D1 refers to the thickness of the first intrinsic layer along the surface of the pyramid.

[0130] Take Figure 6 As shown, the composite passivated back contact cell is taken as an example, and the preparation method thereof comprises the following steps:

[0131] providing a crystalline silicon substrate 10;

[0132] forming a second passivation structure in the second region S12, wherein the second passivation structure comprises a second doped layer 32, and the doping type of the second doped layer 32 is the same as the doping type of the crystalline silicon substrate 10;

[0133] forming a first passivation structure in the first region S11, wherein the first passivation structure comprises a first doped layer 31, and the doping type of the first doped layer 31 is opposite to the doping type of the crystalline silicon substrate 10;

[0134] forming a first intrinsic layer 21 in the third region S13, wherein the first intrinsic layer 21 is in contact with the first doped layer 31 and the second doped layer 32;

[0135] forming a first transparent conductive layer 51 on the first passivation structure, and forming a first electrode 61 on the first transparent conductive layer 51;

[0136] A second transparent conductive layer 52 is formed on the second passivation structure, and a second electrode 62 is formed on the second transparent conductive layer 52.

[0137] The following detailed explanation of each step in the preparation method is provided with specific examples.

[0138] Step 1: First, select an N-type silicon wafer and polish it on both sides.

[0139] For example, the back side of the silicon wafer is polished with a KOH alkaline solution and then acid-washed with HF to remove oxides, forming a smooth surface.

[0140] Step 2: Prepare a second passivation structure in the second region S12, including:

[0141] 1. A tunneling layer, an N-type doped polycrystalline silicon layer, and a mask layer (not shown) are prepared on the first surface S1 of the crystalline silicon substrate 10, and the doping elements are activated by an annealing process to form effective doping.

[0142] For example, a tunneling layer and a phosphorus-doped polycrystalline silicon layer are first grown or deposited on the front and back sides of an N-type silicon wafer. Generally, LPCVD is used to grow the tunneling layer and deposit the intrinsic amorphous silicon layer. Then, phosphorus diffusion is performed to form a phosphorus-doped amorphous silicon layer and a PSG layer, with the PSG layer serving as a mask layer.

[0143] Then, the amorphous silicon layer is annealed in an annealing furnace to form a polycrystalline silicon layer. Oxygen is introduced during the annealing process, and the annealing temperature is 850℃. Annealing can activate the phosphorus dopant from interstitial phosphorus to substituted phosphorus, forming an effective dopant.

[0144] Finally, the PSG layer is removed from one side, and the oxide layer on the second surface is removed using an HF solution diluted to a concentration of 5wt%~10wt%.

[0145] 2. The mask layers of the first region S11 and the third region S13 are removed by laser processing, and the tunneling layers and N-type doped polysilicon layers of the first region S11 and the third region S13 are removed by wet processing to obtain... Figure 8a The structure shown.

[0146] For example, the first region S11 and the third region S13 are patterned by laser process, with a laser wavelength of 495nm~570nm, preferably 532nm, a laser frequency of 500kHz, a power of 11W, a scanning rate of 35m / s, and a point overlap rate of 10%~15%.

[0147] 3. The mask layer of the second region S12 is removed by a wet process, that is, the PSG layer on the surface of the second doped layer 32 is removed.

[0148] For example, an acid washing process is used to remove the PSG layers on the back and sides, leaving the tunneling layer 40 and the second doped layer 32 on the back.

[0149] Step 3, refer Figure 8b As shown, the first region S11, the third region S13, and the second surface S2 of the first surface S1 are texturized.

[0150] The wet process in this step is a texturing process, which uses KOH or NaOH alkaline solution to utilize the anisotropic etching characteristics of crystalline silicon to form a pyramid-shaped textured surface in the first region S11 and the third region S13 of the first surface S1 and the second surface S2. The width of the pyramid base is 0.5μm~5μm and the height of the pyramid is 0.5μm~5μm.

[0151] Step 3, refer Figure 8c As shown, an antireflection layer 70 is prepared on the second surface S2.

[0152] For example, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer are sequentially stacked on the second surface S2 using a tubular PECVD or PVD equipment. The thickness of the aluminum oxide layer is 2nm to 10nm, and the total thickness of the silicon nitride layer and the silicon oxynitride layer is 50nm to 100nm.

[0153] In some embodiments, the mask layer and the anti-reflection layer 70 are simultaneously deposited around the first surface and the side surface. The pickling process in step 2 can be performed after the anti-reflection layer 70 is deposited, which can simultaneously remove the PSG layer and the anti-reflection layer deposited around the first surface S1 and the side surface.

[0154] Step 4, refer Figure 8d , 8e As shown, a first passivation structure and a first intrinsic layer 21 are formed on the first surface S1, including:

[0155] 1. An intrinsic amorphous silicon layer and a P-type doped layer are prepared on the first surface S1.

[0156] For example, silane gas is introduced into a vacuum chamber, and an intrinsic amorphous silicon layer is formed over the entire area of ​​the first surface using a PECVD process. Then, SiH4 gas, H2 gas, and B2H6 (diborane) gas are introduced into the vacuum chamber, and a boron-doped microcrystalline silicon layer is formed on the intrinsic amorphous silicon layer using a PECVD process.

[0157] 2. The intrinsic amorphous silicon layer and boron-doped microcrystalline silicon layer in the third region S13 are removed by laser technology.

[0158] The width of the third region S13 is 5μm~50μm, which can ensure PN isolation effect and a high effective power generation area.

[0159] 3. An intrinsic hydrogenated amorphous silicon layer is prepared on the first surface S1 to form a third intrinsic layer 23 in the first region S1 and a first intrinsic layer 21 in the third region S13.

[0160] Optionally, an intrinsic hydrogenated amorphous silicon layer is prepared on the first surface using a PECVD process, wherein the flow ratio of hydrogen to silane in the PECVD process is greater than or equal to 10:1, and the deposition thickness is 2nm~3nm.

[0161] Optionally, an intrinsic hydrogenated amorphous silicon layer is prepared on the first surface using PECVD process, with a deposition thickness of 5nm~10nm. Then, the intrinsic hydrogenated amorphous silicon layer in the electrode region is subjected to laser crystallization treatment using laser process to transform the intrinsic hydrogenated amorphous silicon layer in the electrode region into an intrinsic hydrogenated microcrystalline silicon layer.

[0162] 4. Laser local windowing: The intrinsic amorphous silicon layer, P-type doped layer and intrinsic hydrogenated amorphous silicon layer on the second passivation structure are removed by laser process. An electrode window is formed in the middle region of the second region S12, while the intrinsic amorphous silicon layer, P-type doped layer and intrinsic hydrogenated amorphous silicon layer are retained in the outer periphery of the second region S12.

[0163] Step 5: Clean the third region S13 with an alkaline solution, which includes 1wt%~3wt% KOH, 5wt%~8wt% isopropanol and 0.1%wt%~0.5wt% corrosion inhibitor.

[0164] By using an alkaline solution to etch away the laser-residual oxide, intrinsic layer, and microcrystalline silicon layer, the second doped layer 32 can form a good contact with the transparent conductive layer.

[0165] Step 6, refer to Figure 8f As shown, a transparent conductive layer is prepared on the first surface S1, and the transparent conductive layer is isolated in the outer peripheral region of the second region S12 to form a first transparent conductive layer 51 in contact with the first passivation structure and a second transparent conductive layer 52 in contact with the second passivation structure; then a first electrode 61 and a second electrode 62 are prepared on the first transparent conductive layer 51 and the second transparent conductive layer 52, respectively.

[0166] For example, the transparent conductive layer is deposited by magnetron sputtering, and a portion of the transparent conductive layer at the PN junction is removed by laser process / screen printing etchant to form an isolation trench 53.

[0167] The electrodes are prepared using a screen printing process. First, a layer of low-temperature conductive silver paste is printed, and then sintered and cured at a low temperature of 150℃~300℃ to form a good ohmic contact.

[0168] This application also provides a photovoltaic module, including: a plurality of the above-mentioned composite passivated back contact cells connected in series to form a solar cell string; an interconnecting member electrically connected to the above-mentioned composite passivated back contact cells to connect the above-mentioned composite passivated back contact cells to form a solar cell string; and an encapsulation layer covering the surface of the plurality of composite passivated back contact cells.

[0169] In some embodiments of this application, the interconnecting components can be solder ribbons, metal wires, conductive tapes, etc.; the encapsulation layer can include a backplate, encapsulating film, cover plate, etc., to improve the stability of the back contact battery string. The cover plate is located on the front of the solar cell string, and the backplate is located on the back of the solar cell string, both serving a protective function; the adhesive film is the adhesive film between the solar cell string and the cover plate and backplate, serving a bonding and fixing function, and must be made of a transparent material.

[0170] In some examples, the encapsulating film can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. In some examples, the cover or backing plate can be a light-transmitting film layer such as a glass cover or a plastic cover.

[0171] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0172] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A composite passivated back contact battery, characterized in that, The composite passivated back contact battery includes: A crystalline silicon substrate includes a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region spaced apart, and a third region located between the first region and the second region; A first passivation structure located in the first region, the first passivation structure including a first doped layer, the doping type of the first doped layer being opposite to the doping type of the crystalline silicon substrate; A second passivation structure located in the second region, the second passivation structure including a second doped layer, the doping type of the second doped layer being the same as the doping type of the crystalline silicon substrate; The first intrinsic layer is located in the third region and is in contact with the first doped layer and the second doped layer to block lateral leakage between the first doped layer and the second doped layer.

2. The composite passivated back contact battery according to claim 1, characterized in that, The width of the third region is 5μm to 50μm.

3. The composite passivated back contact battery according to claim 1, characterized in that, The first passivation structure includes at least one second intrinsic layer, at least one first doped layer, and a third intrinsic layer stacked along the direction away from the crystalline silicon substrate. The first intrinsic layer covers the sides of the second intrinsic layer and the first doped layer and is connected to the third intrinsic layer.

4. The composite passivated back contact battery according to claim 3, characterized in that, The first intrinsic layer and the third intrinsic layer have the same thickness, both ranging from 2 nm to 10 nm; and / or, The first intrinsic layer is an intrinsic hydrogenated amorphous silicon layer; and / or, The third intrinsic layer is an intrinsic hydrogenated amorphous silicon layer or an intrinsic hydrogenated microcrystalline silicon layer.

5. The composite passivated back contact battery according to claim 3, characterized in that, The first intrinsic layer and the third intrinsic layer are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process, wherein the flow ratio of hydrogen to silane in the deposition process is greater than or equal to 10:1, and the thickness of both the first intrinsic layer and the third intrinsic layer is 2nm~3nm; or, The first intrinsic layer is an intrinsic hydrogenated amorphous silicon layer, and the third intrinsic layer is an intrinsic hydrogenated microcrystalline silicon layer at least in the electrode region. The thickness of both the first intrinsic layer and the third intrinsic layer is 5 nm to 10 nm.

6. The composite passivated back contact battery according to claim 3, characterized in that, The second intrinsic layer is an intrinsic amorphous silicon layer or an intrinsic hydrogenated amorphous silicon layer; and / or, The first doped layer is a P-type doped hydrogenated amorphous silicon layer or a hydrogenated microcrystalline silicon layer.

7. The composite passivated back contact battery according to claim 1, characterized in that, The second passivation structure includes at least one tunneling layer and at least one second doped layer stacked along a direction away from the crystalline silicon substrate, wherein the first intrinsic layer covers the sides of the tunneling layer and the second doped layer.

8. The composite passivated back contact battery according to claim 7, characterized in that, The second passivation structure has a middle region and an outer peripheral region on the side surface away from the crystalline silicon substrate, and a third passivation structure is stacked on the outer peripheral region.

9. The composite passivated back contact battery according to claim 8, characterized in that, The third passivation structure includes at least one fourth intrinsic layer, at least one third doped layer, and a fifth intrinsic layer stacked along the direction away from the crystalline silicon substrate. The doping type of the third doped layer is opposite to the doping type of the crystalline silicon substrate. The first intrinsic layer covers the sides of the fourth and third intrinsic layers and is connected to the fifth intrinsic layer.

10. The composite passivated back contact battery according to claim 9, characterized in that, The first intrinsic layer and the fifth intrinsic layer have the same thickness, both ranging from 2 nm to 10 nm; and / or, The first intrinsic layer is an intrinsic hydrogenated amorphous silicon layer; and / or, The fifth intrinsic layer is an intrinsic hydrogenated amorphous silicon layer or an intrinsic hydrogenated microcrystalline silicon layer.

11. The composite passivated back contact battery according to claim 9, characterized in that, The first intrinsic layer and the fifth intrinsic layer are intrinsic hydrogenated amorphous silicon layers formed by a one-step deposition process, wherein the flow ratio of hydrogen to silane in the deposition process is greater than or equal to 10:1, and the thickness of both the first intrinsic layer and the fifth intrinsic layer is 2nm~3nm; or, Both the first intrinsic layer and the fifth intrinsic layer are intrinsic hydrogenated amorphous silicon layers, and the thickness of both the first intrinsic layer and the fifth intrinsic layer is 5nm~10nm.

12. The composite passivated back contact battery according to claim 7, characterized in that, The tunneling layer is a silicon oxide layer or a silicon oxynitride layer with a thickness of 0.5 nm to 3 nm; and / or, The second doped layer is an N-type doped polycrystalline silicon layer.

13. The composite passivated back contact battery according to claim 1, characterized in that, The surface of the crystalline silicon substrate in the first region is lower than the surface of the crystalline silicon substrate in the second region; and / or, The surface of the crystalline silicon substrate in the third region is lower than the surface of the crystalline silicon substrate in the first region, or the surface of the crystalline silicon substrate in the third region is flush with the surface of the crystalline silicon substrate in the first region.

14. The composite passivated back contact battery according to claim 1, characterized in that, The composite passivated back contact battery also includes: A first transparent conductive layer located on the first passivation structure, and a first electrode in contact with the first transparent conductive layer; A second transparent conductive layer located on the second passivation structure, and a second electrode in contact with the second transparent conductive layer.

15. The composite passivated back contact battery according to claim 14, characterized in that, The first transparent conductive layer extends to cover the surface of the first intrinsic layer in the third region; and / or, The first transparent conductive layer and the second transparent conductive layer are electrically isolated in the second region.

16. The composite passivated back contact battery according to claim 1, characterized in that, The first surface of the crystalline silicon substrate is a pyramidal textured surface in the first region; and / or... The first surface of the crystalline silicon substrate is a polished surface in the second region; and / or, The first surface of the crystalline silicon substrate has a pyramidal textured surface in the third region; and / or The second surface of the crystalline silicon substrate is a pyramid-structured textured surface; and / or, An antireflection layer is stacked on the first surface of the crystalline silicon substrate, the antireflection layer comprising one or more of an aluminum oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

17. A method for preparing a composite passivated back contact battery, characterized in that, Includes the following steps: A crystalline silicon substrate is provided, including a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region spaced apart, and a third region located between the first region and the second region; A second passivation structure is formed in the second region. The second passivation structure includes a second doped layer, and the doping type of the second doped layer is the same as the doping type of the crystalline silicon substrate. A first passivation structure is formed in the first region, the first passivation structure including a first doped layer, the doping type of the first doped layer being opposite to the doping type of the crystalline silicon substrate; A first intrinsic layer is formed in the third region, and the first intrinsic layer is in contact with the first doped layer and the second doped layer to block lateral leakage between the first doped layer and the second doped layer; A first transparent conductive layer is formed on the first passivation structure, and a first electrode is formed on the first transparent conductive layer; A second transparent conductive layer is formed on the second passivation structure, and a second electrode is formed on the second transparent conductive layer.

18. The method for preparing a composite passivated back contact battery according to claim 17, characterized in that, The formation of the second passivation structure includes: A tunneling layer, an N-type doped polycrystalline silicon layer, and a mask layer are prepared on the first surface of the crystalline silicon substrate, and the doping elements are activated by an annealing process to form effective doping. The mask layers of the first and third regions are removed by laser technology, and the tunneling layers and N-type doped polysilicon layers of the first and third regions are removed by wet process. The mask layer in the second region is removed using a wet process.

19. The method for preparing a composite passivated back contact battery according to claim 17, characterized in that, The formation of the first passivation layer and the first intrinsic layer includes: An intrinsic amorphous silicon layer and a P-type doped layer are prepared on the first surface; The intrinsic amorphous silicon layer and P-type doped layer in the third region are removed by laser technology; An intrinsic hydrogenated amorphous silicon layer is prepared on the first surface to form a third intrinsic layer in the first region and a first intrinsic layer in the third region.

20. The method for preparing a composite passivated back contact battery according to claim 19, characterized in that, An intrinsic hydrogenated amorphous silicon layer is prepared on the first surface using a PECVD process, wherein the flow ratio of hydrogen to silane in the PECVD process is greater than or equal to 10:1, and the deposition thickness is 2 nm to 3 nm; or, An intrinsic hydrogenated amorphous silicon layer with a deposition thickness of 5 nm to 10 nm was prepared on the first surface using PECVD process. Then, the intrinsic hydrogenated amorphous silicon layer in the electrode region was subjected to laser crystallization treatment using laser process to transform the intrinsic hydrogenated amorphous silicon layer in the electrode region into an intrinsic hydrogenated microcrystalline silicon layer.

21. The method for preparing a composite passivated back contact battery according to claim 19, characterized in that, After removing the intrinsic amorphous silicon layer and P-type doped layer in the third region using laser technology, the process also includes: The third area was cleaned with an alkaline solution, which included 1 wt% to 3 wt% KOH, 5 wt% to 8 wt% isopropanol, and 0.1 wt% to 0.5 wt% corrosion inhibitor.

22. The method for preparing a composite passivated back contact battery according to claim 19, characterized in that, The preparation method further includes: The intrinsic amorphous silicon layer, P-type doped layer, and intrinsic hydrogenated amorphous silicon layer on the second passivation structure are partially removed by laser technology, forming an electrode window in the middle region of the second region and forming a third passivation structure in the outer peripheral region of the second region.

23. The method for preparing a composite passivated back contact battery according to claim 17, characterized in that, The preparation method further includes: A transparent conductive layer is prepared on the first surface, and the transparent conductive layer is isolated in the outer peripheral region of the second region to form a first transparent conductive layer in contact with the first passivation structure and a second transparent conductive layer in contact with the second passivation structure; and / or, An antireflection layer is prepared on the second surface, the antireflection layer comprising one or more of an alumina layer, a silicon oxynitride layer, and a silicon nitride layer; and / or, Alkali texturing is performed on the first and third regions of the first surface and the second surface to form a pyramid-structured texturing surface.

24. A photovoltaic module, characterized in that, The photovoltaic module includes: A battery string, said battery string being formed by electrically connecting a plurality of composite passivated back contact batteries as described in any one of claims 1 to 16 or composite passivated back contact batteries prepared as described in any one of claims 17 to 23; and, An encapsulation layer that covers the surface of the battery string.

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