A solar cell and a method of manufacturing the same

Abstract

This invention discloses a solar cell and its fabrication method. The solar cell may include: a crystalline silicon substrate, comprising a first main surface and a second main surface opposite to each other; the first main surface of the crystalline silicon substrate including a first intermediate region and a first edge region surrounding the first intermediate region; a first passivation layer disposed in the first edge region; and a first doped polycrystalline silicon layer disposed on the first passivation layer; the thickness of the first doped polycrystalline silicon layer on the side closer to the first intermediate region of the crystalline silicon substrate is less than the thickness of the first doped polycrystalline silicon layer on the side farther from the first intermediate region of the crystalline silicon substrate. With the same coverage area of ​​the first doped polycrystalline silicon layer, the smaller thickness on the side closer to the first intermediate region reduces the overall parasitic absorption of light by the first doped polycrystalline silicon layer on the first main surface.

Description

Technical Field

[0001] This invention relates to a solar cell and a method for its fabrication. Background Technology

[0002] Solar cells, based on monocrystalline or polycrystalline silicon wafers, are semiconductor devices that convert light energy into electrical energy. The surface of silicon wafers contains dangling bonds and defects, which easily lead to carrier recombination, thus reducing the photoelectric conversion efficiency of the solar cell. Therefore, passivation of the silicon wafer surface is necessary.

[0003] In a prior art solar cell, the surface of a crystalline silicon substrate facing sunlight (i.e., the front side) includes a central region and an edge region surrounding the central region. A passivation layer is disposed on the edge region, and a doped polycrystalline silicon layer is disposed on the passivation layer, thereby achieving passivation of the edge region of the front side of the crystalline silicon substrate.

[0004] However, the parasitic absorption of light by the doped polycrystalline silicon layer is quite severe, which affects the absorption of light by the solar cell and leads to a decrease in the short-circuit current of the solar cell. Summary of the Invention

[0005] In view of this, the present invention provides a solar cell and a method for preparing the same. The solar cell reduces the parasitic absorption of light by the first doped polycrystalline silicon layer on the first main surface by setting the thickness of the first doped polycrystalline silicon layer located in the first edge region of the first main surface of the crystalline silicon substrate to be smaller on the side closer to the first middle region than on the side farther from the first middle region.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a solar cell, comprising: A crystalline silicon substrate, the crystalline silicon substrate including a first main surface and a second main surface opposite to each other, the first main surface of the crystalline silicon substrate including a first intermediate region and a first edge region disposed around the first intermediate region; A first passivation layer is disposed in the first edge region; A first doped polysilicon layer is disposed on the first passivation layer; The thickness of the first doped polysilicon layer on the side closer to the first intermediate region of the crystalline silicon substrate is less than the thickness of the first doped polysilicon layer on the side farther from the first intermediate region of the crystalline silicon substrate.

[0007] Optionally, the thickness of the first doped polysilicon layer disposed in the first edge region increases from the side closest to the first intermediate region of the crystalline silicon substrate to the side furthest from the first intermediate region of the crystalline silicon substrate.

[0008] Optionally, the thickness of the first doped polysilicon layer on the side closest to the first intermediate region of the crystalline silicon substrate is not less than 50% of the thickness of the first doped polysilicon layer on the side furthest from the first intermediate region of the crystalline silicon substrate (10).

[0009] Optionally, the thickness of the first passivation layer on the side closer to the first intermediate region of the crystalline silicon substrate is less than the thickness of the first passivation layer (20) on the side farther from the first intermediate region of the crystalline silicon substrate.

[0010] Optionally, the thickness of the first passivation layer disposed in the first edge region increases from the side closest to the first intermediate region of the crystalline silicon substrate to the side furthest from the first intermediate region of the crystalline silicon substrate.

[0011] Optionally, the crystalline silicon substrate further includes a side surface located between the first main surface and the second main surface, wherein the first passivation layer and the first doped polysilicon layer extend to the side surface of the crystalline silicon substrate.

[0012] Optionally, the second main surface of the crystalline silicon substrate includes a second intermediate region and a second edge region disposed around the second intermediate region, wherein the first passivation layer and the first doped polycrystalline silicon layer extend to the second edge region of the second main surface.

[0013] Optionally, the conductivity type of the first doped polysilicon layer is the same as that of the crystalline silicon substrate.

[0014] Optionally, the conductivity type of the crystalline silicon substrate is n-type, and the conductivity type of the first doped polycrystalline silicon layer is n-type.

[0015] Optionally, the first main surface is the front side of the crystalline silicon substrate, and the second main surface is the back side of the crystalline silicon substrate.

[0016] Optionally, the first main surface of the crystalline silicon substrate further includes a first isolation region located between the first intermediate region and the first edge region, and disposed around the first intermediate region; a second passivation layer is disposed on the first isolation region and the first intermediate region, and an anti-reflection layer is disposed on the second passivation layer, wherein the hydrogen atom content per unit area of ​​the second passivation layer is greater than the hydrogen atom content per unit area of ​​the first passivation layer; the roughness of the first main surface corresponding to the first intermediate region is greater than the roughness of the first main surface corresponding to the first isolation region, and the roughness of the first main surface corresponding to the first isolation region is greater than or equal to the roughness of the first main surface corresponding to the first edge region.

[0017] Optionally, the first edge region may include a polished structure or a tower base structure.

[0018] Optionally, the first intermediate region has a velvety texture.

[0019] Optionally, the first isolation zone may include a polished structure or a tower base structure.

[0020] Optionally, the first isolation region further includes a velvet structure, the height of which is less than the height of the velvet structure in the first intermediate region.

[0021] Optionally, the height difference between the first main surface of the silicon substrate corresponding to the first intermediate region and the first main surface of the silicon substrate corresponding to the first edge region is greater than or equal to 0.5 μm and less than 5 μm.

[0022] Optionally, the reflectivity of the side surface and the first edge region of the crystalline silicon substrate is greater than the reflectivity of the first middle region of the crystalline silicon substrate.

[0023] Optionally, the first passivation layer includes a silicon oxide layer, and the second passivation layer includes an aluminum oxide layer.

[0024] Optionally, the antireflective layer includes a silicon nitride layer.

[0025] Optionally, the width of the first edge region is 0.1 μm to 1000 μm.

[0026] Optionally, the width of the second edge region is 0.1 μm to 1000 μm.

[0027] Optionally, the total width of the first isolation area and the first edge area is no greater than 1 mm.

[0028] Optionally, the second passivation layer and the antireflection layer further extend to the first doped polysilicon layer corresponding to the first edge region.

[0029] Optionally, the second passivation layer and the antireflection layer also extend to the first doped polysilicon layer on the side of the crystalline silicon substrate.

[0030] Optionally, the first passivation layer and the first doped polysilicon layer extend to a second intermediate region on the second main surface of the crystalline silicon substrate; The solar cell further includes: a carrier collection layer disposed in a first intermediate region of a first main surface of the crystalline silicon substrate, a second passivation layer disposed on the carrier collection layer, wherein the conductivity type of the carrier collection layer is opposite to that of the first doped polycrystalline silicon layer.

[0031] Optionally, the carrier collection layer has a p-type conductivity.

[0032] Optionally, the thickness of the first doped polysilicon layer corresponding to the second intermediate region of the crystalline silicon substrate is greater than the thickness of the first doped polysilicon layer on the side closer to the first intermediate region of the crystalline silicon substrate.

[0033] Optionally, the carrier collection layer includes a doped diffusion layer extending from the first main surface into the interior of the crystalline silicon substrate.

[0034] Optionally, the antireflection layer further extends onto a first doped polycrystalline silicon layer located on a second main surface of the crystalline silicon substrate.

[0035] Optionally, the second passivation layer also extends to the first doped polycrystalline silicon layer located on the second main surface of the crystalline silicon substrate.

[0036] Optionally, the solar cell further includes: a first electrode structure electrically connected to the first doped polycrystalline silicon layer corresponding to the second intermediate region, and a second electrode structure electrically connected to the carrier collection layer.

[0037] Optionally, the second intermediate region of the second main surface of the crystalline silicon substrate includes alternating first conductive regions and second conductive regions, and a second isolation region located between adjacent first conductive regions and second conductive regions, wherein the first conductive region is provided with the first passivation layer and the first doped polycrystalline silicon layer. The solar cell further includes a carrier collection layer disposed in the second conductive region, wherein the conductivity type of the carrier collection layer is opposite to that of the first doped polycrystalline silicon layer.

[0038] Optionally, the thickness of the first doped polysilicon layer disposed in the first conductive region is greater than the thickness of the first doped polysilicon layer on the side closest to the first intermediate region of the crystalline silicon substrate.

[0039] Optionally, the conductive region closest to the second edge region is the first conductive region, and the first passivation layer and the first doped polysilicon layer located in the first conductive region closest to the second edge region are respectively connected to the first passivation layer and the first doped polysilicon layer located in the second edge region.

[0040] Optionally, the first conductive region includes a first portion extending along a first direction and a second portion extending along a second direction intersecting the first direction, and the second conductive region includes a third portion extending along the first direction and a fourth portion extending along the second direction; in the second direction, the first portion and the third portion are arranged alternately; in the first direction, the second portion and the fourth portion are arranged alternately; or, both the first conductive region and the second conductive region are elongated and both extend along the second direction; in the first direction, the first conductive region and the second conductive region are arranged alternately.

[0041] Optionally, the first direction and the second direction are perpendicular.

[0042] Optionally, the carrier collection layer includes a doped diffusion layer extending from the second main surface corresponding to the second conductive region into the interior of the crystalline silicon substrate.

[0043] The carrier collection layer includes a third passivation layer and a second doped polysilicon layer disposed on the third passivation layer.

[0044] Optionally, the third passivation layer includes a silicon oxide layer.

[0045] Optionally, the second passivation layer and the antireflection layer also extend to the second main surface of the crystalline silicon substrate.

[0046] Optionally, the solar cell further includes: a first electrode structure electrically connected to the first doped polycrystalline silicon layer corresponding to the first conductive region, and a second electrode structure electrically connected to the carrier collection layer.

[0047] Optionally, the carrier collection layer includes: an intrinsic amorphous silicon layer and a doped amorphous silicon layer disposed on the intrinsic amorphous silicon layer.

[0048] Optionally, the doped non-polycrystalline silicon layer contains silicon grains with a particle size of no more than 100 nanometers.

[0049] Optionally, the doped amorphous silicon layer contains silicon grains with a particle size of no more than 10 nanometers.

[0050] Optionally, the doped non-polycrystalline silicon layer may further include silicon oxide and / or silicon carbide.

[0051] Optionally, the intrinsic amorphous silicon layer and the doped amorphous silicon layer extend to the side of the crystalline silicon substrate, and the intrinsic amorphous silicon layer is located on the side of the first doped polycrystalline silicon layer away from the crystalline silicon substrate.

[0052] Optionally, if the crystalline silicon substrate has a second passivation layer and an antireflection layer on its side, the intrinsic amorphous silicon layer is located on the antireflection layer.

[0053] Optionally, the solar cell further includes: a first electrode structure electrically connected to the first doped polycrystalline silicon layer corresponding to the first conductive region, and a second electrode structure electrically connected to the carrier collection layer.

[0054] Optionally, the first electrode structure includes a first transparent conductive film layer and a first metal electrode located on the first transparent conductive film layer, wherein the first transparent conductive film layer further extends to the second edge region and the side of the crystalline silicon substrate.

[0055] Optionally, the second electrode structure includes a second transparent conductive film layer and a second metal electrode located on the second transparent conductive film layer.

[0056] Secondly, embodiments of the present invention provide a method for preparing a solar cell, comprising: Step S1: Provide a crystalline silicon substrate, the crystalline silicon substrate including a first main surface and a second main surface opposite to each other, the first main surface of the crystalline silicon substrate including a first intermediate region and a first edge region disposed around the first intermediate region; Step S2: A first passivation layer is formed on the first edge region, and a first doped polysilicon layer is formed on the first passivation layer; The thickness of the first doped polycrystalline silicon layer on the side closer to the first intermediate region of the crystalline silicon substrate is less than the thickness of the first doped polycrystalline silicon layer on the side farther from the first intermediate region of the crystalline silicon substrate.

[0057] Optionally, step S2 specifically includes: Step S21: A first passivation layer, a first doped polysilicon layer, and a mask layer are sequentially stacked on the first edge region and part of the first middle region of the first main surface of the crystalline silicon substrate, wherein the thickness of the first doped polysilicon layer and the mask layer decreases from the edge to the center. Step S22: Remove the mask layer on the first main surface corresponding to the area outside the first edge region; Step S23: Remove the first doped polysilicon layer and the first passivation layer on the first main surface corresponding to the area outside the first edge region; Step S24: Remove the remaining mask layer; Optionally, in step S22, the mask layer corresponding to the area outside the first edge region is removed by laser or wet etching.

[0058] Optionally, step S21 further includes simultaneously and sequentially stacking a first passivation layer, a first doped polysilicon layer, and a mask layer on the side surface of the crystalline silicon substrate and the second main surface to form the entire surface.

[0059] Optionally, the first main surface of the crystalline silicon substrate further includes a first isolation region located between the first intermediate region and the first edge region and disposed around the first intermediate region; in step S21, a first passivation layer, a first doped polycrystalline silicon layer and a mask layer are also sequentially stacked on the first isolation region.

[0060] Optionally, in step S1, the first main surface and the second main surface of the crystalline silicon substrate are polished; in step S23, while removing the first doped polysilicon layer and the first passivation layer on the first main surface corresponding to the area outside the first edge region, the first main surface corresponding to the first middle region is texturized. Step S2 further includes: Step S25, forming a second passivation layer and an antireflection layer on the first doped polysilicon layer in the first intermediate region, the first isolation region and the first edge region; the hydrogen atom content in the second passivation layer per unit area is greater than the hydrogen atom content in the first passivation layer per unit area.

[0061] Optionally, step S25 further includes: simultaneously forming a second passivation layer and an antireflection layer on the first doped polysilicon layer on the side of the crystalline silicon substrate.

[0062] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: a first passivation layer and a first doped polycrystalline silicon layer are provided in the first edge region of the first main surface of the crystalline silicon substrate, which can enhance the passivation effect of the first edge region and reduce carrier recombination in the first edge region. Furthermore, the thickness of the first doped polycrystalline silicon layer on the side closer to the first middle region of the crystalline silicon substrate is less than the thickness of the first doped polycrystalline silicon layer on the side farther from the first middle region of the crystalline silicon substrate. Since reducing the thickness is beneficial to reducing the parasitic absorption of the doped polycrystalline silicon layer, in the solar cell provided by the embodiments of the present invention, when the coverage area of ​​the first doped polycrystalline silicon layer is the same, the thickness on the side closer to the first middle region is smaller, thus reducing the overall parasitic absorption of light by the first doped polycrystalline silicon layer. Attached Figure Description

[0063] Figure 1 This is a partial cross-sectional structural diagram of a solar cell provided in an embodiment of the present invention; Figure 2 This is a partial cross-sectional structural diagram of a solar cell with another structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram showing the relative relationship between the first edge region, the first isolation region, and the first intermediate region of the first main surface of the crystalline silicon substrate provided in an embodiment of the present invention; Figure 4This is a schematic diagram showing the relative relationship between the first and second conductive regions of the finger-crossed structure on the back of a solar cell according to an embodiment of the present invention. The dashed line between the first and second conductive regions in the figure represents the second isolation region. Figure 5 This is a schematic diagram showing the relative relationship between the second edge region, the second isolation region, and the second middle region in the finger-cross structure on the back of a solar cell provided in an embodiment of the present invention. The dashed lines between the first conductive region and the second conductive region, and between the second isolation region and the second conductive region, represent the second isolation region. Figure 6 This is a schematic diagram showing the relative relationship between the first and second conductive regions of the alternating strip structure on the back of a solar cell according to an embodiment of the present invention. The dashed line between the first and second conductive regions in the figure represents the second isolation region. Figure 7 This is a schematic diagram showing the relative relationship between the second edge region, the second isolation region, and the second middle region in the strip structure on the back of a solar cell according to an embodiment of the present invention. The dashed lines between the first conductive region and the second conductive region, and between the second isolation region and the second conductive region, represent the second isolation region. Figure 8 This is a schematic diagram of the main process of a method for preparing a solar cell according to an embodiment of the present invention; Figure 9 This is a schematic cross-sectional view of the structural changes corresponding to each step in the preparation method according to an embodiment of the present invention; Figure 10 This is a schematic cross-sectional view of the structural changes corresponding to each step in step S2 of the preparation method according to an embodiment of the present invention. Figure 11 This is a schematic cross-sectional view of the partial structural changes of the solar cell corresponding to steps S2' and S3, based on the structure obtained in step S24 according to the preparation method of the present invention. Figure 12 This is a SEM image of a portion of the front side of a solar cell according to an embodiment of the present invention.

[0064] The attached figures are labeled as follows: 10 - Crystalline silicon substrate; 11 - First edge region; 12 - Second edge region; 13 - Second intermediate region; 131 - First conductive region; 132 - Second conductive region; 14 - First intermediate region; 20 - First passivation layer; 30 - First doped polycrystalline silicon layer; 30' - Mask layer; 40 - First electrode structure; 41 - First transparent conductive film layer; 42 - First metal electrode; 50 - Carrier collection layer; 51 - Intrinsic amorphous silicon layer; 52 - Doped amorphous silicon layer; 61 - First isolation region; 62 - Second isolation region; 70 - Antireflection layer; 80 - Second electrode structure; 81 - Second transparent conductive film layer; 82 - Second metal electrode; 90 - Transparent conductive film layer. Detailed Implementation

[0065] The solar cell involved in the embodiments of the present invention can have two conductive regions of opposite conductivity types both disposed on the back side of the solar cell, or the two conductive regions of opposite conductivity types can be disposed on the front and back sides of the solar cell. Based on these two structures, the solar cell involved in the embodiments of the present invention includes a tunnel oxide passivated contact (TOPCon) structure on a conductive region of the same conductivity type as the crystalline silicon substrate. The tunnel oxide passivated contact structure generally includes: a first passivation layer 20 and a first doped polycrystalline silicon layer 30 of the same conductivity type as the crystalline silicon substrate 10 disposed on the first passivation layer 20.

[0066] It should be noted that the terms "first" and "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0067] The first main surface of the crystalline silicon substrate 10 involved in the embodiments of the present invention generally refers to the main surface of the crystalline silicon substrate 10 facing sunlight during the operation of the solar cell. The second main surface of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 facing away from sunlight during the operation of the solar cell.

[0068] The embodiments of the present invention involve a film layer located on another film layer or a film layer located on another film layer. It can be that the film layer is located on the side of the other film layer away from the crystalline silicon substrate 10, and unless otherwise described in conflict, the film layer and the other film layer can be in direct contact, and other film layers may also be included between the film layer and the other film layer.

[0069] In the absence of other conflicting descriptions, the edge region of a main surface in embodiments of the present invention generally refers to the area extending inward from the edge where the main surface intersects with the side surface (i.e., from the edge of the main surface towards the center of the main surface) by a certain width. For example, if the main surface is rectangular, then there are four edges where the main surface intersects with the side surface, and the edge region of the rectangular main surface extends inward by a certain width from each edge.

[0070] Unless otherwise contradictory, the intermediate region of a main surface in an embodiment of the present invention can refer to any region on the main surface other than the edge region. Alternatively, it can refer to any region other than the edge region and the isolation zone corresponding to the edge region, wherein the isolation zone corresponding to the edge region is the isolation zone located between the intermediate region and the edge region.

[0071] In the embodiments of the present invention, the connection between one membrane layer and another membrane layer means that there is an uninterrupted region between the one membrane layer and another membrane layer, or there is a contact region between the one membrane layer and another membrane layer.

[0072] In the embodiments of this invention, an n-type doped film or an n-type conductive film generally means that the film is doped with n-type doped atoms such as phosphorus atoms, arsenic atoms, antimony atoms, or bismuth atoms. A p-type doped film or a p-type conductive film generally means that the film is doped with p-type doped atoms such as boron atoms, aluminum atoms, gallium atoms, or indium atoms.

[0073] The doping concentration of a film layer in the embodiments of the present invention generally refers to the average number of activated doped atoms contained in a unit volume of the film layer.

[0074] Specifically, embodiments of the present invention provide a solar cell. More specifically, as... Figure 1 and Figure 2 As shown, the solar cell may include: A crystalline silicon substrate 10; the crystalline silicon substrate 10 includes a first main surface and a second main surface opposite to each other, the first main surface of the crystalline silicon substrate 10 includes a first intermediate region 14 and a first edge region 11 disposed around the first intermediate region 14; A first passivation layer 20 is disposed in the first edge region 11; A first doped polysilicon layer 30 is disposed on the first passivation layer 20; The thickness of the first doped polysilicon layer 30 on the side closer to the first intermediate region 14 of the crystalline silicon substrate 10 is less than the thickness of the first doped polysilicon layer 30 on the side farther from the first intermediate region 14 of the crystalline silicon substrate 10.

[0075] The silicon substrate 10 can be either an n-type or p-type silicon substrate. The conductivity type of the first doped polysilicon layer 30 is generally the same as that of the silicon substrate 10. Alternatively, the conductivity type of the first doped polysilicon layer 30 can be different from that of the silicon substrate 10. For example, if the silicon substrate 10 is an n-type silicon substrate, the conductivity type of the first doped polysilicon layer 30 is n-type, meaning the first doped polysilicon layer 30 contains n-type dopant atoms; if the silicon substrate 10 is a p-type silicon substrate, the conductivity type of the first doped polysilicon layer 30 is p-type, meaning the first doped polysilicon layer 30 contains p-type dopant atoms.

[0076] It is worth noting that, in this embodiment of the invention, the first edge region 11 is disposed around the edge of the first main surface of the crystalline silicon substrate 10. The first edge region 11 is a ring-shaped structure with its ends connected. The ring-shaped structure of the first edge region 11 is consistent with the shape of the first main surface of the crystalline silicon substrate 10. For example, as shown... Figure 3 As shown, the first main surface of the crystalline silicon substrate 10 is rectangular, and correspondingly, the first edge region 11 is a rectangular ring connected end to end. The first intermediate region 14 in this embodiment refers to other regions on the first main surface besides the first edge region 11, or other regions besides the first edge region 11 and the first isolation region 61.

[0077] In this embodiment of the invention, the thickness of the first doped polysilicon layer 30 disposed in the first edge region 11 increases from the side near the first intermediate region 14 of the crystalline silicon substrate 10 to the side away from the first intermediate region 14 of the crystalline silicon substrate 10. This can be understood as the surface of the first doped polysilicon layer 30 away from the first main surface being inclined, and the thickness of the first doped polysilicon layer 20 gradually increasing from the side near the first intermediate region 14 of the crystalline silicon substrate 10 to the side away from the first intermediate region 14 of the crystalline silicon substrate 10.

[0078] On the one hand, by setting a first passivation layer and a first doped polycrystalline silicon layer in the first edge region of the first main surface of the crystalline silicon substrate, the passivation effect of the first edge region can be enhanced, and carrier recombination in the first edge region can be reduced. On the other hand, since reducing the thickness is beneficial to reducing the parasitic absorption of the doped polycrystalline silicon layer, in the solar cell provided by the embodiments of the present invention, when the coverage area of ​​the first doped polycrystalline silicon layer 30 is the same, the thickness near the first middle region is smaller, which reduces the overall parasitic absorption of light by the first doped polycrystalline silicon layer 30 and improves the short-circuit current of the solar cell. It can also be understood that even if the coverage area of ​​the first doped polycrystalline silicon layer 30 is appropriately increased, the overall parasitic absorption of light by the first doped polycrystalline silicon layer 30 will not increase.

[0079] In this embodiment of the invention, the thickness of the side of the first doped polycrystalline silicon layer 30 near the first intermediate region 14 of the crystalline silicon substrate 10 is not less than 50% of the thickness of the side of the first doped polycrystalline silicon layer 30 away from the crystalline silicon substrate 10. For example, the thickness of the side of the first doped polycrystalline silicon layer 30 near the first intermediate region 14 of the crystalline silicon substrate 10 is 55%, 60%, 70%, 80%, 88%, 90%, 95%, or 98% of the thickness of the side of the first intermediate region 14 away from the crystalline silicon substrate 10. By controlling the thickness of the side of the first doped polycrystalline silicon layer 30 near the first intermediate region 14 of the crystalline silicon substrate 10, passivation of the edge region can be ensured, and during the lamination process of preparing photovoltaic modules based on the solar cell, the lamination pressure of the edge region can be better dispersed, effectively reducing the risk of microcracks or fragmentation in the edge region.

[0080] In this embodiment of the invention, the thickness of the first passivation layer 20 on the side near the first intermediate region 14 of the crystalline silicon substrate 10 can also be less than the thickness of the first passivation layer 20 on the side away from the first intermediate region 14 of the crystalline silicon substrate 10. The surface of the first passivation layer 20 away from the first main surface of the crystalline silicon substrate 10 can also be inclined, that is, the thickness of the first passivation layer 20 disposed in the first edge region 11 increases from the side near the first intermediate region 14 of the crystalline silicon substrate 10 to the side away from the first intermediate region 14 of the crystalline silicon substrate 10. The increasing thickness of the first passivation layer 20 disposed in the first edge region 11 from the side near the first intermediate region 14 of the crystalline silicon substrate 10 to the side away from the first intermediate region 14 of the crystalline silicon substrate 10, in conjunction with the gradual increase in the thickness of the first doped polycrystalline silicon layer 20, can ensure the passivation reliability of the first edge region 11 while reducing parasitic absorption of light.

[0081] Furthermore, the crystalline silicon substrate 10 also includes a side surface located between the first main surface and the second main surface, with the first passivation layer 20 and the first doped polycrystalline silicon layer 30 extending to the side surface of the crystalline silicon substrate 10. The side surface of the crystalline silicon substrate 10 also contains dangling bonds and defects. By providing the first passivation layer 20 and the first doped polycrystalline silicon layer 30 on the side surface of the crystalline silicon substrate 10, the side surface of the crystalline silicon substrate 10 can be passivated, preventing carrier recombination from occurring on the side surface of the crystalline silicon substrate 10. In addition, since stress concentration easily occurs at the edge where the first main surface and the side surface intersect, they are easily damaged by external forces such as impacts during solar cell production. Therefore, extending the first passivation layer 20 and the first doped polycrystalline silicon layer 30 from the first edge region 11 of the first main surface to the side surface can protect the edge where the first main surface and the side surface intersect. It is worth noting that the first passivation layer 20 and the first doped polysilicon layer 30 extend to the side of the crystalline silicon substrate 10. The first passivation layer 20 and the first doped polysilicon layer 30 may completely cover the side of the crystalline silicon substrate 10, or the first passivation layer 20 and the first doped polysilicon layer 30 may cover only a portion of the side of the crystalline silicon substrate 10.

[0082] Further, the second main surface of the crystalline silicon substrate 10 includes a second intermediate region 13 and a second edge region 12 disposed around the second intermediate region 13. The first passivation layer 20 and the first doped polysilicon layer 30 extend to the second edge region 12 of the second main surface. In this embodiment of the invention, the second edge region 12 is disposed around the edge of the second main surface of the crystalline silicon substrate 10. This second edge region 12 is also a ring-shaped structure with its ends connected. The ring-shaped structure of the second edge region 12 is consistent with the shape of the second main surface of the crystalline silicon substrate 10, for example, as shown in... Figure 5 and Figure 7 As shown, the second main surface of the crystalline silicon substrate 10 is rectangular, and correspondingly, the second edge region 12 is a rectangular ring connected end to end. The second intermediate region 13 in this embodiment refers to the region on the second main surface other than the second edge region 12. Extending the first passivation layer 20 and the first doped polycrystalline silicon layer 30 from the side to the second edge region 12 of the second main surface can, on the one hand, passivate the second main surface 9 of the crystalline silicon substrate 10 corresponding to the second edge region 12; on the other hand, it can protect the edge where the second main surface and the side intersect. In this embodiment, the first passivation layer 20 disposed in the first edge region 11 is connected to the first passivation layer 20 disposed on the side of the crystalline silicon substrate 10 and the first passivation layer 20 disposed in the second edge region 12, so that the first passivation layer 20 of the first edge region 11, the first passivation layer 20 of the side of the crystalline silicon substrate 10, and the first passivation layer 20 of the second edge region 12 can be formed together, effectively simplifying the fabrication process, ensuring the integrity of the film layer, and improving its passivation effect.

[0083] In this embodiment of the invention, the first passivation layer 20 and the first doped polysilicon layer 30 may be further disposed in the second intermediate region 13 of the second main surface of the crystalline silicon substrate 10, as shown in the figure. Figure 2 As shown, the first passivation layer 20 completely covers the second intermediate region 13; it can also be as follows: Figure 1 As shown, the first passivation layer 20 covers a portion of the second intermediate region 13 at intervals.

[0084] It should be noted that an electric field can be formed between the first doped polysilicon layer 30 and the crystalline silicon substrate 10. When the conductivity types of the first doped polysilicon layer 30 and the crystalline silicon substrate 10 are opposite, a PN junction can be formed between them; when the conductivity types of the first doped polysilicon layer 30 and the crystalline silicon substrate 10 are the same, a high-low junction can be formed between them. The first passivation layer 20 can have a relatively thin thickness, thereby allowing charge carriers to be transported from the crystalline silicon substrate 10 to the first doped polysilicon layer 30 through the tunneling effect; the first passivation layer 20 can also have through-holes, allowing charge carriers to be transported from the crystalline silicon substrate 10 to the first doped polysilicon layer 30 through the through-holes. The first passivation layer 20 may include a silicon oxide layer.

[0085] Furthermore, in the solar cells provided in this embodiment, such as Figures 1 to 3 As shown, the first main surface of the crystalline silicon substrate 10 also includes a first isolation region 61 located between the first intermediate region 14 and the first edge region 11, and surrounding the first intermediate region 14; a second passivation layer is disposed on the first isolation region 61 and the first intermediate region 14, and an anti-reflection layer 70 is disposed on the second passivation layer. The hydrogen atom content per unit area of ​​the second passivation layer is greater than the hydrogen atom content per unit area of ​​the first passivation layer 20; the roughness of the first main surface corresponding to the first intermediate region 14 is greater than the roughness of the first main surface corresponding to the first isolation region 61, and the roughness of the first main surface corresponding to the first isolation region 61 is greater than or equal to the roughness of the first main surface corresponding to the first edge region 11. The first isolation region 61 can ensure electrical isolation between the carrier collection layer disposed on the first intermediate region 14 and the first doped polycrystalline silicon layer 30, thereby preventing short circuits in the solar cell. In addition, by providing a second passivation layer and an antireflection layer 70 on the first isolation region 61 and the first intermediate region 14, the first isolation region 61 and the first intermediate region 14 can be passivated, reducing carrier recombination and light reflection from the first isolation region 61 and the first intermediate region 14, thereby improving the light utilization rate of the solar cell.

[0086] In this embodiment of the invention, the first edge region 11 can be a polished structure or a tower base structure, so that the structure of the first passivation layer 20 and the first doped polysilicon layer 30 formed on the first edge region 11 is relatively complete, improving the passivation effect on the first edge region 11 and further reducing structural defects in the first edge region 11. It is worth noting that a polished structure generally means that the area containing the polished surface in the region accounts for 80% or more of the total area. That is, a polished structure in the first edge region 11 can mean that the entire surface of the first edge region 11 is polished, or that 80% or more of the surface of the first edge region 11 is polished, while the non-polished areas can be textured or tower bases, etc. A tower base structure generally means that the area containing the tower base in the region accounts for 80% or more of the total area. That is, a tower base structure in the first edge region 11 can mean that the surface of the first edge region 11 is uniformly covered by the tower base, or that 80% or more of the surface of the first edge region 11 is uniformly distributed with the tower base, while the areas not covered by the tower base can be textured or polished, etc.

[0087] The first intermediate region 14 can have a textured structure to reduce light reflection and enhance light absorption. The first isolation region 61 can have a polished structure or a tower-based structure. The first isolation region 61 can also include a textured structure, but the height of the textured structure in the first isolation region 61 is less than the height of the textured structure in the first intermediate region 14. That is, the textured structure in the first isolation region 61 is flatter than the textured structure in the first intermediate region 14, making the roughness of the first main surface corresponding to the first isolation region 61 less than the roughness of the first main surface corresponding to the first intermediate region 14. The crystalline silicon substrate 10 with lower roughness has fewer surface defects and is more likely to form a denser and more uniform second passivation layer. Therefore, the first isolation region 61 can achieve a better passivation effect than the first intermediate region 14. At the same time, hydrogen atoms in the second passivation layer can saturate the dangling bonds on the surface of the crystalline silicon substrate. Therefore, the second passivation layer with a higher hydrogen atom content has a better passivation effect than the first passivation layer 20. Therefore, overall, the first main surface of the crystalline silicon substrate 10 corresponding to the first isolation region 61 has a better passivation effect.

[0088] In this embodiment of the invention, the second passivation layer can be a film layer with a high hydrogen atom content, such as an aluminum oxide layer, an intrinsic amorphous silicon layer, or a doped amorphous silicon layer. The antireflection layer 70 may include a silicon nitride layer.

[0089] The scanning electron microscope (SEM) images of the first edge region 11, the first isolation region 61 of the polished surface, and the first intermediate region 14 in the solar cell provided in this embodiment of the invention are shown below. Figure 12 As shown. From Figure 12It can be clearly seen that the first middle area 14 has a velvety surface, while the first edge area 11 and the first isolation area 61 have polished surfaces.

[0090] In this embodiment of the invention, the height difference between the first main surface of the crystalline silicon substrate corresponding to the first intermediate region 14 and the first main surface of the crystalline silicon substrate corresponding to the first edge region 11 is greater than or equal to 0.5 μm and less than 5 μm. It is worth noting that, for the first main surface of the crystalline silicon substrate corresponding to the first intermediate region 14, which is a textured structure, the height difference refers to the height difference between the bottom of the textured structure of the first main surface of the crystalline silicon substrate corresponding to the first intermediate region 14 and the first main surface of the crystalline silicon substrate corresponding to the first edge region 11. For example, the height difference can be 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, or 4.5 μm, etc. By controlling this height difference, on the one hand, the impact of excessive height in the first edge region caused by the edge region during the solar cell manufacturing process can be effectively reduced, thereby reducing edge damage to the solar cell; on the other hand, in the lamination process of photovoltaic module manufacturing based on this solar cell, the first intermediate region 14 and the first edge region 11 can better disperse the lamination pressure, reducing the risk of edge cracking or microcracks in the solar cell.

[0091] In this embodiment of the invention, in the first edge region 11, the thickness of the first passivation layer 20 and the first doped polysilicon layer 30 increases from the side closest to the first intermediate region 14 of the crystalline silicon substrate 10 to the side furthest from the first intermediate region 14 of the crystalline silicon substrate 10. This allows the first passivation layer 20 and the first doped polysilicon layer 30 to be retained in the first edge region 11 through wet etching during the fabrication process, facilitating process implementation. Furthermore, the increasing thickness of the first passivation layer 20 and the first doped polysilicon layer 30 in the first edge region 11 ensures reliable edge passivation and prevents edge recombination on the first main surface.

[0092] In this embodiment of the invention, the width of the first edge region 11 is 0.1μm to 1000μm. For example, the width of the first edge region 11 can be 0.1μm, 1μm, 10μm, 100μm, 500μm or 1000μm, etc.

[0093] In this embodiment of the invention, a portion of the side surface of the crystalline silicon substrate 10 may have an inverted pyramid textured or textured surface. The first passivation layer 20 and the first doped polysilicon layer 30 extending to the side surface of the crystalline silicon substrate 10 generally cover the bottom of the textured pyramid, while the top portion of the textured pyramid is generally not covered by the first passivation layer 20 and the first doped polysilicon layer 30.

[0094] In this embodiment of the invention, the reflectivity of the side surface and the first edge region 11 of the crystalline silicon substrate 10 is greater than that of the first middle region 11 of the crystalline silicon substrate 10, so as to ensure that the first passivation layer 20 and the first doped polycrystalline silicon layer 30 can passivate the side surface and the first edge region 11 of the crystalline silicon substrate 10 better, and ensure that the first middle region 14 of the crystalline silicon substrate 10 can have light trapping properties, thereby improving light utilization.

[0095] In this embodiment of the invention, the width of the second edge region 12 is 0.001μm to 1000μm. For example, the width of the second edge region 12 can be 0.1μm, 1μm, 10μm, 100μm, 500μm or 1000μm, etc.

[0096] Furthermore, the solar cell provided in this embodiment of the invention may further include a carrier collection layer 50 with a conductivity type opposite to that of the first doped polycrystalline silicon layer 30. For example, the conductivity type of the crystalline silicon substrate 10 is n-type, the conductivity type of the first doped polycrystalline silicon layer 30 is n-type, and the conductivity type of the carrier collection layer 50 is p-type; or, the conductivity type of the crystalline silicon substrate 10 is p-type, the conductivity type of the first doped polycrystalline silicon layer 30 is p-type, and the conductivity type of the carrier collection layer 50 is n-type.

[0097] The carrier collection layer 50 can be positioned in the solar cell in three ways.

[0098] The first type is as follows Figure 2 As shown, in a first structure where the carrier collection layer 50 is positioned: the first passivation layer 20 and the first doped polysilicon layer 30 extend to the second intermediate region 13 of the second main surface of the silicon substrate 10, covering the entire second intermediate region 13, i.e., the entire second main surface. The carrier collection layer 50 is disposed in the first intermediate region 14 of the first main surface of the silicon substrate 10. In this configuration, the first isolation region 61 located between the carrier collection layer 50 and the first edge region 11 provides electrical isolation between the carrier collection layer 50 and the first doped polysilicon layer 30 disposed on the first edge region 11, preventing short circuits between the carrier collection layer 50 and the first doped polysilicon layer 30 while ensuring that the first passivation layer 20 and the first doped polysilicon layer 30 work together to passivate the first edge region 11 effectively. The carrier collection layer 50 may include a doped diffusion layer extending from the first main surface into the interior of the silicon substrate 10. Understandably, in this manner, the aforementioned second passivation layer (not shown in the figure) is located between the carrier collection layer 50 and the antireflection layer 70.

[0099] The width of the first isolation region 61 is 0.001 μm to 10 μm to ensure reliable electrical isolation between the carrier collection layer 50 and the first doped polysilicon layer 30. For example, the width of the first isolation region 61 can be 0.001 μm, 0.01 μm, 0.1 μm, 0.5 μm, 1 μm, 3 μm, 5 μm, 8 μm, or 10 μm, etc.

[0100] In this embodiment of the invention, the portion of the first intermediate region 14 corresponding to the carrier collection layer 50 has a textured surface, and the first isolation region 61 has a polished surface, so as to ensure the light trapping property of the region containing the carrier collection layer 50 and improve the light utilization rate. Furthermore, the first isolation region 61 with a polished surface can ensure its isolation effect.

[0101] In embodiments of the present invention, such as Figure 3 As shown, the total width W of the first isolation region 61 and the first edge region 11 is no greater than 1 mm, so as to ensure the effective area of ​​the carrier collection layer 50 and ensure the efficiency of carrier collection and transmission.

[0102] In this method, the antireflection layer 70 can further extend onto the first doped polycrystalline silicon layer 30 located on the second main surface and side surface of the crystalline silicon substrate 10, thereby increasing light absorption on the second main surface of the solar cell. The second passivation layer can also extend onto the first doped polycrystalline silicon layer 30 located on the second main surface and side surface of the crystalline silicon substrate 10, and the antireflection layer 70 remains on the second passivation layer, thus passivating the first doped polycrystalline silicon layer 30 on the second main surface and side surface of the crystalline silicon substrate 10 using the second passivation layer.

[0103] In this configuration, the solar cell further includes: a first electrode structure 40 electrically connected to the first doped polycrystalline silicon layer 30 corresponding to the second intermediate region 13, and a second electrode structure 80 electrically connected to the carrier collection layer 50. Both the second electrode structure 80 electrically connected to the carrier collection layer 50 and the first electrode structure 40 electrically connected to the first doped polycrystalline silicon layer 30 are metal electrodes. Furthermore, at least a portion of the first electrode structure 40 is in direct contact with the first doped polycrystalline silicon layer 30, forming an ohmic contact; at least a portion of the second electrode structure 80 is in direct contact with the carrier collection layer 50, forming an ohmic contact.

[0104] In addition, regarding the first method described above, the thickness of the first doped polysilicon layer 30 corresponding to the second intermediate region 13 of the crystalline silicon substrate 10 is greater than the thickness of the first doped polysilicon layer 30 on the side closer to the first intermediate region 14 of the crystalline silicon substrate 10, so as to ensure the carrier separation and collection efficiency of the first doped polysilicon layer 30 corresponding to the second intermediate region 13 of the crystalline silicon substrate 10, and at the same time, the passivation effect of the first doped polysilicon layer 30 in the first edge region 11 of the crystalline silicon substrate 10 is significantly better than the negative impact of the first doped polysilicon layer 30 on the first edge region 11.

[0105] The second type

[0106] In this configuration, the second intermediate region of the second main surface of the crystalline silicon substrate 10 includes alternating first conductive regions 131 and second conductive regions 132, and a second isolation region 62 located between adjacent first conductive regions 131 and second conductive regions 132. A first passivation layer 20 and a first doped polycrystalline silicon layer 30 are disposed on the first conductive region 131, and a carrier collection layer 50 is disposed on the second conductive region 132.

[0107] Regarding this second method, it can be as follows: Figure 4 and Figure 5 As shown, the first conductive region 131 and the second conductive region 132 are arranged in an interlaced pattern. Specifically, the first conductive region 131 includes a first portion extending along a first direction and a second portion extending along a second direction intersecting the first direction. The second conductive region 132 includes a third portion extending along the first direction and a fourth portion extending along the second direction. In the second direction, the first portion of the first conductive region 131 and the third portion of the second conductive region 132 are arranged alternately; in the first direction, the second portion of the first conductive region 131 and the fourth portion of the second conductive region 132 are arranged alternately. For the second conductive region 132, the third portion has a fourth portion on both sides in the second direction. For the first conductive region 131 adjacent to the second edge region 12, the second portion is only provided on the side of the first portion closer to the second middle region 13. The first portion, second portion, third portion, and fourth portion can all be elongated.

[0108] Regarding this second method, it can also be done as follows: Figure 6 and Figure 7 As shown, both the first conductive region 131 and the second conductive region 132 are elongated strips and extend along the second direction. In the first direction, the first conductive region 131 and the second conductive region 132 are arranged alternately.

[0109] The first direction and the second direction can be perpendicular to each other. For example, the first direction is... Figures 4 to 7 The top and bottom directions. The second direction is... Figures 4 to 7 The left and right directions in the middle.

[0110] It is worth noting that, such as Figure 4 and Figure 5 As shown, the four edges of the second main surface, corresponding to the second edge regions 12, are directly connected to the first conductive region 131 located in the second middle region 13 near the second edge regions 12. The first passivation layer 20 and the first doped polysilicon layer 30 disposed on the second edge regions 12 are respectively connected to the first passivation layer 20 and the first doped polysilicon layer 30 disposed on the first conductive region 131 adjacent to the second edge regions 12. The first doped polysilicon layer 30 is connected. The second conductive region 132 near the second edge regions 12 is isolated from the second edge regions 12 through the second isolation region 62.

[0111] like Figure 6 and Figure 7 As shown, the first conductive region 131, which has a strip-shaped structure, is directly connected to the second edge regions 12 at both ends of its extension direction. The first passivation layer 20 and the first doped polysilicon layer 30, which are respectively disposed on the first conductive region 131, are connected to the first passivation layer 20 and the first doped polysilicon layer 30 disposed on the second edge regions 12 at both ends of the extension direction of the first conductive region 131. The second conductive region 132, which has a strip-shaped structure, is isolated from the second edge regions 12 by the second isolation region 62.

[0112] In this configuration, the carrier collection layer 50 includes a doped diffusion layer extending from the second main surface corresponding to the second conductive region 132 into the interior of the crystalline silicon substrate 10; or, the carrier collection layer 50 includes a third passivation layer and a second doped polycrystalline silicon layer disposed on the third passivation layer.

[0113] In this approach, the third passivation layer may include a silicon oxide layer. The conductivity type of the doped diffusion layer or the second doped polysilicon layer is opposite to that of the first doped polysilicon layer.

[0114] In this configuration, the conductive region closest to the second edge region 12 is generally the first conductive region 131. The first passivation layer 20 and the first doped polysilicon layer 30 located in the first conductive region 131 closest to the second edge region 12 are respectively connected to the first passivation layer 20 and the first doped polysilicon layer 30 of the second edge region 12.

[0115] In this configuration, the second passivation layer and the antireflection layer 70 also extend to the side surface and the second main surface of the crystalline silicon substrate 10. It is understood that, on the side surface and back surface of the crystalline silicon substrate 10, the second passivation layer is located on the first doped polysilicon layer 30, and the antireflection layer 70 is located on the second passivation layer.

[0116] Furthermore, in this embodiment, the solar cell further includes: a first electrode structure 40 electrically connected to the first doped polycrystalline silicon layer 30 corresponding to the first conductive region 13, and a second electrode structure 80 electrically connected to the carrier collection layer 50. In this embodiment, both the first electrode structure 40 and the second electrode structure 80 are metal electrodes. At least a portion of the first electrode structure 40 is in direct contact with the first doped polycrystalline silicon layer 30, forming an ohmic contact; at least a portion of the second electrode structure 80 is in direct contact with the doped diffusion layer or the second doped polycrystalline silicon layer, forming an ohmic contact.

[0117] The third type

[0118] In this configuration, the second intermediate region 13 of the second main surface of the crystalline silicon substrate 10 includes alternating first conductive regions 131 and second conductive regions 132, and a second isolation region 62 located between adjacent first conductive regions 131 and second conductive regions 132. A first passivation layer 20 and a first doped polycrystalline silicon layer 30 are disposed on the first conductive region 131, and a carrier collection layer 50 is disposed on the second conductive region 132.

[0119] In this method, the arrangement of the first conductive region 131 and the second conductive region 132 is described in the second method above, and will not be repeated here.

[0120] In this method, such as Figure 1 As shown, the carrier collection layer 50 includes an intrinsic amorphous silicon layer 51 and a doped amorphous silicon layer 52 disposed on the intrinsic amorphous silicon layer 51. The conductivity type of the doped amorphous silicon layer 52 is opposite to that of the crystalline silicon substrate 10. The doped amorphous silicon layer 52 contains silicon grains with a particle size of no more than 100 nanometers. More specifically, the doped amorphous silicon layer 52 contains silicon grains with a particle size of no more than 10 nanometers. Additionally, the doped amorphous silicon layer 52 also includes silicon oxide and / or silicon carbide.

[0121] In this embodiment of the invention, the intrinsic amorphous silicon layer 51 and the doped non-polycrystalline silicon layer 52 extend to the side of the crystalline silicon substrate 10, and the intrinsic amorphous silicon layer 51 is located on the side of the first doped polycrystalline silicon layer 30 away from the crystalline silicon substrate 10, so as to ensure electrical isolation between the first doped polycrystalline silicon layer 30 extending to the side of the crystalline silicon substrate 10 and the doped non-polycrystalline silicon layer 52 extending to the side of the crystalline silicon substrate 10. It is worth noting that the intrinsic amorphous silicon layer 51 and the doped non-polycrystalline silicon layer 52 can completely cover the side of the crystalline silicon substrate 10, or they can partially cover the side of the crystalline silicon substrate 10.

[0122] Furthermore, such as Figure 1As shown, in this third method, when the crystalline silicon substrate 10 has a second passivation layer and an anti-reflection layer 70 on its side, the intrinsic amorphous silicon layer 51 extending to the side of the crystalline silicon substrate 10 is located on the anti-reflection layer 70, so as to further ensure the reliability of electrical isolation between the first doped polycrystalline silicon layer 30 and the doped amorphous silicon layer 52 extending to the side of the crystalline silicon substrate 10.

[0123] In this configuration, the solar cell further includes: a first electrode structure 40 electrically connected to the first doped polycrystalline silicon layer 30 corresponding to the first conductive region 131, and a second electrode structure 80 electrically connected to the carrier collection layer 50. The first electrode structure 40 includes a first transparent conductive film layer 41 and a first metal electrode 42 located on the first transparent conductive film layer 41, the first transparent conductive film layer 41 extending to the second edge region 12 and the side surface of the crystalline silicon substrate 10. The second electrode structure 80 includes a second transparent conductive film layer 81 and a second metal electrode 82 located on the second transparent conductive film layer 81. The first transparent conductive film layer 41 may cover a portion of the side surface of the crystalline silicon substrate 10 or may completely cover the side surface of the crystalline silicon substrate 10.

[0124] The first transparent conductive film layer 41 and the second transparent conductive film layer 81 can be a single layer or a stacked structure. Both the first transparent conductive film layer 41 and the second transparent conductive film layer 81 can include a metal oxide layer or a metal nitride layer. For example, the metal oxide can be indium oxide, tin oxide, zinc oxide or cadmium oxide, and the metal nitride can be titanium nitride. The first transparent conductive film layer 41 and the second transparent conductive film layer 81 can be doped with one or more of tin, calcium, aluminum, cadmium, zinc, cerium and fluorine.

[0125] The aforementioned metal electrodes can be silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, or nickel / copper / silver multilayer electrodes.

[0126] In the second or third method described above, the thickness of the first doped polysilicon layer 30 disposed in the first conductive region 131 is greater than the thickness of the first doped polysilicon layer 30 on the side near the first intermediate region 14 of the crystalline silicon substrate 10, so as to ensure the carrier separation and collection efficiency of the first doped polysilicon layer 30 disposed in the first conductive region 131, and at the same time, the passivation effect of the first doped polysilicon layer 30 in the first edge region 11 of the crystalline silicon substrate 10 is significantly better than the negative impact of the first doped polysilicon layer 30 on the first edge region 11.

[0127] In addition, in the second and third methods described above, the second passivation layer (not shown in the figure) located in the first intermediate region 14 and the first isolation region 61 is located between the first main surface of the crystalline silicon substrate 10 and the anti-reflection layer 70.

[0128] In a preferred embodiment, in the solar cell provided by any of the above embodiments, the crystalline silicon substrate 10 has an n-type conductivity, the first doped polycrystalline silicon layer 30 has an n-type conductivity, and the carrier collection layer 50 has a p-type conductivity.

[0129] In summary, in this embodiment of the invention, the first passivation layer 20 and the first doped polycrystalline silicon layer 30 work together to passivate the surface of the crystalline silicon substrate 10. The first passivation layer 20, the first doped polycrystalline silicon layer 30, and the first electrode structure 40 work together to not only passivate the surface of the crystalline silicon substrate 10 but also transport charge carriers. Therefore, in the solar cell provided by this embodiment of the invention, the first edge region 11 and the second edge region 12 are passivated by the first passivation layer 20 and the first doped polycrystalline silicon layer 30, and the second intermediate region 13 is transported by the first passivation layer 20, the first doped polycrystalline silicon layer 30, and the first electrode structure 40.

[0130] The solar cell provided in this embodiment of the invention provides a first passivation layer 20 by providing a first passivation layer 20 in a first edge region 11 of a first main surface of a crystalline silicon substrate 10 and a second edge region 12 of a second main surface of the crystalline silicon substrate 10, and providing a first doped polycrystalline silicon layer 30 on the first passivation layer 20. Furthermore, the first passivation layer 20 provided in the second edge region 12 is connected to the first passivation layer 20 provided in the second intermediate region 13 of the second main surface of the crystalline silicon substrate 10. This ensures that the first passivation layer 20 in the first edge region 11 and the second edge region 12 is connected to the first passivation layer 30 in the second intermediate region 13. The consistency of the passivation layer 20 ensures the uniformity of passivation of the first edge region 11, the second edge region 12, and the second intermediate region 13. Furthermore, the first passivation layer 20, in conjunction with the first doped polycrystalline silicon layer 30, can ensure the integrity of the film layers in the first edge region 11 and the second edge region 12, thereby enhancing the passivation effect of the first edge region 11 and the second edge region 12 and reducing carrier recombination in the second edge region 12 and the first edge region 11, thus effectively reducing carrier recombination in the solar cell.

[0131] Furthermore, by connecting the first passivation layer 20 disposed in the second intermediate region 13 with the first passivation layer 20 disposed in the second edge region 12, the structural integrity of the first passivation layer 20 and the first doped polysilicon layer 30 disposed on the second main surface can be ensured, and the risk of leakage current at the edge side of the first doped polysilicon layer 30 in the second intermediate region 13 can also be reduced. In addition, the first passivation layer 20, the first doped polysilicon layer 30, and the first electrode structure 40 in the second intermediate region 13 cooperate to ensure carrier collection and transport.

[0132] like Figure 1As shown, this embodiment of the invention also provides a solar cell, comprising: A crystalline silicon substrate 10 includes a first main surface and a second main surface opposite to each other, and a side surface located between the first main surface and the second main surface. The first main surface of the crystalline silicon substrate 10 includes a first intermediate region 14, a first isolation region 61 disposed around the first intermediate region 14, and a first edge region 11 disposed around the first isolation region 61. The second main surface of the crystalline silicon substrate 10 includes a second intermediate region 13 and a second edge region 12 disposed around the second intermediate region 13. The second intermediate region 13 includes alternating first conductive regions 131 and second conductive regions 132, and a second isolation region 62 located between adjacent first conductive regions 131 and second conductive regions 132. The conductive region adjacent to the second edge region 12 is the first conductive region 131, that is, a second isolation region 62 is provided between the second edge region 12 and the second conductive region 132. The roughness of the first main surface corresponding to the first intermediate region 14 is greater than the roughness of the first main surface corresponding to the first isolation region 61, and the roughness of the first main surface corresponding to the first isolation region 61 is greater than or equal to the roughness of the first main surface corresponding to the first edge region 11. The first main surface corresponding to the first intermediate region 14 is a textured surface, the first main surface corresponding to the first isolation region 61 is a polished surface, and the first main surface corresponding to the first edge region 11 is a polished surface. The second main surfaces corresponding to the first conductive region 131, the second isolation region 62, and the second edge region 12 are polished surfaces, and the second main surface corresponding to the second conductive region 132 is a textured surface.

[0133] The first passivation layer 20 is disposed on the second main surface corresponding to the first conductive region 131, the second main surface corresponding to the second isolation region 62, the second main surface corresponding to the second edge region 12, the side surface, and the first main surface corresponding to the first edge region 11. The first passivation layer 20 can be a silicon oxide layer.

[0134] A first doped polysilicon layer 30 is disposed on the first conductive region 131, the second isolation region 62, the second edge region 12, the side surface, and the first passivation layer 20 corresponding to the first edge region 11. The conductivity type of the first doped polysilicon layer 30 is the same as that of the crystalline silicon substrate 10. Furthermore, the thickness of the first doped polysilicon layer 30 corresponding to the first edge region 11 increases in a direction away from the first intermediate region 14.

[0135] The second passivation layer is disposed on the first doped polysilicon layer 30 corresponding to the side surface and the first edge region 11, and on the first main surface corresponding to the first isolation region 61 and the first intermediate region 14. The hydrogen atom content in the second passivation layer is greater than the hydrogen atom content in the first passivation layer 2. The second passivation layer can be an aluminum oxide layer.

[0136] An antireflection layer 70 is disposed on the second passivation layer corresponding to the side surface, the first edge region 11, the first isolation region 61, and the first intermediate region 14. The antireflection layer 70 may include a silicon nitride layer.

[0137] The intrinsic amorphous silicon layer 51 is disposed on the first doped polycrystalline silicon layer 30 corresponding to the first conductive region 131 and the second isolation region 62, and on the anti-reflection layer 70 corresponding to the side.

[0138] A doped amorphous silicon layer 52 is disposed on the first conductive region 131, the second isolation region 62 and the intrinsic amorphous silicon layer 51 corresponding to the side. The doped amorphous silicon layer 52 contains silicon grains with a particle size of no more than 100 nanometers. The conductivity type of the doped amorphous silicon layer 52 is opposite to that of the crystalline silicon substrate 10.

[0139] The first transparent conductive film layer 41 is disposed on the first doped polycrystalline silicon layer 30 corresponding to the first conductive region 131 and the second edge region 12, and on the doped non-polycrystalline silicon layer 52 corresponding to the side.

[0140] The first metal electrode 42 is disposed on the first transparent conductive film layer 41 corresponding to the first conductive region 131.

[0141] The second transparent conductive film layer 81 is disposed on the doped non-polycrystalline silicon layer 52 corresponding to the second conductive region 132.

[0142] The second metal electrode 82 is disposed on the second transparent conductive film layer 81 corresponding to the second conductive region 132.

[0143] The conductivity type of the crystalline silicon substrate 10 can be n-type. Correspondingly, the conductivity type of the first doped polycrystalline silicon layer 30 is n-type, and the conductivity type of the doped non-polycrystalline silicon layer 52 is p-type.

[0144] The first main surface of the crystalline silicon substrate 10 can be the front side of the crystalline silicon substrate 10, and the second main surface can be the back side of the crystalline silicon substrate 10.

[0145] like Figure 2 As shown, this embodiment of the invention also provides a solar cell, comprising: A crystalline silicon substrate 10 includes a first main surface and a second main surface opposite to each other, and a side surface located between the first main surface and the second main surface. The first main surface of the crystalline silicon substrate 10 includes a first intermediate region 14, a first isolation region 61 disposed around the first intermediate region 14, and a first edge region 11 disposed around the first isolation region 61. The roughness of the first main surface corresponding to the first intermediate region 14 is greater than the roughness of the first main surface corresponding to the first isolation region 61, and the roughness of the first main surface corresponding to the first isolation region 61 is greater than or equal to the roughness of the first main surface corresponding to the first edge region 11. The first main surface corresponding to the first intermediate region 14 is textured, the first main surface corresponding to the first isolation region 61 is polished, and the first main surface corresponding to the first edge region 11 is polished. The second main surface is polished.

[0146] The doped diffusion layer extends from the first main surface corresponding to the first intermediate region 14 into the interior of the crystalline silicon substrate 10. The conductivity type of the doped diffusion layer is opposite to that of the crystalline silicon substrate 10.

[0147] A first passivation layer 20 is disposed on the second main surface, the side surface, and the first main surface corresponding to the first edge region 11. The first passivation layer 20 may be a silicon oxide layer.

[0148] A first doped polysilicon layer 30 is disposed on the second main surface, the side surface, and the first passivation layer 20 corresponding to the first edge region 11. The conductivity type of the first doped polysilicon layer 30 is the same as that of the crystalline silicon substrate 10. Furthermore, the thickness of the first doped polysilicon layer 30 corresponding to the first edge region 11 increases in a direction away from the first intermediate region 14.

[0149] The second passivation layer is disposed on the second main surface, the side surface, and the first doped polysilicon layer 30 corresponding to the first edge region 11, on the first main surface corresponding to the first isolation region 61, and on the doped diffusion layer corresponding to the first intermediate region 14. The hydrogen atom content in the second passivation layer is greater than the hydrogen atom content in the first passivation layer 2. The second passivation layer can be an aluminum oxide layer.

[0150] An antireflection layer 70 is disposed on a second passivation layer corresponding to the second main surface, side surface, first edge region 11, first isolation region 61, and first intermediate region 14. The antireflection layer 70 may include a silicon nitride layer.

[0151] The first electrode structure 40 passes through the antireflection layer 70 and the second passivation layer corresponding to the first intermediate region 14 and contacts the doped diffusion layer. The first electrode structure 40 is a metal electrode.

[0152] The second electrode structure 80 passes through the antireflection layer 70 and the second passivation layer corresponding to the second main surface and contacts the first doped polysilicon layer 30. The second electrode structure 80 is a metal electrode.

[0153] The conductivity type of the crystalline silicon substrate 10 can be n-type. Correspondingly, the conductivity type of the first doped polycrystalline silicon layer 30 is n-type, and the conductivity type of the doped diffusion layer is p-type.

[0154] The first main surface of the crystalline silicon substrate 10 can be the front side of the crystalline silicon substrate 10, and the second main surface can be the back side of the crystalline silicon substrate 10.

[0155] Furthermore, embodiments of the present invention provide a method for fabricating a solar cell. For example... Figure 8 As shown, the preparation method may include the following steps: Step S1: Provide a crystalline silicon substrate 10, which includes a first main surface and a second main surface opposite to each other. The first main surface of the crystalline silicon substrate 10 includes a first intermediate region 14 and a first edge region 11 disposed around the first intermediate region 14.

[0156] Step S2: A first passivation layer 20 is formed on the first edge region 11, and a first doped polysilicon layer 30 is formed on the first passivation layer 20.

[0157] Specifically, for the first passivation layer 20 and the first doped polysilicon layer 30 formed in step S2, the thickness of the first doped polysilicon layer 30 on the side closer to the first intermediate region 14 of the crystalline silicon substrate 10 is less than the thickness of the first doped polysilicon layer 30 on the side farther from the first intermediate region 14 of the crystalline silicon substrate 10.

[0158] Since reducing the thickness helps to reduce the parasitic absorption of the doped polycrystalline silicon layer, in the solar cell obtained by the fabrication method provided in this embodiment of the invention, when the coverage area of ​​the first doped polycrystalline silicon layer 30 is the same, the thickness near the first intermediate region is smaller, thus reducing the overall parasitic absorption of light by the first doped polycrystalline silicon layer 30 and increasing the short-circuit current of the solar cell. It can also be understood that even if the coverage area of ​​the first doped polycrystalline silicon layer 30 is appropriately increased, the overall parasitic absorption of light by the first doped polycrystalline silicon layer 30 will not increase.

[0159] The silicon substrate provided in step S1 can be either an n-type silicon substrate or a p-type silicon substrate.

[0160] One specific implementation of step S2 may include: Step S21: A first passivation layer 20, a first doped polysilicon layer 30, and a mask layer 30' are sequentially stacked on the first edge region 11 and part of the first intermediate region 14 of the first main surface of the crystalline silicon substrate 10, wherein the thickness of the first doped polysilicon layer 30 and the mask layer 30' is along the direction from the edge to the center. Figure 10 The arrow D1 in the image indicates a decrease in the direction from the edge towards the center; Step S22: Remove the mask layer 30' on the first main surface corresponding to the area outside the first edge region 11; Step S23: Remove the first doped polysilicon layer 30 and the first passivation layer 20 from the first main surface, which correspond to the area outside the first edge region 11. Step S24: Remove the remaining mask layer 30'.

[0161] Step S21 further includes simultaneously and sequentially stacking a first passivation layer 20, a first doped polysilicon layer 30, and a mask layer 30' on the side surface and the second main surface of the crystalline silicon substrate 10.

[0162] When the first main surface of the crystalline silicon substrate 10 also includes a first isolation region 61 located between the first intermediate region 14 and the first edge region 11, and disposed around the first intermediate region 14, in step S21, a first passivation layer 20, a first doped polysilicon layer 30, and a mask layer 30' are also sequentially stacked on the first isolation region 61. It can be understood that, since the thicknesses of the first doped polysilicon layer 30 and the mask layer 30' are along the direction from the edge to the center (… Figure 10 The thickness of the first doped polysilicon layer 30 formed on the first isolation region 61 is less than that formed on the first edge region 11, as indicated by arrow D1 (in the direction from the edge towards the center). Similarly, the thickness of the mask layer 30' formed on the first isolation region 61 is less than that formed on the first edge region 11. Furthermore, the first passivation layer 20 formed on the first isolation region 61 has a minimum thickness compared to the first passivation layer 20 formed on the first edge region 11.

[0163] In step S21, the first passivation layer 20 and the first doped polysilicon layer 30 can be formed using plasma vapor deposition (PECVD). Two silicon substrates 10 can be placed in a slot of a graphite boat, with their first main surfaces facing each other. Thus, when the first passivation layer 20, the first doped polysilicon layer 30, and the mask layer 30' are deposited onto the second main surface of the silicon substrate 10, due to the winding deposition, the first passivation layer 20, the first doped polysilicon layer 30, and the mask layer 30' will be formed on the portion of the first edge region 11, the first isolation region 61, and the first middle region 12 of the first main surface near the first isolation region 61 (i.e., obtaining...). Figure 10(The cross-sectional structure corresponding to step S21 in the diagram). Placing two crystalline silicon substrates 10 in a slot position on the graphite boat can improve the production efficiency of solar cells.

[0164] In step S22, the mask layer 30' corresponding to the first edge region 11 is retained, and the mask layer 30' located on the first middle region 12 and the first isolation region 61 is removed.

[0165] In step S23, the first doped polysilicon layer 30 and the first passivation layer 20 corresponding to the first edge region 11 are retained, and the first doped polysilicon layer 30 and the first passivation layer 20 located on the first middle region 12 and the first isolation region 61 are removed.

[0166] In step S22, the mask layer 30' corresponding to the area outside the first edge region 11 is removed by laser or wet etching. Since the thickness of the mask layer 30' decreases from the edge to the center, by controlling the wet etching time, the mask layer 30' located on the first intermediate region 12 and the first isolation region 61 can be removed while the mask layer 30' is retained on the first edge region 11. Wet etching can avoid damage to the silicon substrate 10 caused by laser.

[0167] In addition, by taking steps S21 to S24 above, the height difference between the first edge region 11 and the middle region 14 can be effectively controlled to be greater than or equal to 0.5 μm and less than 5 μm. This can reduce the impact damage to the first edge region 11 during the manufacturing process, thereby improving the yield of finished solar cells.

[0168] In step S2, there are two possible schemes for forming the first passivation layer 20 in the second intermediate region 13 of the second main surface of the silicon substrate 10. The first scheme involves forming the first passivation layer 20 across the entire surface of the second intermediate region 13, with the first passivation layer 20 in the second intermediate region 13 communicating with the first passivation layer 20 in the second edge region 12, thereby covering the entire second main surface of the silicon substrate 10 with the first passivation layer 20. The second scheme involves forming the first passivation layer 20 at intervals in the second intermediate region 13, with each of these intervals communicating with the first passivation layer 20 in the second edge region 12. The cross-sectional structural changes corresponding to these two schemes and a structural change corresponding to step S3 based on these two schemes are as follows: Figure 9 As shown.

[0169] Understandably, the thickness of the first passivation layer 20, the first doped polysilicon layer 30, and the mask layer 30' formed on the first main surface of the silicon substrate 10 can decrease from the edge to the center. This means that the first passivation layer 20, the first doped polysilicon layer 30, and the mask layer 30' are formed only in the edge region of the first main surface of the silicon substrate 10 (this edge region can be the first edge region 11, or the collective term for the first edge region 11 and the first isolation region 61, or the collective term for the first edge region 11, the first isolation region 61, and the portion of the first intermediate region 14 near the first isolation region 61), while the surface of the silicon substrate 10 remains exposed in the intermediate region of the first main surface of the silicon substrate 10.

[0170] In an optional embodiment, step S21 may further include simultaneously and sequentially stacking a first passivation layer 20, a first doped polysilicon layer 30, and a mask layer 30' on the side surface of the crystalline silicon substrate 10. The structural change corresponding to this step S21 is as follows: Figure 10 As shown.

[0171] By using the first passivation layer 20, the first doped polysilicon layer 30, and the mask layer 30' whose thickness decreases from the edge to the center, the mask layer 30' at different positions can be differentiated by wet etching in the subsequent step S22. During the wet etching process, by controlling the wet etching parameters, the mask layer 30' corresponding to the first edge region 11 can be retained. Compared to laser processing, this structure, where the thickness decreases from the edge to the center, combined with wet etching, ensures that the first passivation layer 20 and the first doped polysilicon layer 30 in the first edge region 11 can be retained. Furthermore, the difference between the first isolation region 61 and the first intermediate region 14 (i.e., after step S22, the first isolation region 61 has a thinner first passivation layer 20 and the first doped polysilicon layer 30, while the first intermediate region 14 may not have any film layer) ensures that after step S23, the first intermediate region 14 forms a textured surface, while the first isolation region 61 is a polished surface. In other words, by processing in one step S23, the polished surface of the first isolation region 61 and the textured surface of the first intermediate region 14 are obtained, effectively simplifying the fabrication process and facilitating industrialization and widespread adoption.

[0172] The mask layer 30' can be a doped silicon glass layer or a combination of a doped silicon glass layer and a silicon nitride layer stacked on the doped silicon glass layer.

[0173] In step S22, if a mask layer 30', a first doped polysilicon layer 30, and a first passivation layer 20 are present in the first intermediate region 14, the laser processing can completely remove the mask layer 30', a portion of the first doped polysilicon layer 30, and the first passivation layer 20 corresponding to the first main surface of the first intermediate region 14, or completely remove the aforementioned films. If the aforementioned films are present in the portion of the first intermediate region 14 near the first edge region 11, while other portions of the first intermediate region 14 do not have the aforementioned films (e.g., ... Figure 10 (The structure formed in step S21 shown) can then be removed by laser only the portion of the above-mentioned film layer present in the first intermediate region 14 near the first edge region 11.

[0174] For wet etching to remove the mask layer 30' corresponding to the first intermediate region 14 of the first main surface, if the aforementioned film layer exists in the portion of the first intermediate region 14 near the first edge region 11, while the aforementioned film layer does not exist in other portions of the first intermediate region 14 (e.g.) Figure 10 (The structure formed in step S21 is shown). Then, the wet etching in step S22 can remove the mask layer 30' near the first edge region 11 in the first intermediate region 14 corresponding to the first main surface. The corresponding structural change is as follows: Figure 10 As shown.

[0175] In step S1, the first main surface and the second main surface of the crystalline silicon substrate 10 can be polished. Correspondingly, in step S23, while removing the first doped polysilicon layer 30 and the first passivation layer 20 on the first main surface corresponding to the area outside the first edge region 11, texturing can be performed on the first main surface corresponding to the first intermediate region 14.

[0176] In step S23, the first doped polysilicon layer 30 and the first passivation layer 20 can be simultaneously etched and removed during the texturing process using an alkaline solution.

[0177] Furthermore, for the second intermediate region 13 of the second main surface of the crystalline silicon substrate 10, which includes alternating first conductive regions 131 and second conductive regions 132 and a second isolation region 62 located between adjacent first conductive regions 131 and second conductive regions 132, before texturing, step 23 may further include: laser removal of the mask layer 30' corresponding to the portion of the second conductive region 132 near the second conductive region 132 and the second isolation region 62. It should be noted that the laser in step S23 may only remove the mask layer 30' corresponding to the portion of the second conductive region 132 near the second conductive region 132 and the second isolation region 62, or the laser may simultaneously remove the mask layer 30', the first doped polysilicon layer 30, and the first passivation layer 20 corresponding to the portion of the second conductive region 132 near the second conductive region 132 and the second isolation region 62. Regarding the laser removal of the mask layer 30' corresponding to the portion of the second conductive region 132 and the second isolation region 62 near the second conductive region 132 in step S23, during the texturing process, the portion of the second conductive region 132 and the second isolation region 62 near the second conductive region 132 can be texturized simultaneously, thereby removing the film layers (first doped polysilicon layer 30 and first passivation layer 20) corresponding to the portion of the second conductive region 132 and the second isolation region 62 near the second conductive region 132, so that the portion corresponding to the second conductive region 132 and the second isolation region 62 near the second conductive region 132 forms a textured structure.

[0178] Step S24: Remove the remaining mask layer 30'.

[0179] The structural changes corresponding to steps S23 and S24 are as follows: Figure 10 As shown.

[0180] This step can remove the remaining mask layer 30' by etching with an HF solution.

[0181] It is worth noting that the mass fraction of the solution and the etching parameters used for alkaline etching and HF etching can be adjusted according to the specific process. The mass fraction of the solution and the etching parameters used for alkaline etching and HF etching are not limited here.

[0182] Through the above steps S21 to S24, the first edge region 11 and the first isolation region 61 of the first main surface of the crystalline silicon substrate 10 can be polished, and the first intermediate region 14 can be formed with a textured surface independently of the first edge region 11 and the first isolation region 61. This further enhances the passivation effect of the first edge region 11 and the first isolation region 61 while ensuring that the first intermediate region 14 has strong light-trapping properties, thereby improving the photoelectric conversion efficiency of the solar cell.

[0183] Based on the formation of the first conductive region 131 and the second conductive region 132 on the second main surface of the crystalline silicon substrate 10 in step S2 above, after step S2 and before step S3, the method further includes: step S2': An intrinsic amorphous silicon layer 51 and a doped amorphous silicon layer 52 disposed on the intrinsic amorphous silicon layer 51 are sequentially stacked on the portion of the second conductive region 132 and the second isolation region 62 near the second conductive region 132, the remaining first doped polycrystalline silicon layer 30 on the second main surface, and the antireflection layer 70 on the side of the crystalline silicon substrate 10. The doped amorphous silicon layer 52 and the intrinsic amorphous silicon layer 51 corresponding to the first conductive region are then removed to form a back-contact heterojunction solar cell. The structural change corresponding to step S2' is as follows: Figure 11 As shown.

[0184] In this embodiment of the invention, regardless of whether step S2 is the first or the second scheme, step S2 further includes: step S25: forming a second passivation layer (not shown in the figure) and an anti-reflection layer 70 on the first doped polysilicon layer 30 in the first intermediate region 14, the first isolation region 61, and the first edge region 11. It can be understood that in the first intermediate region 14, the first isolation region 61, and the first edge region 11, the second passivation layer is located between the first doped polysilicon layer 30 and the anti-reflection layer 70.

[0185] Furthermore, in this embodiment of the invention, step S25 further includes: simultaneously forming a second passivation layer (not shown in the figure) and an antireflection layer 70 on the first doped polysilicon layer 30 on the side of the crystalline silicon substrate 10. Understandably, on the side of the crystalline silicon substrate 10, the second passivation layer is located between the first doped polysilicon layer 30 and the antireflection layer 70.

[0186] The structural changes corresponding to step S25 are as follows: Figure 10 As shown.

[0187] Furthermore, based on the second scheme of step S2 and step S2' above, step S3 includes the following steps S31 and S32: Step S31: Simultaneously form transparent conductive film layers on the side surfaces of the second conductive region 131, the first conductive region 132, the second isolation region 62, and the crystalline silicon substrate 10, and remove part of the transparent conductive film layer on the second isolation region 62 to form a first transparent conductive film layer 41 corresponding to the first conductive region 131 and a second transparent conductive film layer 81 corresponding to the second conductive region 132, wherein the first transparent conductive film layer 41 and the second transparent conductive film layer 81 are electrically isolated from each other.

[0188] Step S32: Prepare a first metal electrode 42 on the first transparent conductive film layer 41, and prepare a second metal electrode 82 on the second transparent conductive film layer 81.

[0189] The structural changes corresponding to steps S31 and S32 above are as follows: Figure 11 As shown.

[0190] The above-mentioned methods for preparing solar cells mainly involve deposition, laser or wet etching processes, and the processes are relatively simple and easy to industrialize and promote.

[0191] The above steps are provided only to help understand the method, structure, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A solar cell, characterized in that, include: A crystalline silicon substrate (10) includes a first main surface and a second main surface opposite to each other. The first main surface of the crystalline silicon substrate (10) includes a first intermediate region (14) and a first edge region (11) disposed around the first intermediate region (14). A first passivation layer (20) is disposed in the first edge region (11); A first doped polysilicon layer (30) is disposed on the first passivation layer (20); The thickness of the first doped polysilicon layer (30) on the side closer to the first intermediate region (14) of the crystalline silicon substrate (10) is less than the thickness of the first doped polysilicon layer (30) on the side farther away from the first intermediate region (14) of the crystalline silicon substrate (10).

2. The solar cell according to claim 1, characterized in that, The thickness of the first doped polycrystalline silicon layer (30) disposed in the first edge region (11) increases from the side near the first intermediate region (14) of the crystalline silicon substrate (10) to the side away from the first intermediate region (14) of the crystalline silicon substrate (10). Optionally, the thickness of the first doped polysilicon layer (30) on the side closest to the first intermediate region (14) of the crystalline silicon substrate (10) is not less than 50% of the thickness of the first doped polysilicon layer (30) on the side furthest from the first intermediate region (14) of the crystalline silicon substrate (10); Optionally, the thickness of the first passivation layer (20) on the side closer to the first intermediate region (14) of the crystalline silicon substrate (10) is less than the thickness of the first passivation layer (20) on the side farther from the first intermediate region (14) of the crystalline silicon substrate (10). Optionally, the thickness of the first passivation layer (20) disposed in the first edge region (11) increases from the side near the first intermediate region (14) of the crystalline silicon substrate (10) to the side away from the first intermediate region (14) of the crystalline silicon substrate (10). Optionally, the crystalline silicon substrate (10) further includes a side surface located between the first main surface and the second main surface, wherein the first passivation layer (20) and the first doped polycrystalline silicon layer (30) extend to the side surface of the crystalline silicon substrate (10); Optionally, the second main surface of the crystalline silicon substrate (10) includes a second intermediate region (13) and a second edge region (12) disposed around the second intermediate region (13), wherein the first passivation layer (20) and the first doped polycrystalline silicon layer (30) extend to the second edge region (12) of the second main surface. Optionally, the conductivity type of the first doped polysilicon layer (30) is the same as that of the crystalline silicon substrate (10); Optionally, the conductivity type of the crystalline silicon substrate (10) is n-type, and the conductivity type of the first doped polycrystalline silicon layer (30) is n-type; Optionally, the first main surface is the front side of the crystalline silicon substrate (10), and the second main surface is the back side of the crystalline silicon substrate (10).

3. The solar cell according to claim 1 or 2, characterized in that, The first main surface of the crystalline silicon substrate (10) further includes a first isolation region (61) located between the first intermediate region (14) and the first edge region (11) and surrounding the first intermediate region (14); a second passivation layer is disposed on the first isolation region (61) and the first intermediate region (14), and an anti-reflection layer (70) is disposed on the second passivation layer, wherein the hydrogen atom content per unit area of ​​the second passivation layer is greater than the hydrogen atom content per unit area of ​​the first passivation layer (20); the roughness of the first main surface corresponding to the first intermediate region (14) is greater than the roughness of the first main surface corresponding to the first isolation region (61), and the roughness of the first main surface corresponding to the first isolation region (61) is greater than or equal to the roughness of the first main surface corresponding to the first edge region (11); Optionally, the first edge region (11) includes a polished structure or a tower base structure; Optionally, the first intermediate region (14) has a velvety texture; Optionally, the first isolation zone (61) includes a polished structure or a tower base structure; Optionally, the first isolation region (61) further includes a velvet structure, the height of which is less than the height of the velvet structure in the first intermediate region (14). Optionally, the height difference between the first main surface of the crystalline silicon substrate corresponding to the first intermediate region (14) and the first main surface of the crystalline silicon substrate corresponding to the first edge region (11) is greater than or equal to 0.5 μm and less than 5 μm; Optionally, the reflectivity of the side surface and the first edge region (11) of the crystalline silicon substrate (10) is greater than the reflectivity of the first middle region (14) of the crystalline silicon substrate (10); Optionally, the first passivation layer (20) includes a silicon oxide layer, and the second passivation layer includes an aluminum oxide layer; Optionally, the antireflective layer (70) includes a silicon nitride layer; Optionally, the width of the first edge region (11) is 0.1 μm to 1000 μm; Optionally, the width of the second edge region (12) is 0.1 μm to 1000 μm; Optionally, the width of the first isolation region (61) is 0.001 μm to 10 μm; Optionally, the total width of the first isolation area (61) and the first edge area (11) is not greater than 1 mm; Optionally, the second passivation layer and the antireflection layer (70) further extend to the first doped polysilicon layer (30) corresponding to the first edge region (11); Optionally, the second passivation layer and the antireflection layer (70) also extend to the first doped polysilicon layer (30) on the side of the crystalline silicon substrate (10).

4. The solar cell according to any one of claims 1 to 3, characterized in that, The first passivation layer (20) and the first doped polysilicon layer (30) extend to the second intermediate region (13) of the second main surface of the crystalline silicon substrate (10). The solar cell further includes: a carrier collection layer (50) disposed in a first intermediate region (14) on the first main surface of the crystalline silicon substrate (10), a second passivation layer disposed on the carrier collection layer (50), and the conductivity type of the carrier collection layer (50) being opposite to the conductivity type of the first doped polycrystalline silicon layer (30); Optionally, the carrier collection layer (50) has a p-type conductivity. Optionally, the thickness of the first doped polysilicon layer (30) corresponding to the second intermediate region (13) of the crystalline silicon substrate (10) is greater than the thickness of the first doped polysilicon layer (30) on the side closer to the first intermediate region (14) of the crystalline silicon substrate (10). Optionally, the carrier collection layer (50) includes a doped diffusion layer extending from the first main surface into the interior of the crystalline silicon substrate (10); Optionally, the antireflection layer (70) also extends to the first doped polycrystalline silicon layer (30) located on the second main surface of the crystalline silicon substrate (10); Optionally, the second passivation layer also extends to the first doped polycrystalline silicon layer (30) located on the second main surface of the crystalline silicon substrate (10); Optionally, the solar cell further includes: a first electrode structure (40) electrically connected to the first doped polycrystalline silicon layer (30) corresponding to the second intermediate region (13), and a second electrode structure (80) electrically connected to the carrier collection layer (50).

5. The solar cell according to any one of claims 1 to 3, characterized in that, The second intermediate region (13) of the second main surface of the crystalline silicon substrate (10) includes an alternately arranged first conductive region (131) and a second conductive region (132), and a second isolation region (62) located between adjacent first conductive regions (131) and second conductive regions (132). The first conductive region (131) is provided with the first passivation layer (20) and the first doped polycrystalline silicon layer (30). The solar cell further includes a carrier collection layer (50) disposed in the second conductive region (132), wherein the conductivity type of the carrier collection layer (50) is opposite to that of the first doped polycrystalline silicon layer (30). Optionally, the thickness of the first doped polysilicon layer (30) disposed in the first conductive region (131) is greater than the thickness of the first doped polysilicon layer (30) on the side near the first intermediate region (14) of the crystalline silicon substrate (10). Optionally, the conductive region closest to the second edge region (12) is the first conductive region (131), and the first passivation layer (20) and the first doped polysilicon layer (30) located in the first conductive region (131) closest to the second edge region (12) are respectively connected to the first passivation layer (20) and the first doped polysilicon layer (30) located in the second edge region (12); Optionally, the first conductive region (131) includes a first portion extending along a first direction and a second portion extending along a second direction intersecting the first direction, and the second conductive region (132) includes a third portion extending along the first direction and a fourth portion extending along the second direction; in the second direction, the first portion and the third portion are alternately arranged; in the first direction, the second portion and the fourth portion are alternately arranged; or, the first conductive region (131) and the second conductive region (132) are both elongated and both extend along the second direction; in the first direction, the first conductive region (131) and the second conductive region (132) are alternately arranged. Optionally, the first direction and the second direction are perpendicular.

6. The solar cell according to claim 5, characterized in that, The carrier collection layer (50) includes a doped diffusion layer extending from the second main surface corresponding to the second conductive region (132) into the interior of the crystalline silicon substrate (10); or, The carrier collection layer (50) includes: a third passivation layer and a second doped polysilicon layer disposed on the third passivation layer; Optionally, the third passivation layer includes a silicon oxide layer; Optionally, the second passivation layer and the antireflection layer (70) further extend to the second main surface of the crystalline silicon substrate (10); Optionally, the solar cell further includes: a first electrode structure (40) electrically connected to the first doped polycrystalline silicon layer (30) corresponding to the first conductive region (131), and a second electrode structure (80) electrically connected to the carrier collection layer (50).

7. The solar cell according to claim 5, characterized in that, The carrier collection layer (50) includes: an intrinsic amorphous silicon layer (51) and a doped non-polycrystalline silicon layer (52) disposed on the intrinsic amorphous silicon layer (51). Optionally, the doped non-polycrystalline silicon layer (52) contains silicon grains with a particle size of no more than 100 nanometers; Optionally, the doped non-polycrystalline silicon layer (52) contains silicon grains with a particle size of no more than 10 nanometers; Optionally, the doped non-polycrystalline silicon layer (52) further includes silicon oxide and / or silicon carbide; Optionally, the intrinsic amorphous silicon layer (51) and the doped amorphous silicon layer (52) extend to the side of the crystalline silicon substrate (10), and the intrinsic amorphous silicon layer (51) is located on the side of the first doped polycrystalline silicon layer (30) away from the crystalline silicon substrate (10). Optionally, when the crystalline silicon substrate (10) has a second passivation layer and an antireflection layer (70) on its side, the intrinsic amorphous silicon layer (51) is located on the antireflection layer (70); Optionally, the solar cell further includes: a first electrode structure (40) electrically connected to the first doped polycrystalline silicon layer (30) corresponding to the first conductive region (131), and a second electrode structure (80) electrically connected to the carrier collection layer (50). Optionally, the first electrode structure (40) includes a first transparent conductive film layer (41) and a first metal electrode (42) located on the first transparent conductive film layer (41). Optionally, the first transparent conductive film layer (41) also extends to the second edge region (12) and the side of the crystalline silicon substrate (10); Optionally, the second electrode structure (80) includes a second transparent conductive film layer (81) and a second metal electrode (82) located on the second transparent conductive film layer (81).

8. A method for preparing a solar cell, characterized in that, include: Step S1: Provide a crystalline silicon substrate (10), the crystalline silicon substrate (10) includes a first main surface and a second main surface opposite to each other, the first main surface of the crystalline silicon substrate (10) includes a first intermediate region (14) and a first edge region (11) disposed around the first intermediate region (14). Step S2: A first passivation layer (20) is formed on the first edge region (11), and a first doped polysilicon layer (30) is formed on the first passivation layer (20). The thickness of the first doped polysilicon layer (30) on the side closer to the first intermediate region (14) of the crystalline silicon substrate (10) is less than the thickness of the first doped polysilicon layer (30) on the side farther from the first intermediate region (14) of the crystalline silicon substrate (10).

9. The preparation method according to claim 8, characterized in that, Step S2 specifically includes: Step S21: A first passivation layer (20), a first doped polysilicon layer (30), and a mask layer (30') are sequentially stacked on the first edge region (11) and part of the first middle region (14) of the first main surface of the crystalline silicon substrate (10), wherein the thickness of the first doped polysilicon layer (30) and the mask layer (30') decreases along the direction from the edge to the center; Step S22: Remove the mask layer (30') on the first main surface corresponding to the area outside the first edge region (11); Step S23: Remove the first doped polysilicon layer (30) and the first passivation layer (20) on the first main surface, which correspond to the area outside the first edge region (11). Step S24: Remove the remaining mask layer (30'); Optionally, in step S22, the mask layer (30') corresponding to the area outside the first edge region (11) is removed by laser or wet etching. Optionally, step S21 further includes simultaneously stacking a first passivation layer (20), a first doped polysilicon layer (30), and a mask layer (30') on the side surface of the crystalline silicon substrate (10) and the second main surface in sequence to form the entire surface. Optionally, the first main surface of the crystalline silicon substrate (10) further includes a first isolation region (61) located between the first intermediate region (14) and the first edge region (11) and surrounding the first intermediate region (14); in step S21, a first passivation layer (20), a first doped polycrystalline silicon layer (30) and a mask layer (30') are also sequentially stacked on the first isolation region (61). Optionally, in step S1, the first main surface and the second main surface of the crystalline silicon substrate (10) are polished; in step S23, while removing the first doped polycrystalline silicon layer (30) and the first passivation layer (20) on the first main surface corresponding to the area outside the first edge region (11), the first main surface corresponding to the first middle region (14) is texturized. Step S2 further includes: step S25, forming a second passivation layer and an antireflection layer (70) on the first doped polysilicon layer (30) of the first intermediate region (14), the first isolation region (61) and the first edge region (11); the hydrogen atom content in the second passivation layer per unit area is greater than the hydrogen atom content in the first passivation layer (20) per unit area; Optionally, step S25 further includes: simultaneously forming a second passivation layer and an anti-reflection layer (70) on the first doped polysilicon layer (30) on the side of the crystalline silicon substrate (10).

10. The preparation method according to claim 9, characterized in that, The second intermediate region (13) of the second main surface of the crystalline silicon substrate (10) includes alternating first conductive regions (131) and second conductive regions (132) and a second isolation region (62) located between adjacent first conductive regions (131) and second conductive regions (132). Step S23 further includes: laser removal of the mask layer (30') corresponding to the portion of the second conductive region (62) near the second conductive region, removal of the first doped polysilicon layer (30) and the first passivation layer (20) corresponding to the portion of the second conductive region (132) near the second conductive region (62), and texturing the portion of the second conductive region (132) and the second isolation region (62) near the second conductive region (132); Optionally, after step S2 and before step S3, the method further includes: step S2', sequentially stacking an intrinsic amorphous silicon layer (51) and a doped non-polycrystalline silicon layer (52) disposed on the intrinsic amorphous silicon layer (51) on the portion of the second conductive region (132) and the second isolation region (62) near the second conductive region (132), the remaining first doped polycrystalline silicon layer (30) on the second main surface, and the anti-reflection layer (70) on the side of the crystalline silicon substrate (10), and removing the doped non-polycrystalline silicon layer (52) and the intrinsic amorphous silicon layer (51) corresponding to the first conductive region; Optionally, step S3 includes the following steps S31 and S32: Step S31: Simultaneously form a transparent conductive film layer (90) on the side of the second conductive region (132), the first conductive region (131), the second isolation region (62) and the crystalline silicon substrate (10), and remove part of the transparent conductive film layer (90) on the second isolation region (62) to form a first transparent conductive film layer (41) corresponding to the first conductive region (131) and a second transparent conductive film layer (81) corresponding to the second conductive region (132), wherein the first transparent conductive film layer (41) and the second transparent conductive film layer (81) are electrically isolated from each other; Step S32: Prepare a first metal electrode (42) on the first transparent conductive film layer (41) and prepare a second metal electrode (82) on the second transparent conductive film layer (81).

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