A back contact cell with multiple anti-reflection structures and its preparation method and application

Abstract

This invention belongs to the field of back-contact battery technology, specifically relating to a back-contact battery with multiple anti-reflection structures, its preparation method, and applications. The back-contact battery with multiple anti-reflection structures includes a silicon wafer with a textured front surface. A thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer are sequentially disposed on the textured front surface of the silicon wafer, forming a multiple anti-reflection structure. The refractive index of the thin aluminum oxide layer is lower than that of the first silicon nitride layer, and the refractive indices of the first silicon nitride layer, second silicon nitride layer, silicon oxynitride layer, first silicon oxide layer, and second silicon oxide layer decrease sequentially. When the battery is packaged into a battery module, the reflected waves from the interfaces of the multiple layers on the textured front surface can cancel each other out, achieving almost all optical benefits without sacrificing passivation. It also ensures resistance to acid and alkali corrosion, maximizing the triple improvement of anti-reflection, passivation, and corrosion resistance, thereby improving module efficiency and battery module stability.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a back contact battery with multiple anti-reflection structures, its preparation method, and its application. Background Technology

[0002] Back-contact batteries (or BC batteries) are a technology that moves all the grid lines and PN junctions on the front of the battery to the back to reduce the blocking of incident light by the grid lines on the front, while only a passivation antireflection film is placed on the front to achieve the maximum photoelectric conversion efficiency. Therefore, BC batteries have been widely used.

[0003] However, in the structure where the front side of the back contact battery is textured, after it is packaged into a battery module, passivation films such as aluminum oxide and silicon nitride are deposited on the pyramid of the textured surface. This will affect the incident angle, scattering and reflection path of the incident light. For example, the textured surface (such as the pyramid with a size of 1-2 μm) causes the normal incident light to actually hit the inclined surface at about 54.74° and often causes secondary bounce. This will affect the optical benefits of the passivation antireflection film set on the front side, as well as the anti-ultraviolet degradation performance, resulting in lower battery module efficiency and battery module stability.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing back-contact batteries, such as low optical benefits and poor UV degradation resistance, which lead to poor battery module efficiency and stability. This invention provides a back-contact battery with multiple anti-reflection structures, its preparation method, and its applications. When packaged into a battery module, this invention enables the reflections from the interfaces of the multiple layers on the front textured surface to cancel each other out, minimizing the weighted reflectivity Rw and maximizing the coupling current Jph. This achieves almost all optical benefits without sacrificing passivation. Simultaneously, it ensures resistance to acid and alkali corrosion, maximizing the triple improvement in anti-reflection, passivation, and corrosion resistance. This benefits the increase in short-circuit current density Jsc and open-circuit voltage Voc, and provides good UV degradation resistance, thereby improving module efficiency and battery module stability.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a back contact battery with a multiple anti-reflection structure, comprising a silicon wafer with a textured front surface, wherein a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer are sequentially disposed on the textured front surface of the silicon wafer to form a multiple anti-reflection structure; wherein the refractive index of the thin aluminum oxide layer is less than that of the first silicon nitride layer, and the refractive indices of the first silicon nitride layer, the second silicon nitride layer, the silicon oxynitride layer, the first silicon oxide layer, and the second silicon oxide layer decrease sequentially; wherein the thickness of the thin aluminum oxide layer is 4-18 nm, the sum of the thicknesses of the first silicon nitride layer and the second silicon nitride layer is 15-100 nm, the sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is 25-150 nm, and the thickness of the silicon oxynitride layer is 5-20 nm.

[0007] In some preferred embodiments of the present invention, the refractive indices of the first silicon nitride layer and the second silicon nitride layer are each independently between 1.95 and 2.5, and the refractive indices of the first silicon oxide layer and the second silicon oxide layer are each independently between 1.5 and 1.8.

[0008] In some preferred embodiments of the present invention, the refractive index ratio of the first silicon nitride layer to the second silicon nitride layer is (1.05-1.20):1.

[0009] In some preferred embodiments of the present invention, the thickness of the first silicon nitride layer is less than the thickness of the second silicon nitride layer.

[0010] In some preferred embodiments of the present invention, the thickness of the first silicon nitride layer is 5-50 nm, the thickness of the second silicon nitride layer is 10-80 nm; and / or, the thickness ratio of the first silicon nitride layer to the second silicon nitride layer is (0.2-0.95):1.

[0011] In some preferred embodiments of the present invention, the nitrogen atom ratio in the first silicon nitride layer is less than or equal to the nitrogen atom ratio in the second silicon nitride layer; and / or, the nitrogen atom ratio in the first silicon nitride layer is 42%-46%, and the nitrogen atom ratio in the second silicon nitride layer is 45%-52%.

[0012] In some preferred embodiments of the present invention, the thickness of the first silicon oxide layer is greater than the thickness of the second silicon oxide layer; and / or, the ratio of the thickness of the first silicon oxide layer to the thickness of the second silicon oxide layer is (2-7):1.

[0013] In some preferred embodiments of the present invention, the thickness of the first silicon nitride layer is less than the thickness of the first silicon oxide layer; and / or, the thickness of the second silicon nitride layer is the same as the thickness of the second silicon oxide layer.

[0014] In some preferred embodiments of the present invention, the back contact battery further includes a third silicon oxide layer disposed outside the second silicon oxide layer, wherein the refractive index of the second silicon oxide layer is greater than the refractive index of the third silicon oxide layer.

[0015] In some preferred embodiments of the present invention, the thicknesses of the first silicon oxide layer, the second silicon oxide layer, and the third silicon oxide layer are each independently between 5-80 nm; and / or, the thicknesses of the first silicon oxide layer, the second silicon oxide layer, and the third silicon oxide layer are the same.

[0016] In some preferred embodiments of the present invention, the back contact battery further includes a thin silicon oxide layer disposed between the front side of the silicon wafer and the thin aluminum oxide layer, the thickness of the thin silicon oxide layer being 1-2 nm.

[0017] In some preferred embodiments of the present invention, the refractive index of the thin silicon oxide layer is less than that of the thin aluminum oxide layer; and / or, the refractive index of the thin silicon oxide layer is 1.4-1.61.

[0018] In some preferred embodiments of the present invention, the back contact battery also satisfies at least one of the following conditions:

[0019] (1) The sum of the thicknesses of the first silicon nitride layer and the second silicon nitride layer is 15-60 nm;

[0020] (2) The sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is 20-100 nm;

[0021] (3) The refractive index of the thin alumina layer is 1.45-1.7;

[0022] (4) The refractive index of the silicon oxynitride layer is 1.45-2.3;

[0023] (5) The nitrogen atom content of the oxynitride layer is 20%-40%;

[0024] (6) The front surface of the silicon wafer has a pyramid structure, and the size of the pyramid structure is less than 3μm.

[0025] In some preferred embodiments of the present invention, the textured surface structure on the front side of the silicon wafer is a micro-nano composite textured surface structure, which includes a micron-scale pyramid structure and a nano-scale additional substructure disposed on the surface of the micron-scale pyramid structure. The size of the micron-scale pyramid structure is 1-3 μm, and the size of the nano-scale additional substructure is 300-500 nm.

[0026] In some preferred embodiments of the present invention, the angle between the micron-scale pyramid structure and the horizontal bottom surface of the silicon wafer is 55°-60°; and / or, the nano-scale additional substructure includes at least one of regular shape and irregular shape, and the regular shape includes at least one of pyramid shape, cone shape and hemispherical shape.

[0027] In some preferred embodiments of the present invention, the back contact battery further includes: a semiconductor film layer, a conductive film layer and a metal electrode sequentially disposed on the back side of a silicon wafer, wherein the semiconductor film layer includes a first semiconductor layer and a second semiconductor layer alternately disposed on the back side, and an isolation region disposed between the first semiconductor layer and the second semiconductor layer, and at least a portion of the isolation region is not provided with a conductive film layer.

[0028] In some preferred embodiments of the present invention, the back contact battery further includes at least one of the following structures:

[0029] Structure 1: The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening regions and the first semiconductor opening regions are arranged alternately, and the area between them is an isolation region.

[0030] Structure 2: The first semiconductor layer includes a first passivation layer and a first doped silicon layer, and the second semiconductor layer includes a second passivation layer and a second doped silicon layer. The first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0031] Structure 3: The back surface of the silicon wafer corresponding to the location of the second semiconductor layer is textured, while the other back surface areas are polished.

[0032] Structure 4: An isolation groove is formed on the portion of the conductive film layer located within the isolation region, and the metal electrode is disposed on the outer surface of the corresponding conductive film layer of the first semiconductor layer and the second semiconductor layer.

[0033] In a second aspect, the present invention provides a method for preparing a back contact battery, which is used to prepare the back contact battery with multiple anti-reflection structures as described in the first aspect. The preparation method includes: S1, providing a silicon wafer with a textured front side; S2, sequentially forming a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer on the front side of the silicon wafer to form a multiple anti-reflection structure.

[0034] In some preferred embodiments of the present invention, S1 provides a silicon wafer with a textured surface, the process of which includes: performing a first etching on the front side of the silicon wafer to form a micron-scale pyramid structure, followed by a second etching to form a nano-scale substructure on the surface of the micron-scale pyramid structure, thereby forming a micro-nano composite textured surface structure.

[0035] In some preferred embodiments of the present invention, the first etching is performed by wet etching with an alkaline solution, and the second etching is performed by wet etching with a mixed solution containing inorganic calcium salt and alkali, plasma etching, or reactive ion etching.

[0036] In some preferred embodiments of the present invention, S1 further includes at least one of the following conditions:

[0037] (1) The alkali concentration in the alkaline solution is 1%-5%;

[0038] (2) The volume concentration of inorganic calcium salt in the mixed solution is 0.01%-1.05%, and the mass concentration of alkali is 1%-5%;

[0039] (3) The inorganic calcium salt in the mixed solution includes at least one of calcium chloride, calcium nitrate, and calcium hydroxide;

[0040] (4) In the plasma etching method, the plasma gas source is selected from at least one of sulfur hexafluoride, chlorine and oxygen. When the three gases are sulfur hexafluoride, chlorine and oxygen, the volume flow ratio of these three gases is (15-20): (5-10): (10-20).

[0041] In some preferred embodiments of the present invention, the preparation method further includes a thin silicon oxide layer disposed between the front side of the silicon wafer and the thin alumina layer.

[0042] In some preferred embodiments of the present invention, the thin silicon oxide layer is grown using a dry oxygen thermal oxidation process. The conditions of the dry oxygen thermal oxidation process include: an atmosphere with oxygen and with or without the introduction of a chlorine source, a thermal oxidation temperature of 600-650°C, and a thermal oxidation time of 5-15 min; wherein the chlorine source includes at least one of trichloroethane and dichloroethylene, and / or the volume flow ratio of chlorine source to oxygen is (0-0.10):1.

[0043] In some preferred embodiments of the present invention, the preparation method further includes: performing a pretreatment before forming a thin silicon oxide layer, the pretreatment including scheme A or scheme B, scheme A including sequential RCA cleaning and HF solution cleaning, and scheme B including sequential ozone oxidation and HF solution cleaning.

[0044] In some preferred embodiments of the present invention, the preparation method further includes the step of forming a third silicon oxide layer outside the second silicon oxide layer, wherein the refractive index of the second silicon oxide layer is greater than the refractive index of the third silicon oxide layer.

[0045] In some preferred embodiments of the present invention, the preparation method further includes any one of the following processes:

[0046] Process 1: The first silicon nitride layer and the second silicon nitride layer are formed by PECVD process, and the Si / N ratio in atomic ratio is controlled between 0.75 and 2.0 in PECVD process, and the temperature of PECVD process is 400-450℃.

[0047] Process 2, the preparation method also includes: hydrogenation annealing or sintering after forming the silicon oxynitride layer; wherein, the conditions for hydrogenation annealing include: annealing temperature of 400-430℃, annealing time of 20-30min; the conditions for sintering include: sintering temperature of 750-800℃, time of 3-5s;

[0048] Process 3: The thin alumina layer is formed by deposition using the ALD process. The conditions for the ALD process include: using trimethylaluminum and water vapor as precursors, and a temperature of 150-250℃.

[0049] Process 4, the preparation method also includes: after depositing a thin alumina layer, annealing activation is performed. The annealing activation conditions include: in the presence of nitrogen or a nitrogen- and hydrogen-containing forming gas, the annealing temperature is 400-450℃, and the annealing time is 10-30min.

[0050] Process 5, the preparation method also includes:

[0051] S01. A first semiconductor layer is formed in the first region on the back side;

[0052] Then proceed with S1 and S2;

[0053] Then, SO2 is performed to form a second semiconductor layer in the second region on the back side; wherein one of the first region and the other of the second region is an N-region and the other is a P-region;

[0054] S03. Then, a conductive film layer is formed on the outer surface of both the first semiconductor layer and the second semiconductor layer on the back side, and an isolation area is naturally formed at the same time.

[0055] S04. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers of the first semiconductor layer and the second semiconductor layer, respectively.

[0056] Process 6, the preparation method also includes:

[0057] S101, provides double-sided polished silicon wafers;

[0058] S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer;

[0059] S103. The first etching opening is performed on the back side obtained in S102 to form the second semiconductor opening region;

[0060] Then, S1 is performed to texturing and cleaning, forming a textured surface on the front side and the second semiconductor opening area, and completely removing the mask layer or retaining part of the mask layer; then S2 is performed.

[0061] S104. Deposit a second semiconductor layer on the back side;

[0062] S105. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0063] S106. Deposit a conductive film layer on the back side;

[0064] S107. A third etching opening is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0065] S108. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0066] Thirdly, the present invention provides a battery assembly including a back contact battery with multiple anti-reflection structures as described in the first aspect.

[0067] In some preferred embodiments of the present invention, the battery assembly further includes a transparent film and photovoltaic glass arranged sequentially outward from the multiple anti-reflective structures.

[0068] In some preferred embodiments of the present invention, the battery assembly satisfies at least one of the following conditions:

[0069] (1) The refractive index of the transparent film is 1.4-1.5;

[0070] (2) The transparent encapsulating film is selected from at least one of ethylene-vinyl acetate copolymer, polyolefin elastomer, polyvinyl butyral, thermoplastic polyolefin, thermoplastic polyurethane, silicone, and acrylate films;

[0071] (3) The thickness of the transparent film is 0.1-0.5 mm;

[0072] (4) The light transmittance of photovoltaic glass is ≥90%;

[0073] (5) The thickness of photovoltaic glass is 1-5mm.

[0074] Beneficial effects:

[0075] Research has revealed that the front side of the back-contact battery has a pyramidal textured surface. When it is assembled into a battery module with a transparent film and photovoltaic glass, the front antireflective film optimized according to conventional air (whose refractive index n=1) is prone to optical mismatch after encapsulation. This leads to increased front reflectivity and insufficient incident light coupling, which in turn affects the absorption of incident light on the front side of the battery, reduces current gain, and consequently results in lower module efficiency.

[0076] To address this, the present invention optimizes the use of a transparent film (such as commonly used EVA with a refractive index n=1.49) as the incident medium and a silicon wafer as the substrate, rather than air, when used in the encapsulation of a battery module. Through the aforementioned technical solution, particularly the sequential arrangement of a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer on the textured surface of the back contact battery, with their refractive indices decreasing sequentially, a multi-layer anti-reflection structure is formed. The thin aluminum oxide layer provides excellent chemical passivation to the front side. Combined with the high-refractive-index first and second silicon nitride layers and the low-refractive-index first and second silicon oxide layers, a multi-gradient refractive index double-layer anti-reflection compensation is formed. The appropriate thickness range allows for hydrogenation and bulk passivation while ensuring the overall film thickness meets approximately quarter-wavelength interference anti-reflection conditions. This transforms the overall anti-reflection structure from "insufficient anti-reflection" to "near-zero reflection," facilitating wide-band interference anti-reflection. It absorbs incident light to a great extent; it also works in conjunction with a silicon oxynitride layer to provide a dual function of refractive index transition and partial passivation, and a thin alumina layer is placed close to the silicon wafer as a low-refractive-index "recess." Optically, the thinnest possible alumina layer ensures excellent interface passivation while maintaining effective anti-reflection. Thus, the multi-layer synergistic anti-reflection structure, when encapsulated as a battery module, provides excellent passivation while forming a synergistic effect of multi-layer gradient refractive anti-reflection. With appropriate film thicknesses for each layer, reflected waves from each interface cancel each other out, minimizing the weighted reflectivity Rw and maximizing the coupling current Jph. Almost all optical benefits can be obtained without sacrificing passivation. Simultaneously, it ensures resistance to acid and alkali corrosion, maximizing the triple improvement of anti-reflection, passivation, and corrosion resistance. This benefits the increase in short-circuit current density Jsc and open-circuit voltage Voc, and provides excellent resistance to UV degradation, thereby improving module efficiency (or battery module efficiency) and battery module stability. Furthermore, the first and second silicon nitride layers have a large tolerance for deposition thickness fluctuations, which is beneficial for mass production consistency. Under the same conditions, if the sum of the thicknesses of the first silicon nitride layer and the second silicon nitride layer, and the sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer are not within the above-mentioned suitable thickness range, problems such as insufficient anti-reflection and high front reflection will occur, resulting in large optical loss, large weighted reflectivity Rw, and small coupling current Jph, leading to low short-circuit current density Jsc, which in turn reduces the efficiency and stability of the battery module.

[0077] In a preferred embodiment of the present invention, the back contact cell is further provided with a thin silicon oxide layer. The thin silicon oxide layer and the adjacent thin aluminum oxide layer form a double chemical passivation on the front side, which can reduce the defect state density and carrier surface recombination rate at the front interface of the silicon wafer. This is beneficial to improving the open circuit voltage Voc, short circuit current density Jsc and cell conversion efficiency. While ensuring the anti-reflection effect, it can also effectively shield UV and protect the Si-H bonds of the underlying Si interface, further improving the efficiency of the cell module.

[0078] In a preferred embodiment of the present invention, the back contact battery is further provided with a third silicon oxide layer with a lower refractive index outside the second silicon oxide layer, which enables the thick silicon oxide layer to form a smoother low refractive index gradient transition from the inside to the outside, further reducing the abrupt change in refractive index between the thick silicon oxide layer and the encapsulation film or air, which is more conducive to reducing the reflection loss at the front interface, widening the effective anti-reflection band, and improving the incident light utilization and output power of the encapsulated module. Attached Figure Description

[0079] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0080] Figure 1 This is a schematic diagram of a specific embodiment of the back contact battery of the present invention.

[0081] Figure 2 This is a schematic diagram of a specific embodiment of the textured surface structure on the front side of the silicon wafer according to the present invention.

[0082] Explanation of reference numerals in the attached figures

[0083] 1. Silicon wafer; 2. Tunneling oxide layer; 3. N-type doped polycrystalline silicon layer; 4. Silicon oxynitride layer; 51. Thin silicon oxide layer; 52. Thin aluminum oxide layer; 61. First silicon nitride layer; 62. Second silicon nitride layer; 7. Thick silicon oxide layer; 8. Intrinsic amorphous silicon layer; 9. P-type doped amorphous silicon layer; 10. Transparent conductive film layer; 11. Metal electrode; 12. Micrometer-scale pyramid structure; 13. Nanometer-scale accessory structure; A. Second semiconductor opening region; B. First semiconductor opening region; C. Isolation region; D. Isolation trench. Detailed Implementation

[0084] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0085] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0086] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0087] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside. During application, light enters from the front of the back-contact battery.

[0088] In a first aspect, the present invention provides a back contact battery with a multiple anti-reflection structure, comprising a silicon wafer with a textured front surface, wherein a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer are sequentially disposed on the textured front surface of the silicon wafer to form a multiple anti-reflection structure; wherein the refractive index of the thin aluminum oxide layer is less than the refractive index of the first silicon nitride layer, and the refractive indices of the first silicon nitride layer, the second silicon nitride layer, the silicon oxynitride layer, the first silicon oxide layer, and the second silicon oxide layer decrease sequentially; wherein the thickness of the thin aluminum oxide layer is 4-18 nm, the sum of the thicknesses of the first silicon nitride layer and the second silicon nitride layer is 15-100 nm, the sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is 25-150 nm, and the thickness of the silicon oxynitride layer is 5-20 nm. The refractive index of the thin alumina layer, the first silicon nitride layer, the second silicon nitride layer, the silicon oxynitride layer, the first silicon oxide layer, and the second silicon oxide layer forms a structure with a rapid gradient increase followed by multiple slow gradient decreases from the front side of the silicon wafer outwards. The overall structure transforms from "insufficient anti-reflection" to "near-zero reflection" through a multi-layer anti-reflection structure. Combined with its appropriate film thickness, the reflected waves at each interface cancel each other out, minimizing the weighted reflectivity Rw and maximizing the coupling current Jph. Almost all optical benefits can be obtained without sacrificing passivation. At the same time, it also takes into account acid and alkali corrosion resistance, maximizing the triple improvement of anti-reflection, passivation, and corrosion resistance. It also has excellent resistance to ultraviolet decay, which helps to increase the short-circuit current density Jsc and the open-circuit voltage Voc, thereby improving the module efficiency and the stability of the battery module.

[0089] In this invention, the thickness of the thin alumina layer is 4-18 nm, specifically 4 nm, 4.2 nm, 4.5 nm, 4.7 nm, 5 nm, 5.2 nm, 5.5 nm, 5.8 nm, 5.9 nm, 6 nm, 6.2 nm, 6.5 nm, 6.7 nm, 7 nm, 7.2 nm, 7.5 nm, 7.7 nm, 7.9 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, or 18 nm, as well as any range between two values.

[0090] In this invention, the sum of the thicknesses of the first silicon nitride layer and the second silicon nitride layer is 10-100 nm, specifically, it can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm, or any range between two point values.

[0091] In this invention, the sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is 25-150 nm, specifically, it can be 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 41 nm, 42 nm, 43 nm, 44 nm, 45 nm, 46 nm, 47 nm, 48 nm, 49 nm, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm, 55 nm, 56 nm, 57 nm, 58 nm, 59 nm, 60 nm, 61 nm, 62 nm, 63 nm, 64 nm, 65 nm, 6 ...6 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm, 66 nm nm, 67nm, 68nm, 69nm, 70nm, 71nm, 72nm, 73nm, 74nm, 75nm, 76nm, 77nm, 78nm, 79nm, 80nm, 81nm, 82nm, 83nm, 84nm, 85nm, 86nm, 87nm, 88nm, 89nm, 90nm, 91nm, 92nm, 93nm, 94nm, 95nm, 96nm, 97nm, 98nm, 99nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm or 150nm, and the range between any two point values.

[0092] In this invention, the thickness of the silicon oxynitride layer is 5-20 nm, specifically 5 nm, 5.2 nm, 5.5 nm, 5.8 nm, 5.9 nm, 6 nm, 6.2 nm, 6.5 nm, 6.7 nm, 7 nm, 7.2 nm, 7.5 nm, 7.7 nm, 7.9 nm, 8 nm, 9 nm, 10 nm, 12 nm, 15 nm, 17 nm, 19 nm, or 20 nm, as well as any range between two values.

[0093] In some preferred embodiments of the present invention, the refractive indices of the first silicon nitride layer and the second silicon nitride layer are each independently between 1.95 and 2.5, and the refractive indices of the first silicon oxide layer and the second silicon oxide layer are each independently between 1.5 and 1.8.

[0094] In some preferred embodiments of the present invention, the refractive index ratio of the first silicon nitride layer and the second silicon nitride layer is (1.05-1.20):1. Using a first silicon nitride layer and a second silicon nitride layer with a suitable refractive index ratio can reduce the refractive index gradient from the inside to the outside, adjust the optical path difference of reflected light at the interfaces of each film layer, and achieve destructive interference across the entire 400-1100nm spectrum. This particularly reduces reflection losses in the 600-1000nm visible and near-infrared wavelengths, improves long-wavelength EQE, and is more conducive to increasing Jsc.

[0095] In a first preferred embodiment of the present invention, the thickness of the first silicon nitride layer is less than the thickness of the second silicon nitride layer. In the formation of a multi-layer antireflection structure using six layers—a thin alumina layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer—the first silicon nitride layer, with a higher refractive index, is used as the thicker main antireflection layer, while the second silicon nitride layer, with a lower refractive index, serves as the thinner auxiliary antireflection layer. Furthermore, the second silicon nitride layer acts as a hydrogen passivation / bulk passivation layer, enabling double-layer interference broadband antireflection, increasing light absorption, improving the short-circuit current density Jsc, further enhancing surface passivation, increasing minority carrier lifetime, and increasing the open-circuit voltage Voc.

[0096] More preferably, the thickness of the first silicon nitride layer is 5-50 nm, specifically, it can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm or 50 nm, and any range between two points. This invention employs a thinner, higher-refractive-index first silicon nitride layer as a high-refractive-index matching layer near the silicon wafer. On one hand, this can adapt to the optical matching requirements after the incident medium refractive index increases in the packaged state, enhance the refractive index transition effect between the first silicon nitride layer and the silicon wafer and the second silicon nitride layer, and improve the phase adjustment of the incident light near the silicon wafer. On the other hand, by controlling the thickness of the first silicon nitride layer to be relatively thin, the problems of increased parasitic absorption, increased film stress, and excessively strong refractive index abrupt changes caused by an excessively thick high-refractive-index silicon nitride layer can be avoided. This allows the first silicon nitride layer to mainly play the role of high-refractive-index matching and auxiliary passivation, and work with the subsequent second silicon nitride layer with a lower refractive index and appropriate thickness to undertake the main anti-reflection phase adjustment role, thereby making it more conducive to reducing the frontal reflectivity in the packaged state, improving the coupling current, and increasing the output efficiency at the module end.

[0097] More preferably, the thickness of the second silicon nitride layer is 10-80 nm, specifically, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, or 36 nm. , 37nm, 38nm, 39nm, 40nm, 41nm, 42nm, 43nm, 44nm, 45nm, 46nm, 47nm, 48nm, 49nm, 50nm, 51nm, 52nm, 53 nm, 54nm, 55nm, 56nm, 57nm, 58nm, 59nm, 60nm, 61nm, 62nm, 63nm, 64nm, 65nm, 66nm, 67nm, 68nm, 69nm,

[0098] The range includes 70nm, 71nm, 72nm, 73nm, 74nm, 75nm, 76nm, 77nm, 78nm, 79nm, or 80nm, as well as any two values ​​between these ranges. This invention employs a thicker second silicon nitride layer, which is more conducive to forming a medium-to-high refractive index gradient match with a thinner first silicon nitride layer with a higher refractive index, thereby reducing frontal reflectivity and increasing coupling current Jph and short-circuit current density Js.

[0099] More preferably, the thickness ratio of the first silicon nitride layer to the second silicon nitride layer is (0.2-0.95):1, specifically 0.2:1, 0.25:1, 0.3:1, 0.35:1, 0.4:1, 0.45:1, 0.5:1, 0.55:1, 0.6:1, 0.65:1, 0.7:1, 0.75:1, 0.8:1, 0.85:1, 0.9:1, or 0.95:1, or any range between any two values. This preferred scheme is more conducive to the two layers working together to form a suitable medium-high refractive index gradient and optical thickness distribution, reducing parasitic absorption, film stress, and phase shift problems caused by excessively thick high refractive index films, thereby reducing the front-side weighted reflectivity Rw after encapsulation and improving the coupling current Jph, short-circuit current density Jsc, and module-end output efficiency.

[0100] By precisely controlling the thickness and refractive index of the first silicon nitride layer, the second silicon nitride layer, the first silicon oxide layer, and the second silicon oxide layer, the present invention can more finely adjust the optical performance and passivation effect, thereby maximizing optical benefits and further improving the efficiency and stability of the battery module.

[0101] Further research revealed that corrosion resistance generally increases with increasing nitrogen atom content (nitrogen-rich), and denser nitrogen-rich films better block external erosion. Conversely, silicon-rich films have a more porous structure, leading to decreased corrosion resistance. Therefore, in some preferred embodiments of the present invention, the nitrogen atom content in the first silicon nitride layer is less than or equal to the nitrogen atom content in the second silicon nitride layer. Using this preferred embodiment, the low-nitrogen, i.e., relatively silicon-rich, first silicon nitride layer is closer to the silicon wafer, enhancing the passivation effect. The nitrogen-rich second silicon nitride layer, as the outer layer, is more conducive to reducing self-absorption of short-wavelength light while maintaining corrosion resistance, further increasing short-circuit current density, and improving module efficiency and battery module stability.

[0102] Preferably, in this invention, the nitrogen atom content in the first silicon nitride layer is 42%-46%.

[0103] Preferably, in this invention, the nitrogen atom content in the second silicon nitride layer is 45%-52%.

[0104] In some preferred embodiments of the present invention, the thickness of the first silicon oxide layer is greater than the thickness of the second silicon oxide layer, which is more conducive to the first silicon oxide layer near the silicon oxynitride layer to undertake the main low refractive index transition and optical phase matching function. At the same time, the thinner second silicon oxide layer further reduces the abrupt change in refractive index at the outer interface, avoiding the increase in film stress or anti-reflection phase shift caused by the outer silicon oxide layer being too thick.

[0105] In some preferred embodiments of the present invention, the thickness ratio of the first silicon oxide layer to the second silicon oxide layer is (2-7):1, specifically 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 5.9:1, 6:1, 6.5:1, or 7:1, or any range between two points. This preferred scheme is more conducive to forming an equivalent refractive index gradient that gradually decreases from the inside to the outside within the thick silicon oxide layer, and to ensuring that the overall optical thickness of the thick silicon oxide layer meets the anti-reflection phase matching under the incident conditions of the encapsulating film, thereby reducing the front weighted reflectivity Rw and increasing the coupling current Jph.

[0106] Preferably, the thickness of the second silicon nitride layer and the thickness of the second silicon oxide layer are the same, which is more conducive to forming a mutually compensating optical phase matching relationship between the medium-high refractive index transition layer and the low refractive index outer transition layer, making the destructive interference of reflected light in different bands more balanced, thereby broadening the anti-reflection band and improving the utilization rate of incident light after packaging.

[0107] In a second preferred embodiment of the present invention, the back contact battery further includes a third silicon oxide layer disposed outside the second silicon oxide layer, wherein the refractive index of the second silicon oxide layer is greater than that of the third silicon oxide layer. The present invention preferably employs seven layers: a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, a second silicon oxide layer, and a third silicon oxide layer, forming a multi-layer anti-reflection structure. The silicon oxide layers are divided into three layers with gradually decreasing refractive indexes, which allows for a smoother refractive index transition in the low-refractive-index region near the encapsulating film side, reduces the abrupt change in refractive index at the outer interface of the second silicon oxide layer, and further weakens the superposition of reflected light through optical phase coordination between the multiple silicon oxide layers. This is more conducive to reducing the weighted reflectivity Rw of the encapsulated front side and increasing the coupling current Jph and short-circuit current density Jsc.

[0108] In some preferred embodiments of the present invention, the thicknesses of the first silicon oxide layer, the second silicon oxide layer, and the third silicon oxide layer are each independently between 5-80 nm, specifically 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, and 38 nm. 39nm, 40nm, 41nm, 42nm, 43nm, 44nm, 45nm, 46nm, 47nm, 48nm, 49nm, 50nm, 51nm, 52nm, 53nm, 54nm, 55nm, 56nm, 57nm, 58nm, 59nm, 60nm, 61nm, 62nm, 63nm, 64nm, 65nm, 66nm, 67nm, 68nm, 69nm, 70nm, 71nm, 72nm, 73nm, 74nm, 75nm, 76nm, 77nm, 78nm, 79nm, or 80nm, and the range between any two point values. In this invention, the thicknesses of the first silicon oxide layer, the second silicon oxide layer, and the third silicon oxide layer can be the same or different. It is preferable that they are the same, which is more conducive to forming a uniform and stable stepped optical transition in the low refractive index region of the three silicon oxide layers, reducing the anti-reflection band shift caused by excessively thick or thin local films, and improving the consistency and controllability of the film deposition process.

[0109] Preferably, the refractive index of the second silicon oxide layer is greater than that of the thin aluminum oxide layer, which is greater than that of the third silicon oxide layer. This is more conducive to forming a low refractive index transition structure that gradually decreases from the inside to the outside near the encapsulation film, reducing the abrupt change in refractive index at the interface between the second silicon oxide layer, the thin aluminum oxide layer, and the third silicon oxide layer, reducing the reflection loss at the interface of the outer film layer, and broadening the effective anti-reflection band in the encapsulated state.

[0110] In some preferred embodiments of the present invention, the back contact cell further includes a thin silicon oxide layer disposed between the front side of the silicon wafer and the thin aluminum oxide layer, the thickness of which is 1-2 nm. The present invention preferably employs a thin silicon oxide layer and an adjacent thin aluminum oxide layer to form dual chemical passivation on the front side, which can reduce the defect state density at the front interface of the silicon wafer, suppress carrier recombination at the front interface, improve the open-circuit voltage Voc and cell conversion efficiency, and reduce the risk of increased interface defects caused by UV irradiation while ensuring anti-reflection effects, improve the stability of Si-H bonds at the underlying Si interface, and further enhance the efficiency and long-term reliability of the cell module.

[0111] In this invention, the thickness of the thin silicon oxide layer is 1-2 nm, specifically 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, or 2 nm, or any range between two values. More preferably, the textured surface of the silicon wafer has a pyramid structure, and the thickness of the thin silicon oxide layer on the slope of the pyramid structure is 1-1.8 nm. Precisely controlling the thickness of the thin silicon oxide layer on the slope of the pyramid structure to a suitable ultrathin thickness is more conducive to forming a continuous and uniform interface passivation layer on the textured slope, reducing the interface defect state density and surface recombination rate at the pyramid slope, while avoiding an excessively thick thin silicon oxide layer that could lead to increased series resistance or optical phase matching shift.

[0112] In some preferred embodiments of the present invention, the refractive index of the thin silicon oxide layer is less than that of the thin aluminum oxide layer, which is more conducive to forming a lower refractive index interface transition layer between the front side of the silicon wafer and the thin aluminum oxide layer, reducing the optical abrupt change at the silicon wafer / thin aluminum oxide layer interface, and forming a dual chemical passivation structure with the thin aluminum oxide layer, thereby taking into account both the interface passivation effect and the anti-reflection effect of the component package state.

[0113] Preferably, the refractive index of the thin silicon oxide layer is 1.4-1.61.

[0114] In some preferred embodiments of the present invention, the refractive index of the thin alumina layer is 1.45-1.7.

[0115] In some preferred embodiments of the present invention, the refractive index of the silicon oxynitride layer is 1.45-2.3.

[0116] In some preferred embodiments of the present invention, the nitrogen atom content of the silicon oxynitride layer is 20%-40%. The present invention uses a silicon oxynitride layer with a suitable high nitrogen atom content, which is beneficial to improving its acid and alkali corrosion resistance. Combined with the appropriate refractive index setting of its precursor, it is even more beneficial to achieve a triple improvement in antireflection, high passivation and corrosion resistance of the multiple antireflection structure.

[0117] Preferably, the front surface of the silicon wafer has a pyramid structure, and the size of the pyramid structure is less than 3 μm, more preferably 100 nm to 3 μm.

[0118] In some preferred embodiments of the present invention, the textured surface structure on the front side of the silicon wafer is a micro-nano composite textured surface structure, which includes a micrometer-scale pyramid structure and nanometer-scale additional substructures disposed on the surface of the micrometer-scale pyramid structure. In a preferred embodiment of the present invention, the pyramid morphology of the micro-nano composite textured surface structure has a better anti-reflection effect. Combined with a specific multi-layer anti-reflection structure and its appropriate thickness and refractive index gradient settings, the incident light needs to pass through the anti-reflection and refraction of the multi-layer anti-reflection structure before entering the silicon wafer, and then through the secondary anti-reflection effect of the textured pyramid light trapping effect. The two work together to reduce the refractive index gradient of each film in the light transmission path, which is beneficial to minimize the front reflectivity and reduce the front current loss, while not reducing the chemical passivation and field passivation effect of the front multi-layer anti-reflection structure, thereby further improving the short-circuit current density and improving the efficiency and stability of the battery module.

[0119] More preferably, the size of the micron-scale pyramid structure is between 1 and 3 μm, meaning that its size in any direction is within this range.

[0120] Preferably, the size of the nanoscale addendum structure is 300-500 nm, meaning that its size in any direction is within this range.

[0121] In some preferred embodiments of the present invention, the angle between the micron-scale pyramid structure and the horizontal bottom surface of the silicon wafer is 55°-60°, that is, the angle between the outermost edge of the micron-scale pyramid structure and the horizontal bottom surface of the silicon wafer is 55°-60°.

[0122] Preferably, the nanoscale additional substructures of this invention include at least one of regular and irregular shapes. More preferably, the regular shapes include at least one of pyramidal, conical, and hemispherical shapes.

[0123] In some preferred embodiments of the present invention, the back contact battery further includes: a semiconductor film layer, a conductive film layer, and a metal electrode sequentially disposed on the back side of a silicon wafer. The semiconductor film layer includes a first semiconductor layer and a second semiconductor layer alternately disposed on the back side, and an isolation region disposed between the first semiconductor layer and the second semiconductor layer, wherein at least a portion of the isolation region is not provided with a conductive film layer. The type and thickness of the conductive film layer can be based on existing technologies and can all be used in the present invention. The conductive film layer may only cover the outer surfaces of the first semiconductor layer and the second semiconductor layer, or it may cover the outer surfaces of the first semiconductor layer and the second semiconductor layer, as well as a portion of the outer surface of the isolation region.

[0124] In some preferred embodiments of the present invention, the two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers, and the second semiconductor opening regions and the first semiconductor opening regions are spaced apart, with the area between them forming an isolation region. The front-side multi-anti-reflection structure of the present invention is applicable to back-contact batteries with a finger-crossed structure, and can also be applied to back-contact batteries with other structures.

[0125] In some embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, and the second semiconductor layer includes a second passivation layer and a second doped silicon layer. The first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon, or microcrystalline silicon. One of the first doped silicon layer and the second doped silicon layer is N-type, and the other is P-type.

[0126] In a preferred embodiment, the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline silicon layer sequentially disposed on the back side, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer sequentially disposed on the back side. The second doped silicon layer is doped amorphous silicon or microcrystalline silicon. This combined passivation structure is more conducive to improving the passivation effect and increasing the efficiency of the battery module. The thicknesses and corresponding doping concentrations of the tunneling oxide layer or intrinsic silicon layer, the first doped polycrystalline silicon layer, and the second doped silicon layer can all refer to the ranges of existing technologies and can all be used in this invention. For example, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the intrinsic silicon layer is 5-15 nm, and the thickness of the second doped silicon layer is 7-45 nm with an effective doping concentration of 2e18 cm⁻¹. -3 -3e20cm -3 The thickness of the first doped polycrystalline silicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm⁻¹. -3 .

[0127] In some preferred embodiments of the present invention, the back surface of the silicon wafer corresponding to the location of the second semiconductor layer is a textured surface, and the other back surface areas are polished surfaces.

[0128] In some preferred embodiments of the present invention, an isolation groove is formed on the portion of the conductive film layer located within the isolation region, and the metal electrode is disposed on the outer surface of the corresponding conductive film layer of the first semiconductor layer and the second semiconductor layer.

[0129] Secondly, the present invention provides a method for fabricating a back-contact battery, comprising: S1, providing a silicon wafer with a textured front surface; S2, sequentially forming a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer on the front surface of the silicon wafer, forming a multiple anti-reflection structure. The structure and properties of the thin aluminum oxide layer, the first silicon nitride layer, the second silicon nitride layer, the silicon oxynitride layer, the first silicon oxide layer, and the second silicon oxide layer are the same as those described in the first aspect above, and will not be repeated here.

[0130] In some preferred embodiments of the present invention, S1 provides a silicon wafer with a textured surface, the process of which includes: performing a first etching on the front side of the silicon wafer to form a micron-scale pyramid structure, followed by a second etching to form a nano-scale substructure on the surface of the micron-scale pyramid structure, thereby forming a micro-nano composite textured surface structure.

[0131] In some preferred embodiments of the present invention, the first etching is performed using a wet etching method with an alkaline solution. In this invention, the size and angle of the micron-scale pyramid structure can be adjusted by controlling the composition of the alkaline solution, as well as conditions such as temperature and etching time.

[0132] In some preferred embodiments of the present invention, the alkali concentration in the alkaline solution is 1%-5%.

[0133] Preferably, in this invention, the second etching is performed using a wet etching method with a mixed solution containing inorganic calcium salt and alkali, a plasma etching method, or a reactive ion etching method. In this invention, the size and other structural features of the nanoscale adjoint structures can be adjusted by controlling the process conditions of each etching method.

[0134] In some preferred embodiments of the present invention, the volume concentration of the inorganic calcium salt in the mixed solution is 0.01%-1.05%, and the mass concentration of the alkali is 1%-5%. The role of the inorganic calcium salt is that the calcium ions in the inorganic salt react with SiO2 to form a protective layer on the surface of the SiO2 film, preventing the underlying c-Si from being affected by alkaline etching. Combined with the appropriate concentrations of the alkali and both, this facilitates the formation of a stepped substructure, thereby etching and forming nanoscale additional substructures while protecting the micron-scale pyramid structure.

[0135] In some preferred embodiments of the present invention, the inorganic calcium salt in the mixed solution includes at least one of calcium chloride, calcium nitrate, and calcium hydroxide.

[0136] In this invention, the alkali in the alkaline solution and the mixed solution can be sodium hydroxide and / or potassium hydroxide, respectively, and they can be the same or different. The conditions for wet etching of the alkaline solution and the mixed solution, such as temperature and time, can be adjusted according to the size and angle of the target textured surface structure.

[0137] In some preferred embodiments of the present invention, the plasma gas source in the plasma etching method is selected from at least one of sulfur hexafluoride, chlorine, and oxygen. More preferably, the plasma gas source contains sulfur hexafluoride, chlorine, and oxygen, and the volume flow rate ratio of these three gases is (15-20):(5-10):(10-20).

[0138] In some preferred embodiments of the present invention, the preparation method further includes a thin silicon oxide layer disposed between the front side of the silicon wafer and the thin alumina layer.

[0139] In some preferred embodiments of the present invention, the thin silicon oxide layer is grown using a dry oxygen thermal oxidation process, which is more conducive to forming an ultra-thin, controllable silicon oxide layer with a dense interface and a lower interface state density, resulting in a better passivation effect.

[0140] More preferably, the conditions for the dry oxygen thermal oxidation process include: an oxidation temperature of 600-650°C and an oxidation time of 5-15 minutes in an atmosphere with or without oxygen and a chlorine source. The incorporation of chlorine further facilitates the removal of metallic impurities and reduces the interfacial state density.

[0141] Preferably, the chlorine source is an organic chlorine source. More preferably, the chlorine source includes at least one of trichloroethane and dichloroethylene.

[0142] Preferably, the volumetric flow rate ratio of chlorine source to oxygen is (0-0.10):1.

[0143] In some preferred embodiments of the present invention, the preparation method further includes: performing a pretreatment before forming the thin silicon oxide layer. The pretreatment includes scheme A or scheme B. Scheme A includes sequentially performing RCA cleaning and HF solution cleaning, while scheme B includes sequentially performing ozone oxidation and HF solution cleaning. The pretreatment can obtain a clean textured surface with low metal content, which is more conducive to obtaining a low interface state density.

[0144] In some preferred embodiments of the present invention, the preparation method further includes the step of forming a third silicon oxide layer outside the second silicon oxide layer, wherein the refractive index of the second silicon oxide layer is greater than the refractive index of the third silicon oxide layer.

[0145] In some preferred embodiments of the present invention, the thin alumina layer is formed by deposition using an ALD process. More preferably, the ALD process conditions include: using a precursor of trimethylaluminum and water vapor, and a temperature of 150-250°C. Using a precursor of trimethylaluminum and water vapor results in a lower interface state density and better hydrogen passivation.

[0146] In some preferred embodiments of the present invention, the preparation method further includes annealing and activation after depositing a thin alumina layer, which is more conducive to the formation of negative fixed charge and low interface state density.

[0147] More preferably, the annealing activation conditions include: annealing in the presence of nitrogen or a nitrogen- and hydrogen-containing forming gas, an annealing temperature of 400-450℃, and an annealing time of 10-30 min. Using a suitable low annealing temperature during annealing activation is more conducive to the passivation of H at the interface and the full activation of the negative fixed charge, further effectively reducing the interface state density.

[0148] In some preferred embodiments of the present invention, the first silicon nitride layer and the second silicon nitride layer are formed by PECVD process, and more preferably by high temperature tubular PECVD process.

[0149] More preferably, the Si / N ratio in the PECVD process is controlled to be between 0.75 and 2.0 in atomic ratio. The refractive index in silicon nitride deposition is positively correlated with the silicon-nitrogen ratio (Si / N); the higher the Si / N ratio, the higher the refractive index. In this invention, the refractive index can be adjusted within the aforementioned range.

[0150] More preferably, the PECVD process temperature is 400-450℃, which is more conducive to in-situ hydrogen supply and promotes hydrogen passivation.

[0151] In some preferred embodiments of the present invention, the preparation method further includes: performing hydrogenation annealing or sintering after forming the silicon oxynitride layer, which is more conducive to further releasing and driving hydrogen in the film layer to diffuse to the front interface and near-surface defects of the silicon wafer, passivating defects such as dangling bonds, and reducing the carrier surface recombination rate. During this hydrogenation annealing or sintering, the aforementioned annealing activation may or may not be performed, but is preferably performed.

[0152] More preferably, the hydrogenation annealing conditions include: an annealing temperature of 400-430℃ and an annealing time of 20-30 min.

[0153] More preferably, the sintering conditions include: a sintering temperature of 750-800℃ and a sintering time of 3-5s.

[0154] In some preferred embodiments of the present invention, the preparation method further includes:

[0155] S01. A first semiconductor layer is formed in the first region on the back side;

[0156] Then proceed with S1 and S2;

[0157] Then, SO2 is performed to form a second semiconductor layer in the second region on the back side; wherein one of the first region and the other of the second region is an N-region and the other is a P-region;

[0158] S03. Then, a conductive film layer is formed on the outer surface of both the first semiconductor layer and the second semiconductor layer on the back side, and an isolation area is naturally formed at the same time.

[0159] S04. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers of the first semiconductor layer and the second semiconductor layer. It is understood that at least a portion of the isolation region does not have the first semiconductor layer and the second semiconductor layer.

[0160] In some other preferred embodiments of the present invention, the preparation method further includes:

[0161] S101, provides double-sided polished silicon wafers;

[0162] S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer;

[0163] S103. The first etching opening is performed on the back side obtained in S102 to form the second semiconductor opening region;

[0164] Then, S1 is performed to texturing and cleaning, forming a textured surface on the front side and the second semiconductor opening area, and completely removing the mask layer or retaining part of the mask layer; then S2 is performed.

[0165] S104. Deposit a second semiconductor layer on the back side;

[0166] S105. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0167] S106. Deposit a conductive film layer on the back side;

[0168] S107. A third etching opening is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0169] S108. Metal electrodes are formed on the outer surfaces of the corresponding conductive films in the regions where the first semiconductor opening region and the second semiconductor opening region are located. This post-texturing process can reduce manufacturing costs while ensuring high battery module efficiency.

[0170] Thirdly, the present invention provides a battery assembly including a back contact battery with multiple anti-reflection structures as described in the first aspect.

[0171] In some preferred embodiments of the present invention, the battery module further includes a transparent film and photovoltaic glass arranged sequentially outward from the multiple anti-reflection structure. The back-contact battery with the multiple anti-reflection structure of the present invention can match the incident light refractive index of the transparent film, minimizing the weighted reflectivity Rw and maximizing the coupling current Jph, thereby obtaining almost all optical benefits without sacrificing passivation and improving module efficiency.

[0172] In some preferred embodiments of the present invention, the refractive index of the transparent film is 1.4-1.5.

[0173] The transparent encapsulating film of the present invention can be selected as a high-transmittance, UV-transmittance type encapsulating film. In some preferred embodiments of the present invention, the transparent encapsulating film is selected from at least one of ethylene-vinyl acetate copolymer (EVA), polyolefin elastomer (POE), polyvinyl butyral (PVB), thermoplastic polyolefin (TPO), thermoplastic polyurethane (TPU), silicone, and acrylate films.

[0174] In some preferred embodiments of the present invention, the thickness of the transparent film is 0.1-0.5 mm. The use of a suitable thin transparent film in the present invention, within the limits of mechanical and reliability constraints, better ensures encapsulation and anti-PID effects.

[0175] In some preferred embodiments of the present invention, the light transmittance of the photovoltaic glass is ≥90%. Examples of photovoltaic glass include AR-coated ultra-white low-iron glass (with a light transmittance of up to 94.5%).

[0176] In some preferred embodiments of the present invention, the thickness of the photovoltaic glass is 1-5 mm.

[0177] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0178] Example 1

[0179] A back-contact battery with multiple anti-reflection structures, such as Figure 1As shown, the device includes a silicon wafer 1 with a textured surface on the front side. On the textured surface of the silicon wafer 1, a thin silicon oxide layer 51 (thickness 1.5nm, refractive index 1.48), a thin aluminum oxide layer 52 (thickness 8.5nm, refractive index 1.62), a first silicon nitride layer 61 (thickness 13nm, refractive index 2.23, nitrogen atom content 42.5%), a second silicon nitride layer 62 (thickness 21nm, refractive index 2.08, nitrogen atom content 46%), a silicon oxynitride layer 4 (thickness 18nm, refractive index 1.84, nitrogen atom content 30%), and a thick silicon oxide layer 7 are sequentially arranged. The thick silicon oxide layer 7 is specifically composed of a first silicon oxide layer (thickness 49nm, refractive index 1.73) and a second silicon oxide layer (thickness 20nm, refractive index 1.6) arranged sequentially, forming a multi-layer anti-reflection structure. After conversion, the sum of the thicknesses of the first silicon nitride layer 61 and the second silicon nitride layer 62 is 34 nm, the thickness ratio is 0.62:1, and the refractive index ratio is 1.07:1. The sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is 69 nm, and the thickness ratio is 2.45:1.

[0180] The back contact cell also includes: a first semiconductor layer and a second semiconductor layer alternately disposed on the back side of the silicon wafer 1, wherein the first semiconductor layer comprises a tunneling oxide layer 2 (1.5 nm thick) and an N-type doped polycrystalline silicon layer 3 (120 nm thick, with an effective doping concentration of 5e19cm). -3 The second semiconductor layer comprises an intrinsic amorphous silicon layer 8 (8 nm thick) and a p-type doped amorphous silicon layer 9 (15 nm thick, with an effective doping concentration of 3e19 cm⁻¹). -3 The second semiconductor layer extends outward from both ends to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers, and the second semiconductor opening regions and the first semiconductor opening regions are arranged alternately, with the area between them forming an isolation region. A transparent conductive film layer 10 (specifically ITO, with a thickness of 60 nm) is deposited on the outer surfaces of the first and second semiconductor layers. An isolation trench is formed on the portion of the transparent conductive film layer 10 located within the isolation region. A metal electrode 11 is disposed on the outer surface of the corresponding transparent conductive film layer 10 in the second semiconductor opening region and the first semiconductor opening region. A portion of the silicon wafer 1 located at the second semiconductor opening region has a textured surface, while a portion of the silicon wafer 1 located at the corresponding position of the first semiconductor layer has a polished surface.

[0181] The textured surface on the front side is a micron-sized pyramid structure 12 (with dimensions ranging from 1 to 3 μm, and the angle between the micron-sized pyramid structure 12 and the horizontal bottom surface of the silicon wafer 1 ranging from 55° to 58°). Correspondingly, the micron-sized pyramid structure 12 is formed by wet etching using an alkaline solution with a mass concentration of 3%. The textured surface on the back side of the silicon wafer 1 has the same structure as the front side.

[0182] The back-contact cells are encapsulated into a battery module: After 72 back-contact cells are connected in series and welded together, EVA (thickness 0.3mm, refractive index 1.45) and photovoltaic glass (thickness 2mm, light transmittance ≥90%) are sequentially placed on the front side of the connected battery string. EVA (thickness 0.3mm, refractive index 1.45) and photovoltaic glass (thickness 2mm, light transmittance ≥90%) are sequentially placed on the back side of the connected battery string.

[0183] Example 2

[0184] The process was carried out in accordance with Example 1, except that the textured surface structure on the front side of silicon wafer 1 was adjusted to a micro-nano composite textured surface structure, such as... Figure 2 As shown, the micro / nano composite textured structure includes a micrometer-scale pyramid structure 12 (its specific structure and size are the same as in Example 1) and a nanometer-scale additional substructure 13 (its size is in the range of 300-400 nm and it is a regular pyramid shape) disposed on the surface of the micrometer-scale pyramid structure 12. Correspondingly, the nanometer-scale additional substructure 13 is formed by wet etching after the first etching using a mixed solution of inorganic calcium salt (specifically calcium chloride) and alkali (specifically sodium hydroxide), wherein the volume concentration of inorganic calcium salt in the mixed solution is 0.05% and the mass concentration of alkali is 3%.

[0185] Example 3

[0186] The same procedure was followed as in Example 1, except that a third silicon oxide layer (with a thickness of 5 nm and a refractive index of 1.56) was also provided outside the second silicon oxide layer.

[0187] Example 4

[0188] The procedure was carried out in accordance with Example 1, except that the thickness of the first silicon oxide layer was adjusted to 20 nm while the refractive index remained unchanged. After calculation, the thickness ratio of the first silicon oxide layer to the second silicon oxide layer was 1:1.

[0189] Example 5

[0190] The experiment was conducted in accordance with Example 1, except that the thickness of the second silicon nitride layer 62 was adjusted to 15 nm. After conversion, the thickness ratio of the first silicon nitride layer 61 to the second silicon nitride layer 62 is 0.87:1, and the sum of their thicknesses is 28 nm.

[0191] Example 6

[0192] The same procedure was followed as in Example 1, except that the nitrogen atom ratio in the first silicon nitride layer 61 was adjusted to be the same as that in the second silicon nitride layer 62.

[0193] Example 7

[0194] The procedure was carried out in accordance with Example 1, except that the thin alumina layer 52 (thickness of 10 nm and refractive index of 1.60) was adjusted.

[0195] Example 8

[0196] The same procedure was followed as in Example 1, except that the silicon oxynitride layer 4 (thickness 15 nm, refractive index 1.87) was adjusted.

[0197] Comparative Example 1

[0198] The procedure was carried out in accordance with Example 1, except that a second silicon oxide layer was not provided.

[0199] Comparative Example 2

[0200] The procedure was carried out in accordance with Example 1, except that the refractive index of the second silicon oxide layer was adjusted to be the same as that of the first silicon oxide layer, while the thickness remained unchanged.

[0201] Comparative Example 3

[0202] The same procedure was performed as in Example 1, except that the refractive index of the second silicon nitride layer 62 was adjusted to be the same as that of the first silicon nitride layer 61, while the thickness remained unchanged.

[0203] Comparative Example 4

[0204] The same procedure was followed as in Example 1, except that a second silicon nitride layer 62 was not provided.

[0205] Comparative Example 5

[0206] The procedure was carried out in accordance with Example 1, except that the thin alumina layer 52 was not provided.

[0207] Comparative Example 6

[0208] The same procedure was performed as in Example 1, except that the thickness of the first silicon nitride layer 61 was adjusted to 21 nm. After conversion, the sum of the thicknesses of the first silicon nitride layer 61 and the second silicon nitride layer 62 is 42 nm.

[0209] Test case

[0210] The battery modules obtained from the above embodiments and comparative examples were tested for short-circuit current density Jsc, open-circuit voltage Voc, weighted reflectivity Rw, coupling current Jph, and battery module efficiency. The results are shown in Table 1. The weighted reflectivity Rw and coupling current Jph were measured or calculated using a UV-Vis-NIR spectrophotometer with an integrating sphere to measure the reflectivity spectrum R(λ) of the front side of the battery module in the wavelength range of 300-1200 nm. The reflectivity was then spectrally weighted and integrated using the AM1.5G standard solar spectral photon flux Φ(λ) as the weight to obtain the weighted reflectivity Rw. Simultaneously, the theoretical coupling current Jph was calculated based on the photon flux in the incident spectrum that was not lost due to frontal reflection, combined with the photon-current conversion relationship in the absorbable wavelength band of silicon cells. A lower Rw indicates less reflection loss of incident light on the front side of the module; a higher Jph indicates more effective photons that can couple into the cell and participate in photoelectric conversion. UVLID refers to the light-induced degradation phenomenon that occurs when a battery module is exposed to ultraviolet light (wavelength range 280-400nm) superimposed with simulated sunlight (full-spectrum illumination). The testing method involves continuously irradiating the module with a light box containing ultraviolet light (wavelength range 280-400nm) superimposed with simulated sunlight (full-spectrum illumination) for 2 hours. The power degradation ratio of the battery module before and after cumulative irradiation is evaluated to determine light-induced degradation. The formula for calculating the power degradation ratio is: (Power before irradiation - Power after irradiation) / Power before irradiation. The smaller the power degradation ratio before and after UVLID, the stronger the UVLID resistance to degradation and the higher the stability of the battery module.

[0211] Table 1

[0212]

[0213] The results above show that, compared with the comparative example, the embodiment of the present invention can make the reflected waves of each interface of the multi-film layer on the front surface cancel each other out, so that the weighted reflectivity Rw is at a small level and the coupling current Jph is at a large level. Almost all optical benefits can be obtained without sacrificing passivation, which is conducive to improving the short-circuit current density Jsc and open-circuit voltage Voc, thereby improving the module efficiency and battery module stability.

[0214] Furthermore, as can be seen from Embodiments 1 and 2-10, the preferred scheme of the present invention is more conducive to improving the short-circuit current density Jsc and open-circuit voltage Voc, thereby improving the module efficiency and battery module stability.

[0215] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A back contact battery with a multiple anti-reflection structure, characterized in that, The device includes a silicon wafer with a textured surface on the front side. On the textured surface of the silicon wafer, a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer are sequentially disposed to form a multiple anti-reflection structure. The refractive index of the thin aluminum oxide layer is less than that of the first silicon nitride layer, and the refractive indices of the first silicon nitride layer, the second silicon nitride layer, the silicon oxynitride layer, the first silicon oxide layer, and the second silicon oxide layer decrease sequentially. The thickness of the thin aluminum oxide layer is 4-18 nm, the sum of the thicknesses of the first and second silicon nitride layers is 15-100 nm, the sum of the thicknesses of the first and second silicon oxide layers is 25-150 nm, and the thickness of the silicon oxynitride layer is 5-20 nm.

2. The back contact battery with multiple anti-reflection structures according to claim 1, characterized in that, The refractive indices of the first silicon nitride layer and the second silicon nitride layer are each independently between 1.95 and 2.5, and the refractive indices of the first silicon oxide layer and the second silicon oxide layer are each independently between 1.5 and 1.

8. And / or, the refractive index ratio of the first silicon nitride layer to the second silicon nitride layer is (1.05-1.20):

1.

3. The back contact battery with multiple anti-reflection structures according to claim 1, characterized in that, The thickness of the first silicon nitride layer is less than the thickness of the second silicon nitride layer.

4. The back contact battery with multiple anti-reflection structures according to claim 3, characterized in that, The thickness of the first silicon nitride layer is 5-50 nm, and the thickness of the second silicon nitride layer is 10-80 nm; and / or, the thickness ratio of the first silicon nitride layer to the second silicon nitride layer is (0.2-0.95):

1.

5. The back contact battery with multiple anti-reflection structures according to claim 3, characterized in that, The nitrogen atom percentage in the first silicon nitride layer is less than or equal to the nitrogen atom percentage in the second silicon nitride layer; and / or, The nitrogen atom content in the first silicon nitride layer is 42%-46%, and the nitrogen atom content in the second silicon nitride layer is 45%-52%.

6. The back contact battery with multiple anti-reflection structures according to claim 3, characterized in that, The thickness of the first silicon oxide layer is greater than the thickness of the second silicon oxide layer; and / or the ratio of the thickness of the first silicon oxide layer to the thickness of the second silicon oxide layer is (2-7):

1.

7. The back contact battery with multiple anti-reflection structures according to claim 6, characterized in that, The thickness of the first silicon nitride layer is less than the thickness of the first silicon oxide layer; and / or, the thickness of the second silicon nitride layer is the same as the thickness of the second silicon oxide layer.

8. The back contact battery with multiple anti-reflection structures according to claim 1, characterized in that, The back contact battery also includes a third silicon oxide layer disposed outside the second silicon oxide layer, wherein the refractive index of the second silicon oxide layer is greater than that of the third silicon oxide layer.

9. The back contact battery with multiple anti-reflection structures according to claim 8, characterized in that, The thicknesses of the first silicon oxide layer, the second silicon oxide layer, and the third silicon oxide layer are each independently between 5 and 80 nm; and / or, the thicknesses of the first silicon oxide layer, the second silicon oxide layer, and the third silicon oxide layer are the same.

10. The back contact battery with a multiple anti-reflection structure according to any one of claims 1-9, characterized in that, The back contact battery also includes a thin silicon oxide layer disposed between the front side of the silicon wafer and a thin aluminum oxide layer, the thickness of which is 1-2 nm.

11. The back contact battery with multiple anti-reflection structures according to claim 10, characterized in that, The refractive index of the thin silicon oxide layer is less than that of the thin aluminum oxide layer; and / or, the refractive index of the thin silicon oxide layer is 1.4-1.

61.

12. The back contact battery with a multiple anti-reflection structure according to any one of claims 1-9, characterized in that, Back-contact batteries also meet at least one of the following conditions: (1) The sum of the thicknesses of the first silicon nitride layer and the second silicon nitride layer is 15-60 nm; (2) The sum of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is 20-100 nm; (3) The refractive index of the thin alumina layer is 1.45-1.7; (4) The refractive index of the silicon oxynitride layer is 1.45-2.3; (5) The nitrogen atom content of the oxynitride layer is 20%-40%; (6) The front surface of the silicon wafer has a pyramid structure, and the size of the pyramid structure is less than 3μm.

13. The back contact battery with a multiple anti-reflection structure according to any one of claims 1-9, characterized in that, The textured surface of the silicon wafer is a micro-nano composite textured surface structure, which includes a micron-scale pyramid structure and nano-scale additional substructures disposed on the surface of the micron-scale pyramid structure. The size of the micron-scale pyramid structure is 1-3μm, and the size of the nano-scale additional substructures is 300-500nm.

14. The back contact battery with multiple anti-reflection structures according to claim 13, characterized in that, The angle between the micron-scale pyramid structure and the horizontal base of the silicon wafer is between 55° and 60°; and / or, the nanoscale substructure includes at least one of regular and irregular shapes, with the regular shape including at least one of pyramid, cone, and hemispherical shapes.

15. The back contact battery with multiple anti-reflection structures according to claim 1, characterized in that, The back contact battery also includes: a semiconductor film layer, a conductive film layer and a metal electrode sequentially disposed on the back side of the silicon wafer. The semiconductor film layer includes a first semiconductor layer and a second semiconductor layer alternately disposed on the back side, and an isolation region disposed between the first semiconductor layer and the second semiconductor layer, wherein at least part of the isolation region is not provided with a conductive film layer.

16. The back contact battery with multiple anti-reflection structures according to claim 15, characterized in that, The back contact battery also includes at least one of the following structures: Structure 1: The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening regions and the first semiconductor opening regions are arranged alternately, and the area between them is an isolation region. Structure 2: The first semiconductor layer includes a first passivation layer and a first doped silicon layer, and the second semiconductor layer includes a second passivation layer and a second doped silicon layer. The first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon. Structure 3: The back surface of the silicon wafer corresponding to the location of the second semiconductor layer is textured, while the other back surface areas are polished. Structure 4: An isolation groove is formed on the portion of the conductive film layer located within the isolation region, and the metal electrode is disposed on the outer surface of the corresponding conductive film layer of the first semiconductor layer and the second semiconductor layer.

17. A method for preparing a back-contact battery, characterized in that, It is used to prepare a back contact battery with multiple anti-reflection structures as described in any one of claims 1-16. The preparation method includes: S1, providing a silicon wafer with a textured front side; S2, sequentially forming a thin aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, a first silicon oxide layer, and a second silicon oxide layer on the front side of the silicon wafer to form a multiple anti-reflection structure.

18. The method for preparing a back contact battery according to claim 17, characterized in that, S1 provides a silicon wafer with a textured surface on the front side. The process includes: first etching on the front side of the silicon wafer to form a micron-scale pyramid structure, followed by a second etching to form a nano-scale substructure on the surface of the micron-scale pyramid structure, thereby forming a micro-nano composite textured surface structure.

19. The method for preparing a back contact battery according to claim 18, characterized in that, The first etching is performed using an alkaline solution for wet etching, while the second etching is performed using a mixed solution containing inorganic calcium salts and alkali, plasma etching, or reactive ion etching.

20. The method for preparing a back contact battery according to claim 19, characterized in that, S1 also includes at least one of the following conditions: (1) The alkali concentration in the alkaline solution is 1%-5%; (2) The volume concentration of inorganic calcium salt in the mixed solution is 0.01%-1.05%, and the mass concentration of alkali is 1%-5%; (3) The inorganic calcium salt in the mixed solution includes at least one of calcium chloride, calcium nitrate, and calcium hydroxide; (4) In the plasma etching method, the plasma gas source is selected from at least one of sulfur hexafluoride, chlorine and oxygen. When the three gases are sulfur hexafluoride, chlorine and oxygen, the volume flow ratio of these three gases is (15-20): (5-10): (10-20).

21. The method for preparing a back contact battery according to claim 20, characterized in that, The preparation method also includes a thin silicon oxide layer disposed between the front side of the silicon wafer and the thin aluminum oxide layer.

22. The method for preparing a back contact battery according to claim 21, characterized in that, The thin silicon oxide layer is grown using a dry oxygen thermal oxidation process. The conditions for the dry oxygen thermal oxidation process include: an atmosphere with or without an oxygen source, a thermal oxidation temperature of 600-650℃, and a thermal oxidation time of 5-15 min. The chlorine source includes at least one of trichloroethane and dichloroethylene, and / or the volume flow ratio of chlorine source to oxygen is (0-0.10):

1.

23. The method for preparing a back contact battery according to claim 21 or 22, characterized in that, The preparation method also includes: before forming a thin silicon oxide layer, a pretreatment is performed, which includes scheme A or scheme B. Scheme A includes sequential RCA cleaning and HF solution cleaning, and scheme B includes sequential ozone oxidation and HF solution cleaning.

24. The method for preparing a back contact battery according to claim 17, characterized in that, The preparation method also includes the step of forming a third silicon oxide layer outside the second silicon oxide layer, wherein the refractive index of the second silicon oxide layer is greater than the refractive index of the third silicon oxide layer.

25. The method for preparing a back contact battery according to any one of claims 17-22, characterized in that, The preparation method also includes any of the following processes: Process 1: The first silicon nitride layer and the second silicon nitride layer are formed by PECVD process, and the Si / N ratio in atomic ratio is controlled between 0.75 and 2.0 in PECVD process, and the temperature of PECVD process is 400-450℃. Process 2, the preparation method also includes: hydrogenation annealing or sintering after forming the silicon oxynitride layer; wherein, the conditions for hydrogenation annealing include: annealing temperature of 400-430℃, annealing time of 20-30min; the conditions for sintering include: sintering temperature of 750-800℃, time of 3-5s; Process 3: The thin alumina layer is formed by deposition using the ALD process. The conditions for the ALD process include: using trimethylaluminum and water vapor as precursors, and a temperature of 150-250℃. Process 4, the preparation method also includes: after depositing a thin alumina layer, annealing activation is performed. The annealing activation conditions include: in the presence of nitrogen or a nitrogen- and hydrogen-containing forming gas, the annealing temperature is 400-450℃, and the annealing time is 10-30min. Process 5, the preparation method also includes: S01. A first semiconductor layer is formed in the first region on the back side; Then proceed with S1 and S2; Then, SO2 is performed to form a second semiconductor layer in the second region on the back side; wherein one of the first region and the other of the second region is an N-region and the other is a P-region; S03. Then, a conductive film layer is formed on the outer surface of both the first semiconductor layer and the second semiconductor layer on the back side, and an isolation area is naturally formed at the same time. S04. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers of the first semiconductor layer and the second semiconductor layer, respectively. Process 6, the preparation method also includes: S101, provides double-sided polished silicon wafers; S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer; S103. The first etching opening is performed on the back side obtained in S102 to form the second semiconductor opening region; Then, S1 is performed to texturing and cleaning, forming a textured surface on the front side and the second semiconductor opening area, and completely removing the mask layer or retaining part of the mask layer; then S2 is performed. S104. Deposit a second semiconductor layer on the back side; S105. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. S106. Deposit a conductive film layer on the back side; S107. A third etching opening is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench. S108. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

26. A battery assembly, characterized in that, Including a back contact battery with a multiple anti-reflection structure as described in any one of claims 1-16.

27. The battery assembly according to claim 26, characterized in that, The battery module also includes a transparent film and photovoltaic glass arranged sequentially outward from the multiple anti-reflective structures.

28. The battery assembly according to claim 27, characterized in that, The battery assembly meets at least one of the following conditions: (1) The refractive index of the transparent film is 1.4-1.5; (2) The transparent encapsulating film is selected from at least one of ethylene-vinyl acetate copolymer, polyolefin elastomer, polyvinyl butyral, thermoplastic polyolefin, thermoplastic polyurethane, silicone, and acrylate films; (3) The thickness of the transparent film is 0.1-0.5 mm; (4) The light transmittance of photovoltaic glass is ≥90%; (5) The thickness of photovoltaic glass is 1-5mm.

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