Epitaxial wafer of vertical LED chip and preparation method thereof

Abstract

This invention relates to the field of semiconductor technology, and more particularly to an epitaxial wafer for a vertical LED chip, comprising a substrate, and on the substrate sequentially stacked layers: an h-BN layer, a modified graphene layer, an AlN layer, an undoped GaN layer, an N-type GaN layer, an SL layer, a multi-quantum-well emitting layer, an electron-blocking layer, and a P-type GaN layer. The h-BN layer is etched with H2 to form uniformly distributed nucleation holes, and the thickness of the h-BN layer is 10 nm to 15 nm, with a depth of 5 nm to 8 nm. The modified graphene layer is treated with nitrogen plasma and has a thickness of 1 nm to 2 nm. The AlN layer has a thickness of 16 nm to 20 nm. The SL layer comprises GaN and InGaN layers periodically alternating along the epitaxial direction, and the SL layer has V-shaped pits, which are filled by the multi-quantum-well emitting layer. The epitaxial wafer for the vertical LED chip prepared by this invention has fewer cracks and defects, a low loss rate during peeling, and produces LED chips with good light emission performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an epitaxial wafer for a vertical LED chip and its fabrication method. Background Technology

[0002] Vertical LED chips are thin-film LED chips that have undergone substrate stripping. They use substrates with high thermal conductivity such as Si, Ge, and Cu to replace traditional sapphire substrates. Two electrodes are located on both sides of the epitaxial layer, and current flows vertically through the chip. It is one of the three mainstream structures of LED chips.

[0003] The existing epitaxial wafers of vertical LED chips have the following disadvantages: (1) When growing LEDs on Si substrates, there is a large lattice mismatch between Si and GaN. Epitaxial growth requires the growth of multiple buffer layers, and cracks are easily generated on the surface. The wafers are also prone to cracking during chip operation. (2) When growing LED epitaxial wafers on sapphire substrates, laser stripping or chemical etching is required when making vertical chips. This can easily damage the epitaxial layer and affect the yield.

[0004] Cracks or defects generated during the peeling process of the epitaxial wafer of a vertical LED chip can create current leakage channels. Damaged interfaces can absorb light, and micro-defects in the epitaxial layer can increase non-radiative recombination centers, affecting the luminous performance of the finished LED chip. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides an epitaxial wafer for vertical LED chips. The epitaxial wafer has fewer cracks and defects and a low loss rate during peeling, resulting in LED chips with good light output.

[0006] To address the aforementioned issues, this invention proposes an epitaxial wafer for a vertical LED chip, comprising a substrate, and an h-BN layer, a modified graphene layer, an AlN layer, an undoped GaN layer, an N-type GaN layer, an SL layer, a multiple quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate. The h-BN layer is etched with H2 to form uniformly distributed nucleation pores. The thickness of the h-BN layer is 10nm~15nm, and the depth of the nucleation pores is 5nm~8nm. The modified graphene layer is treated with nitrogen plasma and has a thickness of 1 nm to 2 nm. The thickness of the AlN layer is 16nm~20nm; The SL layer comprises GaN and InGaN layers that are periodically and alternately stacked along the epitaxial direction. The SL layer has V-shaped pits, and the multi-quantum-well light-emitting layer fills the V-shaped pits of the SL layer.

[0007] As an improvement to the above technical solution, the h-BN layer is prepared by the following method: The substrate is placed in the reaction chamber, and B2H6, NH3 and H2 are introduced to deposit an initial h-BN layer on the substrate. Hydrogen etching is performed by introducing H2 and Ar into the reaction chamber, and nucleation pores are formed on the surface of the initial layer of the h-BN layer. The expansion direction of the nucleation pores is consistent with the lattice orientation of the h-BN crystal, thus obtaining the h-BN layer.

[0008] As an improvement to the above technical solution, the deposition temperature of the h-BN layer is 300℃~400℃, the inlet flow rate of B2H6 is 20sccm~60sccm, the inlet flow rate of NH3 is 70sccm~140sccm, and the inlet flow rate of H2 is 5sccm~10sccm. The initial hydrogen etching temperature for the h-BN layer is 950℃~980℃, the etching time is 8~20min, and the volume ratio of H2 introduced to Ar introduced during the etching process is 1.2~2.5. The density of the nucleation pores is 0.3 per μm. 2 ~0.8 per μm 2 The cross-section of the nucleation pore is triangular.

[0009] As an improvement to the above technical solution, the modified graphene layer is prepared by the following method: The device was placed in the reaction chamber, and CH4, H2 and Ar were introduced to deposit a graphene sublayer on the h-BN. N2 or a N2-H2 mixture is introduced into the reaction chamber and ionized into nitrogen plasma. The nitrogen plasma bombards the surface of the graphene sublayer, causing dense nucleation sites to form on its surface.

[0010] As an improvement to the above technical solution, the deposition temperature of the modified graphene layer is 700℃~1000℃, the CH4 inlet flow rate is 15sccm~30sccm, the Ar inlet flow rate is 180sccm~300sccm, and the H2 inlet flow rate is 10sccm~100sccm. The nitrogen plasma treatment has a processing power of 50W~100W, an N2 flow rate of 10sccm~25sccm, a processing pressure of 1atm~5atm, a processing temperature of 450℃~700℃, and a processing time of 30min~300min. In the N2-H2 mixed gas, N2 accounts for 5% to 20% of the total gas volume.

[0011] As an improvement to the above technical solution, the growth temperature of the AlN layer is 600℃~700℃; The growth pressure of the undoped GaN layer is 100 torr to 200 torr, the growth temperature is 1100℃ to 1150℃, and the thickness is 2nm to 3nm. The growth pressure of the N-type GaN layer is 200 torr to 400 torr, the growth temperature is 1080℃ to 1120℃, and the Si doping concentration is 1×10⁻⁶. 19 atoms / cm 3 ~2×10 19 atoms / cm 3 ; The SL layer comprises GaN and InGaN layers stacked alternately in a periodic manner, with a period number of 3 to 6, a growth temperature of 800℃ to 850℃, and a growth pressure of 100 torr to 200 torr. The GaN layer has a thickness of 20nm~30nm, and the GaN layer is doped with Si at a concentration of 4×10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 ; The InGaN layer has an In content of 0.1~0.2 and a thickness of 3nm~5nm; The multi-quantum-well light-emitting layer comprises periodically alternating layers of light-emitting InGaN and GaN barrier layers, with a period number of 8 to 10, a growth temperature of 750°C to 800°C, and a growth pressure of 100 torr to 200 torr. The thickness of the light-emitting InGaN layer is 2nm~3nm, and the In content is 0.3~0.4%. The GaN barrier layer has a thickness of 10 nm to 20 nm, and the Si doping concentration is 1 × 10⁻⁶. 18 atoms / cm 3 ~2×10 18 atoms / cm 3 ; The electron blocking layer comprises an AlGaN layer, grown at a temperature of 950℃~1000℃, with a growth pressure of 100 torr~200 torr, and an Al content of 0.2~0.3%. The growth temperature of the p-type GaN layer is 900℃~980℃, the growth pressure is 100 torr~200 torr, and the Mg doping concentration is 2×10⁻⁶. 19 atoms / cm 3 ~3×10 19 atoms / cm 3 .

[0012] Accordingly, the present invention also provides a method for fabricating an epitaxial wafer of a vertical LED chip, characterized by comprising the following steps: Provide substrate; An h-BN layer is deposited on the substrate, and then H2 etching is performed to form uniformly distributed nucleation pores on the surface. A graphene sublayer is deposited on the h-BN layer, and then the surface of the graphene sublayer is treated with nitrogen plasma to form the modified graphene layer. An AlN layer is deposited on the modified graphene layer; An undoped GaN layer is deposited on the AlN layer; An N-type GaN layer is deposited on the undoped GaN layer; An SL layer is deposited on the N-type GaN layer; The device is placed in a reaction chamber, and NH3 is introduced as the N source, TMIn as the In source, TMGa as the Ga source, and SiH4 as the dopant to deposit and form GaN and InGaN layers that are periodically and alternately stacked along the epitaxial direction. The SL layer has V-shaped pits, and the multi-quantum well light-emitting layer fills the V-shaped pits of the SL layer. A multi-quantum-well light-emitting layer is deposited on the SL layer; An electron blocking layer is deposited on the multi-quantum-well light-emitting layer; A P-type GaN layer is deposited on the electron blocking layer described above.

[0013] As an improvement to the above technical solution, in the step of depositing the h-BN layer, the substrate is placed in a reaction chamber, and B2H6, NH3 and H2 are introduced. The flow rate of B2H6 is 20 sccm~60 sccm, the flow rate of NH3 is 70 sccm~140 sccm, the flow rate of H2 is 5 sccm~10 sccm, and the temperature of the reaction chamber is 300℃~400℃, and an initial h-BN layer is obtained by deposition. After obtaining the initial layer of h-BN, H2 and Ar are introduced for hydrogen etching, with Ar as the carrier gas. The etching temperature is 950℃~980℃ and the etching time is 8~20min. The volume ratio of H2 introduced to Ar introduced during the etching process is 1.2~2.5. The density of the h-BN layer is 50 / 100 μm. 2 The cross-section of the nucleation pore is triangular. As an improvement to the above technical solution, in the step of depositing the modified graphene layer, the device is placed in a reaction chamber, CH4 is used as the carbon source, and the flow rate of CH4 is 15 sccm to 30 sccm; H2 and Ar2 are introduced as carrier gases, the flow rate of Ar is 180 sccm to 300 sccm, and the flow rate of H2 is 10 sccm to 100 sccm; the temperature of the reaction chamber is 700℃ to 1000℃. In the nitrogen plasma deposition process, N2 or a N2-H2 mixed gas is introduced into the reaction chamber and ionized into nitrogen plasma. The processing power is 50W~100W, the N2 flow rate is 10sccm~25sccm, the processing pressure is 1atm~5atm, the processing temperature is 450℃~700℃, and the processing time is 30min~300min. In the N2-H2 mixed gas, N2 accounts for 5% to 20% of the total gas volume.

[0014] As an improvement to the above technical solution, in the step of depositing the AlN layer, an Al target is used, and N2, Ar and O2 are introduced. The volume ratio of Ar to N2 is 4~6, the flow rate of O2 is 1sccm~2sccm, and the deposition temperature is 600℃~700℃. In the step of depositing the undoped GaN layer, NH3 is introduced as the N source, H2 is introduced as the carrier gas, TMGa is introduced as the Ga source, and the growth temperature is 1100℃~1150℃. In the step of depositing the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as N-type dopant, and the growth temperature is 1080℃~1120℃. In the step of depositing the SL layer, NH3 is introduced as the N source, TMIn as the In source, TMGa as the Ga source, and SiH4 as the dopant, and the growth temperature is 800℃~850℃. In the step of depositing the multi-quantum-well light-emitting layer, the multi-quantum-well light-emitting layer includes periodically alternating layers of light-emitting InGaN and GaN barrier layers, with a period number of 8 to 10. In the step of depositing the luminescent InGaN layer, NH3, TMGa and TMIn are used as raw materials, the growth temperature is 750℃~800℃, and the growth pressure is 100 torr~200 torr. In the step of depositing the GaN barrier layer, NH3 and TMGa are used as raw materials, the growth temperature is 750℃~800℃, and the growth pressure is 100 torr~200 torr. In the step of depositing the electron blocking layer, NH3, TMGa and TMAl are used as raw materials, the growth temperature is 950℃~1000℃, and the growth pressure is 100 torr~200 torr; In the step of depositing the P-type GaN layer, NH3 and TMGa are used as raw materials, CP2Mg is used as Mg dopant, the growth temperature is 900℃~980℃, and the growth pressure is 100 torr~200 torr.

[0015] The implementation of this invention has the following beneficial effects: This invention provides an epitaxial wafer for a vertical LED chip, in which an h-BN layer and a modified graphene layer are sequentially disposed between a substrate and an AlN layer. The h-BN layer is etched with hydrogen gas, forming uniformly distributed nucleation pores on its surface. The hydrogen-etched h-BN can induce graphene nucleation, resulting in less defect contamination and ensuring the quality of subsequent film formation. The modified graphene is formed by treating graphene sublayers with nitrogen plasma and is disposed on the h-BN layer. The graphene sublayers are composed of carbon atoms arranged in sp... 2 The alternating hybrid arrangement forms a six-membered ring network 2D structure with a smooth, unsuspended surface. Weak van der Waals bonds between layers reduce stress caused by lattice and thermal mismatches, and minimize substrate-related defects. The graphene sublayer surface is treated with nitrogen plasma to increase the density of nucleation sites, upon which an AlN layer is grown. The surface morphology of the AlN layer inherits from the graphene morphology, resulting in a high-density AlN layer. This provides a foundation for subsequent high-quality UGaN growth and improves the yield of vertical LED chips. Simultaneously, the GaN grown on the graphene surface efficiently absorbs light energy and undergoes thermal decomposition under 248nm excimer laser irradiation. The gas pressure generated during decomposition pushes the graphene film apart, achieving exfoliation. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a vertical LED chip according to an embodiment of the present invention; Figure 2 This is a top view of the h-BN layer according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the front view structure of the h-BN layer according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the SL layer according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a multi-quantum well light-emitting layer according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0018] See Figure 1 and Figure 4As shown, an embodiment of the present invention provides an epitaxial wafer for a vertical LED chip, including a substrate 1, and an h-BN layer 2, a modified graphene layer 3, an AlN layer 4, an undoped GaN layer 5, an N-type GaN layer 6, an SL layer 7, a multi-quantum-well light-emitting layer 8, an electron blocking layer 9, and a P-type GaN layer 10 sequentially stacked on the substrate 1. The h-BN layer 2 is etched with H2 to form uniformly distributed nucleation pores 21. The thickness of the h-BN layer 2 is 10nm~15nm, and the depth of the nucleation pores 21 is 5nm~8nm. The thickness of the h-BN layer 2 can be 10nm, 11nm, 12nm, 13nm, 14nm, or 15nm, but is not limited to these values. The depth of the nucleation pores can be 5nm, 5.3nm, 5.7nm, 5.9nm, 6.8nm, 6.9nm, 7.5nm, 7.8nm, or 8nm, but is not limited to these values. The modified graphene layer 3 is treated with nitrogen plasma and has a thickness of 1 nm to 2 nm; the thickness of the modified graphene layer 3 can be 1 nm, 1.1 nm, 1.3 nm, 1.7 nm, or 2 nm, but is not limited to these. The thickness of the AlN layer 4 is 16nm~20nm; the thickness of the AlN layer 4 can be 16nm, 17nm, 18nm, 19nm, or 20nm, but is not limited to these. The SL layer 7 comprises GaN layers 71 and InGaN layers 72 that are periodically and alternately stacked along the epitaxial direction. The SL layer 7 has V-shaped pits 73, and the multi-quantum-well light-emitting layer 8 fills the V-shaped pits 73 of the SL layer 7. The SL layer 7 works in conjunction with the N-type GaN layer 6 to release stress on the epitaxial substrate.

[0019] In this embodiment, an h-BN layer 2 and a modified graphene layer 3 are sequentially disposed between the substrate 1 and the AlN layer 4. The h-BN layer 2 is etched with hydrogen gas, forming uniformly distributed nucleation pores 21 on its surface. The hydrogen-etched h-BN can induce graphene nucleation, resulting in less defect contamination and ensuring the quality of subsequent film formation. The modified graphene layer 3 is formed by treating a graphene sublayer with nitrogen plasma and is disposed on the h-BN layer 2. The graphene sublayer is composed of carbon atoms arranged in sp... 2The alternating hybrid arrangement forms a six-membered ring network 2D structure with a smooth, unsuspended surface. Weak van der Waals bonds between layers reduce stress caused by lattice and thermal mismatches, and minimize substrate-related defects. The graphene sublayer surface is treated with nitrogen plasma to increase the density of nucleation sites, upon which an AlN layer 4 is grown. The surface morphology of the AlN layer 4 inherits from the graphene morphology, resulting in a high-density AlN layer 4, providing a foundation for subsequent high-quality UGaN growth and improving the yield of vertical LED chips. Simultaneously, the GaN grown on the graphene surface efficiently absorbs light energy and undergoes thermal decomposition under 248nm excimer laser irradiation. The gas pressure generated during decomposition pushes the graphene film apart, achieving exfoliation.

[0020] See Figure 2 and Figure 3 As shown, preferably, the h-BN layer 2 is prepared by the following method: The substrate is placed in the reaction chamber, and B2H6, NH3 and H2 are introduced to deposit an initial h-BN layer on the substrate. Hydrogen etching is performed by introducing H2 and Ar into the reaction chamber, and nucleation pores 21 are formed on the surface of the initial layer of the h-BN layer. The expansion direction of the nucleation pores 21 is consistent with or substantially consistent with the lattice orientation of the h-BN crystal, thus obtaining the h-BN layer 2.

[0021] The hydrogen etching process selectively removes h-BN material, forming a controllable microstructure that helps release thermal and lattice stresses between the h-BN layer 2 and the substrate. The etched h-BN layer 2 acts as a buffer layer, effectively bridging the substrate 1 and the epitaxial layer, reducing defect density caused by excessive buffer layers, and improving the overall epitaxial wafer yield.

[0022] The expansion direction of the nucleation pores 21 is consistent with or substantially consistent with the lattice orientation, which can effectively disperse and release local stress and avoid microcracks caused by stress concentration. At the same time, the uniform pore structure maintains the high thermal conductivity of h-BN, which is conducive to the transfer of heat from the epitaxial layer to the substrate and improves the heat dissipation performance of the LED chip.

[0023] More preferably, the deposition temperature of the h-BN layer 2 is 300℃~400℃, the inlet flow rate of B2H6 is 20sccm~60sccm, the inlet flow rate of NH3 is 70sccm~140sccm, and the inlet flow rate of H2 is 5sccm~10sccm. The deposition temperature of h-BN layer 2 can be 300℃, 310℃, 350℃, 370℃, 380℃, 390℃, or 400℃, but is not limited to these. The inflow rate of B2H6 can be 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm, 50 sccm, 55 sccm, or 60 sccm, but is not limited to these. The inflow rate of NH3 can be 70 sccm, 80 sccm, 90 sccm, 100 sccm, 110 sccm, 120 sccm, 130 sccm, or 140 sccm, but is not limited to these. The inflow rate of H2 can be 5 sccm, 6 sccm, 7 sccm, 8 sccm, 9 sccm, or 10 sccm, but is not limited to these.

[0024] The initial hydrogen etching temperature for the h-BN layer is 950℃~980℃, the etching time is 8~20min, and the volume ratio of H2 introduced to Ar introduced during the etching process is 1.2~2.5. The hydrogen etching temperature can be 950℃, 960℃, 970℃, or 980℃, but is not limited to these. The etching time can be 8 min, 10 min, 12 min, 14 min, 16 min, 18 min, or 20 min, but is not limited to these. The ratio of the volume of H2 introduced to the volume of Ar introduced during the etching process can be 1.2, 1.5, 1.8, 2.1, 2.3, or 2.5, but is not limited to these.

[0025] When the hydrogen etching temperature is below 950℃, the activation energy of the reaction is insufficient, resulting in incomplete etching and difficulty in forming or uneven distribution of pores. When the hydrogen etching temperature is above 980℃, the h-BN layer 2 may undergo thermal decomposition or lattice reconstruction, destroying the boundary structure of the nucleation pores.

[0026] The etching time with hydrogen determines the depth and extent of hole expansion. When the etching time is less than 8 minutes, the hole expansion is insufficient and the edge of the nucleation hole cannot be formed; when the etching time is greater than 20 minutes, the etching exceeds the controllable range and damages the structural integrity of the h-BN layer.

[0027] The volume ratio of H2 to Ar regulates the activity and uniformity of the etching reaction. When the ratio is less than 1.2, the argon gas is excessively diluted, the hydrogen gas has insufficient reactivity, the etching is slow or uneven, resulting in sparse or localized void distribution, weakening the stress buffering effect, increasing interface defects between the epitaxial layer and the substrate, and causing chipping or yield problems. When the ratio is greater than 2.5, the hydrogen concentration is too high, the etching rate is too fast, the void size is out of control or the edges are rough. At the same time, at high temperatures, hydrogen may cause hydrogenation damage to the h-BN layer, producing amorphous regions, reducing thermal conductivity, and affecting the heat dissipation of the LED chip.

[0028] The density of the nucleation pores is 0.3 per μm. 2 ~0.8 per μm 2 The cross-section of the nucleation pore is triangular.

[0029] The cross-sectional shape of the nucleation pores formed after hydrogen etching of the h-BN layer is related to the volume ratio of H2 to Ar introduced. By controlling the volume ratio of H2 to Ar introduced to be 1.2~2.5, the cross-sectional shape of the nucleation pores can be controlled to be triangular.

[0030] The density of the nucleation pores 21 can be 0.3 per μm. 2 0.4 per μm 2 0.5 per μm 2 0.6 perμm 2 0.7 per μm 2 0.8 per μm 2 However, it is not limited to this.

[0031] Preferably, the modified graphene layer 3 is prepared by the following method: The device was placed in the reaction chamber, and CH4, H2 and Ar were introduced to deposit a graphene sublayer on the h-BN. N2 or a N2-H2 mixture is introduced into the reaction chamber and ionized into nitrogen plasma. The nitrogen plasma bombards the surface of the graphene sublayer, causing dense nucleation sites to form on its surface.

[0032] The aforementioned graphene sublayers are a six-membered ring network 2D structure formed by alternating carbon atoms in an sp2 hybridization manner. The resulting surface is smooth and free of hanging, with more than 2 atomic layers. The weak van der Waals bonding between the graphene sublayers can reduce stress caused by lattice mismatch and thermal mismatch, and reduce defects introduced by the substrate.

[0033] More preferably, the deposition temperature of the modified graphene layer 8 is 700℃~1000℃, the CH4 inlet flow rate is 15sccm~30sccm, the Ar inlet flow rate is 180sccm~300sccm, and the H2 inlet flow rate is 10sccm~100sccm. The deposition temperature of the graphene layer can be 700℃, 800℃, 900℃, or 1000℃, but is not limited to these. The CH4 inlet flow rate can be, for example, 15 sccm, 17 sccm, 18 sccm, 19 sccm, 25 sccm, 27 sccm, or 30 sccm, but is not limited to these. The Ar inlet flow rate can be, for example, 180 sccm, 170 sccm, 200 sccm, 220 sccm, 250 sccm, 280 sccm, or 300 sccm, but is not limited to these. The H2 inlet flow rate can be, for example, 10 sccm, 20 sccm, 50 sccm, 70 sccm, 80 sccm, or 100 sccm, but is not limited to these.

[0034] The nitrogen plasma treatment has a processing power of 50W~100W, an N2 flow rate of 10sccm~25sccm, a processing pressure of 1atm~5atm, a processing temperature of 450℃~700℃, and a processing time of 30min~300min. In the N2-H2 mixed gas, N2 accounts for 5% to 20% of the total gas volume.

[0035] Examples of nitrogen plasma treatment power include 50W, 60W, 70W, 80W, and 100W, but are not limited to these. Examples of nitrogen flow rate include 10sccm, 13sccm, 15sccm, 18sccm, 20sccm, and 25sccm, but are not limited to these. Examples of treatment pressure include 1atm, 2atm, 3atm, 4atm, and 5atm, but are not limited to these. Examples of treatment temperature include 450℃, 500℃, 550℃, 600℃, 650℃, and 700℃, but are not limited to these.

[0036] The nitrogen content directly affects the concentration and reactivity of reactive nitride species in the plasma. A nitrogen content of 5%–20% ensures the generation of an appropriate amount of highly reactive nitrogen radicals, which can be uniformly embedded in the graphene lattice to form pyridine nitrogen. Pyridine nitrogen enhances the electron mobility of graphene through lone pair electrons, while also providing dense nucleation sites, thus improving the epitaxial quality of subsequent AlN layers.

[0037] When the volume percentage is less than 5%, the doping concentration is insufficient and the nucleation sites are sparse; when the volume percentage is greater than 20%, nitrogen plasma with excessive energy is easily formed, which leads to excessive etching of the graphene lattice.

[0038] In some embodiments, the growth temperature of the AlN layer 4 is 600℃~700℃; the growth temperature of the AlN layer 4 can be 600℃, 610℃, 630℃, 670℃, or 700℃, but is not limited to these.

[0039] The growth pressure of the undoped GaN layer 5 is 100 torr to 200 torr, the growth temperature is 1100℃ to 1150℃, and the thickness is 2nm to 3nm. The growth pressure of the undoped GaN layer can be 100 torr, 110 torr, 120 torr, 130 torr, 150 torr, 170 torr, 180 torr, or 200 torr, but is not limited to these values. The growth temperature can be 1100℃, 1110℃, 1120℃, 1130℃, 1140℃, or 1150℃, but is not limited to these values. The thickness of the undoped GaN layer can be 2nm, 2.2nm, 2.5nm, 2.7nm, or 3nm, but is not limited to these values.

[0040] The growth pressure of the N-type GaN layer 6 is 200 torr to 400 torr, the growth temperature is 1080℃ to 1120℃, and the Si doping concentration is 1×10⁻⁶. 19 atoms / cm 3 ~2×10 19 atoms / cm 3 The growth pressure of the N-type GaN layer can be 200 torr, 210 torr, 240 torr, 270 torr, 300 torr, 350 torr, or 400 torr, but is not limited to these values. The growth thickness of the N-type GaN layer can be 1080℃, 1090℃, 1100℃, 1110℃, or 1120℃, but is not limited to these values. The Si doping concentration can be 1×10⁻⁶. 19 atoms / cm 3 1.1×10 19 atoms / cm 3 1.3×10 19 atoms / cm 3 1.5×10 19 atoms / cm 3 1.7×10 19 atoms / cm 3 1.9×10 19 atoms / cm 3 2×10 19 atoms / cm 3 However, it is not limited to this.

[0041] See Figure 1 and Figure 4As shown, the SL layer 7 has V-shaped pits for releasing stress in the underlying layer. It comprises periodically alternating GaN layers 71 and InGaN layers 72, with a cycle number of 3 to 6, a growth temperature of 800℃ to 850℃, and a growth pressure of 100 torr to 200 torr. The cycle number can be 3, 4, 5, or 6. The growth temperature of the SL layer 7 can be 800℃, 810℃, 820℃, 830℃, 840℃, or 850℃, but is not limited to these. The growth pressure of the SL layer 7 can be 100 torr, 110 torr, 150 torr, 170 torr, 180 torr, or 200 torr, but is not limited to these.

[0042] The GaN layer 71 has a thickness of 20nm~30nm, and the GaN layer 71 is doped with Si at a concentration of 4×10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 The GaN layer thickness can be 20nm, 22nm, 25nm, 26nm, 28nm, or 30nm, but is not limited to these. The Si doping concentration can be 4×10⁻⁶. 18 atoms / cm 3 4.1×10 18 atoms / cm 3 4.3×10 18 atoms / cm 3 4.5×10 18 atoms / cm 3 4.8×10 18 atoms / cm 3 5×10 18 atoms / cm 3 However, it is not limited to this.

[0043] The InGaN layer 72 has an In content of 0.1~0.2 and a thickness of 3nm~5nm; the In content of the InGaN layer 72 can be 0.1, 0.11, 0.17, 0.18, or 0.2, but is not limited to these. The thickness of the InGaN layer 72 can be 3nm, 3.2nm, 3.7nm, 3.9nm, 4.3nm, 4.7nm, 4.8nm, or 5nm, but is not limited to these.

[0044] See Figure 5As shown, the multi-quantum-well light-emitting layer 8 comprises periodically alternating layers of light-emitting InGaN layers 81 and GaN barrier layers 82, with a period number of 8 to 10, a growth temperature of 750℃ to 800℃, and a growth pressure of 100 torr to 200 torr; the period number can be 8, 9, or 10. The growth temperature can be 750℃, 760℃, 770℃, 780℃, 790℃, or 800℃, but is not limited to these. The growth pressure can be 100 torr, 110 torr, 120 torr, 130 torr, 140 torr, 150 torr, 160 torr, 170 torr, 180 torr, 190 torr, or 200 torr, but is not limited to these.

[0045] The thickness of the light-emitting InGaN layer 81 is 2nm~3nm, and the In content is 0.3~0.4%. The thickness of the light-emitting InGaN layer 81 can be 2nm, 2.1nm, 2.3nm, 2.5nm, 2.8nm, or 3nm, but is not limited to these. The In content can be 0.3, 0.32, 0.35, 0.37, 0.39, or 0.4, but is not limited to these.

[0046] The GaN barrier layer 82 has a thickness of 10nm~20nm and a Si doping concentration of 1×10⁻⁶. 18 atoms / cm 3 ~2×10 18 atoms / cm 3 The thickness of the GaN barrier layer 82 can be 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, or 20nm, but is not limited to these. The Si doping content can be 1×10⁻⁶. 18 atoms / cm 3 1.1×10 18 atoms / cm 3 1.4×10 18 atoms / cm 3 1.7×10 18 atoms / cm 3 1.8×10 18 atoms / cm 3 2×10 18 atoms / cm 3 However, it is not limited to this.

[0047] The electron blocking layer 9 comprises an AlGaN layer, grown at a temperature of 950℃~1000℃, a growth pressure of 100 torr~200 torr, and an Al content of 0.2~0.3%. The growth temperature of the electron blocking layer 9 can be 950℃, 960℃, 970℃, 980℃, 990℃, or 1000℃, but is not limited to these. The growth pressure of the electron blocking layer 9 can be 100 torr, 110 torr, 120 torr, 150 torr, 170 torr, 190 torr, or 200 torr, but is not limited to these. The Al content of the electron blocking layer 9 can be 0.2%, 0.22%, 0.25%, 0.27%, 0.28%, or 0.3%, but is not limited to these.

[0048] The growth temperature of the p-type GaN layer 10 is 900℃~980℃, the growth pressure is 100 torr~200 torr, and the Mg doping concentration is 2×10⁻⁶. 19 atoms / cm 3 ~3×10 19 atoms / cm 3 The growth temperature of the p-type GaN layer 10 can be 900℃, 910℃, 930℃, 950℃, 970℃, or 980℃, but is not limited to these. The growth pressure of the p-type GaN layer 10 can be 100 torr, 120 torr, 140 torr, 150 torr, 170 torr, 190 torr, or 200 torr, but is not limited to these. The Mg doping concentration can be 2 × 10⁻⁶. 19 atoms / cm 3 2.2×10 19 atoms / cm 3 2.4×10 19 atoms / cm 3 2.5×10 19 atoms / cm 3 2.7×10 19 atoms / cm 3 2.8×10 19 atoms / cm 3 3×10 19 atoms / cm 3 However, it is not limited to this.

[0049] Accordingly, this invention also provides a method for fabricating an epitaxial wafer of a vertical LED chip, comprising the following steps: Provide substrate; A sapphire substrate was selected and loaded into the MOCVD process. The reaction chamber temperature was controlled at 1000℃~1200℃ and the pressure at 200 torr~600 torr. The sapphire substrate was subjected to high-temperature annealing for 5 min~8 min in an H2 atmosphere to clean the particles and oxides on the surface of the sapphire substrate.

[0050] An h-BN layer is deposited on the substrate, and then H2 etching is performed to form uniformly distributed nucleation pores on the surface. The substrate is placed in a reaction chamber, and B2H6, NH3 and H2 are introduced. The flow rate of B2H6 is 20 sccm to 60 sccm, the flow rate of NH3 is 70 sccm to 140 sccm, and the flow rate of H2 is 5 sccm to 10 sccm. The temperature of the reaction chamber is 300℃ to 400℃, and an initial layer of h-BN is deposited. After obtaining the initial layer of h-BN, H2 and Ar are introduced for hydrogen etching, with Ar as the carrier gas. The etching temperature is 950℃~980℃ and the etching time is 8~20min. The volume ratio of H2 introduced to Ar introduced during the etching process is 1.2~2.5. The density of the nucleation pores is 0.3 per μm. 2 ~0.8 per μm 2 The cross-section of the nucleation pore is triangular, and the expansion direction of the nucleation pore is consistent with the orientation of the h-BN grain.

[0051] A graphene sublayer is deposited on the h-BN layer, and then the surface of the graphene sublayer is treated with nitrogen plasma to form the modified graphene layer. The device is placed in the reaction chamber, with CH4 as the carbon source and the CH4 flow rate being 15 sccm to 30 sccm; H2 and Ar2 are introduced as carrier gases, with the Ar flow rate being 180 sccm to 300 sccm and the H2 flow rate being 10 sccm to 100 sccm; the reaction chamber temperature is 700℃ to 1000℃. In the nitrogen plasma deposition process, N2 or a N2-H2 mixed gas is introduced into the reaction chamber and ionized into nitrogen plasma. The processing power is 50W~100W, the N2 flow rate is 10sccm~25sccm, the processing pressure is 1atm~5atm, the processing temperature is 450℃~700℃, and the processing time is 30min~300min. In the N2-H2 mixed gas, N2 accounts for 5% to 20% of the total gas volume.

[0052] An AlN layer is deposited on the modified graphene layer; Using an Al target, N2, Ar and O2 are introduced, with the volume ratio of Ar to N2 being 4 to 6, the O2 flow rate being 1 sccm to 2 sccm, and the deposition temperature being 600℃ to 700℃. An undoped GaN layer is deposited on the AlN layer; Using an Al target, N2, Ar and O2 are introduced, with the volume ratio of Ar to N2 being 4 to 6, the O2 flow rate being 1 sccm to 2 sccm, and the deposition temperature being 600℃ to 700℃. An N-type GaN layer is deposited on the undoped GaN layer; Using NH3 and TMGa as raw materials, and SiH4 as an N-type dopant, the growth temperature is 1080℃~1120℃; An SL layer is deposited on the N-type GaN layer; The device is placed in a reaction chamber, and NH3 is introduced as the N source, TMIn as the In source, TMGa as the Ga source, and SiH4 as the dopant. The growth temperature is 800℃~850℃, and GaN and InGaN layers are deposited and periodically stacked along the epitaxial direction. The SL layer has V-shaped pits, and the multi-quantum well light-emitting layer fills the V-shaped pits of the SL layer. A multi-quantum-well light-emitting layer is deposited on the SL layer; The multi-quantum-well light-emitting layer comprises periodically alternating layers of light-emitting InGaN and GaN barrier layers, with a period number of 8 to 10. In the step of depositing the luminescent InGaN layer, NH3, TMGa and TMIn are used as raw materials, the growth temperature is 750℃~800℃, and the growth pressure is 100 torr~200 torr. In the step of depositing the GaN barrier layer, NH3 and TMGa are used as raw materials, the growth temperature is 750℃~800℃, and the growth pressure is 100 torr~200 torr. An electron blocking layer is deposited on the multi-quantum-well light-emitting layer; Using NH3, TMGa and TMAl as raw materials, the growth temperature is 950℃~1000℃ and the growth pressure is 100 torr~200 torr; A P-type GaN layer is deposited on the electron blocking layer described above.

[0053] Using NH3 and TMGa as raw materials and CP2Mg as Mg dopant, the growth temperature was 900℃~980℃ and the growth pressure was 100 torr~200 torr.

[0054] The present invention will be further illustrated below with specific embodiments.

[0055] Example 1 This invention provides an epitaxial wafer for a vertical LED chip, comprising a substrate, and an h-BN layer, a modified graphene layer, an AlN layer, an undoped GaN layer, an N-type GaN layer, an SL layer, a multiple quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate. The h-BN layer is etched with H2 to form uniformly distributed nucleation pores. The thickness of the h-BN layer is 12.5 nm, the depth of the nucleation pores is 6.5 nm, the distribution density of the nucleation pores is 0.5 μm2, and the cross-section of the nucleation pores is triangular. The modified graphene layer is treated with nitrogen plasma and has a thickness of 1.5 nm. The thickness of the AlN layer is 18 nm; The SL layer comprises GaN and InGaN layers that are periodically and alternately stacked along the epitaxial direction, with a period number of 4. The SL layer has V-shaped pits, and the multi-quantum-well light-emitting layer fills the V-shaped pits of the SL layer. The GaN layer has a thickness of 25 nm and is doped with Si at a concentration of 4.5 × 10⁻⁶. 18 atoms / cm 3 ; The InGaN layer has an In content of 0.15 and a thickness of 4 nm.

[0056] A method for fabricating an epitaxial wafer of a vertical LED chip includes the following steps: Provide substrate; An h-BN layer is deposited on the substrate, and then H2 etching is performed to form uniformly distributed nucleation pores on the surface. Specifically, in the step of depositing the h-BN layer, the substrate is placed in a reaction chamber, and B2H6, NH3 and H2 are introduced. The flow rate of B2H6 is 40 sccm, the flow rate of NH3 is 100 sccm, the flow rate of H2 is 7.5 sccm, and the temperature of the reaction chamber is 350°C, so as to obtain the initial h-BN layer. After obtaining the initial layer of h-BN, H2 and Ar were introduced for hydrogen etching, with Ar as the carrier gas. The etching temperature was 965℃ and the etching time was 14min. The volume ratio of H2 introduced to Ar introduced during the etching process was 1.8. A graphene sublayer is deposited on the h-BN layer, and then the surface of the graphene sublayer is treated with nitrogen plasma to form the modified graphene layer. Specifically, in the step of depositing the modified graphene layer, the device is placed in a reaction chamber, with CH4 as the carbon source and a CH4 flow rate of 22.5 sccm; H2 and Ar2 are introduced as carrier gases, with an Ar flow rate of 240 sccm and an H2 flow rate of 55 sccm; the reaction chamber temperature is 850°C. In the nitrogen plasma deposition process, N2 or a N2-H2 mixed gas is introduced into the reaction chamber and ionized into nitrogen plasma. The processing power is 75W, the N2 flow rate is 17.5sccm, the processing pressure is 3atm, the processing temperature is 575℃, and the processing time is 215min. In the N2-H2 mixture, N2 accounts for 12.5% ​​of the total gas volume; An AlN layer is deposited on the modified graphene layer; Specifically, in the step of depositing the AlN layer, an Al target is used, and N2, Ar and O2 are introduced, with a volume ratio of Ar to N2 of 5, an O2 flow rate of 1.5 sccm, and a deposition temperature of 650°C. An undoped GaN layer is deposited on the AlN layer; Specifically, in the step of depositing the undoped GaN layer, NH3 is introduced as the N source, H2 as the carrier gas, TMGa as the Ga source, the growth temperature is 1125℃, the growth pressure is 150 torr, and the thickness is 2.5nm. An N-type GaN layer is deposited on the undoped GaN layer; Specifically, in the step of depositing the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as the N-type dopant, the growth temperature is 1080℃~1120℃, the growth pressure is 300 torr, and the Si doping concentration is 1.5×10⁻⁶. 19 atoms / cm 3 ; An SL layer is deposited on the N-type GaN layer; Specifically, in the step of depositing the SL layer, NH3 is introduced as the N source, TMIn as the In source, TMGa as the Ga source, and SiH4 as the dopant, and the growth temperature is 825℃. The SL layer comprises GaN and InGaN layers stacked alternately in a periodic manner, with a period of 4, a growth temperature of 825°C, and a growth pressure of 150 torr. The GaN layer has a thickness of 25 nm and is doped with Si at a concentration of 4.5 × 10⁻⁶. 18 atoms / cm 3 ; The InGaN layer has an In content of 0.15 and a thickness of 4 nm. A multi-quantum-well light-emitting layer is deposited on the SL layer; Specifically, in the step of depositing the multi-quantum-well light-emitting layer, the multi-quantum-well light-emitting layer includes periodically alternating layers of light-emitting InGaN and GaN barrier layers, with a period number of 8 to 10; In the step of depositing the luminescent InGaN layer, NH3, TMGa and TMIn are used as raw materials, the growth temperature is 775℃, the growth pressure is 150 torr, the thickness of the luminescent InGaN layer is 2.5 nm, and the In content is 0.35. In the step of depositing the GaN barrier layer, NH3 and TMGa were used as raw materials, the growth temperature was 775℃, the growth pressure was 150 torr, the thickness of the GaN barrier layer was 15 nm, and the Si doping concentration was 1.5 × 10⁻⁶. 18 atoms / cm 3 ; An electron blocking layer is deposited on the multi-quantum-well light-emitting layer; Specifically, in the step of depositing the electron blocking layer, NH3, TMGa and TMAl are used as raw materials, the growth temperature is 975℃, the growth pressure is 150 torr, and the Al component content is 0.25%. A P-type GaN layer is deposited on the electron blocking layer described above; Specifically, in the step of depositing the p-type GaN layer, NH3 and TMGa are used as raw materials, CP2Mg is used as the Mg dopant, the growth temperature is 940℃, the growth pressure is 150 torr, and the Mg doping concentration is 2.5 × 10⁻⁶. 19 atoms / cm 3 .

[0057] Example 2 The difference between this embodiment and Embodiment 1 is that: In the hydrogen etching step of h-BN, the etching time is 8 min, and the volume ratio of H2 introduced to Ar introduced during the etching process is 1.2.

[0058] Example 3 The difference between this embodiment and Embodiment 1 is that: In the hydrogen etching step of h-BN, the etching time is 20 min, and the volume ratio of H2 introduced to Ar introduced during the etching process is 2.5.

[0059] Example 4 The difference between this embodiment and Embodiment 1 is that: In the step of nitrogen plasma treatment of graphene sublayer, the treatment power of nitrogen plasma treatment is 50W and the treatment time is 30min. In the N2-H2 mixture, N2 accounts for 5% of the total gas volume.

[0060] Example 5 The difference between this embodiment and Embodiment 1 is that: In the step of nitrogen plasma treatment of graphene sublayer, the treatment power of nitrogen plasma treatment is 100W and the treatment time is 300min. In the N2-H2 mixed gas, N2 accounts for 20% of the total gas volume.

[0061] Comparative Example 1 The difference between this comparative example and Example 1 is as follows: The epitaxial wafer of the vertical LED chip does not contain an h-BN layer or a modified graphene layer.

[0062] Comparative Example 2 The difference between this comparative example and Example 1 is as follows: The vertical LED chip does not have an h-BN layer in its epitaxial wafer.

[0063] Comparative Example 3 The difference between this comparative example and Example 1 is as follows: The modified graphene layer is not provided in the epitaxial wafer of the vertical LED chip.

[0064] Performance testing: The epitaxial wafers of the vertical LED chips prepared in Examples 1-5 and Comparative Examples 1-3 were fabricated into 200μm×200μm chips by substrate lift-off and transfer under high-energy pulsed laser irradiation. 2 Photoelectric performance tests were conducted at a current density, and the luminous efficiency improvement compared to Comparative Example 1 was calculated for Examples 1-5 and Comparative Examples 2-3.

[0065]

[0066] Referring to Examples 1-5 and Comparative Examples 1-3 above, by sequentially setting an h-BN layer (etched with hydrogen) and a modified graphene layer between the substrate and the AlN layer of the vertical LED chip epitaxial wafer, damage to the LED chip can be reduced and the peeling yield can be improved, thereby improving the light output effect of the LED chip and reducing the chip's operating energy consumption.

[0067] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An epitaxial wafer for a vertical LED chip, characterized in that, It includes a substrate, and an h-BN layer, a modified graphene layer, an AlN layer, an undoped GaN layer, an N-type GaN layer, an SL layer, a multiple quantum well light-emitting layer, an electron blocking layer and a P-type GaN layer that are sequentially stacked on the substrate. The h-BN layer is etched with H2 to form uniformly distributed nucleation pores. The thickness of the h-BN layer is 10nm~15nm, and the depth of the nucleation pores is 5nm~8nm. The modified graphene layer is treated with nitrogen plasma and has a thickness of 1 nm to 2 nm. The thickness of the AlN layer is 16nm~20nm; The SL layer comprises GaN and InGaN layers that are periodically and alternately stacked along the epitaxial direction. The SL layer has V-shaped pits, and the multi-quantum-well light-emitting layer fills the V-shaped pits of the SL layer.

2. The epitaxial wafer of the vertical LED chip as described in claim 1, characterized in that, The h-BN layer is prepared by the following method: The substrate is placed in the reaction chamber, and B2H6, NH3 and H2 are introduced to deposit an initial h-BN layer on the substrate. Hydrogen etching is performed by introducing H2 and Ar into the reaction chamber, and nucleation pores are formed on the surface of the initial layer of the h-BN layer. The expansion direction of the nucleation pores is consistent with the lattice orientation of the h-BN crystal, thus obtaining the h-BN layer.

3. The epitaxial wafer of the vertical LED chip as described in claim 2, characterized in that, The deposition temperature of the h-BN layer is 300℃~400℃, the inlet flow rate of B2H6 is 20sccm~60sccm, the inlet flow rate of NH3 is 70sccm~140sccm, and the inlet flow rate of H2 is 5sccm~10sccm. The initial hydrogen etching temperature for the h-BN layer is 950℃~980℃, the etching time is 8~20min, and the volume ratio of H2 introduced to Ar introduced during the etching process is 1.2~2.

5. The density of the nucleation pores is 0.3 per μm. 2 ~0.8 per μm 2 The cross-section of the nucleation pore is triangular.

4. The epitaxial wafer of the vertical LED chip as described in claim 1, characterized in that, The modified graphene layer was prepared by the following method: The device was placed in the reaction chamber, and CH4, H2 and Ar were introduced to deposit a graphene sublayer on the h-BN. N2 or a N2-H2 mixture is introduced into the reaction chamber and ionized into nitrogen plasma. The nitrogen plasma bombards the surface of the graphene sublayer, causing dense nucleation sites to form on its surface.

5. The epitaxial wafer of the vertical LED chip as described in claim 4, characterized in that, The deposition temperature of the modified graphene layer is 700℃~1000℃, the CH4 inlet flow rate is 15sccm~30sccm, the Ar inlet flow rate is 180sccm~300sccm, and the H2 inlet flow rate is 10sccm~100sccm. The nitrogen plasma treatment has a processing power of 50W~100W, an N2 flow rate of 10sccm~25sccm, a processing pressure of 1atm~5atm, a processing temperature of 450℃~700℃, and a processing time of 30min~300min. In the N2-H2 mixed gas, N2 accounts for 5% to 20% of the total gas volume.

6. The epitaxial wafer of the vertical LED chip as described in claim 4, characterized in that, The growth temperature of the AlN layer is 600℃~700℃; The growth pressure of the undoped GaN layer is 100 torr to 200 torr, the growth temperature is 1100℃ to 1150℃, and the thickness is 2nm to 3nm. The growth pressure of the N-type GaN layer is 200 torr to 400 torr, the growth temperature is 1080℃ to 1120℃, and the Si doping concentration is 1×10⁻⁶. 19 atoms / cm 3 ~2×10 19 atoms / cm 3 ; The SL layer comprises GaN and InGaN layers stacked alternately in a periodic manner, with a period number of 3 to 6, a growth temperature of 800℃ to 850℃, and a growth pressure of 100 torr to 200 torr. The GaN layer has a thickness of 20nm~30nm, and the GaN layer is doped with Si at a concentration of 4×10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 ; The InGaN layer has an In content of 0.1~0.2 and a thickness of 3nm~5nm; The multi-quantum-well light-emitting layer comprises periodically alternating layers of light-emitting InGaN and GaN barrier layers, with a period number of 8 to 10, a growth temperature of 750°C to 800°C, and a growth pressure of 100 torr to 200 torr. The thickness of the light-emitting InGaN layer is 2nm~3nm, and the In content is 0.3~0.4%. The GaN barrier layer has a thickness of 10 nm to 20 nm, and the Si doping concentration is 1 × 10⁻⁶. 18 atoms / cm 3 ~2×10 18 atoms / cm 3 ; The electron blocking layer comprises an AlGaN layer, grown at a temperature of 950℃~1000℃, with a growth pressure of 100 torr~200 torr, and an Al content of 0.2~0.3%. The growth temperature of the p-type GaN layer is 900℃~980℃, the growth pressure is 100 torr~200 torr, and the Mg doping concentration is 2×10⁻⁶. 19 atoms / cm 3 ~3×10 19 atoms / cm 3 .

7. A method for fabricating an epitaxial wafer of a vertical LED chip as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Provide substrate; An h-BN layer is deposited on the substrate, and then H2 etching is performed to form uniformly distributed nucleation pores on the surface. A graphene sublayer is deposited on the h-BN layer, and then the surface of the graphene sublayer is treated with nitrogen plasma to form the modified graphene layer. An AlN layer is deposited on the modified graphene layer; An undoped GaN layer is deposited on the AlN layer; An N-type GaN layer is deposited on the undoped GaN layer; An SL layer is deposited on the N-type GaN layer; The device is placed in a reaction chamber, and NH3 is introduced as the N source, TMIn as the In source, TMGa as the Ga source, and SiH4 as the dopant to deposit and form GaN and InGaN layers that are periodically and alternately stacked along the epitaxial direction. The SL layer has V-shaped pits, and the multi-quantum well light-emitting layer fills the V-shaped pits of the SL layer. A multi-quantum-well light-emitting layer is deposited on the SL layer; An electron blocking layer is deposited on the multi-quantum-well light-emitting layer; A P-type GaN layer is deposited on the electron blocking layer described above.

8. The method for fabricating the epitaxial wafer of a vertical LED chip as described in claim 7, characterized in that, In the step of depositing the h-BN layer, the substrate is placed in a reaction chamber, and B2H6, NH3 and H2 are introduced. The flow rate of B2H6 is 20 sccm to 60 sccm, the flow rate of NH3 is 70 sccm to 140 sccm, the flow rate of H2 is 5 sccm to 10 sccm, and the temperature of the reaction chamber is 300℃ to 400℃. The initial h-BN layer is deposited. After obtaining the initial layer of h-BN, H2 and Ar are introduced for hydrogen etching, with Ar as the carrier gas. The etching temperature is 950℃~980℃ and the etching time is 8~20min. The volume ratio of H2 introduced to Ar introduced during the etching process is 1.2~2.

5. The density of the h-BN layer is 50 / 100 μm. 2 The cross-section of the nucleation pore is triangular.

9. The method for fabricating the epitaxial wafer of a vertical LED chip as described in claim 7, characterized in that, In the step of depositing the modified graphene layer, the device is placed in a reaction chamber, with CH4 as the carbon source and a CH4 flow rate of 15 sccm to 30 sccm; H2 and Ar2 are introduced as carrier gases, with an Ar flow rate of 180 sccm to 300 sccm and an H2 flow rate of 10 sccm to 100 sccm; the reaction chamber temperature is 700℃ to 1000℃. In the nitrogen plasma deposition process, N2 or a N2-H2 mixed gas is introduced into the reaction chamber and ionized into nitrogen plasma. The processing power is 50W~100W, the N2 flow rate is 10sccm~25sccm, the processing pressure is 1atm~5atm, the processing temperature is 450℃~700℃, and the processing time is 30min~300min. In the N2-H2 mixed gas, N2 accounts for 5% to 20% of the total gas volume.

10. The method for fabricating the epitaxial wafer of a vertical LED chip as described in claim 7, characterized in that, In the step of depositing the AlN layer, an Al target is used, and N2, Ar and O2 are introduced. The volume ratio of Ar to N2 is 4 to 6, the flow rate of O2 is 1 sccm to 2 sccm, and the deposition temperature is 600℃ to 700℃. In the step of depositing the undoped GaN layer, NH3 is introduced as the N source, H2 is introduced as the carrier gas, TMGa is introduced as the Ga source, and the growth temperature is 1100℃~1150℃. In the step of depositing the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as N-type dopant, and the growth temperature is 1080℃~1120℃. In the step of depositing the SL layer, NH3 is introduced as the N source, TMIn as the In source, TMGa as the Ga source, and SiH4 as the dopant, and the growth temperature is 800℃~850℃. In the step of depositing the multi-quantum-well light-emitting layer, the multi-quantum-well light-emitting layer includes periodically alternating layers of light-emitting InGaN and GaN barrier layers, with a period number of 8 to 10. In the step of depositing the luminescent InGaN layer, NH3, TMGa and TMIn are used as raw materials, the growth temperature is 750℃~800℃, and the growth pressure is 100 torr~200 torr. In the step of depositing the GaN barrier layer, NH3 and TMGa are used as raw materials, the growth temperature is 750℃~800℃, and the growth pressure is 100 torr~200 torr. In the step of depositing the electron blocking layer, NH3, TMGa and TMAl are used as raw materials, the growth temperature is 950℃~1000℃, and the growth pressure is 100 torr~200 torr; In the step of depositing the P-type GaN layer, NH3 and TMGa are used as raw materials, CP2Mg is used as Mg dopant, the growth temperature is 900℃~980℃, and the growth pressure is 100 torr~200 torr.

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