Epitaxial wafer processing method and micro-led device

Abstract

This invention discloses a method for processing epitaxial wafers and a MicroLED device. By selecting two epitaxial wafers with different light-emitting colors and performing temporary bonding, substrate peeling, and patterning respectively, two types of array-shaped light-emitting units are obtained. The epitaxial light-emitting layers of the two types of light-emitting units are basically flush, forming a near-coplanar light-emitting structure. This avoids defocusing problems caused by height differences between different epitaxial light-emitting layers, improving the uniformity of light emission and display consistency of the device from the process source. Furthermore, a buffer gap is formed at the alignment bonding interface of the two types of light-emitting units, so the bonding pressure only acts on one type of light-emitting unit, while the surface of the other type of light-emitting unit is not subjected to pressure load. This reduces the bonding pressure required, eliminates the problem of insufficient bonding caused by uneven thickness, improves product yield, and also shortens process time and improves production efficiency by reducing bonding pressure.

Description

Technical Field

[0001] This invention relates to the field of light-emitting technology, and in particular to an epitaxial wafer processing method and a MicroLED device. Background Technology

[0002] Existing MicroLED colorization solutions all have significant drawbacks: the X~Cube three-color splicing solution has a large overall size and high mass production cost; the blue light epitaxy combined with quantum dot color conversion solution is difficult to balance device brightness and long-term operational reliability; the vertical stacking of multi-color light-emitting units results in a relatively high overall pixel thickness, which cannot meet the application requirements of ultra-high PPI near-eye displays.

[0003] To overcome the drawbacks of the above-mentioned solutions, the industry has developed a fabrication process that arranges different color light-emitting units laterally in a coplanar manner. However, this process still faces a difficult technical bottleneck: there is a significant vertical height difference between the epitaxial light-emitting layers of various light-emitting units. In AR near-eye display scenarios, the distance between the human eye and the display panel is very close. Inconsistent heights of the light-emitting layers can lead to differences in the optical distance between different color light sources, resulting in problems such as image defocusing, spot distortion, pixel color mixing, and image blurring, which severely weakens the imaging effect. In addition, there is no buffer gap when the two epitaxial wafers are directly bonded together. The bonding pressure can easily cause cracking of the semiconductor epitaxial layer and lattice damage, resulting in a low yield of finished devices. Summary of the Invention

[0004] This invention provides an epitaxial wafer processing method and a MicroLED device to reduce the problems of defocusing and high bonding pressure, thereby improving the display effect of the MicroLED device.

[0005] In a first aspect, embodiments of the present invention provide a method for processing an epitaxial wafer, comprising: A second epitaxial wafer and a third epitaxial wafer with different light colors are selected. The second epitaxial wafer is subjected to a substrate removal process. Then, the second epitaxial wafer and the third epitaxial wafer after the removal process are patterned to prepare a second light-emitting unit and a third light-emitting unit arranged in an array on a temporary substrate. The second light-emitting unit and the third light-emitting unit are located on different temporary substrates. In this case, the original substrate is selectively removed from the third epitaxial wafer or the original substrate is retained before the patterning is performed. The patterned second epitaxial wafer and the third epitaxial wafer are aligned and bonded through a temporary bonding layer to form an integrated bonding structure, so that the second light-emitting unit and the third light-emitting unit are alternately arranged in the lateral direction, and the upper surface of the epitaxial light-emitting layer of the second light-emitting unit and the upper surface of the epitaxial light-emitting layer of the third light-emitting unit are flush. The second light-emitting unit and the third light-emitting unit have a buffer gap at their alignment bonding interface. The buffer gap is configured such that during alignment bonding, the bonding pressure acts on the third light-emitting unit but not on the second light-emitting unit.

[0006] Optionally, during alignment bonding, the thickness of the temporary bonding layer on the surface of the third light-emitting unit is greater than the thickness of the temporary bonding layer on the surface of the second light-emitting unit, so as to form the buffer gap; After the alignment bonding is completed, the following is also included: The temporary substrate of the third light-emitting unit is peeled off, and the temporary bonding layer on the surfaces of the second and third light-emitting units is planarized to make the surfaces of the second and third light-emitting units flush.

[0007] Optionally, the second epitaxial wafer undergoes a raw substrate lift-off process, and the lifted second epitaxial wafer is then patterned to fabricate a second light-emitting unit arrayed on a temporary substrate, including: The second epitaxial wafer is temporarily bonded to the first temporary substrate, and the original substrate of the second epitaxial wafer is peeled off. The second epitaxial wafer after stripping the original substrate is patterned; The patterned second epitaxial wafer is temporarily bonded a second time to the temporary substrate, and the first temporary substrate is peeled off to prepare the second light-emitting unit arrayed on the temporary substrate; Patterning the third epitaxial wafer to fabricate a third light-emitting unit arrayed on a temporary substrate includes: The third epitaxial wafer is temporarily bonded for the first time to the temporary substrate, and the original substrate of the third epitaxial wafer is peeled off. The third epitaxial wafer, after being stripped from the original substrate, is patterned to prepare the third light-emitting unit arranged in an array on the temporary substrate.

[0008] Optionally, after the alignment bonding is completed, the integrated bonding structure is sequentially subjected to dielectric filling and chemical mechanical polishing.

[0009] Optional, also includes: The thickness difference between the temporary bonding layer on the surface of the second light-emitting unit and the temporary bonding layer on the surface of the third light-emitting unit is 0.03 μm to 3 μm.

[0010] Optionally, the thickness of the N-type semiconductor layer of the third epitaxial wafer is greater than the thickness of the N-type semiconductor layer of the second epitaxial wafer. When the second epitaxial wafer and the third epitaxial wafer are aligned and bonded, the N-type semiconductor layer of the second epitaxial wafer and the N-type semiconductor layer of the third epitaxial wafer are located in the same layer and form a height difference at the alignment and bonding interface. The height difference constitutes the buffer gap.

[0011] Optionally, the second epitaxial wafer undergoes a raw substrate lift-off process, and the lifted second epitaxial wafer is then patterned to fabricate a second light-emitting unit arrayed on a temporary substrate, including: The second epitaxial wafer is temporarily bonded to the first temporary substrate, and the original substrate of the second epitaxial wafer is peeled off. The second epitaxial wafer after the original substrate is stripped is patterned to prepare the second light-emitting unit arrayed on the temporary substrate; Patterning the third epitaxial wafer to fabricate a third light-emitting unit arrayed on a temporary substrate includes: A temporary bonding layer is deposited on the surface of the third epitaxial wafer, and the third epitaxial wafer is patterned to prepare the third light-emitting unit arranged in an array on the temporary substrate.

[0012] Optionally, after alignment bonding is completed, the following may also be included: The original substrate corresponding to the third light-emitting unit is stripped off, and the N-type semiconductor layer of the second light-emitting unit and the N-type semiconductor layer of the third light-emitting unit are planarized to make the surfaces of the second light-emitting unit and the third light-emitting unit flush.

[0013] Optionally, after flattening, the process also includes: The second and third light-emitting units, after planarization, are flipped and bonded to another temporary substrate through a temporary bonding layer.

[0014] Secondly, embodiments of the present invention also provide a MicroLED device, characterized in that it is fabricated using the epitaxial wafer processing method described above, and the device comprises: A driving substrate and multiple light-emitting pixels arranged in an array; The light-emitting pixel includes at least a second light-emitting unit and a third light-emitting unit with different light-emitting colors. The second light-emitting unit and the third light-emitting unit are patterned from different monochromatic epitaxial wafers and are alternately arranged on the same plane after alignment bonding and peeling off the original substrate. The epitaxial light-emitting layers of the second light-emitting unit and the third light-emitting unit are located on the same layer.

[0015] In the technical solution of this invention, the epitaxial light-emitting layers of the two types of light-emitting units are basically flush, forming a nearly coplanar light-emitting structure. This avoids defocusing problems caused by height differences between different epitaxial light-emitting layers, improving the uniformity of light emission and display consistency from the fundamental process. Furthermore, a buffer gap is formed at the alignment and bonding interface between the two types of light-emitting units, so the bonding pressure only acts on one type of light-emitting unit, while the surface of the other type of light-emitting unit is not subjected to pressure load. This reduces the bonding pressure required, eliminates insufficient bonding caused by uneven thickness, improves product yield, and by reducing bonding pressure, also shortens process time and improves production efficiency.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a MicroLED device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a second epitaxial wafer provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a first temporary substrate provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a first bonding sheet provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the first bonding sheet after the original substrate has been peeled off, according to an embodiment of the present invention. Figure 6 This is a schematic diagram of a structure for depositing a temporary bonding layer on a first bonding wafer according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a structure in which a first bonding sheet forms a second light-emitting unit, according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a second bonding sheet provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the second bonding sheet after the first temporary substrate has been peeled off, according to an embodiment of the present invention. Figure 10 This is a schematic diagram of a structure in which a third bonding sheet forms a third light-emitting unit, according to an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of a fourth bonding sheet provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of the fourth bonding sheet after the third temporary substrate has been removed, according to an embodiment of the present invention. Figure 13 This is a schematic diagram of the planarized structure of a fourth bonding sheet provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a fifth bonding sheet provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of a structure for peeling off the second temporary substrate from the fifth bonding sheet according to an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of a third light-emitting unit provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of the structure of a fifth bonding sheet provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of a fifth bonding sheet peeling off the original substrate according to an embodiment of the present invention; Figure 19 This is a schematic diagram of the planarized structure of a fifth bonding sheet provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of the structure of a sixth bonding sheet provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of a structure for peeling off the first temporary substrate from the sixth bonding sheet, provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Example 1 like Figure 1 As shown, the MicroLED device includes a driving substrate 10 and a plurality of light-emitting pixels arranged in an array on one side of the driving substrate 10. Taking any light-emitting pixel as an example, the light-emitting pixel includes a second light-emitting unit 102 and a third light-emitting unit 103 arranged horizontally in a preset manner, which are alternately arranged on the same plane; the light-emitting pixel may also include a first light-emitting unit 101, which is an optional structure and can be arranged as a whole on the lower or upper layer of the second light-emitting unit 102 and the third light-emitting unit 103. The embodiment of the present invention does not specifically limit the arrangement position of the first light-emitting unit 101. For example, as Figure 1 As shown, the first light-emitting unit 101 is disposed below the second light-emitting unit 102 and the third light-emitting unit 103, and the second light-emitting unit 102 and the third light-emitting unit 103 are at least partially vertically stacked directly above the epitaxial light-emitting layer of the first light-emitting unit 101. It can be understood that even if the first light-emitting unit 101 is omitted, the fabrication of the MicroLED device can be completed solely by the horizontally laid-out second light-emitting unit 102 and the third light-emitting unit 103, without affecting the formation of the basic light-emitting structure of the device.

[0022] The first light-emitting unit 101 emits light of a first color, the second light-emitting unit 102 emits light of a second color, and the third light-emitting unit 103 emits light of a third color. The emitted colors of the first light-emitting unit 101, the second light-emitting unit 102, and the third light-emitting unit 103 are distinct from each other, and each color of light can be selected as any one of red, green, or blue light. For example, the first light-emitting unit 101 emits red light, the second light-emitting unit 102 emits green light, and the third light-emitting unit 103 emits blue light.

[0023] Various light-emitting units can be combined to form light-emitting pixels. The combination of units of a single light-emitting pixel is not limited to a single structure. For example, a single light-emitting pixel can also include a first light-emitting unit 101, a second light-emitting unit 102, and a third light-emitting unit 103, forming a standard RGB full-color pixel based on red, green, and blue light sources. For another example, a single full-color pixel can also be configured as a combination of a first light-emitting unit 101, two second light-emitting units 102, and a third light-emitting unit 103, forming multiple specifications of full-color pixels such as RGBG, GRGB, or RGGB based on the ratio of one red, two green, and one blue light source.

[0024] The main material of the driving substrate 10 can be formed from semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, and indium phosphide, or it can be made from non-conductive materials such as glass, plastic, or sapphire wafers. The driving substrate 10 can be a CMOS backplane or a TFT glass substrate, etc., and it has a driving circuit. The driving circuit is used to provide electrical signals to the light-emitting unit to control the brightness.

[0025] The first light-emitting unit 101, the second light-emitting unit 102, and the third light-emitting unit 103 can all be constructed by sequentially stacking three epitaxial functional layers along the thickness direction of the substrate, with the middle layer being an epitaxial light-emitting layer. The thickness of the epitaxial light-emitting layer is set to 0.05 μm to 0.5 μm. The epitaxial light-emitting layer can adopt a single quantum well structure, a multiple quantum well structure, or a composite structure with well layers and barrier layers stacked alternately. The two sides of the epitaxial light-emitting layer are an N-type semiconductor layer and a P-type semiconductor layer, respectively. For example, the first light-emitting unit 101 includes a first P-type semiconductor layer 1013, a first light-emitting layer 1012, and a first N-type semiconductor layer 1011 sequentially stacked along the thickness direction of the driving substrate 10. The second light-emitting unit 102 includes a second P-type semiconductor layer 1023, a second light-emitting layer 1022, and a second N-type semiconductor layer 1021 stacked sequentially along the thickness direction of the driving substrate 10; the third light-emitting unit 103 includes a third P-type semiconductor layer 1033, a third light-emitting layer 1032, and a third N-type semiconductor layer 1031 stacked sequentially along the thickness direction of the driving substrate 10.

[0026] When configured as a full-color pixel structure, the lateral dimension of the epitaxial light-emitting layer of the first light-emitting unit 101 is larger than the lateral dimensions of the epitaxial light-emitting layers of the second light-emitting unit 102 and the third light-emitting unit 103. That is, the lateral dimension of the first epitaxial light-emitting layer 1012 is larger than the lateral dimensions of the second epitaxial light-emitting layer 1022 and the third epitaxial light-emitting layer 1032. This overlapping arrangement can reduce the overall area occupied by a single full-color pixel and improve the pixel integration density.

[0027] Because P-type semiconductor layers have poor conductivity, they are prone to uneven lateral current distribution and large differences in local luminous intensity. To optimize conductivity and balance current distribution, a current spreading layer can be added to the surface of the P-type semiconductor layer. The current spreading layer has two optional structures: one is a single-layer integrated structure, using ITO material as both the ohmic contact layer and the current transport layer; the other is a composite layered structure, composed of independent ohmic contact layers and independent current transport layers. The ohmic contact layer can be made of ITO or Ni / ITO material, while the current transport layer can be made of ITO or ultrathin highly conductive nano-metal films such as Al or Ag. When using metal materials, the metal film thickness must be controlled to the nanometer level to ensure high light transmittance and avoid obstructing the light path of the epitaxial light-emitting layer. Furthermore, to balance conductivity and light transmittance, the current transport layer in the middle region of the pixel can preferably be set as an ITO conductive layer.

[0028] The thickness of the P-type semiconductor layer is 0.05 μm to 5 μm. The P-type semiconductor layer can be P-type GaN, for example, a P-type semiconductor layer can be formed by doping GaN with elements such as magnesium and boron. In other implementations, the P-type semiconductor layer can also be P-type InGaN, P-type GaP, P-type AlInP, etc., without specific limitations.

[0029] The thickness of the N-type semiconductor layer is 0.1 μm to 5 μm. Typically, N-type GaN doped with phosphorus or arsenic impurities can be used. In other alternative embodiments, semiconductor materials such as N-type InGaN and N-type AlInGaP can also be used, and no specific limitations are imposed here.

[0030] In this embodiment, the second light-emitting unit 102 and the third light-emitting unit 103 are arranged in a flat, pre-defined pattern. The second light-emitting layer 1022 of the second light-emitting unit 102 and the third light-emitting layer 1032 of the third light-emitting unit 103 are essentially flush, forming a nearly coplanar light-emitting structure. In the prior art, the epitaxial light-emitting layers of different light-emitting units within the same pixel generally have a vertical height difference, and sometimes two types of light-emitting units are stacked into two layers. This results in the light-emitting surfaces not being on the same reference plane. The staggered light-emitting structure causes deviations in the propagation path, refraction angle, and optical focal length of the emitted light from different light-emitting units, leading to defects such as optical defocus, light spot distortion, abnormal pixel mixing, and blurred or fuzzy display images, severely affecting the display imaging quality. This invention provides a technical solution to achieve the above objectives by setting the second light-emitting layer 1022 of the second light-emitting unit 102 and the third light-emitting layer 1032 of the third light-emitting unit 103 to a basically flush coplanar structure. This eliminates the vertical interlayer height difference of the light-emitting units within the pixel from the root of the device structure, unifies the light-emitting reference plane and optical focal plane of each light-emitting unit, ensures the consistency of the optical path and focal length of the light emitted by each unit, effectively avoids optical defocus defects, and significantly improves the light emission uniformity, color reproduction accuracy and overall display effect of a single pixel.

[0031] Example 2: A method for fabricating a MicroLED device Based on the same inventive concept, this invention also provides a method for fabricating a MicroLED device, used to fabricate a MicroLED device comprising a second light-emitting unit and a third light-emitting unit as described above. The specific fabrication steps are as follows: S101. Provide a second epitaxial wafer. like Figure 2 As shown, the second epitaxial wafer includes a primary substrate 11 and an epitaxial layer grown on one side of the primary substrate 11. The epitaxial layer includes a second N-type semiconductor layer 1021, a second light-emitting layer 1022, and a second P-type semiconductor layer 1023 sequentially stacked along the thickness direction of the primary substrate 11. In this step, the thickness parameters and material selection of each functional layer of the epitaxial wafer are the same as in Example 1, and will not be repeated here.

[0032] S102. Temporary bonding of the second epitaxial wafer like Figure 3 and Figure 4As shown, a first temporary substrate 21 is selected, and a temporary bonding layer 30 is deposited on the first temporary substrate 21 and the epitaxial layer of the second epitaxial wafer, respectively. The thickness of the temporary bonding layer 30 ranges from 0.05 to 5 μm, depending on the material and process conditions. The first temporary substrate 21 and the second epitaxial wafer are temporarily bonded to obtain the first bonded wafer. The first temporary substrate 21 can be selected from silicon, sapphire, silicon carbide, gallium nitride, or optical glass, preferably silicon wafer, which has high compatibility with front-end processes such as photolithography, deposition, and etching. The material of the temporary bonding layer 30 can be silicon oxide, silicon nitride, or other organic material bonding layers, etc., without specific limitations.

[0033] S103. Peel off the original substrate Based on the material of the original substrate 11 in the second epitaxial wafer, the original substrate is peeled off using the corresponding process. The following examples use sapphire substrate and gallium arsenide substrate as two commonly used substrates: If the original substrate 11 is a sapphire substrate, an ultraviolet laser lift-off process can be used, employing ultraviolet lasers in the 248nm, 308nm, or 355nm bands incident from the back side of the sapphire substrate. This band of ultraviolet light has a transmittance of over 90% for sapphire, allowing the laser to penetrate the substrate and reach the sapphire-GaN epitaxial interface. The GaN active layer strongly absorbs the ultraviolet laser energy, causing the interface region to instantly heat up to several thousand degrees Celsius, triggering GaN thermal decomposition and generating metallic Ga and nitrogen gas. The rapid expansion of the interface gas within a short time generates high pressure, which, combined with the thermal stress from the high temperature, causes the interfacial bonds between the substrate and the epitaxial layer to break. This allows for the complete lift-off of the entire sapphire substrate without significant mechanical stress, and the overall damage to the epitaxial crystal lattice structure is minimal.

[0034] If the original substrate 11 is a gallium arsenide substrate, selective wet etching can be used for stripping. An ammonia-based selective etching solution is selected, and the gallium arsenide substrate is fully wetted by immersion or spraying. The etching solution preferentially dissolves the gallium arsenide substrate, with almost no corrosion to the epitaxial layer. By precisely controlling the solution concentration, etching temperature, and immersion time, the original gallium arsenide substrate can be completely removed, maintaining the morphology and optoelectronic properties of the epitaxial layer.

[0035] like Figure 5 and Figure 6 As shown, after the stripping is completed, a temporary bonding layer 30 is deposited on the second N-type semiconductor layer 1021. The second P-type semiconductor layer 1023 is located on the side closer to the first temporary substrate 21, and the second N-type semiconductor layer 1021 is located on the side farther away from the first temporary substrate 21.

[0036] S104. First bonding wafer photolithography patterning like Figure 7As shown, the epitaxial layer of the first bonding wafer is patterned using standard semiconductor photolithography and dry etching processes. Following resist coating, exposure, development, and selective etching, the arrayed second light-emitting units 102 are fabricated. At least a portion of the temporary bonding layer 30 beneath the second P-type semiconductor layer 1023 is etched.

[0037] S105. Secondary substrate replacement bonding like Figure 8 As shown, the first bonding sheet for patterning the second light-emitting unit 102 is temporarily bonded to the second temporary substrate 25 via a temporary bonding layer 30 on the side where the second N-type semiconductor 1021 is located, to obtain the second bonding sheet. The second temporary substrate 25 can be silicon, sapphire, SiC, GaN, or optical glass, with silicon substrate being preferred.

[0038] S106. Remove the first temporary substrate like Figure 9 As shown, the first temporary substrate 21 on the second bonding sheet is peeled off, leaving the temporary bonding layer 30 on the surface of the second P-type semiconductor layer 1023. Taking a silicon temporary substrate as an example, plasma dry etching or mechanical polishing combined with chemical mechanical polishing can be used. After removing the first temporary substrate 21 and the temporary bonding layer, the second P-type semiconductor layer 1023 is located on the side away from the second temporary substrate 25, and the second N-type semiconductor layer 1021 is located on the side closer to the second temporary substrate 25.

[0039] S107. Preparation of the third bonded sheet Similar to the preparation method of the second bonding wafer, a third epitaxial wafer is also prepared. The third epitaxial wafer includes a primary substrate 11 and an epitaxial layer grown on one side of the primary substrate. The epitaxial layer includes a third N-type semiconductor layer 1031, a third light-emitting layer 1032, and a third P-type semiconductor layer 1033, which are sequentially stacked along the direction away from the primary substrate. In this step, the thickness parameters and material selection of each functional layer of the epitaxial wafer are the same as in Example 1, and will not be repeated here.

[0040] like Figure 10 As shown, based on the third epitaxial wafer, steps S101 to S104 are repeated to obtain the third bonding wafer, and an array of third light-emitting units 103 are fabricated on it. The difference is that the thickness of the temporary bonding layer 30 on the surface of the P-type semiconductor side 1031 of the third epitaxial wafer is thicker than the thickness of the temporary bonding layer 30 at the corresponding position on the surface of the second epitaxial wafer, preferably by 0.03~3 μm. After fabrication, the third N-type semiconductor layer 1031 is located on the side away from the third temporary substrate 26, and a temporary bonding layer 30 is deposited on its surface; the third P-type semiconductor layer 1033 is located on the side closer to the third temporary substrate 26.

[0041] S108. Precise alignment bonding like Figure 11 As shown, the second and third bonding sheets are precisely aligned and bonded, forming a buffer gap at the alignment bonding interface to create a fourth bonding sheet. The fourth bonding sheet is an integrated bonding structure. The second and third light-emitting units are laterally complementary and laid flat to form an integrated bonding structure. The N-type semiconductor layers below each light-emitting layer are of approximately equal thickness. The second light-emitting layer 1022 and the third light-emitting layer 1032 are coplanar, with their light-emitting surfaces flush, forming a coplanar light-emitting pixel structure.

[0042] S109. Remove temporary substrate like Figure 12 As shown, the third temporary substrate 26 on the fourth bonding sheet is peeled off. During the alignment bonding process, the bonding pressure is only applied to one side of the third light-emitting unit 103. The surface of the second light-emitting unit 102 is not subjected to bonding pressure load. The specific process can be referred to step S106.

[0043] S110. Planarization of the fourth bonded wafer like Figure 13 As shown, the dielectric material is filled into the gaps between the light-emitting units on the fourth bonded sheet, and then chemical mechanical polishing is performed until the surfaces of each light-emitting unit tend to be flush. Alternatively, chemical mechanical polishing can be performed first, and then the dielectric layer can be deposited and polished again after the substrate is subsequently peeled off. The specific method can be flexibly adjusted according to the process requirements.

[0044] S111. Fourth bonding sheet bonding like Figure 14 As shown, the processed fourth bonding sheet is bonded to the driving substrate 10 with its P-type semiconductor layer side to obtain the fifth bonding sheet.

[0045] S112. Temporary substrate removal like Figure 15 As shown, the second temporary substrate 25 on the fifth bonding sheet is peeled off, and then a dual-color light-emitting device is fabricated using the existing MicroLED standardized process route. The specific process can be referred to in step S106.

[0046] In this embodiment, after the two types of light-emitting units are aligned and bonded, their initial heights of the light-emitting layers are basically the same, that is, the second light-emitting layer and the third light-emitting layer are on the same layer and the light-emitting end faces are basically flush, so that the two light-emitting units have the same optical object distance, avoiding the defocusing problem caused by the height difference between different epitaxial light-emitting layers, and improving the uniformity of light emission and the consistency of display from the process source.

[0047] Furthermore, since the thickness of the temporary bonding layer on the surface of the third epitaxial wafer is greater than that on the surface of the second epitaxial wafer, during this bonding process, the bonding pressure only acts on the temporary bonding layer of the third epitaxial wafer, while the surface of the temporary bonding layer of the second epitaxial wafer is not subjected to pressure load. This design has two advantages: firstly, it reduces the bonding pressure required; secondly, it avoids the risk of bonding failure caused by process uniformity deviations. If the process uniformity is poor, the thickness of the temporary bonding layer on the P-type semiconductor layer in the second epitaxial wafer may exceed the thickness of the temporary bonding layer on the P-type semiconductor layer in the third epitaxial wafer in some areas, resulting in insufficient bonding at the bonding interface and ultimately bonding failure defects. Therefore, this solution can significantly improve mass production adaptability: on the one hand, it eliminates the problem of insufficient bonding of the third epitaxial wafer caused by uneven thickness, improving product yield; on the other hand, it shortens process time and improves production efficiency by reducing bonding pressure.

[0048] Example 3 Based on the same inventive concept, this embodiment provides another method for fabricating a MicroLED device, used to fabricate the full-color MicroLED device comprising a second light-emitting unit and a third light-emitting unit as described in Embodiment 1. The specific steps are as follows: S201. Provide a second epitaxial wafer. See Figure 2 This step is the same as step S101 in Example 2, and will not be repeated here.

[0049] S202. Temporary bonding of the second epitaxial wafer See Figure 3 and Figure 4 This step is the same as step S102 in Example 2, and will not be repeated here.

[0050] S203. Peel off the original substrate See Figure 5 and Figure 6 This step is the same as step S103 in Example 2, and will not be repeated here.

[0051] S204. First bonding wafer photolithography patterning See Figure 7 This step is the same as step S104 in Example 2, and will not be repeated here.

[0052] S205. Provides a third epitaxial wafer. A third epitaxial wafer is provided, comprising a primary substrate 11 and an epitaxial layer grown on one side of the primary substrate 11. The epitaxial layer comprises a third N-type semiconductor layer 1031, a third light-emitting layer 1032, and a third P-type semiconductor layer 1033 sequentially stacked along the thickness direction of the primary substrate. The thickness of the third N-type semiconductor layer 1031 is greater than the thickness of the second N-type semiconductor layer 1021. A temporary bonding layer 30 is deposited on the third P-type semiconductor layer 1033 of the third epitaxial wafer. The overall thickness of the third P-type semiconductor layer 1033 and the temporary bonding layer 30 on the third epitaxial wafer is comparable to the overall thickness of the second P-type semiconductor layer 1023 and the temporary bonding layer on the second epitaxial wafer.

[0053] S206. Photolithographic patterning of the third epitaxial wafer See Figure 16 The epitaxial layer of the third epitaxial wafer is patterned using standard semiconductor photolithography and dry etching processes. After coating, exposure, development, and selective etching, the arrayed third light-emitting units 103 are prepared. In this step, the third P-type semiconductor layer 1033 is located on the side away from the original substrate 11, and the third N-type semiconductor layer 1031 is located on the side closer to its original substrate 11.

[0054] S207. Precise alignment bonding See Figure 17 The first bonding sheet and the third epitaxial sheet are aligned and bonded with high precision to obtain the fifth bonding sheet, so that the second light-emitting unit 102 and the third light-emitting unit 103 are laid out in a complementary manner in the lateral direction, and the second light-emitting layer 1022 and the third light-emitting layer 1032 are located in the same layer with the light-emitting surfaces basically flush, forming a pixel structure with approximately coplanar light emission.

[0055] S208. Stripping the substrate of the second bonding layer. See Figure 18 The original substrate 11 on the fifth bonding wafer is peeled off. The substrate peeling process is the same as step S103 in Example 2. The original 11 on the original third epitaxial wafer is completely peeled off and removed, leaving only the complete epitaxial layer structure. The N-type semiconductor layers of the second light-emitting unit 102 and the third light-emitting unit 103 are exposed to the outside.

[0056] S209. Planarization of the second bonding layer See Figure 19 The dielectric material is filled into the gaps between the light-emitting units on the fifth bonded wafer, and then chemical mechanical polishing is performed until the surface of the N-type semiconductor layer of each light-emitting unit tends to be flush. Alternatively, chemical mechanical polishing can be performed first, and then the dielectric layer is deposited and polished again after the substrate is subsequently peeled off. The specific method can be flexibly adjusted according to the process requirements.

[0057] S210. Substrate replacement bonding See Figure 20The processed fifth bonding sheet is temporarily bonded to the second temporary substrate 25 with its N-type semiconductor layer side to obtain the sixth bonding sheet. The N-type semiconductor layer of all light-emitting units is located on the side closer to the second temporary substrate 25, and the P-type semiconductor layer is located on the side farther away from the second temporary substrate 25.

[0058] S211. Remove the first temporary substrate. See Figure 21 The first temporary substrate 21 on the sixth bonding sheet is peeled off, and the specific process can be referred to S106 in Example 2. After removing the first temporary substrate, the P-type semiconductor layer of all light-emitting units is located on the side away from the second temporary substrate 25, and the N-type semiconductor layer is located on the side closer to the second temporary substrate 25.

[0059] In this embodiment, the process flow is simplified, eliminating the step of separately transferring the temporary substrate to the third light-emitting unit in Embodiment 2. The third epitaxial wafer is directly used for bonding, resulting in fewer steps, faster production cycle, and lower manufacturing cost.

[0060] Since the thickness of the third N-type semiconductor layer 1031 is greater than that of the second N-type semiconductor layer 1021, the bonding pressure is applied only to the third epitaxial wafer during this bonding process. The surface of the second epitaxial wafer is not subjected to pressure load, which can reduce the bonding pressure required, eliminate the problem of insufficient bonding caused by uneven thickness, and improve product yield. By reducing the bonding pressure, the process time can also be shortened and production efficiency improved.

[0061] It is understood that, for Embodiments 2 and 3, before the bonding sheet with the second and third light-emitting units is bonded to the driving substrate, a first epitaxial wafer can be taken separately. After the first light-emitting unit is patterned, it is first bonded to the driving substrate and the original substrate is peeled off to obtain a substrate bonding sheet. Then, the substrate bonding sheet is aligned and bonded to the bonding sheet containing the second and third light-emitting units prepared in Embodiments 2 or 3, so that the second and third light-emitting units are stacked on top of the first light-emitting unit. Then, the substrate containing the bonding sheet containing the second and third light-emitting units is peeled off to obtain a full-color light-emitting device.

[0062] The aforementioned process is a P-side bonding fabrication scheme, where the P-type semiconductor layer is directly bonded to the driving substrate. In addition, this process system is also applicable to N-side bonding structures. During N-side bonding fabrication, the fourth bonding sheet processed in step S110 needs to be temporarily bonded to another temporary substrate with the P-type semiconductor layer end face, completing the structure flipping so that the N-type semiconductor layer faces upwards and the P-type semiconductor layer faces downwards, achieving N-side structure transfer. Subsequently, the original temporary substrate of the fourth bonding sheet is peeled off, and the flipped N-type semiconductor layer is used as the bonding surface to complete bonding with the target driving substrate, ultimately realizing the N-side bonded MicroLED device structure. This invention allows for flexible selection of either P-side or N-side bonding processes based on the MicroLED device's structural design, circuit layout, and packaging process requirements; this embodiment does not specifically limit this selection.

[0063] Understandably, as an alternative, the thickness of functional layers such as ITO and P-type semiconductors above the light-emitting layer can be adjusted. However, it should be noted that uneven thickness of functional layers can easily lead to differences in the optoelectronic performance of the device.

[0064] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for processing an epitaxial wafer, characterized in that, include: A second epitaxial wafer and a third epitaxial wafer with different light colors are selected. The second epitaxial wafer is subjected to a substrate removal process. Then, the second epitaxial wafer and the third epitaxial wafer after the removal process are patterned to prepare a second light-emitting unit and a third light-emitting unit arranged in an array on a temporary substrate. The second light-emitting unit and the third light-emitting unit are located on different temporary substrates. In this case, the original substrate is selectively removed from the third epitaxial wafer or the original substrate is retained before the patterning is performed. The patterned second epitaxial wafer and the third epitaxial wafer are aligned and bonded through a temporary bonding layer to form an integrated bonding structure, so that the second light-emitting unit and the third light-emitting unit are alternately arranged in the lateral direction, and the upper surface of the epitaxial light-emitting layer of the second light-emitting unit and the upper surface of the epitaxial light-emitting layer of the third light-emitting unit are flush. The second light-emitting unit and the third light-emitting unit have a buffer gap at their alignment bonding interface. The buffer gap is configured such that during alignment bonding, the bonding pressure acts on the third light-emitting unit but not on the second light-emitting unit.

2. The method for processing an epitaxial wafer according to claim 1, characterized in that: During alignment bonding, the thickness of the temporary bonding layer on the surface of the third light-emitting unit is greater than the thickness of the temporary bonding layer on the surface of the second light-emitting unit, so as to form the buffer gap; After the alignment bonding is completed, the following is also included: The temporary substrate of the third light-emitting unit is peeled off, and the temporary bonding layer on the surfaces of the second and third light-emitting units is planarized to make the surfaces of the second and third light-emitting units flush.

3. The method for processing an epitaxial wafer according to claim 1, characterized in that: The second epitaxial wafer undergoes a raw substrate removal process, and the removed second epitaxial wafer is then patterned to fabricate a second light-emitting unit arrayed on a temporary substrate, comprising: The second epitaxial wafer is temporarily bonded to the first temporary substrate, and the original substrate of the second epitaxial wafer is peeled off. The second epitaxial wafer after stripping the original substrate is patterned; The patterned second epitaxial wafer is temporarily bonded a second time to the temporary substrate, and the first temporary substrate is peeled off to prepare the second light-emitting unit arrayed on the temporary substrate; Patterning the third epitaxial wafer to fabricate a third light-emitting unit arrayed on a temporary substrate includes: The third epitaxial wafer is temporarily bonded for the first time to the temporary substrate, and the original substrate of the third epitaxial wafer is peeled off. The third epitaxial wafer, after being stripped from the original substrate, is patterned to prepare the third light-emitting unit arranged in an array on the temporary substrate.

4. The method for processing an epitaxial wafer according to claim 1, characterized in that: After the alignment bonding is completed, the integrated bonding structure is sequentially subjected to dielectric filling and chemical mechanical polishing.

5. The method for processing an epitaxial wafer according to claim 2, characterized in that: The thickness difference between the temporary bonding layer on the surface of the second light-emitting unit and the temporary bonding layer on the surface of the third light-emitting unit is 0.03 μm to 3 μm.

6. The method for processing an epitaxial wafer according to claim 1, characterized in that: The thickness of the N-type semiconductor layer of the third epitaxial wafer is greater than that of the N-type semiconductor layer of the second epitaxial wafer. When the second epitaxial wafer and the third epitaxial wafer are aligned and bonded, the N-type semiconductor layer of the second epitaxial wafer and the N-type semiconductor layer of the third epitaxial wafer are located in the same layer and form a height difference at the alignment and bonding interface. The height difference constitutes the buffer gap.

7. The method for processing an epitaxial wafer according to claim 6, characterized in that: The second epitaxial wafer undergoes a raw substrate removal process, and the removed second epitaxial wafer is then patterned to fabricate a second light-emitting unit arrayed on a temporary substrate, comprising: The second epitaxial wafer is temporarily bonded to the first temporary substrate, and the original substrate of the second epitaxial wafer is peeled off. The second epitaxial wafer after the original substrate is stripped is patterned to prepare the second light-emitting unit arrayed on the temporary substrate; Patterning the third epitaxial wafer to fabricate a third light-emitting unit arrayed on a temporary substrate includes: A temporary bonding layer is deposited on the surface of the third epitaxial wafer, and the third epitaxial wafer is patterned to prepare the third light-emitting unit arranged in an array on the temporary substrate.

8. The method for processing an epitaxial wafer according to claim 6, characterized in that: After the alignment bonding is completed, the following is also included: The original substrate corresponding to the third light-emitting unit is stripped off, and the N-type semiconductor layer of the second light-emitting unit and the N-type semiconductor layer of the third light-emitting unit are planarized to make the surfaces of the second light-emitting unit and the third light-emitting unit flush.

9. The method for processing an epitaxial wafer according to claim 8, characterized in that, After flattening, the process also includes: The second and third light-emitting units, after planarization, are flipped and bonded to another temporary substrate through a temporary bonding layer.

10. A MicroLED device, characterized in that, The MicroLED device is fabricated using the epitaxial wafer processing method according to any one of claims 1 to 9, and comprises: A driving substrate and multiple light-emitting pixels arranged in an array; The light-emitting pixel includes at least a second light-emitting unit and a third light-emitting unit with different light-emitting colors. The second light-emitting unit and the third light-emitting unit are patterned from different monochromatic epitaxial wafers and are alternately arranged on the same plane after alignment bonding and stripping of the original substrate. The epitaxial light-emitting layers of the second light-emitting unit and the third light-emitting unit are in the same layer.

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