LED chip with upper and lower layers and preparation method thereof

Abstract

This invention provides a stacked LED chip and its fabrication method. The chip includes a substrate, LED modules, and a connection module. The LED module includes multiple LED units located above the substrate and electrode units fabricated on the LED units. The connection module includes insulating planarization units disposed on all LED units and electrode units, through-hole units disposed on the insulating planarization units, and conductive connection pillar units disposed in the through-hole units. The electrode units pass through the through-hole units and are in contact with the conductive connection pillar units. The stacked LED chip of this invention forms a vertically stacked parallel structure, which can significantly increase the luminous intensity per unit projected area without increasing the chip's bottom area. At the same time, each LED module operates independently, and the failure of one module does not affect other modules, significantly improving overall reliability and light output density.

Description

Technical Field

[0001] This invention relates to the field of LED manufacturing technology, and in particular to a stacked LED chip and its preparation method. Background Technology

[0002] In applications such as micro-displays, high-density backlighting, and visible light communication, the requirements for brightness density of light sources within a limited projected area are constantly increasing. The current mainstream solution is to reduce the size of LED chips and arrange them in a two-dimensional planar array. However, this method is limited by chip spacing and die bonding precision, resulting in a bottleneck in the number of light-emitting units that can be integrated per unit area. At the same time, each chip needs to be electrically connected independently, and the complexity of wiring increases sharply with the number of chips.

[0003] To overcome the limitations of planar arrangement, a technology has emerged that stacks multiple LED chips vertically. This involves connecting the P and N electrodes of the upper and lower chips in series to increase the operating voltage and reduce the drive current, thus matching the high-voltage drive circuit. However, the series structure has inherent drawbacks: failure of any one chip leads to an overall open circuit, and the drive voltage increases exponentially, making it incompatible with general low-voltage constant-current drive systems. Another stacking approach involves directly growing multilayer epitaxial structures to form stacked PN junctions, but this suffers from severe lattice mismatch issues between different wavelengths or materials, resulting in an extremely narrow process window and hindering practical mass production.

[0004] If multiple independent thin-film LED chips can be stacked vertically and electrically connected in parallel, the luminous area can be increased several times over while maintaining the low-voltage, high-current operating characteristics, significantly improving the light output power per unit area. Furthermore, the failure of a single chip does not affect the operation of other chips. However, parallel connection requires the positive and negative electrodes of the upper and lower chips to be connected correspondingly. Traditional chips typically have electrodes located on the same side or opposite surfaces, making direct stacking prone to short circuits. Additionally, challenges such as reliable interlayer interconnection, insulation, and high-precision alignment need to be addressed. Therefore, currently, there is no effective solution that can stably achieve parallel stacking of LED chips. Summary of the Invention In view of the shortcomings of the prior art, the purpose of this invention is to provide an LED chip with stacked layers, which aims to solve the technical problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: A stacked LED chip includes a substrate, an LED module, and a connection module. The LED module includes a plurality of LED units located above the substrate and electrode units fabricated on the LED units. The connection module includes an insulating planarization unit, a through-hole unit disposed on the insulating planarization unit, and a conductive connection post unit disposed in the through-hole unit. The insulating planarization unit covers the top and sides of all LED units except the topmost LED unit and all electrode units except the topmost electrode unit, and the insulating planarization unit also covers the sides of the topmost LED unit and the topmost electrode unit. The electrode units pass through the through-hole units and are in contact with the conductive connection post units.

[0006] According to one aspect of the above technical solution, a transparent bonding layer is provided between the substrate and the LED unit.

[0007] According to one aspect of the above technical solution, the LED unit includes a first LED unit disposed on the transparent bonding layer. The first LED unit includes, from bottom to top, a first P-type semiconductor layer, a first active layer, and a first N-type semiconductor layer. The electrode unit includes a first P-electrode disposed on the first P-type semiconductor layer and a first N-electrode disposed on the first N-type semiconductor layer. The insulation planarization unit includes a first insulation planarization layer, which covers the upper surface and sidewalls of the first LED unit, the first P-electrode, and the first N-electrode.

[0008] According to one aspect of the above technical solution, a first DBR layer and a first PV protective layer are sequentially disposed above the first N-type semiconductor layer, and the first PV protective layer is located below the first insulating planarization layer.

[0009] According to one aspect of the above technical solution, the LED unit further includes a second LED unit disposed above the first insulating planarization layer. The second LED unit includes, from bottom to top, a second N-type semiconductor layer, a second active layer, and a second P-type semiconductor layer. The electrode unit further includes a second P electrode disposed on the second P-type semiconductor layer and a second N electrode disposed on the second N-type semiconductor layer. A second DBR layer is disposed between the first insulating planarization layer and the second N-type semiconductor layer, and a second PV protective layer is disposed above the second P-type semiconductor layer.

[0010] According to one aspect of the above technical solution, the insulation planarization unit further includes a second insulation planarization layer, which covers the sidewalls of the second LED unit, the second P electrode, and the second N electrode.

[0011] According to one aspect of the above technical solution, the insulation planarization unit further includes a second insulation planarization layer, which covers the upper surface and sidewalls of the second LED unit, the second P electrode, and the second N electrode.

[0012] According to one aspect of the above technical solution, the LED unit further includes a third LED unit disposed above the second insulating planarization layer. The third LED unit includes, from bottom to top, a third N-type semiconductor layer, a third active layer, and a third P-type semiconductor layer. The electrode unit further includes a third P electrode disposed on the third P-type semiconductor layer and a third N electrode disposed on the third N-type semiconductor layer. A third DBR layer is disposed between the second insulating planarization layer and the third N-type semiconductor layer. A third PV protective layer is disposed above the third P-type semiconductor layer. The insulating planarization unit further includes a third insulating planarization layer, which covers the sidewalls of the third LED unit, the third P electrode, and the third N electrode.

[0013] According to one aspect of the above technical solution, the through-hole unit includes a first through-hole and a second through-hole that penetrate the insulating planarization unit, and the conductive connection post unit includes a P-type conductive post disposed in the first through-hole and an N-type conductive post disposed in the second through-hole. The lower ends of the P-type conductive post and the N-type conductive post are both connected to the transparent bonding layer. The P-type conductive post is connected to each P electrode in the electrode unit, and the N-type conductive post is connected to each N electrode in the electrode unit.

[0014] The present invention also provides a method for fabricating LED chips with stacked layers, comprising the following steps: A plurality of LED units are provided, and an electrode unit is fabricated on each of the LED units; An insulating planarization unit is fabricated on all LED units, and a through-hole unit is formed on the insulating planarization unit, with the electrode unit passing through the through-hole unit; The through-hole unit is filled with conductive material to form a conductive connection post unit, which is then connected to the electrode unit to connect multiple LED units in parallel. The LED units connected in parallel are fixed to the substrate.

[0015] The present invention also provides a method for fabricating LED chips with stacked layers, comprising the following steps: A plurality of LED units are provided, and an electrode unit is fabricated on each of the LED units; Insulating planarization units are fabricated on all LED units and electrode units, and through-hole units are formed on the insulating planarization units, with the electrode units passing through the through-hole units; The through-hole unit is filled with conductive material to form a conductive connection post unit, which is then connected to the electrode unit to connect multiple LED units in parallel. The LED units connected in parallel are fixed to the substrate.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: By setting multiple LED units and electrode units on each LED unit, then setting insulating planarization units between adjacent LED units, and setting via units on the insulating planarization units, conductive connection pillar units are formed in the via units. The insulating planarization units and conductive connection pillar units are used to realize the P-P connection and N-N connection of the electrodes on each LED unit, and a vertical parallel structure is successfully constructed. This doubles the light output of the chip per unit area, while maintaining low voltage drive (comparable to the working voltage of a single LED unit), and is perfectly compatible with existing low voltage constant current drive solutions. LED units are independently manufactured thin-film chips that can freely select the same or different emission wavelengths. By mixing and superimposing them, white light or a specific spectrum can be achieved. In parallel mode, even if a single unit fails, the remaining units can still work normally, which greatly improves the overall reliability. The fabrication method provided by this invention can be implemented based on wafer-level processes, such as temporary bonding, planarization, electroplating vias, wafer-to-wafer (W2W) or chip-to-wafer (C2W) flip-chip bonding, etc., which have the advantages of high precision, high capacity and low cost, and are conducive to large-scale mass production. The insulation planarization unit serves the functions of interlayer insulation, planarization, and structural support, avoiding welding defects or short circuits caused by electrode height differences, and ensuring the mechanical stability and electrical interconnection yield of the laminated structure. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the stacked LED chips in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the stacked LED chips in the second embodiment of the present invention; Figure 3 This is a flowchart illustrating the method for fabricating stacked LED chips according to the second embodiment of the present invention. Explanation of key component symbols:

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Please see Figure 1 The image shows a stacked LED chip according to a first embodiment of the present invention, comprising a substrate 10, an LED module, and a connection module. The LED module includes a plurality of LED units located above the substrate 10 and electrode units fabricated on the LED units. The connection module includes an insulating planarization unit, a through-hole unit disposed on the insulating planarization unit, and a conductive connection post unit disposed in the through-hole unit. The insulating planarization unit covers the top and sides of all LED units except the topmost LED unit and all electrode units except the topmost electrode unit, and the insulating planarization unit also covers the sides of the topmost LED unit and the topmost electrode unit. The electrode units pass through the through-hole units and are in contact with the conductive connection post units.

[0023] Understandably, this invention sets up multiple LED units, with electrode units on each LED unit, and then sets up insulating planarization units between adjacent LED units, and through-hole units on the insulating planarization units, so that conductive connection pillar units are formed in the through-hole units. By using the insulating planarization units and conductive connection pillar units, the P-P connection and N-N connection of the electrodes on each LED unit are realized, and a vertical parallel structure is successfully constructed, which doubles the light output of the chip per unit area, while maintaining low voltage drive (comparable to the working voltage of a single LED unit), and is perfectly compatible with existing low-voltage constant current drive schemes. LED units are independently manufactured thin-film chips that can freely select the same or different emission wavelengths. By mixing and superimposing them, white light or a specific spectrum can be achieved. In parallel mode, even if a single unit fails, the remaining units can still work normally, which greatly improves the overall reliability. The fabrication method provided by this invention can be implemented based on wafer-level processes, such as temporary bonding, planarization, electroplating vias, wafer-to-wafer (W2W) or chip-to-wafer (C2W) flip-chip bonding, etc., which have the advantages of high precision, high capacity and low cost, and are conducive to large-scale mass production. The insulation planarization unit simultaneously serves as interlayer insulation, planarization, and structural support, preventing welding defects or short circuits caused by electrode height differences, and ensuring the mechanical stability and electrical interconnection yield of the laminated structure.

[0024] Furthermore, in this embodiment, a transparent bonding layer 20 is provided between the substrate 10 and the LED unit. The LED unit includes a first LED unit disposed on the transparent bonding layer 20. The first LED unit includes, from bottom to top, a first P-type semiconductor layer 30, a first active layer 31, and a first N-type semiconductor layer 32. The electrode unit includes a first P-electrode 33 disposed on the first P-type semiconductor layer 30 and a first N-electrode 34 disposed on the first N-type semiconductor layer 32. The insulating planarization unit includes a first insulating planarization layer 40, which covers the upper surface and sidewalls of the first LED unit, the first P-electrode 33, and the first N-electrode 34. A first DBR layer 35 and a first PV protective layer 36 are disposed sequentially above the first N-type semiconductor layer 32, and the first PV protective layer 36 is located below the first insulating planarization layer 40.

[0025] Understandably, substrate 10 is a permanent carrier substrate, made of double-sided polished sapphire or quartz glass, possessing high light transmittance and good thermal conductivity. The first LED unit is a thin-film flip-chip LED with the native substrate removed, consisting of a first P-type semiconductor layer 30, a first active layer 31, and a first N-type semiconductor layer 32 from bottom to top. The first P-type semiconductor layer 30 is p-GaN, the first active layer 31 is an InGaN / GaN multi-quantum-well structure, and the first N-type semiconductor layer 32 is n-GaN. The lower surface of the first P-type semiconductor layer 30 is fixed to the permanent carrier substrate 10 by a transparent bonding layer 20, which is a silicon dioxide-based bonding adhesive or spin-coated glass SOG. On the upper surface of the first P-type semiconductor layer 30, a first P-electrode 33 is formed by deposition and photolithography. On the upper surface of the first N-type semiconductor layer 32, a first N-electrode 34 is formed by deposition and photolithography. The first P-electrode 33 and the first N-electrode 34 are arranged alternately to balance current expansion and light-emitting area. The DBR layer is a distributed Bragg reflector, which can improve the light extraction efficiency of the LED unit and prevent optical crosstalk. The PV protective layer can achieve electrical insulation and short circuit protection. The subsequent DBR layer and PV protective layer have the same function.

[0026] The first insulating planarization layer 40 is made of photosensitive benzocyclobutene (BCB) or polyimide material with excellent insulation and planarization capabilities. It is spin-coated to cover the entire upper surface and sidewalls of the first LED unit, the first P electrode 33 and the first N electrode 34. After photolithography and thermal curing, a smooth plane with a thickness of about 2~5μm is formed. A portion of the first P electrode 33 and the first N electrode 34 penetrates from the side of the first insulating planarization layer 40 and is embedded in the first insulating planarization layer 40 to prepare for subsequent connection with the conductive connection pillar unit.

[0027] Furthermore, the LED unit also includes a second LED unit disposed above the first insulating planarization layer 40. The second LED unit includes, from bottom to top, a second N-type semiconductor layer 51, a second active layer 52, and a second P-type semiconductor layer 53. The electrode unit also includes a second P-electrode 54 disposed on the second P-type semiconductor layer 53 and a second N-electrode 55 disposed on the second N-type semiconductor layer 51. A second DBR layer 56 is disposed between the first insulating planarization layer 40 and the second N-type semiconductor layer 51. A second PV protective layer 57 is disposed above the second P-type semiconductor layer 53. The insulating planarization unit also includes a second insulating planarization layer 60, which covers the sidewalls of the second LED unit, the second P-electrode 54, and the second N-electrode 55.

[0028] Understandably, the second LED unit is also a thin-film LED with the growth substrate removed, but its semiconductor arrangement direction is opposite to that of the first LED unit. From bottom to top, it includes a second N-type semiconductor layer 51, a second active layer 52, and a second P-type semiconductor layer 53. Similarly, the second N-type semiconductor layer 51 is n-GaN, the second active layer 52 is an InGaN / GaN multi-quantum-well structure, and the second P-type semiconductor layer 53 is p-GaN.

[0029] The second insulating planarization layer 60 is also made of photosensitive benzocyclobutene (BCB) or polyimide material with excellent insulation and planarization capabilities. It is spin-coated to cover the entire sidewall of the second LED unit, the second P electrode 54 and the second N electrode 55. After photolithography and thermal curing, a smooth plane with a thickness of about 2~5μm is formed. A part of the second P electrode 54 and the second N electrode 55 penetrates from the side of the second insulating planarization layer 60 and is embedded in the second insulating planarization layer 60 to prepare for subsequent connection with the conductive connection pillar unit.

[0030] Furthermore, the via unit includes a first via and a second via that penetrate the insulating planarization unit, and the conductive connection post unit includes a P-type conductive post 70 disposed in the first via and an N-type conductive post 71 disposed in the second via. The lower ends of the P-type conductive post 70 and the N-type conductive post 71 are both connected to the transparent bonding layer 20. The P-type conductive post 70 is connected to each P electrode in the electrode unit, and the N-type conductive post 71 is connected to each N electrode in the electrode unit.

[0031] Understandably, in this embodiment, the P electrode on each LED unit is located on the left side of the epitaxial layer, and the N electrode is located on the right side of the epitaxial layer. Therefore, the P-type conductive pillar 70 is located in the first through hole on the left side, and the N-type conductive pillar 71 is located in the second through hole on the right side. The conductive pillar is formed by electroplating copper or chemically depositing nickel-gold into the first and second through holes. In this way, during the formation of the conductive pillar, it will naturally come into contact with the electrode pre-embedded in the through hole to achieve connection.

[0032] It should be noted that if the LED chip prepared by this embodiment is ultimately used as a conventional structure, a PAD needs to be placed at the top of the conductive pillar. If it is ultimately used as a flip structure, the bottom of the conductive pillar needs to penetrate the transparent bonding layer 20, and a PAD needs to be placed at the bottom of the conductive pillar.

[0033] The above structure enables the LED chips to form a stacked parallel structure in the vertical direction, which can multiply the luminous intensity per unit projected area without increasing the chip bottom area. At the same time, each LED module works independently, and the failure of one module does not affect the other modules, significantly improving the overall reliability and light output density.

[0034] Please see Figure 2 The image shows a stacked LED chip in the second embodiment of the present invention, which is designed based on the stacked LED chip in the first embodiment.

[0035] Specifically, the insulating planarization unit further includes a second insulating planarization layer 60, which covers the upper surface and sidewalls of the second LED unit, the second P electrode 54, and the second N electrode 55. The LED unit further includes a third LED unit disposed above the second insulating planarization layer 60. The third LED unit includes, from bottom to top, a third N-type semiconductor layer 80, a third active layer 81, and a third P-type semiconductor layer 82. The electrode unit further includes a third P electrode 83 disposed on the third P-type semiconductor layer 82 and a third N electrode 84 disposed on the third N-type semiconductor layer 80. A third DBR layer 85 is disposed between the second insulating planarization layer 60 and the third N-type semiconductor layer 80. A third PV protective layer 86 is disposed above the third P-type semiconductor layer 82.

[0036] Understandably, in the second embodiment, the second insulating planarization layer 60 no longer only covers the side of the second LED unit, but, like the first insulating planarization layer 40, covers the entire upper surface and sidewall of the second LED unit, the second P electrode 54, and the second N electrode 55, and then the third LED unit is disposed above the second insulating planarization layer 60. The third LED unit is also a thin-film LED with the growth substrate removed, but its semiconductor arrangement direction is opposite to that of the first LED unit. From bottom to top, it includes a third N-type semiconductor layer 80, a third active layer 81, and a third P-type semiconductor layer 82. Similarly, the third N-type semiconductor layer 80 is n-GaN, the third active layer 81 is an InGaN / GaN multiple quantum well structure, and the third P-type semiconductor layer 82 is p-GaN.

[0037] It should be noted that, except for the bottom LED unit which adopts a flip-chip structure (i.e., from bottom to top, it is a P-type semiconductor layer-active layer-N-type semiconductor layer), the rest of the LED units adopt a standard-chip structure (i.e., from bottom to top, it is an N-type semiconductor layer-active layer-P-type semiconductor layer).

[0038] Furthermore, the insulation planarization unit also includes a third insulation planarization layer 90, which covers the sidewalls of the third LED unit, the third P electrode 83, and the third N electrode 84.

[0039] Understandably, the second insulating planarization layer 60 is also made of photosensitive benzocyclobutene (BCB) or polyimide material with excellent insulation and planarization capabilities. It is spin-coated to cover the entire sidewall of the third LED unit, the third P electrode 83 and the third N electrode 84. After photolithography and thermal curing, a smooth plane with a thickness of about 2~5μm is formed. A portion of the third P electrode 83 and the third N electrode 84 penetrates from the side of the third insulating planarization layer 90 and is embedded in the third insulating planarization layer 90 to prepare for subsequent connection with the conductive connection pillar unit.

[0040] Finally, as in the first embodiment, through holes are made in each insulating planarization layer, and conductive pillars are prepared in the through holes so that the conductive pillars make contact with all electrodes. Then, the prepared structure is transferred to the substrate 10.

[0041] In other embodiments, new LED units can be stacked on the third LED unit according to specific needs, following the manner in the first and second embodiments.

[0042] Each LED unit can use the same blue light chip to obtain an ultra-high brightness blue light source, or it can achieve white light emission by stacking blue, green, and red chips and using parallel driving with fine-tuning resistors, which is suitable for scenarios such as miniature projectors or augmented reality glasses. To ensure parallel current sharing, the forward voltage difference between the selected units at the same current density is controlled within 0.2V.

[0043] Please see Figure 3 The third embodiment of the present invention provides a method for fabricating an LED chip with stacked upper and lower layers, comprising the following steps: S10, providing multiple LED units, and fabricating electrode units on each LED unit; Each LED unit is prefabricated, and each LED unit has prefabricated electrode units. S20, an insulating planarization unit is prepared on all LED units and electrode units, and a through-hole unit is opened on the insulating planarization unit, and the electrode unit is disposed in the through-hole unit; Following the order of the LED units, for each LED unit fabricated, an insulating planarization unit is set on that LED unit. Then another LED unit is superimposed on the insulating planarization unit, and so on. The topmost LED unit and electrode unit only have insulating planarization units fabricated on the side. S30, fill the through hole unit with conductive material to form a conductive connection post unit, and connect the conductive connection post unit with the electrode unit to connect multiple LED units in parallel; Through-hole units are fabricated on all insulating planarization units, and conductive connection pillar units are fabricated within the through-hole units, so that the conductive connection pillar units are connected to the electrode units; S40, fix the parallel LED units to the substrate.

[0044] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0045] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A stacked LED chip, characterized in that, The device includes a substrate, an LED module, and a connection module. The LED module includes multiple LED units located above the substrate and electrode units fabricated on the LED units. The connection module includes an insulating planarization unit, a through-hole unit disposed on the insulating planarization unit, and a conductive connection post unit disposed in the through-hole unit. The insulating planarization unit covers the top and sides of all LED units except the topmost LED unit and all electrode units except the topmost electrode unit. The insulating planarization unit also covers the sides of the topmost LED unit and the topmost electrode unit. The electrode units pass through the through-hole unit and are in contact with the conductive connection post unit.

2. The LED chip with stacked layers according to claim 1, characterized in that, A transparent bonding layer is provided between the substrate and the LED unit.

3. The stacked LED chip according to claim 2, characterized in that, The LED unit includes a first LED unit disposed on the transparent bonding layer. The first LED unit includes, from bottom to top, a first P-type semiconductor layer, a first active layer, and a first N-type semiconductor layer. The electrode unit includes a first P-electrode disposed on the first P-type semiconductor layer and a first N-electrode disposed on the first N-type semiconductor layer. The insulation planarization unit includes a first insulation planarization layer, which covers the upper surface and sidewalls of the first LED unit, the first P-electrode, and the first N-electrode.

4. The stacked LED chip according to claim 3, characterized in that, A first DBR layer and a first PV protective layer are sequentially disposed above the first N-type semiconductor layer, with the first PV protective layer located below the first insulating planarization layer.

5. The stacked LED chip according to claim 3, characterized in that, The LED unit further includes a second LED unit disposed above the first insulating planarization layer. The second LED unit includes, from bottom to top, a second N-type semiconductor layer, a second active layer, and a second P-type semiconductor layer. The electrode unit further includes a second P electrode disposed on the second P-type semiconductor layer and a second N electrode disposed on the second N-type semiconductor layer. A second DBR layer is disposed between the first insulating planarization layer and the second N-type semiconductor layer, and a second PV protective layer is disposed above the second P-type semiconductor layer.

6. The stacked LED chip according to claim 5, characterized in that, The insulation planarization unit further includes a second insulation planarization layer, which covers the sidewalls of the second LED unit, the second P electrode, and the second N electrode.

7. The stacked LED chip according to claim 5, characterized in that, The insulation planarization unit further includes a second insulation planarization layer, which covers the upper surface and sidewalls of the second LED unit, the second P electrode, and the second N electrode.

8. The stacked LED chip according to claim 7, characterized in that, The LED unit further includes a third LED unit disposed above the second insulating planarization layer. The third LED unit includes, from bottom to top, a third N-type semiconductor layer, a third active layer, and a third P-type semiconductor layer. The electrode unit further includes a third P electrode disposed on the third P-type semiconductor layer and a third N electrode disposed on the third N-type semiconductor layer. A third DBR layer is disposed between the second insulating planarization layer and the third N-type semiconductor layer. A third PV protective layer is disposed above the third P-type semiconductor layer. The insulating planarization unit further includes a third insulating planarization layer, which covers the sidewalls of the third LED unit, the third P electrode, and the third N electrode.

9. The stacked LED chip according to claim 2, characterized in that, The via unit includes a first via and a second via that penetrate the insulating planarization unit. The conductive connection post unit includes a P-type conductive post disposed in the first via and an N-type conductive post disposed in the second via. The lower ends of the P-type conductive post and the N-type conductive post are both connected to the transparent bonding layer. The P-type conductive post is connected to each P electrode in the electrode unit, and the N-type conductive post is connected to each N electrode in the electrode unit.

10. A method for fabricating LED chips stacked in layers, characterized in that, Includes the following steps: A plurality of LED units are provided, and an electrode unit is fabricated on each of the LED units; Insulating planarization units are fabricated on all LED units and electrode units, and through-hole units are formed on the insulating planarization units, with the electrode units passing through the through-hole units; The through-hole unit is filled with conductive material to form a conductive connection post unit, which is then connected to the electrode unit to connect multiple LED units in parallel. The LED units connected in parallel are fixed to the substrate.

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