Method of manufacturing a display device

Abstract

A method of manufacturing a display device includes: applying an active layer on a portion of a base substrate in a display region, the base substrate defining the display region and a pad region; applying a gate electrode overlapping the active layer in the display region and applying a bottom pad in the pad region; applying a contact electrode connected to the active layer in the display region and applying a first pad connected to the bottom pad in the pad region; applying a via insulating layer covering the contact electrode; applying a via electrode through the via insulating layer connected to the contact electrode and a second pad connected to the first pad; partially etching an upper portion of the first pad or an upper portion of the second pad while etching the via insulating layer in the pad region; and applying a light-emitting element electrically connected to the via electrode.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices, methods of manufacturing display devices, and electronic devices including display devices. For example, embodiments of this disclosure relate to display devices including connecting electrodes and pads, methods of manufacturing display devices, and electronic devices including display devices. Background Technology

[0002] Display devices, such as organic light-emitting diode (OLED) display devices and / or liquid crystal display (LCD) devices, may include a display substrate comprising thin-film transistors (TFTs) and one or more suitable wirings. Display structures, including electrodes and an emission layer, may be formed on the display substrate.

[0003] Electrodes may include wiring and contact electrodes that electrically connect the transistor structure to the display structure. Additionally, electrodes may include pads for applying signals to the display structure.

[0004] When forming pads, additional etching processes may be performed, which may cause physical and / or chemical damage to the pads.

[0005] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure and may contain information that does not constitute prior art. Summary of the Invention

[0006] One or more embodiments of this disclosure relate to a display device having improved electrical characteristics and structural reliability.

[0007] One or more embodiments of this disclosure relate to a method of manufacturing a display device having improved electrical characteristics and structural reliability.

[0008] One or more embodiments of this disclosure relate to electronic devices including display devices with improved electrical characteristics and structural reliability.

[0009] Additional aspects will be set forth in part in the description below, and in part highlighted from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0010] According to one or more embodiments of this disclosure, a method of manufacturing a display device includes: forming (e.g., applying) an active layer on a portion of a base substrate in a display region, wherein the base substrate includes (e.g., defining) a display region and a pad region; forming (e.g., applying) a gate electrode overlapping the active layer in the display region, and forming (e.g., applying) a bottom pad on a portion of the base substrate in the pad region; forming (e.g., applying) a contact electrode connected to the active layer in the display region, and forming (e.g., applying) a first pad connected to the bottom pad in the pad region; forming (e.g., applying) a via insulating layer covering the contact electrode; forming (e.g., applying) a via electrode connected to the contact electrode through the via insulating layer in the display region, and forming (e.g., applying) a second pad connected to the first pad in the pad region; partially etching an upper portion of the first pad or an upper portion of the second pad while etching the via insulating layer in the pad region; and forming a light-emitting element electrically connected to the via electrode.

[0011] In one or more embodiments, forming (e.g., applying) a via insulating layer may include: forming (e.g., applying) a first via insulating layer covering a contact electrode; forming (e.g., applying) a second via insulating layer on the first via insulating layer; and forming (e.g., applying) a third via insulating layer on the second via insulating layer. Forming (e.g., applying) a via electrode may include: forming (e.g., applying) a first via electrode that penetrates (extends through) the first via insulating layer and is connected to a contact electrode; and forming (e.g., applying) a second via electrode that penetrates (extends through) the second via insulating layer and is connected to the first via electrode.

[0012] In one or more embodiments, forming (e.g., applying) a second via electrode may include forming (e.g., applying) a third conductive layer on the second via insulating layer to cover the second pad in the pad region.

[0013] In one or more embodiments, the method may further include partially etching the upper portion of the second pad while etching a portion of the third conductive layer in the pad region.

[0014] In one or more embodiments, the second pad may have a structure in which a first metal layer, a second metal layer, and a third metal layer are stacked sequentially. Partially etching the upper portion of the second pad while etching a portion of the third conductive layer may include etching the third metal layer of the second pad.

[0015] In one or more embodiments, partially etching the upper portion of the first pad or the upper portion of the second pad while etching the via insulating layer can include etching the second metal layer of the second pad while etching the third via insulating layer in the pad region.

[0016] In one or more embodiments, the third metal layer of the second pad may include titanium (Ti). The second metal layer of the second pad may include aluminum (Al).

[0017] In one or more embodiments, forming (e.g., applying) a first via electrode may include forming (e.g., applying) a second conductive layer on the first via insulating layer to cover the first pad in the pad region.

[0018] In one or more embodiments, the method may further include partially etching the upper portion of the first pad while etching a portion of the second conductive layer in the pad region.

[0019] In one or more embodiments, the first pad may have a structure in which a first metal layer, a second metal layer, and a third metal layer are stacked sequentially. Partially etching the upper portion of the first pad while etching a portion of the second conductive layer may include etching the third metal layer of the first pad.

[0020] In one or more embodiments, partially etching the upper portion of the first pad or the upper portion of the second pad while etching the via insulating layer can include etching the second metal layer of the first pad while etching the second via insulating layer in the pad region.

[0021] In one or more embodiments, the third metal layer of the first pad may include titanium (Ti). The second metal layer of the first pad may include aluminum (Al).

[0022] In one or more embodiments, the method may further include: forming (e.g., applying) a bottom metal layer on a portion of the base substrate in the display area prior to forming (e.g., applying) an active layer; and forming (e.g., applying) a bottom contact portion connected to the bottom metal layer prior to forming (e.g., applying) a via insulating layer.

[0023] In one or more embodiments, the first pad may be formed (e.g., applied) together with the bottom contact portion.

[0024] In one or more embodiments, the through-hole insulating layer may include an organic polymer material.

[0025] According to one or more embodiments of this disclosure, a display device includes: a base substrate including (e.g., defining) a display area and a pad area; a transistor structure disposed on the base substrate of the display area; a through-hole electrode connected to the transistor structure; a light-emitting element electrically connected to the transistor structure through the through-hole electrode; and a pad disposed on the base substrate of the pad area, having a structure of sequentially stacked bottom pad, first pad, and second pad. The second pad partially contacts the upper portion of the first pad, and the second pad has fewer stacked layers or a smaller thickness than the first pad, or the second pad may have more stacked layers or a larger thickness than the first pad (e.g., the second pad has a different number of stacked layers than the first pad and / or a different thickness than the first pad, and the second pad partially contacts the upper portion of the first pad when the number of stacked layers of the second pad is less than the number of stacked layers of the first pad and / or the thickness of the second pad is less than the thickness of the first pad).

[0026] In one or more embodiments, the number of stacked layers or the thickness of the second pad may be greater than the number of stacked layers or the thickness of the first pad, and the second pad may completely cover the upper portion and side surface of the first pad (e.g., it may cover the entire upper portion and side surface of the first pad).

[0027] In one or more embodiments, the via electrode may include a contact portion and a wiring portion connected to the upper portion of the contact portion, and the number or thickness of one of the first pads or the second pads may be less than the number or thickness of the wiring portion.

[0028] According to one or more embodiments, an electronic device includes a display device, a memory device, and a processor configured to control the operation of the display device by executing data included in the memory device. The display device may include: a base substrate including (e.g., defining) a display area and a pad area; a transistor structure disposed on the base substrate in the display area; a through-hole electrode connected to the transistor structure; a light-emitting element electrically connected to the transistor structure via the through-hole electrode; and pads disposed on the base substrate in the pad area, having a structure of sequentially stacked bottom pads, first pads, and second pads. The second pad partially contacts an upper portion of the first pad, and the second pad has fewer stacked layers or a smaller thickness than the first pad, or the second pad may have more stacked layers or a larger thickness than the first pad (e.g., the second pad has a different number of stacked layers than the first pad and / or a different thickness than the first pad, and the second pad partially contacts the upper portion of the first pad when the number of stacked layers of the second pad is less than the number of stacked layers of the first pad and / or the thickness of the second pad is less than the thickness of the first pad).

[0029] In one or more embodiments, the electronic device may include virtual reality glasses, augmented reality glasses, smartphones, tablet PCs, laptop computers, TVs, desktop monitors, smart glasses, head-mounted displays, smartwatches, or vehicle displays.

[0030] According to one or more embodiments of this disclosure, pads with a multilayer structure can be formed by using a process for forming contact electrodes or via electrodes for forming display areas and an etching process for an insulating layer. Therefore, pads with a multilayer structure can be formed without additional etching processes.

[0031] According to one or more embodiments of this disclosure, damage to the bottom pads and excessive step height or thickness increases can be prevented or reduced, and physically and chemically stable pads can be formed. For example, portions or layers of the pads can be etched during an etching process used to form contacts or vias and / or contact electrodes or via electrodes in the display area. This allows for a reduction in pad thickness without additional etching processes, and the reduction in pad thickness reduces the likelihood of cracking and / or damage to the bottom pads, thereby improving the structural reliability of the display device. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings: Figure 1 This is a schematic plan view showing the pixel arrangement of a display device according to one or more embodiments of the present disclosure.

[0033] Figure 2 This is a schematic cross-sectional view showing a display device according to one or more embodiments of the present disclosure.

[0034] Figures 3 to 19 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0035] Figure 20 This is an enlarged partial cross-sectional view showing the stacked structure of contact electrodes and through-hole electrodes of a display device according to one or more embodiments of the present disclosure.

[0036] Figures 21 to 24 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0037] Figure 25 This is a schematic cross-sectional view showing a display device according to one or more embodiments of the present disclosure.

[0038] Figures 26 to 32 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0039] Figures 33 to 35 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0040] Figure 36 This is a schematic cross-sectional view showing a display device according to one or more embodiments of the present disclosure.

[0041] Figure 37 This is a schematic cross-sectional view showing a display device according to one or more embodiments of the present disclosure.

[0042] Figure 38 This is an equivalent circuit diagram of a display device according to one or more embodiments of the present disclosure.

[0043] Figure 39 This is a block diagram illustrating an electronic device according to one or more embodiments of the present disclosure.

[0044] Figure 40 Various embodiments according to this disclosure are illustrated. Figure 39 A schematic diagram of the electronic device. Detailed Implementation

[0045] This disclosure can be modified in many alternative forms, and therefore specific embodiments will be shown and described in more detail in the accompanying drawings. However, it should be understood that this is not intended to limit this disclosure to the specific forms disclosed, but rather to cover all modifications, equivalents, and substitutions that fall within the spirit and scope of this disclosure.

[0046] In the following description, exemplary embodiments will be described in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described.

[0047] Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, their repeated descriptions may be omitted.

[0048] It will be understood that when an element, such as a region, layer, membrane, area, or portion, is referred to as being “on,” “connected to,” or “attached to” another element, it can be directly on, directly connected to, or directly attached to the other element, or one or more intervening elements may be present. Conversely, when an element or layer is referred to as being “directly” on, directly connected to, directly attached to, or “adjacent to” another element or layer, no intervening element or layer is present. Furthermore, it will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may be present.

[0049] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0050] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated (e.g., including length, width, and thickness).

[0051] For ease of explanation, spatially relative terms such as “above,” “below,” “lower,” “under,” “above,” and “upper” may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s) or another element(s). It will be understood that, in addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary terms “below” and “under” can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein should be interpreted accordingly.

[0052] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that when the terms “comprises,” “comprising,” “includes,” “including,” “have,” “having,” “contain,” and “containing” are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprise(s) / comprising,” “include(s) / including,” “have / has / having,” “contain / containing,” or similar terms include or support the terms “composed of,” and “substantially composed of,” indicating the presence of the stated features, integrals, steps, operations, elements, and / or components, while other features, integrals, steps, operations, elements, components, and / or groups thereof are absent or substantially absent.

[0053] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. Unless otherwise expressly stated in this disclosure, when expressions such as “at least one of…”, “multiples,” “one of…” and other prepositional phrases precede a list of elements, if written as a parallel list, they should be understood to include a disjunctive relation, and vice versa. For example, expressions “at least one of a, b, and c,” “at least one of a, b, and / or c,” “choose one of the group consisting of a, b, and c,” “choose at least one of a, b, and c,” “at least one of a, b, and c,” “one of a, b, and c,” “at least one of a to c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all or variations thereof of a, b, and c.

[0054] As used in this article, the terms “use,” “using,” and “used” can be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0055] Figure 1 This is a schematic plan view showing the pixel arrangement of a display device according to one or more embodiments of the present disclosure.

[0056] exist Figure 1 In this context, the first direction and the second direction may refer to being orthogonal to each other (e.g., perpendicular) and parallel to the base substrate 100 (e.g., see [reference]). Figure 2 The two directions of the upper surface of the display device or the display surface of the display device. For example, the first direction may correspond to the X direction (row direction) of the display device, and the second direction may correspond to the Y direction (column direction) of the display device.

[0057] The third direction can be orthogonal (e.g., perpendicular) to the first and second directions. The third direction can correspond to the Z-direction (thickness direction) of the display device.

[0058] refer to Figure 1 Multiple pixels PX11 to PXnm can be arranged in the display area DA of the display device or the base substrate 100 (e.g., the display device and / or the base substrate can be referred to as defining the display area DA), where m and n are integers greater than 1.

[0059] According to one or more embodiments, pixel circuitry comprising scan lines (or gate lines) SL1 to SLn forming first to nth rows and data lines DL1 to DLm forming first to mth columns can be arranged on a base substrate 100. Each of pixels PX11 to PXnm can be connected to a corresponding first to nth row scan line among the plurality of scan lines SL1 to SLn, and connected to a corresponding first to mth column data line among the plurality of data lines DL1 to DLm.

[0060] For example, scan lines SL1 to SLn can be connected to the gate electrode included in a thin-film transistor (TFT). Data lines DL1 to DLm can be connected to contact electrodes (e.g., first contact electrode CNT1 or third contact electrode CNT3) that are configured as source electrodes.

[0061] Each of pixels PX11 to PXnm may include pixel circuitry comprising transistor structures and light-emitting elements, as will be described in more detail later. In one or more embodiments, the pixel circuitry may also include wiring such as power lines and ground lines.

[0062] exist Figure 1 In the diagram, data lines DL1 to DLm are shown extending in the second direction, and scan lines SL1 to SLn are shown extending in the first direction, but data lines DL1 to DLm and scan lines SL1 to SLn are not necessarily limited to these.

[0063] The peripheral circuitry PC can be located in the non-display area NDA of the display device. For example, the peripheral circuitry PC may include gate drive circuitry. The gate drive circuitry can be integrated into the display device using oxide silicon gate (OSG), amorphous silicon gate (ASG), or polysilicon gate (PSG) drive circuitry processes.

[0064] The display device may also include a printed circuit board 200. The pads 190 of the pixel circuitry (e.g., data lines DL1 to DLm) may be clustered on one side of the non-display area NDA. The non-display area NDA may include a pad area PDA (e.g., see...). Figure 2 Furthermore, pad 190 can be arranged in the pad area of ​​the PDA.

[0065] The printed circuit board 200 can be electrically connected to the pixel circuit via pads 190. For example, the printed circuit board 200 can be electrically connected to the pads 190 via a thermocompression process using a conductive intermediate structure such as an anisotropic conductive film (ACF).

[0066] The printed circuit board 200, pads 190, and driver circuit device IC can be electrically connected. The driver circuit device IC may include an integrated circuit chip. In one or more embodiments, the integrated circuit chip may be mounted on the printed circuit board 200 in a chip-on-film (COF) configuration.

[0067] The driver circuit device IC may include driver circuitry for a display device and driver circuitry for an electronic device (e.g., an application processor (AP) chip). The driver circuit device IC may also include a circuit board (such as a motherboard) on which the chip including the driver circuitry is mounted.

[0068] Figure 2 This is a schematic cross-sectional view showing a display device according to one or more embodiments of the present disclosure.

[0069] refer to Figure 2 The display device or base substrate 100 may include a display area DA and a pad area PDA (e.g., the display device and / or base substrate 100 may be referred to as defining the display area DA and the pad area PDA). See reference... Figure 1 As described, the pad area PDA can be included in the non-display area NDA.

[0070] On the base substrate 100 of the display area DA, a pixel circuit including transistor structures TR1 and TR2 and a light-emitting element electrically connected to the pixel circuit can be included. The light-emitting element can be electrically connected to the transistor structure through a through-hole electrode VE.

[0071] The transistor structure may include a first transistor structure TR1 and a second transistor structure TR2. The first transistor structure TR1 and the second transistor structure TR2 may be used as the driving transistor and the switching transistor for the corresponding pixel, respectively.

[0072] The base substrate 100 can be configured as a backplane substrate for a display device or display panel. A glass substrate or a plastic substrate can be used as the base substrate 100.

[0073] In one or more embodiments, the base substrate 100 may include a polymeric material that is transparent and has a degree of flexibility. For example, the base substrate 100 may include a polymeric material such as polyimide, polysiloxane, epoxy resin, acrylic resin, or polyester. In one or more embodiments, the base substrate 100 may include polyimide.

[0074] In one or more embodiments, a glass substrate may be used as the base substrate 100.

[0075] A barrier layer 105 may be formed on the upper surface of the base substrate 100. The barrier layer 105 may block or reduce the penetration of moisture through the base substrate 100, and may block or reduce the diffusion of impurities between the base substrate 100 and the structures formed on the base substrate 100. The barrier layer 105 may completely cover the upper surface of the base substrate 100 (e.g., the barrier layer 105 may cover the entire upper surface of the base substrate 100).

[0076] For example, barrier layer 105 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride. These materials may be used alone or in combination of two or more. In one or more embodiments, barrier layer 105 may have a stacked structure comprising a silicon oxide film and a silicon nitride film. In one or more embodiments, barrier layer 105 may comprise an organic layer and may have a multilayer structure comprising organic and inorganic layers.

[0077] The bottom metal layer BML can be disposed on the barrier layer 105. The bottom metal layer BML can be disposed below the first transistor structure TR1 and can overlap with the first transistor structure TR1 in the thickness direction.

[0078] The bottom metal layer (BML) may include metals such as silver (Ag), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), molybdenum (Mo), platinum (Pt), or palladium (Pd), or alloys containing at least one of these metals.

[0079] The bottom metal layer (BML) can be used as a blocking layer to block or reduce external light incident on the first transistor structure TR1. The bottom metal layer (BML) can also be used as a bias electrode. In one or more embodiments, the bottom metal layer (BML) can be a floating electrode in the form of an island separated from other wiring or electrodes. In one or more embodiments, the bottom metal layer (BML) can be configured as a back gate or source-sink electrode.

[0080] A buffer layer 110 covering the bottom metal layer BML can be formed on the barrier layer 105. Furthermore, the buffer layer 110 can prevent or reduce the possibility of impurities penetrating into the active layers ACT1 and ACT2 of the transistor structures TR1 and TR2. The buffer layer 110 may include inorganic insulating materials such as silicon nitride, silicon oxide, and / or silicon nitride. The buffer layer 110 may have a single-layer structure or a multi-layer structure including inorganic insulating materials.

[0081] The first transistor structure TR1 and the second transistor structure TR2 can be disposed on the buffer layer 110. The first transistor structure TR1 may include a first active layer ACT1, a first gate electrode GE1, and a first overlapping electrode OE1. The second transistor structure TR2 may include a second active layer ACT2, a second gate electrode GE2, and a second overlapping electrode OE2.

[0082] Gate insulating layers 120 and 130 may be commonly included in the first transistor structure TR1 and the second transistor structure TR2 (and may be disposed across both the first transistor structure TR1 and the second transistor structure TR2). Each of the first transistor structure TR1 and the second transistor structure TR2 may also include a contact electrode CNT.

[0083] The first active layer ACT1 and the second active layer ACT2 can be arranged on the buffer layer 110.

[0084] The active layers ACT1 and ACT2 may each comprise a silicon compound such as polycrystalline silicon or amorphous silicon. Some regions of the active layers ACT1 and ACT2 may be doped with p-type or n-type dopants and may include source regions, drain regions, and channel regions.

[0085] The active layers ACT1 and ACT2 may include oxide semiconductors such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO).

[0086] The first gate insulating layer 120 can be formed on the active layers ACT1 and ACT2, and the first gate electrode GE1 and the second gate electrode GE2 can be stacked on the first gate insulating layer 120. The first gate insulating layer 120 can extend continuously across multiple pixels and can be used as a common layer for multiple transistor structures.

[0087] Alternatively, in one or more embodiments, the first gate insulating layer 120 may partially cover each active layer ACT1 and ACT2, and may be formed as an independent pattern for each in the transistor structure.

[0088] The first gate electrode GE1 can overlap with the channel region of the first active layer ACT1 in the third direction (thickness direction). The second gate electrode GE2 can overlap with the channel region of the second active layer ACT2 in the third direction (thickness direction). The scan signal can be transmitted from the scan line through the gate electrodes GE1 and GE2.

[0089] In one or more embodiments, p-type or n-type dopants can be implanted into the active layers ACT1 and ACT2 using an ion implantation process that uses gate electrodes GE1 and GE2 as ion implantation masks. Therefore, the first contact region CR1 and the second contact region CR2 can be formed on one side and the other side of the first active layer ACT1, respectively. The first contact region CR1 and the second contact region CR2 can correspond to the source region and the drain region, respectively. The third contact region CR3 and the fourth contact region CR4 can be formed on one side and the other side of the second active layer ACT2. The third contact region CR3 and the fourth contact region CR4 can correspond to the source region and the drain region, respectively.

[0090] In one or more embodiments, the first gate insulating layer 120 can be formed into a pattern covering the channel region by an etching process using gate electrodes GE1 and GE2 as etching masks. When the active layers ACT1 and ACT2 comprise oxide semiconductors, hydrogen (H) included in the second gate insulating layer 130 can diffuse or migrate into the active layers ACT1 and ACT2 during the formation of the second gate insulating layer 130. Therefore, the carrier concentration can be increased by hydrogen, allowing contact regions CR1, CR2, CR3, and CR4 to be formed at the side portions of the active layers ACT1 and ACT2.

[0091] The second gate insulating layer 130 may cover the gate electrodes GE1 and GE2 on the first gate insulating layer 120. Overlapping electrodes OE1 and OE2 may be formed on the second gate insulating layer 130. The first overlapping electrode OE1 may overlap with the first gate electrode GE1 in the thickness direction, and the second overlapping electrode OE2 may overlap with the second gate electrode GE2 in the thickness direction.

[0092] In one or more embodiments, the overlapping electrodes OE1 and OE2 may be configured as the upper gate electrodes. In one or more embodiments, the storage capacitor may be defined by the gate electrodes GE1 and GE2, the second gate insulating layer 130, and the overlapping electrodes OE1 and OE2 (e.g., the first gate electrode GE1, the second gate insulating layer 130, and the first overlapping electrode OE1 may define a first storage capacitor, and the second gate electrode GE2, the second gate insulating layer 130, and the second overlapping electrode OE2 may define a second storage capacitor). An interlayer insulating layer (ILD) covering the overlapping electrodes OE1 and OE2 may be formed on the second gate insulating layer 130.

[0093] In one or more embodiments, at least one of the overlapping electrodes OE1 and OE2 may not be provided. In such embodiments, the second gate insulating layer 130 and the interlayer insulating layer ILD may be formed substantially as a single interlayer insulating layer.

[0094] The gate insulating layers 120 and 130 and the interlayer insulating layer ILD may each comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon nitride, metal oxide, etc.

[0095] The gate electrodes GE1 and GE2 and the overlapping electrodes OE1 and OE2 may each comprise a metal, alloy thereof, or nitride thereof, such as Ag, Mg, Al, W, Cu, Ni, Cr, Mo, Ti, Pt, Ta, Nd, Sc, etc. In one or more embodiments, each of the gate electrodes GE1 and GE2 and / or the overlapping electrodes OE1 and OE2 may have a multilayer structure (e.g., Ti layer-Al layer-Ti layer).

[0096] On the interlayer insulating layer (ILD), contact electrodes CNT1, CNT2, CNT3, and CNT4 may be formed that are contacted or electrically connected to at least one of the active layers ACT1 and / or ACT2.

[0097] The contact electrode CNT may include a first contact electrode CNT1 connected to and / or in contact with a first contact region CR1 of the first active layer ACT1, and a second contact electrode CNT2 connected to and / or in contact with a second contact region CR2 of the first active layer ACT1. The first contact electrode CNT1 and the second contact electrode CNT2 may be used as the source electrode and drain electrode of the first transistor structure TR1, respectively.

[0098] The contact electrode CNT may include a third contact electrode CNT3 connected to and / or in contact with a third contact region CR3 of the second active layer ACT2, and a fourth contact electrode CNT4 connected to and / or in contact with a fourth contact region CR4 of the second active layer ACT2. The third contact electrode CNT3 and the fourth contact electrode CNT4 may be respectively configured as the source electrode and drain electrode of the second transistor structure TR2.

[0099] In one or more embodiments, the display device may further include a bottom contact BC that contacts and / or is electrically connected to the bottom metal layer BML by penetrating (extending through) the interlayer insulating layer ILD and the buffer layer 110. The bottom contact BC may also penetrate (extend through) the gate insulating layers 120 and 130.

[0100] In one or more embodiments, the bottom contact portion BC may be connected to a first contact electrode CNT1, which is configured as a source contact portion. In one or more embodiments, the bottom contact portion BC may be configured as a source-sink contact portion.

[0101] Through-hole insulating layer VIA and through-hole electrode VE can be stacked on the interlayer insulating layer ILD and the contact electrodes CNT1, CNT2, CNT3 and CNT4.

[0102] A first via insulating layer VIA1 may be formed on the interlayer insulating layer ILD and may cover contact electrodes CNT1, CNT2, CNT3 and CNT4. A first via electrode VE1 may be formed on the first via insulating layer VIA1 and may be connected to and / or contact each of contact electrodes CNT1, CNT2, CNT3 and CNT4.

[0103] The first via electrode VE1 may include a first wiring portion WP1 disposed on the first via insulating layer VIA1, and a first contact portion CP1 that penetrates (extends through) the first via insulating layer VIA1 and connects to contact electrodes CNT1, CNT2, CNT3, and CNT4. Each of the first wiring portion WP1 and the first contact portion CP1 may be substantially formed as a single integral component.

[0104] A second via insulating layer VIA2 may be formed on the first via insulating layer VIA1 and may cover the first via electrode VE1. A second via electrode VE2 may be formed on the second via insulating layer VIA2 and may be connected to and / or contact the first via electrode VE1.

[0105] The second via electrode VE2 may include a second wiring portion WP2 disposed on the second via insulating layer VIA2, and a second contact portion CP2 that penetrates (extends through) the second via insulating layer VIA2 and is connected to the first via electrode VE1. Each of the second wiring portion WP2 and the second contact portion CP2 may be substantially formed as a single integral component.

[0106] The third through-hole insulating layer VIA3 can be formed on the second through-hole insulating layer VIA2 and can cover the second through-hole electrode VE2.

[0107] Each of the first through-hole insulating layer VIA1, the second through-hole insulating layer VIA2, and the third through-hole insulating layer VIA3 may comprise an organic polymer material. For example, the first through-hole insulating layer VIA1, the second through-hole insulating layer VIA2, and the third through-hole insulating layer VIA3 may comprise polyimide, epoxy-based resin, acrylic-based resin, polyester, siloxane-based resin, or benzocyclobutene (BCB).

[0108] The first through-hole electrode VE1 and the second through-hole electrode VE2 may comprise the metal or alloy described above with respect to the gate electrode.

[0109] On the third via insulating layer VIA3, light-emitting elements (e.g., each of a plurality of light-emitting elements) including a pixel electrode PE, an emitting portion EL, and a counter electrode CE can be stacked. In one or more embodiments, the pixel electrode PE can be electrically connected to the second contact electrode CNT2 of the first transistor structure TR1 via a first via electrode VE1 and a second via electrode VE2. The pixel electrode PE may include a via portion that penetrates (extends through) the third via insulating layer VIA3 and is connected to and / or contacts the second via electrode VE2, and is connected to and / or contacts the second wiring portion WP2.

[0110] The pixel electrode PE can be configured as an anode and can include a high work function conductive material that promotes hole injection. The pixel electrode PE can also be configured as a transmission electrode. The pixel electrode PE can include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO).

[0111] The pixel electrode PE can also be configured as a semi-transmissive electrode or a reflective electrode. The pixel electrode PE may include a metal selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Vr, Li, Ca, Mo, Ti, W, In, Sn and Zn, or a compound thereof (e.g., LiF), or an alloy of two or more thereof.

[0112] The pixel electrode PE can have a single-layer structure or a multi-layer structure. For example, the pixel electrode PE can have a three-layer structure such as ITO / Ag / ITO or ITO / Al / ITO.

[0113] The pixel defining layer (PDL) can be formed on the third via insulating layer (VIA3), and the upper surface of the pixel electrode (PE) can be at least partially exposed by the pixel defining layer (PDL). The pixel defining layer (PDL) can cover the peripheral portion of the pixel electrode (PE).

[0114] The emitting region (or pixel region) can be defined by the sidewalls of the pixel-defining layer (PDL). For example, a green emitting region, a blue emitting region, and a red emitting region can be defined and separated by the pixel-defining layer (PDL). Therefore, the light-emitting element can include a blue light-emitting element, a green light-emitting element, and a red light-emitting element.

[0115] In one or more embodiments, the light-emitting elements can all be either white light-emitting elements or blue light-emitting elements.

[0116] The pixel defining layer (PDL) may include organic materials such as polysiloxane resins, polyimide resins, acrylic resins, etc. The pixel defining layer (PDL) may also include colorants (such as black pigments and / or black dyes) dispersed in the resin material.

[0117] An emitting portion (EL) can be disposed on the pixel electrode (PE) and the pixel definition layer (PDL). The emitting portion (EL) may include an organic emitting layer that is independently patterned for red, green, and blue pixels to produce a different color of light for each pixel.

[0118] In one or more embodiments, the emitting portion EL may extend continuously and commonly across multiple pixels. In such embodiments, the emitting portion EL may include a white emitting layer or a blue emitting layer. In one or more embodiments, the emitting portion EL may include emitting layers corresponding to multiple emitting layers, wherein the emitting layers correspond to different colors of light, and the emitting portion EL may include a stacked body having a cascaded structure including the emitting layers.

[0119] On the emitting section EL, a relative electrode CE can be provided. The relative electrode CE can be a common electrode that is continuously and commonly provided across multiple emitting regions or pixels.

[0120] The relative electrode CE can be configured as an electron injection electrode or a cathode. The relative electrode CE can include metals, alloys, conductive compounds, etc., with low work function.

[0121] For example, the relative electrode CE can include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, etc. These materials can be used alone or in combination of two or more.

[0122] The relative electrode CE can be configured as a transmission electrode, a semi-transmission electrode, or a reflection electrode. The relative electrode CE can have a single-layer structure or a multi-layer structure.

[0123] The emitting portion (EL) may further include a hole transport layer and an electron transport layer. According to one or more embodiments, the hole transport layer, the emitting layer, the electron transport layer, and the opposing electrode (CE) may be sequentially stacked from the upper surface of the pixel electrode (PE).

[0124] The hole transport layer may include hole transport materials such as m-MTDATA (4,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine), TDATA (4,4',4"-tris(N,N-diphenylamino)triphenylamine), 2-TNATA (4,4',4"-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), NPB (N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine), TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), TCTA (4,4',4"-tris(N-carbazolyl)triphenylamine), PEDOT / PSS (poly(3,4-ethylenedioxythiophene) / poly(sodium 4-styrenesulfonate)), etc.

[0125] The electron transport layer may include electron transport materials such as anthracene-based compounds, Alq3 (tris(8-hydroxyquinoline)aluminum), TPBi (1,3,5-tris(1-phenyl-1H-benzis[d]imidazol-2-yl)benzene), BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-diphenyl-1,10-phenanthroline), and TAZ (3-(4-biphenyl) (4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ (4-(naphthyl-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD (2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq (bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum), etc.

[0126] In one or more embodiments, a hole injection layer may be disposed between the pixel electrode PE and the hole transport layer, and an electron injection layer may be disposed between the relative electrode CE and the electron transport layer.

[0127] In one or more embodiments, the emission layer included in the emission portion EL can be selectively patterned within the emission region defined by the pixel-defined layer PDL. Therefore, the emission layer can be separated into islands for each of a plurality of pixels.

[0128] In one or more embodiments, the layers included in the emission portion EL (e.g., hole transport layer and electron transport layer) may extend continuously and commonly across the entire upper surface of multiple emission regions and pixel-defined layers PDL.

[0129] An organic light-emitting diode (OLED) device can be formed from the pixel electrode PE, the emitting portion EL, and the counter electrode CE as described above.

[0130] An encapsulation layer can be formed on the opposing electrode CE. The encapsulation layer can be disposed on the pixel defining layer (PDL) and the light-emitting element, and can protect the light-emitting element from moisture or oxygen.

[0131] The encapsulation layer may include: an inorganic film containing silicon nitride (SiN) x ), silicon oxide (SiO) x Indium tin oxide, indium zinc oxide, or combinations thereof (e.g., any suitable); organic membranes, including polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), epoxy resins (e.g., AGE (aliphatic glycidyl ether), etc.) or combinations thereof (e.g., any suitable); and / or combinations of inorganic and organic membranes (e.g., any suitable).

[0132] The encapsulation layer can be formed as a single layer or a multi-layer structure. In one or more embodiments, the encapsulation layer can have a structure in which a first inorganic layer, an organic layer, and a second inorganic layer are stacked in sequence.

[0133] In one or more embodiments, a color control layer overlapping the emitting portion (EL) may be disposed on the encapsulation layer. The color control layer may include a color conversion layer comprising quantum dots and / or color filters.

[0134] Pad 190 (for example, see Figure 1 It can be formed on the pad area of ​​the display device or the base substrate 100 PDA.

[0135] The pad 190 may include a bottom pad BPD, a first pad PAD1, and a second pad PAD2. According to one or more embodiments, the bottom pad BPD, the first pad PAD1, and the second pad PAD2 may be sequentially stacked from the upper surface of the first gate insulating layer 120.

[0136] The bottom pad BPD can be disposed on the first gate insulating layer 120 and can be formed of a layer comprising the same material as the gate electrodes GE1 and GE2 (e.g., the bottom pad BPD and the gate electrodes GE1 and GE2 can be formed simultaneously in the same layer). In one or more embodiments, the bottom pad BPD and the gate electrodes GE1 and GE2 can have substantially the same thickness.

[0137] The first pad PAD1 can contact the upper surface of the bottom pad BPD and can be on the second gate insulating layer 130 and the interlayer insulating layer ILD. The first pad PAD1 can be formed of a layer comprising the same material as the contact electrode CNT (e.g., the first pad PAD1 and the contact electrode CNT can be formed simultaneously in the same layer).

[0138] The first via insulating layer VIA1 can partially cover the first pad PAD1. The second pad PAD2 can contact the upper surface of the first pad PAD1 and can be on the first via insulating layer VIA1, and the second pad PAD2 can contact the portion of the upper surface of the first pad PAD1 adjacent to the first via insulating layer VIA1.

[0139] According to one or more embodiments, the thickness of the second pad PAD2 may be less than the thickness of the first pad PAD1, and the number of stacked layers of the second pad PAD2 may be less than the number of stacked layers of the first pad PAD1.

[0140] In one or more embodiments, the thickness of the second pad PAD2 may be less than the thickness of each of the first wiring portions WP1 of the first via electrode VE1.

[0141] As described above, by reducing the thickness of the second pad PAD2, cracking and damage to the bottom pad BPD caused by an excessive increase in the number of stacked layers included in the pad 190 can be prevented or reduced. Furthermore, in one or more embodiments, by reducing the number of interlayer interfaces included in the pad 190, the conductivity through the pad 190 can be improved.

[0142] Figures 3 to 19 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure. Figures 3 to 19 It is an explanation of manufacturing reference Figure 2 A cross-sectional view of the method for describing the display device.

[0143] refer to Figure 3 A barrier layer 105 can be formed on the base substrate 100, and a bottom metal layer BML can be formed on the barrier layer 105 of the display area DA. Subsequently, a buffer layer 110 covering the bottom metal layer BML can be formed on the barrier layer 105.

[0144] The barrier layer 105 and the buffer layer 110 can be formed by an application process or deposition process such as chemical vapor deposition (CVD), such that the barrier layer 105 and the buffer layer 110 comprise the inorganic insulating material described above. The barrier layer 105 and the buffer layer 110 can be formed continuously and commonly on the display area DA and the pad area PDA.

[0145] A conductive layer comprising the metal or alloy described above can be formed by an application process or deposition process such as sputtering or physical vapor deposition (PVD), and a bottom metal layer (BML) can be formed by patterning the conductive layer through photolithography and etching processes.

[0146] refer to Figure 4 An active layer comprising a first active layer ACT1 and a second active layer ACT2 can be formed on the buffer layer 110 of the display area DA.

[0147] For example, a semiconductor layer comprising a silicon-based compound or oxide semiconductor can be formed on the buffer layer 110 by an application or deposition process such as sputtering or PVD. Subsequently, the semiconductor layer can be patterned by a photolithography etching process to form a first active layer ACT1 and a second active layer ACT2.

[0148] Subsequently, a first gate insulating layer 120 covering the active layers ACT1 and ACT2 can be formed on the buffer layer 110. For example, the first gate insulating layer 120 can be formed by applying or depositing the inorganic insulating material described above using a CVD process.

[0149] The first gate insulating layer 120 can be continuously and commonly formed on the display area DA and the pad area PDA.

[0150] refer to Figure 5 Gate electrodes GE1 and GE2 can be formed on the first gate insulating layer 120 of the display area DA, and bottom pad BPD can be formed on the first gate insulating layer 120 of the pad area PDA.

[0151] According to one or more embodiments, a gate conductive layer comprising the metal or alloy described above can be formed on the first gate insulating layer 120 by an application process or deposition process such as sputtering or PVD. The gate conductive layer can be patterned by a photolithography etching process to form a first gate electrode GE1, a second gate electrode GE2, and a bottom pad BPD.

[0152] As described above, the bottom pad BPD can be formed using the same etching process with the same material layers as the gate electrodes GE1 and GE2. In one or more embodiments, the first gate electrode GE1, the second gate electrode GE2, and the bottom pad BPD can have the same stacked structure. In one or more embodiments, the first gate electrode GE1, the second gate electrode GE2, and the bottom pad BPD can have a three-layer structure of Ti-Al-Ti layer.

[0153] refer to Figure 6 Contact regions can be formed on the side portions of the active layers ACT1 and ACT2.

[0154] According to one or more embodiments, a first contact region CR1 and a second contact region CR2 can be formed at one side and another side of the first active layer ACT1, respectively, using an ion implantation process that uses gate electrodes GE1 and GE2 as ion implantation masks. A third contact region CR3 and a fourth contact region CR4 can be formed at one side and another side of the second active layer ACT2, respectively.

[0155] refer to Figure 7 A second gate insulating layer 130 covering the gate electrodes GE1 and GE2 and the bottom pad BPD can be formed on the first gate insulating layer 120.

[0156] In one or more embodiments, in the display region DA, the first gate insulating layer 120 may be formed as a patterned layer that partially overlaps with the active layers ACT1 and ACT2 beneath the gate electrodes GE1 and GE2. In such an embodiment, if the active layers ACT1 and ACT2 comprise oxide semiconductors (e.g., when the active layers ACT1 and ACT2 comprise oxide semiconductors), hydrogen from the second gate insulating layer 130 may be transferred to the active layers ACT1 and ACT2 (e.g., by etching defect sites caused by the first gate insulating layer 120), thereby forming contact regions CR1, CR2, CR3, and CR4.

[0157] refer to Figure 8 Overlapping electrodes OE1 and OE2 can be formed on the second gate insulating layer 130 of the display area DA.

[0158] For example, an overlapping conductive layer comprising the metal or alloy described above can be formed on the second gate insulating layer 130 by sputtering or PVD processes, and the overlapping conductive layer can be patterned by photolithography etching processes to form overlapping electrodes OE1 and OE2.

[0159] According to one or more embodiments, a first overlapping electrode OE1 and a second overlapping electrode OE2 may be formed on the second gate insulating layer 130, such that the first overlapping electrode OE1 and the second overlapping electrode OE2 overlap with the first gate electrode GE1 and the second gate electrode GE2, respectively.

[0160] refer to Figure 9 An interlayer insulating layer (ILD) covering the overlapping electrodes OE1 and OE2 can be formed on the second gate insulating layer 130.

[0161] The interlayer insulating layer (ILD) can be formed, for example, by a CVD process, such that the ILD comprises the inorganic insulating material described above. The ILD can be formed continuously and commonly on the display area (DA) and the pad area (PDA).

[0162] refer to Figure 10 The first contact hole CH1, the second contact hole CH2, the third contact hole CH3, and the fourth contact hole CH4, which expose the active layers ACT1 and ACT2 respectively, can be formed by partially etching the interlayer insulating layer ILD on the display area DA.

[0163] In one or more embodiments, a fifth contact hole CH5 exposing the bottom metal layer BML can be formed by partially etching the interlayer insulating layer ILD.

[0164] The first contact hole CH1, the second contact hole CH2, the third contact hole CH3, and the fourth contact hole CH4 can all penetrate (extend through) the interlayer insulating layer ILD, the second gate insulating layer 130, and the first gate insulating layer 120. The fifth contact hole CH5 can all penetrate (extend through) the interlayer insulating layer ILD, the second gate insulating layer 130, the first gate insulating layer 120, and the buffer layer 110.

[0165] According to one or more embodiments, the first pad hole PH1, which exposes the upper surface of the bottom pad BPD, can be formed on the pad area PDA by the etching process described above for forming contact holes.

[0166] The first pad via PH1 can penetrate (extend through) the interlayer insulating layer ILD and expose the bottom pad BPD. The first pad via PH1 can also penetrate (extend through) the interlayer insulating layer ILD and the second gate insulating layer 130.

[0167] refer to Figure 11 A first conductive layer can be formed on the interlayer insulating layer (ILD). The first conductive layer can fill contact holes CH1, CH2, CH3, CH4, and CH5. The first conductive layer can be formed by an application process or deposition process such as sputtering or PVD, such that the first conductive layer can include the metals or alloys described above.

[0168] A portion of the first conductive layer formed on the upper surface of the interlayer insulating layer (ILD) can be partially removed by photolithography etching, thereby forming contact electrodes CNT1, CNT2, CNT3, and CNT4 that contact and / or connect to the first contact region CR1, the second contact region CR2, the third contact region CR3, and the fourth contact region CR4, respectively, in the first contact hole CH1, the second contact hole CH2, the third contact hole CH3, and the fourth contact region CH4. A bottom contact portion BC that contacts or connects to the bottom metal layer BML can be formed in the fifth contact hole CH5.

[0169] On the pad area PDA, a first pad PAD1 can be formed using the first conductive layer through the application / deposition process and etching process described above. The first pad PAD1 can be formed on the interlayer insulating layer ILD, can fill the first pad hole PH1, and can contact and / or connect to the bottom pad BPD.

[0170] refer to Figure 12 A first via insulating layer VIA1 can be formed on the interlayer insulating layer (ILD). The first via insulating layer VIA1 can be formed by a coating process such as spin coating, and the first via insulating layer VIA1 can include the organic polymer material described above.

[0171] The first through-hole insulating layer VIA1 can cover the contact electrodes CNT1, CNT2, CNT3 and CNT4 on the display area DA and the bottom contact portion BC, and can also cover the first pad PAD1 on the pad area PDA.

[0172] Subsequently, the first via VH1 can be formed by partially etching the first via insulating layer VIA1. The upper surface of the contact electrode CNT can be exposed through each of the first via VH1. The etching process of the first via insulating layer VIA1 allows the formation of a second pad hole PH2 on the pad area PDA, exposing the upper surface of the first pad PAD1.

[0173] refer to Figure 13A second conductive layer filling the first via VH1 and the second pad via PH2 can be formed on the first via insulating layer VIA1. The second conductive layer can be formed by an application process or deposition process such as sputtering or PVD, and the second conductive layer can include the metal or alloy described above.

[0174] Subsequently, the portion of the second conductive layer formed on the upper surface of the first via insulating layer VIA1 can be partially removed by photolithography etching, thereby forming the first via electrode VE1 and the second pad PAD2.

[0175] The first via electrode VE1 may include a first contact portion CP1 filling the first via VH1, and a first wiring portion WP1 formed on the upper surface of the first via insulating layer VIA1. A second pad PAD2 may be formed on the upper surface of the first via insulating layer VIA1, may fill the second pad hole PH2, and may contact and / or connect to the upper surface of the first pad PAD1.

[0176] refer to Figure 14 A second via insulating layer VIA2 covering the first via electrode VE1 can be formed on the first via insulating layer VIA1 in the display area DA. The second via insulating layer VIA2 can be formed by a coating process such as spin coating, and the second via insulating layer VIA2 can include the organic polymer material described above.

[0177] Subsequently, a second via VH2 can be formed by partially etching the second via insulating layer VIA2 to expose the upper surface of the first via electrode VE1 (e.g., the first wiring portion WP1).

[0178] refer to Figure 15 A third conductive layer CL3 can be formed on the second via insulating layer VIA2. The third conductive layer CL3 can be formed by an application process or deposition process such as sputtering or PVD, and the third conductive layer CL3 can include the metal or alloy described above.

[0179] The third conductive layer CL3 can fully fill the second via VH2 and can be formed on the upper surface of the second via insulating layer VIA2. The third conductive layer CL3 can be continuously and commonly formed on the display area DA and the pad area PDA.

[0180] refer to Figure 16On the display area DA, a second via electrode VE2 can be formed by partially etching a portion of the third conductive layer CL3 formed on the upper surface of the second via insulating layer VIA2. The second via electrode VE2 may include a second wiring portion WP2 formed on the upper surface of the second via insulating layer VIA2, and a second contact portion CP2 that contacts and / or connects to the first wiring portion WP1 within the second via insulating layer VIA2.

[0181] According to one or more embodiments, the third conductive layer CL3 can be substantially removed from the pad region PDA using the etching process described above. In one or more embodiments, the upper portion of the second pad PAD2 can also be partially etched by etching the third conductive layer CL3 on the pad region PDA, thereby reducing the thickness of the second pad PAD2.

[0182] According to one or more embodiments, the etching of the third conductive layer CL3 may include dry etching, and the upper portion of the second pad PAD2 may be partially etched by dry etching.

[0183] refer to Figure 17 A third through-hole insulating layer VIA3 covering the second through-hole electrode VE2 can be formed on the second through-hole insulating layer VIA2. The third through-hole insulating layer VIA3 can be formed by a coating process such as spin coating, and the third through-hole insulating layer VIA3 can include the organic polymer material described above.

[0184] In one or more embodiments, the third via insulating layer VIA3 may be formed together on the display area DA and the pad area PDA.

[0185] refer to Figure 18 This process can remove the portion of the third via insulating layer VIA3 formed on the pad area of ​​the PDA. According to one or more embodiments, the portion of the third via insulating layer VIA3 formed on the pad area of ​​the PDA can be removed by a wet etching process.

[0186] In one or more embodiments, after forming a photoresist layer that selectively covers the portion of the third via insulating layer VIA3 formed on the display area DA, the photoresist layer can be used as an etching mask to etch the portion of the third via insulating layer VIA3 formed on the pad area PDA.

[0187] According to one or more embodiments, the upper portion of the second pad PAD2 can be partially removed by a wet etching process of the third through-hole insulating layer VIA3, thereby further reducing the thickness of the second pad PAD2.

[0188] In one or more embodiments, the thickness of the second pad PAD2 may be less than the thickness of the second wiring portion WP2 of the second via electrode VE2.

[0189] refer to Figure 19 A reference can be formed on the portion of the third through-hole insulating layer VIA3 within the display area DA. Figure 2 The light-emitting element described.

[0190] According to one or more embodiments, a via can be formed on the upper surface of the second wiring portion WP2 that exposes at least one of the second via electrodes VE2 by partially etching the third via insulating layer VIA3. Thereafter, a pixel electrode layer filling the via can be formed on the third via insulating layer VIA3, and pixel electrodes PE (e.g., multiple pixel electrodes PE, e.g., one pixel electrode PE per pixel) can be formed by patterning the pixel electrode layer.

[0191] In one or more embodiments, the formation and referencing of the through-hole can be performed together using the same process. Figure 18 The removal of the insulating layer VIA3 in the third via on the pad area of ​​the PDA is described.

[0192] A pixel defining layer (PDL) covering the peripheral portion of the pixel electrode (PE) can be formed on the upper surface of the third via insulating layer (VIA3). In one or more embodiments, the pixel defining layer (PDL) can be formed by coating a photosensitive organic material such as a polysiloxane resin, polyimide resin, or acrylic resin and performing an exposure and development process. In one or more embodiments, the pixel defining layer (PDL) can also be formed by a printing process such as an inkjet printing process using polymeric or inorganic materials.

[0193] The emission portion EL can be formed on the upper surface of the pixel electrode PE exposed by the pixel defining layer PDL and on the sidewall of the pixel defining layer PDL.

[0194] The emitting portion EL can be formed by application processes such as thermal deposition, evaporation deposition, vacuum deposition, spin coating, inkjet printing, laser printing, casting, laser thermal transfer, etc., and the emitting portion EL can include the organic light-emitting materials described above.

[0195] As described above, the emitting section EL may include a hole transport layer, an emitting layer, and an electron transport layer.

[0196] In one or more embodiments, the hole transport layer and the electron transport layer may be formed continuously and commonly across multiple pixels or pixel electrodes (PEs) and pixel defining layers (PDLs). In one or more embodiments, the emitter layer may be selectively patterned for each pixel electrode (PE) of a given pixel.

[0197] After forming the opposing electrode CE, which serves as a common electrode on the pixel defining layer (PDL) and the emitting portion (EL), an encapsulation layer protecting the pixel and the opposing electrode CE can be formed. The encapsulation layer can be formed such that it includes a multilayer structure comprising an inorganic insulating layer and an organic insulating layer. For example, the encapsulation layer can be formed as a structure of sequentially stacked first inorganic insulating layer, organic insulating layer, and second inorganic insulating layer.

[0198] According to one or more embodiments of this disclosure, the formation of the first pad PAD1 and the second pad PAD2, as well as the partial etching of the second pad PAD2, can be performed using a through-hole electrode and through-hole insulating layer formation process or a patterning process.

[0199] Therefore, pads 190 with an appropriate or suitable number of stacked layers can be formed, and damage to the bottom pad BPD can be prevented or reduced.

[0200] Figure 20 This is an enlarged partial cross-sectional view showing the stacked structure of contact electrodes and through-hole electrodes of a display device according to one or more embodiments of the present disclosure.

[0201] refer to Figure 20 For reference Figure 2 As described, a multilayer structure of contact electrode CNT, first via electrode VE1, and second via electrode VE2 can be formed on the display area DA (center). Like the first via electrode VE1 and the second via electrode VE2, the contact electrode CNT can each have a wiring portion WP and a contact portion CP.

[0202] In one or more embodiments, each of the contact electrode CNT, the first via electrode VE1, and the second via electrode VE2 may have a multilayer structure. In one or more embodiments, each of the contact electrode CNT, the first via electrode VE1, and the second via electrode VE2 may have a multilayer structure consisting of a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3.

[0203] The second metal layer ML2 may include a metal having a lower resistance than the metals included in the first metal layer ML1 and the third metal layer ML3. For example, the second metal layer ML2 may include Al or Ag. In one or more embodiments, the second metal layer ML2 may include Al.

[0204] Each of the first metal layer ML1 and the third metal layer ML3 may include a metal that is chemically more stable than the metal included in the second metal layer ML2. For example, each of the first metal layer ML1 and the third metal layer ML3 may include Ti or Ta. In one or more embodiments, each of the first metal layer ML1 and the third metal layer ML3 may include Ti.

[0205] In one or more embodiments, each of the contact electrode CNT, the first through-hole electrode VE1, and the second through-hole electrode VE2 may have a sequential multilayer structure of Ti-Al-Ti layers.

[0206] Figures 21 to 24 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of this disclosure. It may not be repeated with reference to the preceding text. Figures 3 to 19 A detailed description of a process that is substantially the same as or similar to the described process.

[0207] refer to Figure 21 It can be executed and referenced. Figures 3 to 15 The processes described are essentially the same or similar.

[0208] Therefore, the bottom pad BPD, the first pad PAD1, the second pad PAD2, and the third conductive layer CL3 can be sequentially stacked on the pad area PDA. Each of the first pad PAD1, the second pad PAD2, and the third conductive layer CL3 can have a sequentially stacked structure of a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3.

[0209] refer to Figure 22 It can be executed and referenced. Figure 16 The processes described are essentially the same or similar.

[0210] Therefore, if the third conductive layer CL3 is removed from the pad region PDA (e.g., when the third conductive layer CL3 is removed from the pad region PDA), the upper portion of the second pad PAD2 can be partially removed. In one or more embodiments, as described above, while removing the third conductive layer CL3 by dry etching, a third metal layer ML3 of the second pad PAD2, for example comprising titanium (Ti), can be removed.

[0211] refer to Figure 23 It can be executed and referenced. Figure 17 The described processes are essentially the same or similar. Therefore, a third via insulating layer VIA3 can be formed on the second pad PAD2.

[0212] refer to Figure 24 It can be executed and referenced. Figure 18 The processes described are essentially the same or similar.

[0213] In one or more embodiments, while removing the portion of the third via insulating layer VIA3 formed on the pad region PDA by wet etching, the second metal layer ML2 of the second pad PAD2, for example, comprising aluminum (Al), can be removed. Therefore, the second pad PAD2, which substantially retains the first metal layer ML1, can remain on the first pad PAD1.

[0214] While maintaining the stacked structure of the first metal layer ML1, the second metal layer ML2 and the third metal layer ML3, the first pad PAD1 can be included in the pad 190.

[0215] Figure 25 This is a schematic cross-sectional view illustrating a display device according to one or more embodiments of the present disclosure. It may be omitted from the reference. Figure 2 The configurations and structures described are substantially the same or similar in detail.

[0216] refer to Figure 25 ,refer to Figure 2 The described transistor structures TR1 and TR2, via electrodes VE1 and VE2, and light-emitting elements can be arranged on the display area DA.

[0217] Pads 190, including bottom pad BPD, first pad PAD1, and second pad PAD2, can be arranged on the pad area PDA.

[0218] For reference Figure 2 As described, the bottom pad BPD can be disposed on the first gate insulating layer 120 and can be formed of a layer of the same material as the gate electrodes GE1 and GE2 (e.g., the bottom pad BPD and the gate electrodes GE1 and GE2 can be formed simultaneously in the same layer). In one or more embodiments, the bottom pad BPD and the gate electrodes GE1 and GE2 can have substantially the same thickness.

[0219] The second gate insulating layer 130 and the interlayer insulating layer ILD can partially cover the bottom pad BPD. The first pad PAD1 can be formed on the interlayer insulating layer ILD, can penetrate (extend through) the interlayer insulating layer ILD, and can contact and / or connect to the upper surface of the bottom pad BPD.

[0220] The second pad PAD2 can be disposed on the interlayer insulating layer (ILD) and can cover the first pad PAD1. According to one or more embodiments, the second pad PAD2 can completely cover the upper surface of the first pad PAD1 (e.g., it can cover the entire upper surface of the first pad PAD1). The second pad PAD2 can completely cover both the upper and side surfaces of the first pad PAD1 (e.g., it can cover the entire upper and side surfaces of the first pad PAD1).

[0221] The second pad PAD2 may have a greater thickness than the first pad PAD1. According to one or more embodiments, the thickness of the second pad PAD2 may be substantially the same as the thickness of the second wiring portion WP2 of the second via electrode VE2. The thickness of the first pad PAD1 may be less than the thickness of the contact electrode CNT on the upper surface of the interlayer insulating layer ILD.

[0222] As described above, the thickness of the first pad PAD1 can be reduced, thereby preventing or reducing cracking and damage to the bottom pad BPD that can be caused by an excessive increase in the number of stacked layers included in the pad 190. Furthermore, in one or more embodiments, the number of interlayer interfaces included in the pad 190 can be reduced, thereby improving the conductivity through the pad 190.

[0223] Figures 26 to 32 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of this disclosure. It may not be repeated with reference to the preceding text. Figures 2 to 19 A detailed description of a process that is substantially the same as or similar to the described process.

[0224] refer to Figure 26 It can be executed and referenced. Figures 3 to 11 The processes described are essentially the same or similar.

[0225] Therefore, a first transistor structure TR1 can be formed on the base substrate 100 of the display area DA (see, for example, see...). Figure 2 The second transistor structure TR2. Furthermore, in one or more embodiments, a bottom contact BC connected to the bottom metal layer BML can be formed.

[0226] The bottom pad BPD can be formed together with the gate electrodes GE1 and GE2 on the base substrate 100 of the pad region PDA. In addition, in one or more embodiments, a first pad PAD1 can be formed on the interlayer insulating layer ILD to contact or connect to the bottom pad BPD by penetrating (extending through) the interlayer insulating layer ILD.

[0227] As described above, the contact electrode CNT and the first pad PAD1 can be formed together by the application / deposition process of the first conductive layer and the etching process.

[0228] refer to Figure 27 A first via insulating layer VIA1 covering the contact electrode CNT can be formed on the display area DA. Subsequently, a first via VH1 exposing the upper surface of the contact electrode CNT can be formed by partially etching the first via insulating layer VIA1.

[0229] refer to Figure 28A second conductive layer CL2, which fills the first via VH1, can be formed on the upper surface of the first via insulating layer VIA1. On the pad area PDA, the second conductive layer CL2 can be formed on the interlayer insulating layer ILD, and the second conductive layer CL2 can completely cover the first pad PAD1 (e.g., it can cover the entire first pad PAD1).

[0230] refer to Figure 29 The first via electrode VE1 can be formed by partially etching the second conductive layer CL2. The portion of the second conductive layer CL2 formed on the pad area PDA can be substantially completely etched (e.g., substantially completely removed).

[0231] According to one or more embodiments, the upper portion of the first pad PAD1 can be partially etched together with the etching of the second conductive layer CL2. Therefore, the thickness of the first pad PAD1 can be reduced. The etching of the second conductive layer CL2 can include dry etching.

[0232] refer to Figure 30 A second via insulating layer VIA2 can be formed on the first via insulating layer VIA1, covering the first via electrode VE1. The second via insulating layer VIA2 can be etched and substantially removed from the pad area PDA.

[0233] According to one or more embodiments, the upper portion of the first pad PAD1 can be partially etched by etching the second via insulating layer VIA2. Therefore, the thickness of the first pad PAD1 can be further reduced. Etching of the second via insulating layer VIA2 may include wet etching.

[0234] The second via VH2, which exposes the upper surface of the first via electrode VE1, can be formed by etching a portion of the second via insulating layer VIA2 formed in the display area DA.

[0235] In one or more embodiments, the etching of the second via insulating layer VIA2 on the pad region PDA can be performed together with the formation of the second via VH2.

[0236] refer to Figure 31 A third conductive layer can be formed on the upper surface of the second via insulating layer VIA2, and the second via electrode VE2 and the second pad PAD2 can be formed by etching the third conductive layer.

[0237] The second pad PAD2 can completely cover the upper and side surfaces of the first pad PAD1 (e.g., it can cover the entire upper and side surfaces of the first pad PAD1). The second pad PAD2 can have a thickness substantially the same as the thickness of the second wiring portion WP2 of the second via electrode VE2.

[0238] refer to Figure 32 A third through-hole insulating layer VIA3, which covers the second through-hole electrode VE2 and the second pad PAD2, can be formed on the second through-hole insulating layer VIA2.

[0239] Subsequently, a third via VH3 exposing at least one of the second via electrodes VE2 can be formed by partially etching the third via insulating layer VIA3. A second pad hole PH2 exposing the upper surface of the second pad PAD2 can be formed on the pad region PDA by etching the third via insulating layer VIA3.

[0240] Subsequently, as per reference Figure 19 The described light-emitting element can be formed including a pixel electrode PE that fills a third through-hole VH3 and is formed on a third through-hole insulating layer VIA3.

[0241] Figures 33 to 35 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of this disclosure. It may not be repeated with reference to the preceding text. Figures 25 to 32 A detailed description of a process that is substantially the same as or similar to the described process.

[0242] refer to Figure 33 It can be executed and referenced. Figures 25 to 28 The processes described are essentially the same or similar.

[0243] Therefore, a bottom pad BPD can be formed on the first gate insulating layer 120, and a first pad PAD1 and a second conductive layer CL2 can be sequentially formed on the bottom pad BPD. Each of the first pad PAD1 and the second conductive layer CL2 can have a multilayer structure of a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3.

[0244] refer to Figure 34 It can be executed and referenced. Figure 29 The processes described are essentially the same or similar.

[0245] Therefore, when the second conductive layer CL2 is removed on the pad area PDA, the third metal layer ML3 of the first pad PAD1, including, for example, Ti, can be removed together with the second conductive layer CL2.

[0246] refer to Figure 35 It can be executed and referenced. Figure 30 and Figure 31 The processes described are essentially the same or similar.

[0247] According to one or more embodiments, as referenced Figure 30As described, the second metal layer ML2 of the first pad PAD1, including, for example, Al, can be selectively etched or removed together with the second via insulating layer VIA2 on the display area DA by wet etching. Therefore, only the first metal layer ML1 within the first pad PAD1 can be substantially retained.

[0248] Subsequently, as per reference Figure 31 As described, a second pad PAD2 can be formed on the first pad PAD1 with a sequential multilayer structure having a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3.

[0249] Figure 36 and Figure 37 This is a schematic cross-sectional view illustrating a display device according to one or more embodiments of the present disclosure. According to one or more embodiments, Figure 36 and Figure 37 A display device is shown in which transistors having active layers formed of oxide semiconductors and transistors having active layers based on silicon are combined. (This is not repeated from the reference.) Figure 2 and Figure 25 The configurations and structures described are substantially the same or similar in detail.

[0250] refer to Figure 36 and Figure 37 The first transistor structure TR1 and the second transistor structure TR2 can be arranged on the base substrate 100 of the display area DA.

[0251] The first transistor structure TR1 may include a first active layer ACT1 comprising a silicon-based compound as described above, and the second transistor structure TR2 may include a second active layer ACT2 comprising an oxide semiconductor as described above.

[0252] The second active layer ACT2 can be located at a level higher than the first active layer ACT1. The first active layer ACT1 can be arranged on the buffer layer 110.

[0253] According to one or more embodiments, the interlayer insulating layer (ILD) may include a first interlayer insulating layer (ILD1) and a second interlayer insulating layer (ILD2). The first interlayer insulating layer (ILD1) may be formed on the second gate insulating layer 130 and may cover the overlapping electrode OE and the bottom metal layer (BML).

[0254] The overlapping electrode OE can overlap with the first gate electrode GE1 in the thickness direction, and the second gate insulating layer 130 is inserted therebetween. The bottom metal layer BML can be disposed below the second active layer ACT2 and can overlap with the second active layer ACT2 in the thickness direction, and the first interlayer insulating layer ILD1 is inserted therebetween.

[0255] The second active layer ACT2 can be disposed on the upper surface of the first interlayer insulating layer ILD1. The second gate electrode GE2 can overlap with the channel region of the second active layer ACT2, and the gate insulating pattern 145 is inserted therebetween. The second interlayer insulating layer ILD2 can cover the second gate electrode GE2 on the first interlayer insulating layer ILD1.

[0256] Each of the first contact electrode CNT1 and the second contact electrode CNT2 can penetrate (extend through) the interlayer insulating layer ILD, the second gate insulating layer 130 and the first gate insulating layer 120, and can respectively contact and / or connect to the first contact region CR1 or the second contact region CR2 of the first active layer ACT1.

[0257] Each of the third contact electrode CNT3 and the fourth contact electrode CNT4 can penetrate (extend through) the second interlayer insulating layer ILD2 and can respectively contact and / or connect to the third contact region CR3 or the fourth contact region CR4 of the second active layer ACT2. In one or more embodiments, as referenced Figure 2 As described, a bottom contact portion BC can be formed that connects to the bottom metal layer BML and the third contact electrode CNT3.

[0258] A stacked structure of at least one of the first through-hole electrodes VE1 and one of the second through-hole electrodes VE2 can be arranged on the upper surface of the second contact electrode CNT2.

[0259] like Figure 36 The description in the reference Figure 2 The pads 190 described are substantially the same or similar and can be arranged on the base substrate 100 of the pad area PDA. The pads 190 may include a bottom pad BPD, a first pad PAD1, and a second pad PAD2 with a relatively reduced thickness.

[0260] like Figure 37 The description in the reference Figure 25 The pads 190 described are substantially the same or similar and can be arranged on the base substrate 100 of the pad area PDA. The pads 190 may include a bottom pad BPD, a first pad PAD1 with a relatively reduced thickness, and a second pad PAD2 surrounding the first pad PAD1.

[0261] Figure 38 This is an equivalent circuit diagram of a display device according to one or more embodiments of the present disclosure.

[0262] refer to Figure 38Each pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

[0263] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be connected to a storage capacitor CST. The first terminal may be connected to a second transistor T2. The second terminal may be connected to a sixth transistor T6. The first transistor T1 may generate a drive current ID based on the voltage difference between the gate terminal and the first terminal. For example, the first transistor T1 may be referred to as a drive transistor.

[0264] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 may receive a first gate signal Gs1. The second transistor T2 may be turned on or off in response to the first gate signal Gs1. The first terminal of the second transistor T2 may receive a data voltage DATA. The second transistor T2 may provide the data voltage DATA to the first terminal of the first transistor T1 in response to the first gate signal Gs1. For example, the second transistor T2 may be referred to as a switching transistor.

[0265] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a first gate signal Gs1. The first terminal may be connected to the gate terminal of the first transistor T1. The second terminal may be connected to the second terminal of the first transistor T1. The third transistor T3 may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be configured as a compensation transistor.

[0266] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a second gate signal Gs2. The first terminal may be connected to the gate terminal of the first transistor T1. The second terminal may receive an initialization voltage VINT. The fourth transistor T4 may initialize the gate terminal of the first transistor T1.

[0267] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a transmit control signal ELC. The first terminal may receive a high power supply voltage ELVDD. The second terminal may be connected to the first transistor T1.

[0268] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive an emitter control signal ELC. The first terminal may be connected to the first transistor T1. The second terminal may be connected to the organic light-emitting diode (OLED). The sixth transistor T6 may transmit a drive current ID to the OLED in response to the emitter control signal ELC.

[0269] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a third gate signal Gs3. The first terminal may be connected to an organic light-emitting diode (OLED). The second terminal may receive an initialization voltage VINT. The seventh transistor T7 can initialize the OLED.

[0270] The storage capacitor CST may include a first terminal and a second terminal. The first terminal may receive a high power supply voltage ELVDD, and the second terminal may be connected to the gate terminal of the first transistor T1.

[0271] An organic light-emitting diode (OLED) may include a first terminal and a second terminal. The first terminal may be connected to a sixth transistor T6. The second terminal may receive a low power supply voltage ELVSS. The OLED may emit light based on a drive current ID.

[0272] In one or more embodiments, including references Figure 36 and Figure 37 The first transistor structure TR1 of the first active layer ACT1 of the silicon semiconductor described herein can be used as the first transistor T1. In one or more embodiments, the second transistor structure TR2, which includes a second active layer ACT2 comprising an oxide semiconductor, can be used as the second transistor T2.

[0273] exist Figure 38 The image shows a 7T1C structure in which seven thin-film transistors and a storage capacitor CST are included in each pixel PX, but the pixel structure of the display device disclosed in this application is not limited to this.

[0274] For example, each pixel PX may include two or more transistors and may have a structure such as 2T1C, 5T1C, 6T1C, 5T2C, 6T2C, etc.

[0275] Figure 39 This is a block diagram illustrating an electronic device according to one or more embodiments of the present disclosure.

[0276] refer to Figure 39 An electronic device 10 according to one or more embodiments may include a display module 11, a processor 12, a storage device 13, and a power module 14.

[0277] The processor 12 may include a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and / or a controller.

[0278] Storage device 13 can store data information used to operate processor 12 or display module 11. When processor 12 executes an application stored in storage device 13, image data signals and / or input control signals can be transmitted to display module 11, and display module 11 can process the received signals and output image information through the display screen.

[0279] The power module 14 may include a power supply module such as a power adapter, a battery device, etc., and a power conversion module that converts the power supplied by the power supply module and generates power for operating the electronic device 10.

[0280] At least one of the components of the electronic device 10 described above may be included in a display device according to one or more embodiments described above. Furthermore, in one or more embodiments, some modules included in a single functional module may be included in the display device, and other modules may be disposed separately from the display device. For example, display module 11 may include the display device, and processor 12, storage device 13, and power module 14 may be disposed as other devices within the electronic device 10 instead of the display device.

[0281] Figure 40 Various embodiments according to this disclosure are illustrated. Figure 39 A schematic diagram of the electronic device.

[0282] refer to Figure 40 Non-limiting examples of one or more suitable electronic devices that can be used with the display device according to one or more embodiments described above may include image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, desktop monitors 10_1e, etc.; wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.; and vehicle electronic devices 10_3 including display modules such as central information displays (CIDs) arranged on the dashboard, center console, or instrument panel of a vehicle, interior mirror displays, etc. The electronic devices may also include virtual reality glasses or augmented reality glasses.

[0283] This disclosure can be applied to display devices and electronic devices that include display devices. For example, this disclosure can be applied to televisions (TV), digital TVs, 3D TVs, mobile phones, smartphones, tablet computers, laptop computers, personal computers (PCs), home electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0284] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted as having an ideal or overly formal meaning.

[0285] Furthermore, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure".

[0286] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree and are intended to allow for inherent deviations in measured or calculated values ​​that would be recognized by a person skilled in the art. As used herein, “substantially” includes the stated value and means within an acceptable range of deviation for a particular value, as determined by a person skilled in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “substantially” could mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, it should be understood that even if the terms “about,” “approximately,” or “substantially” are not expressly stated in a given element (e.g., a claim element), the scope of that element is intended to include non-substantial variations or variations as understood by a person skilled in the art. For example, the numerical values ​​and ranges provided herein are intended to include tolerances and measurement uncertainties that would be recognized by a person skilled in the art, and elements (e.g., claim elements) should be interpreted accordingly to include such equivalents.

[0287] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges containing the same numerical precision within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and including) the described minimum value of 1.0 and the described maximum value of 10.0, i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0288] Display devices, electronic devices, means for manufacturing display devices, and / or other related means or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of the device may be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard storage devices such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as, for example, CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0289] In view of the entire contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0290] In the claims, the device plus function clauses are intended to cover the structures described herein for performing the recited functions, and to cover not only structural equivalents but also equivalent structures.

[0291] It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, unless expressly indicated otherwise, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in relation to a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in relation to other embodiments. It will be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A method for manufacturing a display device, comprising: An active layer is applied on a portion of a base substrate in the display area, wherein the base substrate defines the display area and the pad area; A gate electrode overlapping the active layer is applied in the display area, and a bottom pad is applied on a portion of the base substrate in the pad area; A contact electrode connected to the active layer is applied in the display area, and a first pad connected to the bottom pad is applied in the pad area; Apply an insulating layer covering the through-holes of the contact electrodes; A via electrode is applied in the display area, passing through the via insulating layer and connected to the contact electrode, and a second pad is applied in the pad area, connected to the first pad; While etching the via insulating layer in the pad region, the upper portion of the first pad or the upper portion of the second pad is partially etched; and A light-emitting element electrically connected to the through-hole electrode is applied.

2. The method according to claim 1, wherein, Applying the through-hole insulating layer includes: Apply an insulating layer covering the first through-hole of the contact electrode; Apply a second through-hole insulating layer onto the first through-hole insulating layer; and A third through-hole insulating layer is applied on the second through-hole insulating layer, and Applying the through-hole electrode includes: A first through-hole electrode is applied, the first through-hole electrode extending through the first through-hole insulating layer and connecting to the contact electrode; and A second through-hole electrode is applied, which extends through the second through-hole insulating layer and connects to the first through-hole electrode.

3. The method according to claim 2, wherein, Applying the second via electrode includes applying a third conductive layer on the second via insulating layer to cover the second pad in the pad region.

4. The method according to claim 3, wherein, The method further includes: while etching a portion of the third conductive layer in the pad region, partially etching the upper portion of the second pad.

5. The method according to claim 4, wherein, The second pad has a structure in which a first metal layer, a second metal layer, and a third metal layer are stacked in sequence, and Partially etching the upper portion of the second pad while etching the portion of the third conductive layer includes etching the third metal layer of the second pad.

6. The method according to claim 5, wherein, Partially etching the upper portion of the first pad or the upper portion of the second pad includes etching the second metal layer of the second pad while etching the third via insulating layer in the pad region.

7. The method according to claim 2, wherein, Applying the first via electrode includes: applying a second conductive layer on the first via insulating layer to cover the first pad in the pad region.

8. The method according to claim 7, wherein, The method further includes: while etching a portion of the second conductive layer in the pad region, partially etching the upper portion of the first pad.

9. The method according to claim 8, wherein, The first pad has a structure in which a first metal layer, a second metal layer, and a third metal layer are stacked in sequence, and Partially etching the upper portion of the first pad while etching the portion of the second conductive layer includes etching the third metal layer of the first pad.

10. The method according to claim 9, wherein, Partially etching the upper portion of the first pad or the upper portion of the second pad includes etching the second metal layer of the first pad while etching the second via insulating layer in the pad region.

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